WO2022100725A1 - 硅片的刻蚀方法 - Google Patents

硅片的刻蚀方法 Download PDF

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Publication number
WO2022100725A1
WO2022100725A1 PCT/CN2021/130553 CN2021130553W WO2022100725A1 WO 2022100725 A1 WO2022100725 A1 WO 2022100725A1 CN 2021130553 W CN2021130553 W CN 2021130553W WO 2022100725 A1 WO2022100725 A1 WO 2022100725A1
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Prior art keywords
etching
etching step
silicon
equal
mixed gas
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English (en)
French (fr)
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朱海云
蒋中伟
王京
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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Priority to JP2023528429A priority Critical patent/JP7530519B2/ja
Priority to KR1020237015700A priority patent/KR102750856B1/ko
Priority to US18/252,705 priority patent/US20240006182A1/en
Publication of WO2022100725A1 publication Critical patent/WO2022100725A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the technical field of semiconductor technology, in particular, to a method for etching silicon wafers.
  • Plasma etching processes are widely used in semiconductor fabrication.
  • the anisotropic etching properties of plasma enabled further reductions in the size of integrated circuit components, laying a solid foundation for the continued prosperity of integrated circuits in subsequent decades.
  • the limit of Moore's Law (the number of transistors that can be accommodated on an integrated circuit will double approximately every 24 months) is getting closer and closer. (called a wafer or silicon wafer) to create more space in the vertical direction to place more electronic components.
  • the application of high aspect ratio etching process can prepare finer micro-nano structures, but in the existing high aspect ratio etching process such as the etching of deep trench silicon, the etching pattern is isotropic etching, that is, the lateral The etching is severe. For example, when the bosh process is used for deep silicon etching, a scallop effect (Scallop) will appear on the sidewall of the pattern (trench or via), resulting in rough and uneven sidewall morphology.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and proposes an etching method for silicon wafers, which solves the problem that the etching of deep silicon with a high aspect ratio in the prior art is prone to rough sidewalls and irregularities. leveling problem.
  • a method for etching a silicon wafer comprising:
  • the main etching step using the first mixed gas to perform a plasma etching process to etch the silicon wafer until the pattern on the silicon wafer reaches a specified aspect ratio; the first mixed gas is set to It can etch silicon and react with silicon to generate non-volatile reaction products;
  • Auxiliary etching step using a second mixed gas to perform a plasma etching process; the second mixed gas is set to be able to react with silicon to generate a non-volatile reaction product, and the non-volatile reaction product in the auxiliary etching step The formation rate of reaction products is greater than the formation rate of the non-volatile reaction products of the main etching step;
  • the main etching step and the auxiliary etching step are performed alternately at least once until the pattern on the silicon wafer reaches a specified etching depth.
  • the specified etching depth is less than the target etching depth
  • the main etching step and the auxiliary etching step are performed alternately at least once, the main etching step is performed again, so that the pattern on the silicon wafer reaches the target etching depth.
  • the specified aspect ratio reached after each main etching step is completed is greater than or equal to N-1:1, and less than or equal to N:1, where N is the sequence number of the main etching step .
  • the specified aspect ratio is greater than or equal to 3:1 and less than or equal to 5:1.
  • the execution duration of the auxiliary etching step is greater than or equal to 2s and less than or equal to 3s.
  • the first mixed gas includes sulfur hexafluoride, and also includes one or more of oxygen, hydrogen bromide, silicon tetrafluoride and silicon tetrachloride;
  • the second mixed gas includes oxygen, One or more of hydrogen bromide, silicon tetrafluoride and silicon tetrachloride.
  • the first mixed gas The flow rate of each gas included in the mixed gas in the four gases is smaller than the flow rate of the same gas included in the second mixed gas in the four gases;
  • first mixed gas and the second mixed gas contain at least partially different gas types in the four gases of oxygen, hydrogen bromide, silicon tetrafluoride and silicon tetrachloride, then the first mixed gas will The total flow rate of the four gases is smaller than the total flow rate of the four gases in the second mixed gas.
  • the second mixed gas further includes sulfur hexafluoride.
  • the first mixed gas includes sulfur hexafluoride, oxygen, hydrogen bromide and silicon tetrafluoride, and the flow ratio of the sulfur hexafluoride, oxygen, hydrogen bromide and silicon tetrafluoride is ( 1.7-2.3):(1.3-1.7):(13-17):1.
  • the upper radio frequency power is greater than or equal to 300W and less than or equal to 2500W
  • the lower radio frequency power is greater than or equal to 15W and less than or equal to 800W
  • the chamber pressure is greater than or equal to 10mT and less than or equal to 90mT;
  • the upper radio frequency power is greater than or equal to 500W and less than or equal to 2000W
  • the lower radio frequency power is greater than or equal to 50W and less than or equal to 500W
  • the chamber pressure is greater than or equal to 10mT and less than or equal to 100mT.
  • the method before performing the first main etching step, the method further includes:
  • Pre-etching step using a pre-etching gas to perform a plasma etching process to etch the silicon wafer and remove the oxide layer on the surface of the silicon wafer.
  • the silicon wafer etching method provided by the present application includes alternately performing at least one main etching step and auxiliary etching step, the first mixed gas used in the main etching step can etch the silicon wafer, and the first mixed gas Both the gas and the second mixed gas used in the auxiliary etching step can react with silicon to generate non-volatile reaction products during the etching process.
  • the isotropy of silicon etching is ensured, and the anisotropic silicon etching is ensured.
  • the auxiliary etching step can generate more non-volatile reaction products at the same time, so as to enhance the protection of the sidewall of the pattern, so that the lateral etching in the next main etching step can be reduced,
  • the reduction of lateral etching can avoid the scallop effect caused by excessive lateral etching, so that the roughness of the sidewall of the pattern can be significantly improved, and a smoother sidewall morphology is obtained, which is more conducive to the subsequent gate oxide. Growth and filling of polysilicon; on the other hand, the occurrence of "under cut" at the top can be further suppressed.
  • Fig. 1 is the figure topography figure that exists scallop effect in the prior art
  • Fig. 2 is the groove topography diagram of the phenomenon of "eating edge" in the prior art
  • Fig. 3 is a figure topography diagram with a steep sidewall in the prior art
  • FIG. 4 is a schematic flowchart of a method for etching a silicon wafer provided by an embodiment of the present application
  • 5a-5e are trench topography diagrams obtained by using the silicon wafer etching method provided in the embodiments of the present application.
  • the reasons for the problems such as rough sidewall morphology and unevenness in the high aspect ratio etching process in the prior art are studied and analyzed.
  • the etched pattern due to the strong chemical activity of the etching gas, the etched pattern (groove or hole) exhibits isotropic etching, that is, the lateral corrosion is strong, resulting in a large lateral etching, although
  • the protective layer formed in the deposition step can protect the sidewall of the pattern, but the protective layer is not enough to inhibit the isotropic etching in the etching step. Therefore, multiple After cycling, a scallop effect (Scallop) as shown in Figure 1 may occur on the sidewall.
  • the etching depth reaches a certain level
  • the phenomenon of "under cut” as shown in Figure 2 will appear, which will cause the loss of critical dimensions.
  • the alternating process of etching step and deposition step can only obtain the morphology with steep sidewall as shown in Figure 3, while for TSV (through silicon via etching), IGBT (insulated gate bipolar transistor), etc.
  • the slightly inclined trench angle is more suitable for the generation of gate oxide and the increase of polysilicon.
  • this embodiment provides a silicon wafer etching method (hereinafter referred to as etching method), which can be applied to any plasma etching equipment, and can be applied to integrated circuits MEMS (Micro Electro Mechanical Systems), TSV and In the silicon deep hole and trench etching process in IGBT and other fields, it is especially suitable for etching high aspect ratio patterns on silicon wafers.
  • the silicon wafer is, for example, a silicon wafer, and the silicon can be single crystal silicon or polycrystalline silicon.
  • the pattern etched on the silicon wafer may be a groove with a rectangular cross-section, or a through hole or a groove with a circular cross-section, which is not specifically limited in this implementation.
  • the etching method of the silicon wafer provided in this embodiment may include:
  • the first mixed gas is used to perform a plasma etching process to etch the silicon wafer until the pattern on the silicon wafer reaches a specified aspect ratio; the first mixed gas is set to be able to etch the silicon etch, and react with silicon to form non-volatile reaction products;
  • the plasma etching process is performed using the second mixed gas;
  • the second mixed gas is set to be capable of reacting with silicon to generate non-volatile reaction products, and the generation rate of the non-volatile reaction products in the auxiliary etching step a rate of formation of the nonvolatile reaction product greater than that of the main etch step;
  • the main etching step S1 and the auxiliary etching step S2 are alternately performed at least once until the pattern on the silicon wafer reaches the specified etching depth.
  • the above-mentioned plasma etching process specifically includes: feeding the first mixed gas into the process chamber of the semiconductor process equipment, and turning on the upper radio frequency power supply and the lower radio frequency power supply, and the upper radio frequency power loaded by the upper radio frequency power supply to the upper electrode can excite the first mixed gas.
  • the gas forms a plasma
  • the lower RF power loaded by the lower RF power source to the susceptor in the process chamber can attract the plasma to move towards the silicon wafer.
  • inductively coupled plasma etching equipment can be used to perform the above-mentioned plasma etching process.
  • the specified aspect ratios achieved by the main etching steps S1 are different.
  • the specified aspect ratio to be achieved in each main etching step S1 can be estimated based on process parameters such as etching rate, etching time, gas flow and the like.
  • the so-called aspect ratio refers to the ratio of the depth to the width of the pattern (groove or hole).
  • the specified aspect ratio achieved after each main etching step S1 is completed is greater than or equal to N-1:1, and less than or equal to N:1, where N is the second of the main etching step. serial number.
  • the auxiliary etching step S2 when performing the first main etching step S1, you can switch to the auxiliary etching step S2 when the specified aspect ratio is 1:1, and the auxiliary etching step S2 is completed (for example, the etching duration is 2 After -3s,), switch to the second main etching step S1; when the second main etching step S1 is performed, when the specified aspect ratio is 2:1, switch to the auxiliary etching step S2, the auxiliary etching step S2.
  • the number of cycles of alternating between the main etching step S1 and the auxiliary etching step S2 can be specifically set according to the specified etching depth and morphology requirements. For the deep silicon etching process with a higher aspect ratio, it can be appropriately Increase the number of loops for smoother high aspect ratio graphics.
  • the above-mentioned non-volatile reaction products generated can be attached to the sidewalls and the top of the pattern to form a protective layer, which can inhibit the silicon etching in all directions Isotropic, ensuring that the silicon etching is anisotropic (that is, the etching in the depth direction is much larger than the width direction, or even only etching in the depth direction), and at the same time, the adhesion of these non-volatile reaction products to the sidewalls of the pattern can also increase
  • the etching selectivity ratio between the mask and the mask (such as a silicon dioxide mask) can prevent the mask from being etched too much, thereby avoiding the above-mentioned "edge-eating" phenomenon.
  • the auxiliary etching step S2 can be relatively In the main etching step S1, more non-volatile reaction products are generated at the same time to enhance the protection of the sidewall of the pattern, so that the lateral etching in the subsequent main etching step S1 can be reduced, that is, using
  • the auxiliary etching step S2 can generate a protective layer of sufficient thickness to reduce the lateral etching.
  • the reduction of the lateral etching can avoid the scalloping effect caused by the excessive lateral etching, so that the roughness of the sidewall of the pattern is obvious. Improvement, a smoother sidewall morphology is obtained, which is more conducive to the subsequent gate oxide growth and polysilicon filling; on the other hand, the generation of the top "under cut” phenomenon can be further suppressed.
  • the above-mentioned auxiliary etching step S2 is mainly used to generate more non-volatile reaction products to reduce lateral etching.
  • the above-mentioned second mixed gas may not contain The gas that can etch silicon, or can also contain a gas that can etch silicon, and make the etching rate of the auxiliary etching step S2 smaller than the etching rate of the main etching step S1, which is helpful for etching
  • a small amount of silicon is etched, and more non-volatile reaction products are generated at the same time, so that the generated amount is sufficient to completely cover the sidewalls of the pattern and improve the smoothness of the sidewalls.
  • this embodiment does not specifically limit the etching duration of each auxiliary etching step S2, and the etching duration of different auxiliary etching steps S2 may be the same or different.
  • the above-mentioned specified etching depth is smaller than the target etching depth, and the target etching depth is the etching depth of the finally obtained pattern.
  • the main etching step S1 and the auxiliary etching step S2 are performed alternately at least once, the main etching step S1 is performed again, so that the pattern on the silicon wafer reaches the target etching depth.
  • the main etching step S1 By performing the main etching step S1 at the end, less non-volatile reaction products can be formed on the sidewalls, which is more beneficial to obtain a pattern with a slightly inclined sidewall; moreover, due to the etching rate of the main etching step S1 higher, it can make the etching depth reach the target etching depth faster, so that the overall etching efficiency can be improved.
  • the above-mentioned specified etching depth may be a value smaller than and close to the target etching depth.
  • the above-mentioned specified etching depth can also be made equal to the target etching depth. In this case, it is not necessary to perform the main etching step S1 and the auxiliary etching step S2 alternately at least once, and then perform one more time. Main etching step S1.
  • the first mixed gas may include sulfur hexafluoride (SF 6 ), and may also include one of oxygen (O 2 ), hydrogen bromide (HBr), silicon tetrafluoride, and silicon tetrachloride (SiF 4 ). or more.
  • sulfur hexafluoride (SF 6 ) is used for etching silicon wafers, hydrogen bromide (HBr), silicon tetrafluoride (SiF 4 ), silicon tetrachloride (SiCl 4 ) and oxygen (O 2 ), etc.
  • the gas can react with silicon (which can include direct and indirect reactions) to form silicon dioxide, as well as reaction products (polymers) such as Si-Br-O, SiOFx , SiOClx , and the like.
  • silicon which can include direct and indirect reactions
  • reaction products polymers
  • Si-Br-O, SiOFx , SiOClx and the like.
  • an RF bias can be formed on the susceptor, which can attract the plasma to etch the silicon while attracting these non-volatile reactions
  • the product adheres to the sidewalls of the pattern (trenches or holes).
  • the main etching principle of the above-mentioned first mixed gas in the process of etching silicon (Si) is as follows:
  • SF 6 is used as the main etching gas, and its reaction process is as follows:
  • SiF 4 (SiCl 4 ) and oxygen plasma generate SiOFx (SiOCl X ) polymer, which can be attached to the sidewall and top of the pattern to reduce lateral etching.
  • SiOFx SiOCl X
  • HBr reacts with Si to generate Si-Br polymer, which can be attached to the sidewall of the pattern, and O 2 reacts with Si-Br polymer to generate SiO 2 and Si-Br-O polymer,
  • the polymer can further protect the sidewalls of the graphics.
  • the first mixed gas can also include helium (He), and helium can be used as a dilution gas to adjust the flow rate of other types of gases under the pressure condition of ensuring the process chamber, for example, the flow of other gases can be reduced by increasing the flow of helium.
  • helium can improve the uniformity of etching.
  • the first mixed gas may include four gases of sulfur hexafluoride, oxygen, hydrogen bromide and silicon tetrafluoride.
  • the flow ratio of sulfur fluoride, oxygen, hydrogen bromide and silicon tetrafluoride is (1.7-2.3):(1.3-1.7):(13-17):1. This setting can make various gases in the silicon During the etching process, the reaction can be fully reacted, and on the premise of ensuring the etching rate, the generation amount of non-volatile reaction products is increased, so as to effectively protect the sidewall of the pattern.
  • the flow ratio of sulfur hexafluoride, oxygen, hydrogen bromide and silicon tetrafluoride is 2:1.5:15:1, and this ratio has the best protection effect on the sidewall of the pattern.
  • the flow rates of sulfur hexafluoride and oxygen can both be greater than or equal to 10 sccm and less than or equal to 200 sccm, and hydrogen bromide can be used as an optional process adjustment gas, and its flow rate can be greater than or equal to 5 sccm and less than or equal to 1000 sccm.
  • the value range of the upper RF power (continuous wave) output by the upper RF power supply can be greater than or equal to 300W and less than or equal to 2500W;
  • the value range of the lower radio frequency power (continuous wave) can be greater than or equal to 15W and less than or equal to 800W.
  • the frequencies of the upper RF power supply and the lower RF power supply may both be 13.56 MHz.
  • the pressure in the process chamber (that is, the chamber pressure) can be in the range of 10mT or more and 90mT or less;
  • the temperature range of the base (for example, the electrostatic chuck) can be 100°C or less, preferably 20°C or more °C and less than or equal to 80 °C, the temperature of the process chamber may be greater than or equal to 10 °C and less than or equal to 40 °C.
  • both the main etching step S1 and the auxiliary etching step S2 can be performed under lower process pressure conditions, thereby reducing energy consumption and saving resources. It should be noted that the above parameters such as power, pressure and temperature are only a specific implementation of this embodiment, and this embodiment is not limited thereto.
  • the second mixed gas may also include one or more of oxygen, hydrogen bromide, silicon tetrafluoride and silicon tetrachloride.
  • the mixed gas may also contain an appropriate amount of sulfur hexafluoride for etching.
  • the flow rate of each gas included in the four gases in the first mixed gas is smaller than the flow rate of the same gas included in the four gases in the second mixed gas.
  • the flow rates of oxygen and/or hydrogen bromide and/or silicon tetrafluoride and/or silicon tetrachloride in the main etching gas may be smaller than those of oxygen and/or hydrogen bromide and/or respectively in the auxiliary etching gas Flow rate of silicon tetrafluoride and/or silicon tetrachloride.
  • the flow rate of oxygen in the main etching gas is smaller than the flow rate of oxygen in the auxiliary etching gas; or, the flow rate of hydrogen bromide in the main etching gas is smaller than the flow rate of hydrogen bromide in the auxiliary etching gas; or, The flow rate of silicon tetrafluoride in the main etching gas is smaller than the flow rate of silicon tetrafluoride in the auxiliary etching gas.
  • the gas species included in the first mixed gas and the second mixed gas in the four gases of oxygen, hydrogen bromide, silicon tetrafluoride and silicon tetrachloride are at least partially different (ie, partially different or completely different)
  • the total flow rate of the four gases in the first mixed gas is smaller than the total flow rate of the four gases in the second mixed gas.
  • This setting can ensure that the auxiliary etching step S2 can generate enough non-volatile reaction products, further reduce the lateral etching, and play a more effective protective effect on the sidewall and top of the etched pattern, thereby ensuring that the deeper and wider Better sidewall topography than during silicon etch.
  • the value range of the upper radio frequency power (continuous wave) output by the upper radio frequency power supply can be greater than or equal to 500W and less than or equal to 2000W; the lower radio frequency power supply
  • the value range of the output lower RF power (continuous wave) can be greater than or equal to 50W and less than or equal to 500W
  • the frequencies of the upper RF power supply and the lower RF power supply can both be 13.56MHz
  • the pressure in the process chamber that is, the chamber pressure
  • the temperature of the process chamber can be 10°C or more and 40°C or less.
  • the method before performing the first main etching step S1, the method further includes:
  • Pre-etching step use a pre-etching gas to perform a plasma etching process to etch the silicon wafer and remove the oxide layer on the surface of the silicon wafer.
  • the pre-etch gas may include one or more combinations of carbon tetrafluoride (CF 4 ) or other fluorine-containing hydrocarbon organic gases (CHxFy) to remove the oxide layer on the silicon surface.
  • CF 4 carbon tetrafluoride
  • CHxFy fluorine-containing hydrocarbon organic gases
  • the critical dimension of the silicon wafer is 0.3 ⁇ m
  • the target etching depth of the pattern is required to be 1.6 ⁇ m
  • the target aspect ratio is about 5:1.
  • the etching method can be divided into four stages:
  • the first stage includes the pre-etching step, the first main etching step S1 and the first auxiliary etching step S2, which are performed in sequence.
  • the aspect ratio is 1:1
  • the second stage includes the second main etching step S1 and the second auxiliary etching step S2 performed in sequence, wherein, when the second main etching step S1 is performed, the etching can be performed until the specified aspect ratio is 2 : 1, switch to the second auxiliary etching step S2; the etching duration of the second auxiliary etching step S2 is about 2-3s.
  • the third stage includes the third main etching step S1 and the third auxiliary etching step S2 performed in sequence, wherein, when the third main etching step S1 is performed, the etching can be performed until the specified aspect ratio is 3 : 1, switch to the third auxiliary etching step S2; the etching duration of the third auxiliary etching step S2 is about 2-3s.
  • the fourth stage includes the fourth main etching step S1, the fourth auxiliary etching step S2, and the fifth main etching step S1, which are performed in sequence.
  • the etching time of the fourth sub-etching step S2 is about 2-3s; perform the fifth main etching step S1 , until the specified aspect ratio is 5:1, so as to obtain an etched topography with smooth sidewalls and no undercut on the top as shown in Figure 5a-5e.
  • the method for etching a silicon wafer includes performing at least one main etching step and an auxiliary etching step alternately, and the first mixed gas used in the main etching step can etch the silicon wafer , and both the first mixed gas and the second mixed gas used in the auxiliary etching step can react with silicon to generate non-volatile reaction products during the etching process, and the non-volatile reaction products can be attached to the sidewall and top of the pattern.
  • a protective layer inhibiting the isotropy of silicon etching, ensuring that silicon etching is anisotropic, and at the same time, by making the generation rate of non-volatile reaction products in the auxiliary etching step greater than that in the main etching step
  • the generation rate of reaction products can make the auxiliary etching step generate more non-volatile reaction products at the same time than the main etching step, so as to enhance the protection of the sidewall of the pattern, so that the next main etching step can be reduced.
  • the reduction of lateral etching can avoid the scallop effect caused by excessive lateral etching, so that the roughness of the sidewall of the pattern can be significantly improved, and a smoother sidewall morphology can be obtained. It is more conducive to the subsequent gate oxide growth and polysilicon filling; on the other hand, it can further suppress the occurrence of the "under cut" phenomenon at the top.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two elements.

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Abstract

本申请提供一种硅片的刻蚀方法，包括：主刻蚀步骤：采用第一混合气体进行等离子体刻蚀工艺，以对硅片进行刻蚀，直至硅片上的图形达到指定深宽比；第一混合气体被设置为能够对硅进行刻蚀，并与硅反应生成不挥发性反应产物；辅刻蚀步骤：采用第二混合气体进行等离子体刻蚀工艺；第二混合气体被设置为能够与硅反应生成不挥发性反应产物，且辅刻蚀步骤的不挥发性反应产物的生成速率大于主刻蚀步骤的不挥发性反应产物的生成速率；交替执行主刻蚀步骤和辅刻蚀步骤至少一次，直至硅片上的图形达到指定刻蚀深度。应用本申请，可以解决现有技术中高深宽比的深硅刻蚀容易出现侧壁形貌粗糙、不平整的问题。

Description

硅片的刻蚀方法 技术领域
本发明涉及半导体工艺技术领域，具体地，涉及一种的硅片的刻蚀方法。
背景技术
等离子体刻蚀工艺被广泛应用于半导体制备过程中。等离子体的各向异性刻蚀特性使得集成电路元器件的尺寸得以进一步缩小，从而为集成电路后来几十年的持续繁荣打下了坚实基础。
而随着集成电路元器件尺寸的不断缩小，摩尔定律(集成电路上可以容纳的晶体管数目在大约每经过24个月便会增加一倍)的极限越来越近，人们试图在硅片(又称晶圆或硅晶圆)的垂直方向上制造更多的空间，从而放置更多的电子元器件。应用高深宽比刻蚀工艺可以制备更加精细的微纳结构，但是在现有的高深宽比刻蚀工艺如深槽硅的刻蚀中，刻蚀图形表现为各向同性刻蚀，即，横向刻蚀严重，例如在采用bosh工艺进行深硅刻蚀时，在图形(沟槽或通孔)侧壁会出现扇贝效应(Scallop)，导致侧壁形貌粗糙、不平整。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种硅片的刻蚀方法，解决现有技术中高深宽比的深硅刻蚀容易出现侧壁形貌粗糙、不平整的问题。
为实现本发明的目的而提供一种硅片的刻蚀方法，包括：
主刻蚀步骤：采用第一混合气体进行等离子体刻蚀工艺，以对所述硅片进行刻蚀，直至所述硅片上的图形达到指定深宽比；所述第一混合气体被设置为能够对硅进行刻蚀，并与硅反应生成不挥发性反应产物；
辅刻蚀步骤：采用第二混合气体进行等离子体刻蚀工艺；所述第二混合气体被设置为能够与硅反应生成不挥发性反应产物，且所述辅刻蚀步骤的所述不挥发性反应产物的生成速率大于所述主刻蚀步骤的所述不挥发性反应产物的生成速率；
交替执行所述主刻蚀步骤和所述辅刻蚀步骤至少一次，直至所述硅片上的图形达到指定刻蚀深度。
可选地，所述指定刻蚀深度小于目标刻蚀深度；
在交替执行所述主刻蚀步骤和所述辅刻蚀步骤至少一次之后，再执行一次所述主刻蚀步骤，以使所述硅片上的图形达到所述目标刻蚀深度。
可选地，每次所述主刻蚀步骤完成后达到的所述指定深宽比大于等于N-1：1，且小于等于N：1，其中，N为所述主刻蚀步骤的次序号。
可选地，所述指定深宽比大于等于3：1，且小于等于5：1。
可选地，所述辅刻蚀步骤的执行时长大于等于2s，且小于等于3s。
可选地，所述第一混合气体包括六氟化硫，还包括氧气、溴化氢、四氟化硅及四氯化硅中的一种或多种；所述第二混合气体包括氧气、溴化氢、四氟化硅及四氯化硅中的一种或多种。
可选的，若所述第一混合气体和第二混合气体在氧气、溴化氢、四氟化硅及四氯化硅这四种气体中所包括的气体种类完全相同，则所述第一混合气体在这四种气体中所包括的每种气体的流量均小于所述第二混合气体在这四种气体中所包括的同种气体的流量；
若所述第一混合气体和第二混合气体在氧气、溴化氢、四氟化硅及四氯化硅这四种气体中所包括的气体种类至少部分不同，则所述第一混合气体中这四种气体的总流量小于所述第二混合气体中这四种气体的总流量。
可选地，所述第二混合气体还包括六氟化硫。
可选地，所述第一混合气体包括六氟化硫、氧气、溴化氢及四氟化硅， 且所述六氟化硫、氧气、溴化氢及四氟化硅的流量比为(1.7-2.3):(1.3-1.7):(13-17):1。
可选地，当执行所述主刻蚀步骤时，上射频功率大于等于300W，且小于等于2500W，下射频功率大于等于15W，且小于等于800W，腔室压力大于等于10mT，且小于等于90mT；
当执行所述辅刻蚀步骤时，上射频功率大于等于500W，且小于等于2000W，下射频功率大于等于50W，且小于等于500W，腔室压力大于等于10mT，且小于等于100mT。
可选地，在执行第一次所述主刻蚀步骤之前，还包括：
预刻蚀步骤：采用预刻蚀气体进行等离子体刻蚀工艺，以对所述硅片进行刻蚀，去除所述硅片表面的氧化层。
本申请具有以下有益效果：
本申请提供的硅片的刻蚀方法，包括交替执行至少一次的主刻蚀步骤和辅刻蚀步骤，主刻蚀步骤采用的第一混合气体能够对硅片进行刻蚀，且该第一混合气体和辅刻蚀步骤采用的第二混合气体均能够在刻蚀过程中与硅反应生成不挥发性反应产物，该不挥发性反应产物可以附着在图形的侧壁和顶部，形成保护层，抑制了硅刻蚀的各向同性，保证了硅刻蚀为各向异性，同时通过使辅刻蚀步骤的不挥发性反应产物的生成速率大于主刻蚀步骤的不挥发性反应产物的生成速率，可以使辅刻蚀步骤相对于主刻蚀步骤在同一时间内生成更多的不挥发性反应产物，以增强对图形侧壁的保护，从而可以减少下一主刻蚀步骤中的横向刻蚀，横向刻蚀的减少一方面可以避免因横向刻蚀过大而产生扇贝效应，从而使得图形的侧壁的粗糙度得以明显改善，获得了更为平滑的侧壁形貌，更有利于后面栅氧生长和多晶硅的填充；另一方面可以进一步抑制顶部“吃边”现象(under cut)的产生。
附图说明
图1为现有技术中存在扇贝效应的图形形貌图；
图2为现有技术中存在“吃边”现象的沟槽形貌图；
图3为现有技术中具有陡直侧壁的图形形貌图；
图4为本申请实施例提供的硅片的刻蚀方法的流程示意图；
图5a-图5e为采用本申请实施例提供的硅片的刻蚀方法获得的沟槽形貌图。
具体实施方式
下面详细描述本申请，本申请的实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本申请的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”和“该”也可包括复数形式。应该理解，当我们称元件被“连接”或“耦接”到另一元件时，它可以直接连接或耦接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
下面结合附图以具体的实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。
本实施例对现有技术中高深宽比刻蚀工艺过程中出现侧壁形貌粗糙、不平整等问题的原因进行了研究分析，发现：当采用刻蚀步和沉积步交替执行的方法进行高深宽比刻蚀工艺时，由于刻蚀气体的化学活性较强，刻蚀的图形(沟槽或孔)表现为各向同性刻蚀，即横向腐蚀强烈，导致横向刻蚀较大，虽然在刻蚀步和沉积步交替执行的过程中，在沉积步形成的保护层可以对图形的侧壁进行保护，但是，该保护层不足以抑制刻蚀步中的各向同性刻蚀，因此，多个循环后，可能会导致侧壁出现如图1所示的扇贝效应(Scallop)。另外，当刻蚀深度达到一定程度时，图形顶部在长期受到刻蚀气体腐蚀的情况下，还会出现如图2所示的“吃边”现象(under cut)，继而造成关键尺寸的损失。并且该刻蚀步和沉积步交替的工艺只能得到如图3所示的具有陡直侧壁的形貌，而对于TSV(硅通孔刻蚀)、IGBT(绝缘栅双极形晶体管)等功率器件来说，略倾斜的沟槽角度更适用于栅氧的生成及多晶硅的增充。
基于上述分析研究，本实施例提供一种硅片的刻蚀方法(下述简称刻蚀方法)，可适用于任意等离子体刻蚀设备，可应用于集成电路MEMS(微机电系统)、TSV及IGBT等领域的硅深孔及沟槽刻蚀工艺中，尤其适用于在硅片上刻蚀获得高深宽比的图形。其中，硅片例如为硅的晶圆，硅可以是单晶硅，也可以是多晶硅。在硅片上刻蚀的图形可以是截面为矩形的沟槽，也可以是截面为圆形的通孔或凹槽，本实施对此不作具体限定。
如图4所示，本实施例提供的硅片的刻蚀方法可以包括：
主刻蚀步骤S1，采用第一混合气体进行等离子体刻蚀工艺，以对硅片进行刻蚀，直至硅片上的图形达到指定深宽比；第一混合气体被设置为能够对硅进行刻蚀，并与硅反应生成不挥发性反应产物；
辅刻蚀步骤S2，采用第二混合气体进行等离子体刻蚀工艺；第二混合气 体被设置为能够与硅反应生成不挥发性反应产物，且辅刻蚀步骤的不挥发性反应产物的生成速率大于主刻蚀步骤的所述不挥发性反应产物的生成速率；
交替执行主刻蚀步骤S1和辅刻蚀步骤S2至少一次，直至硅片上的图形达到指定刻蚀深度。
上述等离子体刻蚀工艺具体包括：向半导体工艺设备的工艺腔室内通入第一混合气体，并开启上射频电源和下射频电源，由上射频电源向上电极加载的上射频功率可以激发第一混合气体形成等离子体，由下射频电源向工艺腔室中的基座加载的下射频功率可以吸引等离子体朝向硅片移动。在一些可选的实施例中，可采用电感耦合等离子刻蚀设备进行上述等离子体刻蚀工艺。
需要说明的是，随着主刻蚀步骤S1的次数的增加，图形的刻蚀深度也会不断增大，因此，各次主刻蚀步骤S1所达到的指定深宽比是不同的，在实际应用中，各次主刻蚀步骤S1所要达到的指定深宽比，可以基于诸如刻蚀速率、刻蚀时长、气体流量等的工艺参数预估所得。
所谓深宽比，是指图形(沟槽或孔)的深度与宽度的比值。
于本申请另一具体实施方式中，每次主刻蚀步骤S1完成后达到的指定深宽比大于等于N-1：1，且小于等于N：1，其中，N为主刻蚀步骤的次序号。可选的，指定深宽比大于等于3：1，且小于等于5：1。
例如，进行第1次主刻蚀步骤S1时，可以在刻蚀至指定深宽比为1：1时，切换至辅刻蚀步骤S2，该辅刻蚀步骤S2完成(刻蚀时长例如为2-3s，)后切换至第2次主刻蚀步骤S1；进行第2次主刻蚀步骤S1时，可以在指定深宽比为2：1时，再切换至辅刻蚀步骤S2，该辅刻蚀步骤S2完成后切换至第3次主刻蚀步骤S1，进行第3次主刻蚀步骤S1时，可以在指定深宽比为3：1时，再切换至辅刻蚀步骤S2；如此交替执行主刻蚀步骤S1和辅刻蚀步骤S2，直至硅片上的图形达到指定刻蚀深度，然后再执行最后一次主刻蚀步骤S1，最后的主刻蚀步骤S1刻蚀完成后，获得具有目标刻蚀深度的图形。
需要说明的是，主刻蚀步骤S1和辅刻蚀步骤S2交替的循环次数具体可根据指定刻蚀深度和形貌要求等进行设定，对于较高深宽比的深硅刻蚀工艺，可以适当增加循环次数，以能够获得更为平滑的高深宽比的图形。
在进行主刻蚀步骤S1和辅刻蚀步骤S2的过程中，生成的上述不挥发性反应产物可以附着在图形的侧壁和顶部，形成保护层，该保护层能够抑制硅刻蚀的各向同性，保证硅刻蚀为各向异性(即深度方向的刻蚀远大于宽度方向，甚至只进行深度方向的刻蚀)，同时，这些不挥发性反应产物附着在图形的侧壁上还可以增加其与掩膜(例如二氧化硅掩膜)的刻蚀选择比，从而避免掩膜被过多的刻蚀，进而可以避免出现上述的“吃边”现象。
通过在进行主刻蚀步骤S1和辅刻蚀步骤S2的过程中均与硅反应生成不挥发性反应产物，可以保证主刻蚀步骤S1和辅刻蚀步骤S2进行的硅刻蚀均为各向异性，从而可以减小横向刻蚀；同时，通过使辅刻蚀步骤的不挥发性反应产物的生成速率大于主刻蚀步骤的不挥发性反应产物的生成速率，可以使辅刻蚀步骤S2相对于主刻蚀步骤S1在同一时间内生成更多的不挥发性反应产物，以增强对图形侧壁的保护，从而可以减少后续的主刻蚀步骤S1中的横向刻蚀，也就是说，利用辅助刻蚀步骤S2可以生成足够厚度的保护层，以减少横向刻蚀，横向刻蚀的减少一方面可以避免因横向刻蚀过大而产生扇贝效应，从而使得图形的侧壁的粗糙度得以明显改善，获得了更为平滑的侧壁形貌，更有利于后面栅氧生长和多晶硅的填充；另一方面，可以进一步抑制顶部“吃边”现象(under cut)的产生。
需要说明的是，上述辅刻蚀步骤S2主要用于生成更多的不挥发性反应产物，以减小横向刻蚀，在这种情况下，可选的，上述第二混合气体中可以不包含能够对硅进行刻蚀的气体，或者，也可以包含能够对硅进行刻蚀的气体，并使辅刻蚀步骤S2的刻蚀速率小于主刻蚀步骤S1的刻蚀速率，这样有助于刻蚀少量的硅，同时生成更多的不挥发性反应产物，使之生成量足以完 全覆盖图形侧壁，提高侧壁的平滑度。
还需要说明的是，本实施例对各次辅刻蚀步骤S2的刻蚀时长也不作具体限定，且不同次的辅刻蚀步骤S2的刻蚀时长可以相同也可以不同。
于本申请另一具体实施方式中，上述指定刻蚀深度小于目标刻蚀深度，该目标刻蚀深度即为最终获得的图形的刻蚀深度。在这种情况下，在交替执行主刻蚀步骤S1和辅刻蚀步骤S2至少一次之后，再执行一次主刻蚀步骤S1，以使硅片上的图形达到目标刻蚀深度。通过在最后执行一次主刻蚀步骤S1，可以使侧壁上形成有较少的不挥发性反应产物，更有利于得到侧壁稍微倾斜的图形；而且，由于主刻蚀步骤S1的刻蚀速率较高，其可以更快地使刻蚀深度达到目标刻蚀深度，从而可以提高整体刻蚀效率。
上述指定刻蚀深度可以是小于并接近目标刻蚀深度的数值。当然，在实际应用中，也可以使上述指定刻蚀深度等于目标刻蚀深度，在这种情况下，则无需在交替执行主刻蚀步骤S1和辅刻蚀步骤S2至少一次之后，再执行一次主刻蚀步骤S1。
于本申请一具体实施方式中，上述第一混合气体和第二混合气体各自的种类有多种。例如，第一混合气体可以包括六氟化硫(SF 6)，还可以包括氧气(O 2)、溴化氢(HBr)、四氟化硅及四氯化硅(SiF 4)中的一种或多种。其中，六氟化硫(SF 6)用于对硅片进行刻蚀，溴化氢(HBr)、四氟化硅(SiF 4)、四氯化硅(SiCl 4)与氧气(O 2)等气体可以与硅反应(可包括直接反应和间接反应)形成二氧化硅，以及Si-Br-O、SiOF X、SiOCl X等反应产物(聚合物)。在进行刻蚀工艺时，借助于加载至基座上的下射频功率，可以在基座上形成射频偏压，该射频偏压可以吸引等离子体对硅进行刻蚀，同时吸引这些不挥发性反应产物附着在图形(沟槽或孔)的侧壁上。
上述第一混合气体在刻蚀硅(Si)的过程中的主要刻蚀原理如下：
(1)SF 6作为主要刻蚀气体，其反应过程如下：
SF 6↑—→SxFy↑+F↑，Si+4F—→Si F4↑
(2)O 2与Si生成SiO 2，SiO 2用于对侧壁进行保护。
(3)SiF 4(SiCl 4)与氧等离子体生成SiOFx(SiOCl X)聚合物，该聚合物可以附着在图形的侧壁及顶部，以减小横向刻蚀，具体反应过程如下：
SiFx+O—>SiOFx
(4)HBr与Si反应，生成Si-Br聚合物，该聚合物可以附着在图形的侧壁，并且，O 2与Si-Br聚合物反应，生成SiO 2和Si-Br-O聚合物，该聚合物可以进一步对图形的侧壁进行保护。
于本申请一可选的实施方式中，第一混合气体中还可以包括氦气(He)，氦气可作为稀释气体，用以在保证工艺腔室的压力条件下调节其它种类气体的流量，例如，可以通过增加氦气的流量，来减小其他种类气体的流量。此外，氦气作为良好的导热气体，可以提高刻蚀的均匀性。
于本申请一具体实施方式中，第一混合气体可以包括六氟化硫、氧气、溴化氢及四氟化硅四种气体，可以根据上述反应原理，设计各种气体的流量，例如，六氟化硫、氧气、溴化氢及四氟化硅的流量比为(1.7-2.3):(1.3-1.7):(13-17):1，这样设置，可以使各种气体在对硅的刻蚀过程中能够充分反应，并在保证刻蚀速率的前提下，增加不挥发性反应产物的生成量，以对图形的侧壁起到有效的保护作用。优选地，六氟化硫、氧气、溴化氢及四氟化硅的流量比为2:1.5:15:1，该比例对图形的侧壁的保护作用最佳。进一步地，其中，六氟化硫和氧气的流量均可以大于等于10sccm，且小于等于200sccm，溴化氢可作为可选工艺调节气体，其流量可以大于等于5sccm，且小于等于1000sccm。
于本申请另一具体实施方式中，当执行主刻蚀步骤S1时，上射频电源输出的上射频功率(连续波)的取值范围可以为大于等于300W，且小于等于2500W；下射频电源输出的下射频功率(连续波)的取值范围可以为大于 等于15W，且小于等于800W。可选的，上射频电源和下射频电源的频率可以均为13.56MHz。工艺腔室内的压力(即，腔室压力)的取值范围可以为大于等于10mT，且小于等于90mT；基座(例如静电卡盘)的温度范围可以为小于等于100℃，优选为大于等于20℃，且小于等于80℃，工艺腔室的温度可以为大于等于10℃，且小于等于40℃。
本实施例采用的刻蚀方法，主刻蚀步骤S1及辅刻蚀步骤S2均可以在较低的工艺压力条件下进行，从而可降低能耗，节省资源。需要说明的是，上述的功率、压强及温度等参数只是本实施例的一种具体实施方式，本实施例并不以此为限。
与第一混合气体的设计类似，第二混合气体也可以包括氧气、溴化氢、四氟化硅及四氯化硅中的一种或多种，在此基础上，可选的，第二混合气体也可以含有适量的六氟化硫，用于刻蚀。
于本申请一可选的实施方式中，若第一混合气体和第二混合气体在氧气、溴化氢、四氟化硅及四氯化硅这四种气体中所包括的气体种类完全相同，则第一混合气体在这四种气体中所包括的每种气体的流量均小于第二混合气体在这四种气体中所包括的同种气体的流量。即，主刻蚀气体中的氧气和/或溴化氢和/或四氟化硅和/或四氯化硅的流量可分别小于辅刻蚀气体中的氧气和/或溴化氢和/或四氟化硅和/或四氯化硅的流量。例如，主刻蚀气体中的氧气的流量小于辅刻蚀气体中的氧气的流量；或者，主刻蚀气体中的溴化氢的流量小于辅刻蚀气体中的溴化氢的流量；或者，主刻蚀气体中的四氟化硅的流量小于辅刻蚀气体中的四氟化硅的流量。若第一混合气体和第二混合气体在氧气、溴化氢、四氟化硅及四氯化硅这四种气体中所包括的气体种类至少部分不同(即，部分不同或者完全不同)，则第一混合气体中这四种气体的总流量小于第二混合气体中这四种气体的总流量。这样设置，可以保证辅刻蚀步骤S2能够产生足够多的不挥发性反应产物，进一步减少横向刻蚀，对 刻蚀图形的侧壁及顶部起到更有效的保护作用，从而保证在更深深宽比硅刻蚀过程中获得更好的侧壁形貌。
于本申请另一具体实施方式中，当执行辅刻蚀步骤S2时，上射频电源输出的上射频功率(连续波)的取值范围可以为大于等于500W，且小于等于2000W，；下射频电源输出的下射频功率(连续波)的取值范围可以为大于等于50W，且小于等于500W，上射频电源和下射频电源的频率可以均为13.56MHz，工艺腔室内的压力(即，腔室压力)的取值范围为大于等于10mT，且小于等于100mT，工艺腔室的温度可以为大于等于10℃，且小于等于40℃。需要说明的是，这里的功率、压强及温度等参数只是本实施例的一种具体实施方式，本实施例并不以此为限。
于本申请一可选的实施方式中，在执行第一次主刻蚀步骤S1之前，还包括：
预刻蚀步骤：采用预刻蚀气体进行等离子体刻蚀工艺，以对硅片进行刻蚀，去除硅片表面的氧化层。
预刻蚀气体可以包括四氟化碳(CF 4)或其他含氟的烃类有机气体(CHxFy)的一种或多种组合，以去除硅表面的氧化层。
于本申请一典型实施例中，硅片的关键尺寸为0.3μm,图形的目标刻蚀深度要求1.6μm，目标深宽比约5：1。参照下述表1，该刻蚀方法可分为四个阶段：
第一阶段，包括依次进行的预刻蚀步骤、第1次主刻蚀步骤S1和第1次辅刻蚀步骤S2，其中，进行第1次主刻蚀步骤S1时，可以在刻蚀至指定深宽比为1：1时，切换至第1次辅刻蚀步骤S2；第1次辅刻蚀步骤S2的刻蚀时长大约2-3s。
第二阶段，包括依次进行的第2次主刻蚀步骤S1和第2次辅刻蚀步骤S2，其中，进行第2次主刻蚀步骤S1时，可以在刻蚀至指定深宽比为2：1 时，切换至第2次辅刻蚀步骤S2；第2次辅刻蚀步骤S2的刻蚀时长大约2-3s。
第三阶段，包括依次进行的第3次主刻蚀步骤S1和第3次辅刻蚀步骤S2，其中，进行第3次主刻蚀步骤S1时，可以在刻蚀至指定深宽比为3：1时，切换至第3次辅刻蚀步骤S2；第3次辅刻蚀步骤S2的刻蚀时长大约2-3s。
第四阶段，包括依次进行的第4次主刻蚀步骤S1、第4次辅刻蚀步骤S2和第5次主刻蚀步骤S1，其中，进行第4次主刻蚀步骤S1时，可以在刻蚀至指定深宽比为4：1时，切换至第4次辅刻蚀步骤S2；第4次辅刻蚀步骤S2的刻蚀时长大约2-3s；进行第5次主刻蚀步骤S1，直至刻蚀至指定深宽比为5：1，从而获得具有如图5a-图5e所示的侧壁光滑，顶部没有under cut的刻蚀形貌图。
表1 本实施例采用的刻蚀方法的各个阶段与参数的对照表
Figure PCTCN2021130553-appb-000001
Figure PCTCN2021130553-appb-000002
综上所述，本实施例提供的硅片的刻蚀方法，包括交替执行至少一次的主刻蚀步骤和辅刻蚀步骤，主刻蚀步骤采用的第一混合气体能够对硅片进行刻蚀，且该第一混合气体和辅刻蚀步骤采用的第二混合气体均能够在刻蚀过程中与硅反应生成不挥发性反应产物，该不挥发性反应产物可以附着在图形的侧壁和顶部，形成保护层，抑制了硅刻蚀的各向同性，保证了硅刻蚀为各向异性，同时通过使辅刻蚀步骤的不挥发性反应产物的生成速率大于主刻蚀步骤的不挥发性反应产物的生成速率，可以使辅刻蚀步骤相对于主刻蚀步骤在同一时间内生成更多的不挥发性反应产物，以增强对图形侧壁的保护，从而可以减少下一主刻蚀步骤中的横向刻蚀，横向刻蚀的减少一方面可以避免因横向刻蚀过大而产生扇贝效应，从而使得图形的侧壁的粗糙度得以明显改善，获得了更为平滑的侧壁形貌，更有利于后面栅氧生长和多晶硅的填充；另一方面可以进一步抑制顶部“吃边”现象(under cut)的产生。
可以理解的是，以上实施方式仅仅是为了说明本申请的原理而采用的示例性实施方式，然而本申请并不局限于此。对于本领域内的普通技术人员而言，在不脱离本申请的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本申请的保护范围。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描 述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (11)

  1. 一种硅片的刻蚀方法，其特征在于，包括：
    主刻蚀步骤：采用第一混合气体进行等离子体刻蚀工艺，以对所述硅片进行刻蚀，直至所述硅片上的图形达到指定深宽比；所述第一混合气体被设置为能够对硅进行刻蚀，并与硅反应生成不挥发性反应产物；
    辅刻蚀步骤：采用第二混合气体进行等离子体刻蚀工艺；所述第二混合气体被设置为能够与硅反应生成不挥发性反应产物，且所述辅刻蚀步骤的所述不挥发性反应产物的生成速率大于所述主刻蚀步骤的所述不挥发性反应产物的生成速率；
    交替执行所述主刻蚀步骤和所述辅刻蚀步骤至少一次，直至所述硅片上的图形达到指定刻蚀深度。
  2. 根据权利要求1所述的刻蚀方法，其特征在于，所述指定刻蚀深度小于目标刻蚀深度；
    在交替执行所述主刻蚀步骤和所述辅刻蚀步骤至少一次之后，再执行一次所述主刻蚀步骤，以使所述硅片上的图形达到所述目标刻蚀深度。
  3. 根据权利要求1或2所述的刻蚀方法，其特征在于，每次所述主刻蚀步骤完成后达到的所述指定深宽比大于等于N-1：1，且小于等于N：1，其中，N为所述主刻蚀步骤的次序号。
  4. 根据权利要求3所述的刻蚀方法，其特征在于，所述指定深宽比大于等于3：1，且小于等于5：1。
  5. 根据权利要求1或2所述的刻蚀方法，其特征在于，所述辅刻蚀步骤的执行时长大于等于2s，且小于等于3s。
  6. 根据权利要求1或2所述的刻蚀方法，其特征在于，所述第一混合气体包括六氟化硫，还包括氧气、溴化氢、四氟化硅及四氯化硅中的一种或多种；所述第二混合气体包括氧气、溴化氢、四氟化硅及四氯化硅中的一种或多种。
  7. 根据权利要求6所述的刻蚀方法，其特征在于，若所述第一混合气体和第二混合气体在氧气、溴化氢、四氟化硅及四氯化硅这四种气体中所包括的气体种类完全相同，则所述第一混合气体在这四种气体中所包括的每种气体的流量均小于所述第二混合气体在这四种气体中所包括的同种气体的流量；
    若所述第一混合气体和第二混合气体在氧气、溴化氢、四氟化硅及四氯化硅这四种气体中所包括的气体种类至少部分不同，则所述第一混合气体中这四种气体的总流量小于所述第二混合气体中这四种气体的总流量。
  8. 根据权利要求6所述的刻蚀方法，其特征在于，所述第二混合气体还包括六氟化硫。
  9. 根据权利要求6所述的刻蚀方法，其特征在于，所述第一混合气体包括六氟化硫、氧气、溴化氢及四氟化硅，且所述六氟化硫、氧气、溴化氢及四氟化硅的流量比为(1.7-2.3):(1.3-1.7):(13-17):1。
  10. 根据权利要求1、2或6所述的刻蚀方法，其特征在于，当执行所述主刻蚀步骤时，上射频功率大于等于300W，且小于等于2500W，下射频功率大于等于15W，且小于等于800W，腔室压力大于等于10mT，且小于等于90mT；
    当执行所述辅刻蚀步骤时，上射频功率大于等于500W，且小于等于 2000W，下射频功率大于等于50W，且小于等于500W，腔室压力大于等于10mT，且小于等于100mT。
  11. 根据权利要求1所述的刻蚀方法，其特征在于，在执行第一次所述主刻蚀步骤之前，还包括：
    预刻蚀步骤：采用预刻蚀气体进行等离子体刻蚀工艺，以对所述硅片进行刻蚀，去除所述硅片表面的氧化层。
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