WO2022095297A1 - 判决反馈均衡器以及数据的采集与校正方法 - Google Patents

判决反馈均衡器以及数据的采集与校正方法 Download PDF

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Publication number
WO2022095297A1
WO2022095297A1 PCT/CN2021/075309 CN2021075309W WO2022095297A1 WO 2022095297 A1 WO2022095297 A1 WO 2022095297A1 CN 2021075309 W CN2021075309 W CN 2021075309W WO 2022095297 A1 WO2022095297 A1 WO 2022095297A1
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Prior art keywords
sampling
circuit
differential
data
decision
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PCT/CN2021/075309
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English (en)
French (fr)
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靳佳伟
宋飞
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硅谷数模(苏州)半导体有限公司
硅谷数模国际有限公司
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Priority to JP2021573783A priority Critical patent/JP7333419B2/ja
Priority to KR1020217040538A priority patent/KR102579662B1/ko
Priority to US17/312,006 priority patent/US20240015053A1/en
Publication of WO2022095297A1 publication Critical patent/WO2022095297A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03254—Operation with other circuitry for removing intersymbol interference
    • H04L25/03267—Operation with other circuitry for removing intersymbol interference with decision feedback equalisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/068—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate

Definitions

  • the technical field of data transmission of the present application in particular, relates to a decision feedback equalizer and a method for collecting and correcting data.
  • intersymbol interference is caused due to the non-ideal characteristics of the channel, which affects the signal integrity.
  • a full-rate decision feedback equalizer is used to eliminate intersymbol interference.
  • the full-rate decision feedback equalizer uses the already decided data to help eliminate the ISI existing in the current decision data and restore the correct code pattern.
  • the full-rate equalizer has very strict requirements on the timing design of the circuit, resulting in increased design cost and difficulty.
  • Half-rate equalizers mean that the sampling frequency is half of the data stream frequency, which makes the circuit timing design more lenient. , however, since the half-rate decision feedback equalizer first collects and subtracts the influence value of the previous signal on the latter signal in both odd and even paths, and then determines which acquisition value to retain, four samplers need to be used for sampling, As a result, the power consumption and area of the half-rate decision feedback equalizer will increase.
  • the half-rate decision feedback equalizer adopts multiple collectors, which leads to the problems of large power consumption and large size of the circuit, and no effective solution has been proposed yet.
  • the present application provides a decision feedback equalizer and a method for collecting and correcting data, so as to solve the problems in the related art that the half-rate decision feedback equalizer adopts multiple collectors, resulting in high power consumption and large size of the circuit .
  • a decision feedback equalizer includes: a first decision sampling circuit; a second decision sampling circuit, wherein the first decision sampling circuit and the second decision sampling circuit are sampled by opposite sampling clock signals; wherein, the input end of the first decision sampling circuit receiving sampling data, the input end of the first decision sampling circuit is also connected to the output end of the second decision sampling circuit, and is configured to receive the first sampling result output by the second decision sampling circuit in the last sampling period, so as to pass the first sampling
  • the result determines the first correction mode of the sampled data, and corrects the sampled data through the first correction mode; the input end of the second decision and sampling circuit receives the sampled data, and the input end of the second decision and sampling circuit is also connected with the first decision and sampling circuit.
  • the output end is connected, and is configured to receive the second sampling result output by the first decision sampling circuit in the last sampling period, so as to determine the second correction mode of the sampled data through the second sampling result, and to perform the sampling process on the sampled data through the second correction method. Correction.
  • the first correction method is one of the following: superimposing the sampled data and the first sampled correction data, or subtracting the sampled data from the first sampled correction data
  • the second correction method is one of the following: adding the sampled data to The second sampling correction data is superimposed, or the sampling data and the second sampling correction data are subtracted.
  • the first decision sampling circuit or the second decision sampling circuit includes: a selection sampling circuit, an input end of the selection sampling circuit to receive sampling data, and a sampling result collected in a previous sampling period, and the sampling result is determined according to the sampling result.
  • a data correction method correcting and amplifying the sampling data, and outputting the first sampling data;
  • an amplifying and comparing circuit the input end of the amplifying and comparing circuit is connected to the output end of the selection sampling circuit, and is configured to amplify the first sampling data, And make positive and negative judgments according to the amplification results, and output the judgment results;
  • the holding circuit the input terminal of the holding circuit is connected to the output terminal of the amplifying and comparing circuit, and is configured to hold the judgment results, and the maintained judgment results are determined as the current sampling Period of sampling results.
  • the selection sampling circuit includes: a first differential amplifying circuit; a second differential amplifying circuit, wherein the first differential amplifying circuit and the second differential amplifying circuit are respectively connected to the same sampling clock signal; wherein the first differential amplifying circuit
  • the first input terminal of the first differential amplifier receives the sampling results collected in the previous sampling period, and determines whether to turn on or off the first differential amplifier circuit according to the sampling results.
  • the two differential input terminals of the first differential amplifier circuit receive the sampling data and the sampling Correct the result of data superposition, amplify the superimposed result, and output two first differential output signals; the first input terminal of the second differential amplifier circuit receives the sampling result collected in the previous sampling period, and passes the sampling result through the sampling result.
  • the second differential amplifier circuit is turned on or off.
  • the two differential input terminals of the second differential amplifier circuit respectively receive the result of subtracting the sampled data and the sampled correction data, and amplify the subtracted result, and output two first Two differential output signals.
  • the amplification and comparison circuit includes: a third differential amplification circuit, connected to the sampling clock signal, and configured to amplify the two first differential output signals or the two second differential output signals to obtain two third differential outputs signal; a comparison circuit, connected to the sampling clock signal, is configured to receive two third differential output signals, and compare the two third differential output signals to obtain a first decision signal and a second decision signal.
  • the third differential amplifier circuit includes two groups of differential input terminals, wherein the first group of differential input terminals are respectively connected to the two differential output terminals of the first differential amplifier circuit, and are configured to disconnect the second differential amplifier circuit, and the second group of differential input terminals are turned on, amplify the two first differential output signals and output two third differential output signals; the second group of differential input terminals are respectively connected with the second differential amplifier circuit.
  • the two differential output terminals are connected and configured to amplify the two second differential output signals when the first differential amplifying circuit is disconnected and the first group of differential input terminals are turned on to obtain two third differential outputs Signal.
  • the selection sampling circuit further includes: a first function circuit; a second function circuit, wherein the input terminals of the first function circuit and the second function circuit are respectively connected to the sampling results in the previous cycle; wherein the first function circuit
  • the output terminal of the circuit is connected to the first group of differential input terminals of the third differential amplifier circuit, and is configured to judge whether the first group of differential input terminals is turned on through the sampling result: the output terminal of the second functional circuit is connected to the output terminal of the third differential amplifier circuit.
  • the second group of differential input terminals is connected, and is configured to determine whether the second group of differential input terminals is turned on through the sampling result.
  • the comparison circuit includes: a first inverter; a second inverter, wherein the first inverter and the second inverter are respectively connected to the sampling clock signal; the input end of the first inverter and the first inverter The output terminals of the two inverters are connected, the input terminal of the second inverter is connected to the output terminal of the first inverter, and the input terminal of the first inverter and the input terminal of the second inverter respectively receive two second inverters.
  • Three differential output signals, the output end of the first inverter and the output end of the second inverter respectively output the first decision signal and the second decision signal.
  • the holding circuit is a latch.
  • Another embodiment of the present invention also provides a data collection and correction method, which is applied to any of the above decision feedback equalizers.
  • the method includes: acquiring sampling results obtained by collecting sampling data in a previous sampling period, and determining a correction method of the sampling data according to the sampling results, wherein the correction method is to superimpose the sampling data and the sampling correction data, or to combine the sampling data with the sampling data.
  • the sampling correction data is subtracted; the sampling data is corrected by the correction method, and the corrected data is obtained; the corrected data is collected, and the collection result is output.
  • a first decision sampling circuit through: a first decision sampling circuit; a second decision sampling circuit, wherein the first decision sampling circuit and the second decision sampling circuit are sampled by opposite sampling clock signals; wherein, the input end of the first decision sampling circuit receiving sampling data, the input end of the first decision sampling circuit is also connected to the output end of the second decision sampling circuit, and is configured to receive the first sampling result output by the second decision sampling circuit in the last sampling period, so as to pass the first sampling
  • the result determines the first correction mode of the sampled data, and corrects the sampled data through the first correction mode; the input end of the second decision and sampling circuit receives the sampled data, and the input end of the second decision and sampling circuit is also connected with the first decision and sampling circuit.
  • the output end is connected, and is configured to receive the second sampling result output by the first decision sampling circuit in the last sampling period, so as to determine the second correction mode of the sampled data through the second sampling result, and to perform the sampling process on the sampled data through the second correction method.
  • the correction solves the problems of high power consumption and large size of the circuit caused by the use of multiple collectors in the half-rate decision feedback equalizer in the related art.
  • the first decision sampling circuit and the second decision sampling circuit first determine the correction method of the sampled data, and then correct and collect the sampled data, thereby reducing the use of the collector, thereby achieving the effects of reducing circuit power consumption and circuit size.
  • FIG. 1 is a schematic diagram of a decision feedback equalizer provided according to the related art
  • Fig. 2 is the sampling timing diagram of the decision feedback equalizer provided according to the related art
  • FIG. 3 is a schematic diagram of a decision feedback equalizer provided according to Embodiment 1 of the present application.
  • FIG. 4 is a schematic diagram of a selection sampling circuit in a decision feedback equalizer provided according to Embodiment 1 of the present application;
  • FIG. 5 is a schematic diagram of a third differential amplifier circuit in a decision feedback equalizer provided according to Embodiment 1 of the present application;
  • FIG. 6 is a schematic diagram of a comparison circuit in a decision feedback equalizer provided according to Embodiment 1 of the present application;
  • FIG. 7 is a schematic diagram of a hold circuit in a decision feedback equalizer provided according to Embodiment 1 of the present application;
  • FIG. 8 is a flowchart of a method for collecting and calibrating data according to Embodiment 2 of the present application.
  • ISI Inter-Symbol Interference
  • the full English name is Inter-Symbol Interference, which refers to the correlated interference between high-speed propagation signals.
  • Sampler SA for short, full English name Sampler Amplifier.
  • the data is sampled by the sampler (SA) of the odd (odd) and even (even) paths, where CKB is the inverse phase of CK, and the odd data path obtains the data odd , the even data path gets the data even.
  • SA sampler
  • CKB the inverse phase of CK
  • Figure 2 is the sampling timing diagram of Figure 1. As shown in Figure 2, in order to eliminate the influence of data1 on data2, before the even data channel samples data2, the odd data channel is used to sample the result of data1 to determine whether data2 is to add an H1 or a Subtract one H1 (H1 represents the magnitude of the voltage to remove the influence of ISI).
  • the sampling result of data1 is 1, it means that its influence on data2 is positive, which will cause the data of data2 to have the effect of voltage rise.
  • the data selector MUX
  • the SA with negative H1 will be selected through the MUX. Therefore, the half-rate decision feedback equalizer in the related art uses 4 SAs, which increases power consumption and area.
  • a decision feedback equalizer is provided.
  • FIG. 3 is a flowchart of a decision feedback equalizer according to Embodiment 1 of the present application. As shown in Figure 3, the decision equalizer includes:
  • the first decision sampling circuit is The first decision sampling circuit.
  • the second decision sampling circuit wherein the first decision sampling circuit and the second decision sampling circuit perform sampling by using opposite sampling clock signals.
  • the input end of the first decision sampling circuit receives the sampling data
  • the input end of the first decision sampling circuit is also connected to the output end of the second decision sampling circuit, and is configured to receive the data output by the second decision sampling circuit in the last sampling period. the first sampling result, so as to determine the first correction method of the sampled data according to the first sampling result, and correct the sampled data by the first correction method;
  • the input end of the second decision sampling circuit receives the sampling data
  • the input end of the second decision sampling circuit is also connected to the output end of the first decision sampling circuit, and is configured to receive the second decision sampling circuit output in the last sampling period.
  • the sampling result is used to determine the second correction mode of the sampled data according to the second sampling result, and the sampled data is corrected by the second correction mode.
  • the rising edge signal CK of the sampling clock can be used to collect the data of the even sequence through the first decision sampling circuit of the even channel.
  • the first decision sampling circuit and the second decision sampling circuit are circuits in the dashed box in the odd channel and the even channel respectively.
  • the circuit in the dashed box integrates the functions of a MUX and an SA.
  • receive the sampling result collected by another channel in the previous sampling period for the even channel, the sampling result odd of the odd channel is received, and for the odd channel, the sampling result even of the even channel is received
  • MUX first determines the correction method based on the sampling results
  • SA collects the corrected sampling data.
  • it reduces the number of samplers used, thereby reducing power consumption and area by nearly half.
  • T SA refers to the time when the SA collects data and transmits it to the MUX
  • Tmux refers to the time from the mux input terminal to the output terminal
  • 1UI refers to the sum of the high and low levels of the sampling clock
  • the first correction method is one of the following: The first sampling correction data is superimposed, or the sampling data is subtracted from the first sampling correction data: the second correction method is one of the following: the sampling data and the second sampling correction data are superimposed, or the sampling data and the second sampling correction data are superimposed subtract.
  • the decision feedback equalizer uses the first decision sampling circuit; the second decision sampling circuit, wherein the first decision sampling circuit and the second decision sampling circuit perform sampling by using opposite sampling clock signals;
  • the input end of the decision sampling circuit receives the sampling data, and the input end of the first decision sampling circuit is also connected to the output end of the second decision sampling circuit, and is configured to receive the first sampling result output by the second decision sampling circuit in the last sampling period , to determine the first correction method of the sampled data through the first sampling result, and correct the sampled data by the first correction method;
  • the input end of the second decision sampling circuit receives the sample data, and the input end of the second decision sampling circuit is also connected with
  • the output end of the first decision sampling circuit is connected, and is configured to receive the second sampling result output by the first decision sampling circuit in the last sampling period, so as to determine the second correction mode of the sampled data through the second sampling result, and pass the second sampling result.
  • the correction method corrects the sampled data, and solves the problems of high power consumption and large size of the circuit caused by the use of multiple collectors in the half-rate decision feedback equalizer in the related art.
  • the first decision sampling circuit and the second decision sampling circuit first determine the correction method of the sampled data, and then correct and collect the sampled data, thereby reducing the use of the collector, thereby achieving the effects of reducing circuit power consumption and circuit size.
  • the first correction method is to add H1 on the basis of the sampled data of the even channel, or subtract H1 from the sampled data of the even channel.
  • the second correction method is to add H1 on the basis of the sampled data of the odd channel, or subtract H1 from the sampled data of the odd channel.
  • the first decision sampling circuit or the second decision sampling circuit includes: a selection sampling circuit , select the input end of the sampling circuit to receive the sampling data, and receive the sampling results collected in the previous sampling period, determine the correction method of the sampling data through the sampling results, correct and amplify the sampling data, and output the first sampling data; amplify;
  • a comparison circuit the input end of the amplifying and comparing circuit is connected to the output end of the selection sampling circuit, and is configured to amplify the first sampled data, and make positive and negative judgments according to the amplification results, and output the judgment result;
  • the holding circuit the input end of the holding circuit It is connected to the output end of the amplifying and comparing circuit, and is configured to hold the judgment result, and determine the held judgment result as the sampling result of the current sampling period.
  • the selection sampling circuit is used to realize the function of selecting first and then sampling, the sampled data is the corrected data, the amplifying and comparing circuit is used to judge the corrected data, and the holding circuit is used to hold the judgment result, so as to facilitate the judgment Read the result.
  • the selection sampling circuit is functionally a sampling pre-amplifier circuit with mux selection function.
  • the selection sampling circuit includes: a first differential amplifier circuit; a second differential amplifier circuit circuit, wherein the first differential amplifying circuit and the second differential amplifying circuit are respectively connected to the same sampling clock signal; wherein, the first input terminal of the first differential amplifying circuit receives the sampling results collected in the previous sampling period, and passes The sampling result determines whether to turn on or off the first differential amplifying circuit.
  • the two differential input ends of the first differential amplifying circuit respectively receive the result of the superposition of the sampling data and the sampling correction data, and amplify the superimposed result, and output two thirds.
  • the first input terminal of the second differential amplifier circuit receives the sampling result collected in the last sampling period, and determines whether to turn on or off the second differential amplifier circuit according to the sampling result, and the two differential amplifier circuit
  • Each of the differential input terminals respectively receives the result of the subtraction of the sampled data and the sampled correction data, and amplifies the subtraction result to output two second differential output signals.
  • this embodiment takes the first decision sampling circuit of the even channel as an example to introduce the structure of the selection sampling circuit.
  • the first differential amplifier circuit is composed of switch tubes M3L, M4L, M1L, M2L and M01L.
  • the amplifying circuit is composed of switch tubes M3, M4, M1, M2 and M01, and the first differential amplifying circuit and the second differential amplifying circuit are respectively connected to the same sampling clock signal CK.
  • the first input terminal of the first differential amplifier circuit receives the sampling result collected in the last sampling period of the odd channel. Since M01L is an NMOS tube, the sampling result is 0, that is, When it is a low-level signal TAPL, the first differential amplifier circuit is turned on, and the two differential input terminals of the first differential amplifier circuit, that is, the G pins of M1L and M2L, respectively receive the result of the subtraction of the sampling data and the sampling correction data. IPL and INL, amplify the subtracted result, and output two first differential output signals ONL and OPL.
  • the first input terminal of the second differential amplifier circuit receives the sampling result collected in the last sampling period of the odd channel. Since M01L is an NMOS tube, the sampling result is 1, that is, the high voltage When the signal TAPH is flat, the second differential amplifier circuit is turned on.
  • the two differential input terminals of the second differential amplifier circuit that is, the G pins of M1 and M2, respectively receive the results IPH and INH of the sampling data and the sampling correction data.
  • the superimposed result is amplified, and two second differential output signals ONH and OPH are output.
  • the amplification and comparison circuit is used to amplify and judge the two first differential output signals or the two second differential output signals output by the selection sampling circuit, so that the sampling result can be read.
  • the amplification and comparison circuit includes: a third differential amplification circuit, connected to the sampling clock signal, and configured to amplify the two first differential output signals or the two second differential output signals to obtain two third differential output signals. a differential output signal; the comparison circuit, connected to the sampling clock signal, is configured to receive two third differential output signals, and compare the two third differential output signals to obtain a first decision signal and a second decision signal.
  • the third differential amplifier circuit is composed of switch tubes M33, M44, M111, M222, M11, M22 and M02, which are the same as the selection sampling circuit, and are connected to the sampling clock signal CK.
  • the third differential amplifier circuit amplifies the two first differential output signals ONL and OPL when the first differential amplifier circuit is turned on and the second differential amplifier circuit is turned off to obtain two third differential output signals SP and SN ;
  • the second differential amplifier circuit is turned on and the first differential amplifier circuit is turned off, amplify the two second differential output signals ONH and OPH to obtain two third differential output signals SP and SN.
  • the third differential amplifier circuit includes two groups of differential input terminals, wherein the first group of differential input terminals is respectively connected to the two differential outputs of the first differential amplifier circuit. terminal is connected, and is configured to amplify the two first differential output signals and output two third differential output signals when the second differential amplifying circuit is disconnected and the second group of differential input terminals are turned on;
  • a group of differential input terminals are respectively connected to the two differential output terminals of the second differential amplifier circuit, and are configured to provide two second differential amplifier circuits when the first differential amplifier circuit is disconnected and the first group of differential input terminals is turned on.
  • the differential output signal is amplified to obtain two third differential output signals.
  • the first group of differential input terminals M111 and M222 are connected to the output terminals M1L and M2L of the first differential amplifier circuit
  • the second group of differential input terminals M11 and M22 are connected to the output terminals M1 and M2 of the second differential amplifier circuit.
  • the second group of differential input terminals M11 and M22 are controlled to be turned on. After M11 and M22 are turned on, they are equivalent to wires. , avoiding the influence of the second differential amplifying circuit when amplifying the two first differential output signals.
  • the second group of differential input terminals M111 and M222 are controlled to be turned on. The influence of the first differential amplifying circuit when amplifying the two second differential output signals is eliminated.
  • the functional circuit of the selection sampling circuit is used to control the turn-on and turn-off of the first group of differential input terminals and the second group of differential input terminals.
  • the selection sampling circuit further includes: a first functional circuit; a second functional circuit, wherein the input ends of the first functional circuit and the second functional circuit are respectively connected to the sampling results in the previous cycle; wherein the output end of the first functional circuit is connected to the third differential amplifier circuit.
  • the first group of differential input terminals is connected to the first group of differential input terminals, and is configured to determine whether the first group of differential input terminals is turned on through the sampling result: the output terminal of the second functional circuit is connected to the second group of differential input terminals of the third differential amplifier circuit, and is configured In order to judge whether the second group of differential input terminals is turned on through the sampling result.
  • the first functional circuit is composed of switches ML0 and ML1
  • the second functional circuit is composed of switches MH0 and MH1, ML0, ML1, MH0 and MH1 are PMOS tubes, and the second decision sampler in the odd channel
  • the output result is 0, that is, when TAPL is low, ONL and OPL are 1, the first group of differential input terminals M111 and M222 are turned on, and the third differential amplifier circuit performs two second differential output signals ONH and OPH.
  • M111 and M222 are equivalent to wires, avoiding the influence of the first differential amplifier circuit.
  • the amplification decision circuit further includes a comparison circuit.
  • the comparison circuit includes: a first inverter; and a second inverter, wherein, The first inverter and the second inverter are respectively connected to the sampling clock signal; the input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the first inverter
  • the output terminals of the inverter are connected to each other, the input terminal of the first inverter and the input terminal of the second inverter respectively receive two third differential output signals, and the output terminal of the first inverter and the output terminal of the second inverter respectively receive two third differential output signals.
  • the first decision signal and the second decision signal are respectively output.
  • the comparison circuit is also connected to the sampling clock signal CK, and the comparison circuit includes M6, M8, M5, M7, M9, M03, wherein M6 and M5 constitute a first inverter, and M8 and M7 constitute a second inverter.
  • M6 and M5 constitute a first inverter
  • M8 and M7 constitute a second inverter.
  • Inverter the input end of the first inverter is connected with the output end of the second inverter, the input end of the second inverter is connected with the output end of the first inverter, and the input end of the first inverter is connected with The third differential output signal SN, and the input terminal of the second inverter is connected to the third differential output signal SP.
  • ONL, OPL, ONH and OPH are rising edge signals with different slopes or falling edge signals with different slopes
  • SP and SN are the slope signals amplified by the third differential amplifier circuit, that is, the two slopes are different.
  • a comparison circuit is used to compare the slopes of SP and SN to obtain a first decision signal and a second decision signal.
  • a signal with a large slope is judged as 1, and a signal with a small slope is judged as 0.
  • the signal with a large slope is judged as 0, and the signal with a small slope is judged as 1, so as to realize the judgment on the sampled data.
  • the holding circuit is a latch.
  • the holding circuit can be a latch, input the judgment results SP and SN, and obtain the maintained judgment results OUP and OUTN. Reading of corrected sample data.
  • the second embodiment of the present application further provides a method for collecting and calibrating data. It should be noted that the method for collecting and calibrating data in the embodiment of the present application may be applied to the decision feedback equalizer provided by the embodiment of the present application. The methods for collecting and correcting data provided by the embodiments of the present application will be introduced below.
  • FIG. 8 is a flowchart of a method for collecting and calibrating data according to Embodiment 2 of the present application. As shown in Figure 8, the method includes the following steps:
  • Step S802 acquiring the sampling result obtained by collecting the sampling data in the last sampling period, and determining the correction method of the sampling data according to the sampling result, wherein the correction method is to superimpose the sampling data and the sampling correction data, or to combine the sampling data and the sampling data. Correction data is subtracted.
  • Step S804 correcting the sampled data in a correction manner to obtain corrected data.
  • Step S806 collect the corrected data, and output the collection result.
  • the sampling result in the last sampling period is the sampling result of the last sampling data
  • the correction method is determined according to the current sampling data and the last sampling data, for example, the transmitted data is 001, the last sampling data is 0,
  • the current sampling data is 1
  • the previous sampling data 0 has a negative effect on the current sampling data 1
  • the sampling data 1 and the sampling correction data are superimposed, so as to realize the correction of the sampling data.
  • the transmitted data is 011
  • the last sampled data is 1
  • the current sampled data is 1
  • the last sampled data 1 has a positive effect on the current sampled data 1
  • the sampled data 1 is subtracted from the sampled correction data. Correction of sampled data.
  • the correction method is determined first, and then the sampled data is corrected and collected.
  • the number of samplers used is reduced, thereby reducing the power consumption by nearly half. consumption and area.
  • the timing constraint of the half-rate decision feedback equalizer T SA +Tmux ⁇ 1UI in the related art its timing constraint is equivalent to relaxing the time of one Tmux, so that a higher data stream can be sampled and the decision feedback is improved.
  • the sample rate of the equalizer compared with the timing constraint of the half-rate decision feedback equalizer.
  • the data collection and correction method provided by the embodiment of the present application is obtained by acquiring the sampling result obtained by collecting the sampling data in the last sampling period, and determining the correction method of the sampled data according to the sampling result, wherein the correction method is to compare the sampled data with The sampling correction data is superimposed, or the sampling data is subtracted from the sampling correction data; the sampling data is corrected by the correction method, and the corrected data is obtained;
  • the rate decision feedback equalizer uses multiple collectors, which leads to the problems of high power consumption and large size of the circuit. By first determining the correction method of the sampled data, and then correcting and collecting the sampled data, the use of collectors is reduced, and the circuit is reduced. The effect of power consumption and circuit size reduction.
  • the embodiments of the present application may be provided as a method, a system or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • the decision equalizer includes: a first decision sampling circuit; a second decision sampling circuit; an input end of the first decision sampling circuit receives sampling data, and receives the output of the second decision sampling circuit in a previous sampling period
  • the first sampling result is used to determine the first correction method of the sampled data according to the first sampling result, and the sampled data is corrected by the first correction method
  • the input end of the second decision sampling circuit receives the sample data and receives the first decision sample
  • the second sampling result output by the circuit in the last sampling period is used to determine the second correction mode of the sampled data according to the second sampling result, and correct the sampled data by the second correction method.
  • the first decision sampling circuit and the second decision sampling circuit first determine the correction method of the sampled data, and then correct and collect the sampled data, which reduces the use of collectors and solves the problem that the half-rate decision feedback equalizer in the related art uses multiple collectors. , resulting in high power consumption and large size of the circuit.

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Abstract

本申请公开了一种判决反馈均衡器以及数据的采集与校正方法。该判决均衡器包括：第一判决采样电路；第二判决采样电路；第一判决采样电路的输入端接收采样数据，并接收第二判决采样电路在上一采样周期输出的第一采样结果，以通过第一采样结果确定采样数据的第一校正方式，并通过第一校正方式对采样数据进行校正；第二判决采样电路的输入端接收采样数据，并接收第一判决采样电路在上一采样周期输出的第二采样结果，以通过第二采样结果确定采样数据的第二校正方式，并通过第二校正方式对采样数据进行校正。

Description

判决反馈均衡器以及数据的采集与校正方法
本申请要求于2020年11月5日提交中国专利局、申请号为202011224933.0、申请名称“判决反馈均衡器以及数据的采集与校正方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请数据传输技术领域，具体而言，涉及一种判决反馈均衡器以及数据的采集与校正方法。
背景技术
在高速数据传输过程中，由于信道的非理想特性从而引起了码间干扰，影响了信号完整性。
相关技术中采用全速率判决反馈均衡器消除码间干扰，全速率判决反馈均衡器是一种采用已判决出来的数据，来帮助消除当前判决数据中存在的ISI，恢复出正确的码型。随着高速接口传输速率的不断提升，全速率均衡器对电路的时序设计要求非常严格，从而导致其设计成本和难度加大。
为了解决全速率均衡器时序要求严格，设计成本和难度加大的问题，相关技术中出现了半速率均衡器，半速率均衡器是指采样频率是数据流频率的一半，使电路时序设计更加宽裕，但是，由于半速率判决反馈均衡器在奇通路和偶通路均先采集增加以及减去前一信号对后一信号的影响数值，再判断保留哪个采集值，需要采用4个采样器进行采样，导致半速率判决反馈均衡器的功耗和面积会变大。
针对相关技术中半速率判决反馈均衡器采用多个采集器，导致电路功耗大、尺寸大的问题，目前尚未提出有效的解决方案。
发明内容
本发明至少部分实施例本申请提供一种判决反馈均衡器以及数据的采集与校正方法，以解决相关技术中半速率判决反馈均衡器采用多个采集器，导致电路功耗大、尺寸大的问题。
根据本发明其中一实施例提供了一种判决反馈均衡器。该判决均衡器包括：第一判决采样电路；第二判决采样电路，其中，第一判决采样电路和第二判决采样电路通过相反的采样时钟信号进行采样；其中，第一判决采样电路的输入端接收采样数据， 第一判决采样电路的输入端还与第二判决采样电路的输出端连接，被配置为接收第二判决采样电路在上一采样周期输出的第一采样结果，以通过第一采样结果确定采样数据的第一校正方式，并通过第一校正方式对采样数据进行校正；第二判决采样电路的输入端接收采样数据，第二判决采样电路的输入端还与第一判决采样电路的输出端连接，被配置为接收第一判决采样电路在上一采样周期输出的第二采样结果，以通过第二采样结果确定采样数据的第二校正方式，并通过第二校正方式对采样数据进行校正。
可选地，第一校正方式为以下之一：将采样数据与第一采样校正数据叠加，或将采样数据与第一采样校正数据相减：第二校正方式为以下之一：将采样数据与第二采样校正数据叠加，或将采样数据与第二采样校正数据相减。
可选地，第一判决采样电路或第二判决采样电路中包括：选择采样电路，选择采样电路的输入端接收采样数据，以及接收上一采样周期内采集到的采样结果，通过采样结果确定采样数据的校正方式，并对采样数据进行校正以及放大，输出第一采样数据；放大比较电路，放大比较电路的输入端与选择采样电路的输出端连接，被配置为对第一采样数据进行放大，并根据放大结果进行正负判决，输出判决结果；保持电路，保持电路的输入端与放大比较电路的输出端连接，被配置为对判决结果进行保持，并将所保持的判决结果确定为当前采样周期的采样结果。
可选地，选择采样电路包括：第一差分放大电路；第二差分放大电路，其中，第一差分放大电路和第二差分放大电路分别接入相同的采样时钟信号；其中，第一差分放大电路的第一输入端接收上一采样周期内采集到的采样结果，并通过采样结果确定接通或断开第一差分放大电路，第一差分放大电路的两个差分输入端分别接收采样数据与采样校正数据叠加的结果，并对叠加的结果进行放大处理，输出两个第一差分输出信号；第二差分放大电路的第一输入端接收上一采样周期内采集到的采样结果，并通过采样结果确定接通或断开第二差分放大电路，第二差分放大电路的两个差分输入端分别接收采样数据与采样校正数据相减的结果，并对相减的结果进行放大处理，输出两个第二差分输出信号。
可选地，放大比较电路包括：第三差分放大电路，接入采样时钟信号，被配置为对两个第一差分输出信号或两个第二差分输出信号进行放大，得到两个第三差分输出信号；比较电路，接入采样时钟信号，被配置为接收两个第三差分输出信号，并对两个第三差分输出信号进行比较，得到第一判决信号和第二判决信号。
可选地，第三差分放大电路包括两组差分输入端，其中，第一组差分输入端，分别与第一差分放大电路的两个差分输出端连接，被配置为在断开第二差分放大电路，且第二组差分输入端导通的情况下，对两个第一差分输出信号进行放大，输出两个第三差分输出信号；第二组差分输入端，分别与第二差分放大电路的两个差分输出端连 接，被配置为在断开第一差分放大电路，且第一组差分输入端导通的情况下，对两个第二差分输出信号进行放大，得到两个第三差分输出信号。
可选地，选择采样电路还包括：第一功能电路；第二功能电路，其中，第一功能电路和第二功能电路的输入端分别接入上一周期内的采样结果；其中，第一功能电路的输出端与第三差分放大电路的第一组差分输入端连接，被配置为通过采样结果判断第一组差分输入端是否导通：第二功能电路的输出端与第三差分放大电路的第二组差分输入端连接，被配置为通过采样结果判断第二组差分输入端是否导通。
可选地，比较电路包括：第一反相器；第二反相器，其中，第一反相器和第二反相器分别接入采样时钟信号；第一反相器的输入端和第二反相器的输出端相连，第二反相器的输入端和第一反相器的输出端相连，第一反相器的输入端和第二反相器的输入端分别接收两个第三差分输出信号，第一反相器的输出端和第二反相器的输出端分别输出第一判决信号和第二判决信号。
可选地，保持电路为锁存器。
本发明的另一实施例还提供了一种数据的采集与校正方法，应用于上述任意一项的判决反馈均衡器。该方法包括：获取上一采样周期内对采样数据进行采集得到的采样结果，并通过采样结果确定采样数据的校正方式，其中，校正方式为将采样数据与采样校正数据叠加，或将采样数据与采样校正数据相减；采用校正方式对采样数据进行校正，得到校正后的数据；对校正后的数据进行采集，并输出采集结果。
通过本申请，通过：第一判决采样电路；第二判决采样电路，其中，第一判决采样电路和第二判决采样电路通过相反的采样时钟信号进行采样；其中，第一判决采样电路的输入端接收采样数据，第一判决采样电路的输入端还与第二判决采样电路的输出端连接，被配置为接收第二判决采样电路在上一采样周期输出的第一采样结果，以通过第一采样结果确定采样数据的第一校正方式，并通过第一校正方式对采样数据进行校正；第二判决采样电路的输入端接收采样数据，第二判决采样电路的输入端还与第一判决采样电路的输出端连接，被配置为接收第一判决采样电路在上一采样周期输出的第二采样结果，以通过第二采样结果确定采样数据的第二校正方式，并通过第二校正方式对采样数据进行校正，解决了相关技术中半速率判决反馈均衡器采用多个采集器，导致电路功耗大、尺寸大的问题。通过第一判决采样电路和第二判决采样电路先确定采样数据的校正方式，再校正并采集采样数据，减少了采集器的使用，进而达到了减少电路功耗、降低电路尺寸的效果。
附图说明
构成本申请的一部分的附图用来提供对本申请的进一步理解，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是根据相关技术中提供的判决反馈均衡器的示意图；
图2是根据相关技术中提供的判决反馈均衡器的采样时序图；
图3是根据本申请实施例一提供的判决反馈均衡器的示意图；
图4是根据本申请实施例一提供的判决反馈均衡器中的选择采样电路的示意图；
图5是根据本申请实施例一提供的判决反馈均衡器中的第三差分放大电路的示意图；
图6是根据本申请实施例一提供的判决反馈均衡器中的比较电路的示意图；
图7是根据本申请实施例一提供的判决反馈均衡器中的保持电路的示意图；
图8是根据本申请实施例二提供的数据的采集与校正方法的流程图。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
为了便于描述，以下对本申请实施例涉及的部分名词或术语进行说明：
码间干扰：简称ISI，英文全称Inter-Symbol Interference，是指高速传播的信号间 的相关干扰。
采样器：简称SA，英文全称Sampler Amplifier。
数据选择器：简称MUX，英文全称multiplexer。
为了解决相关技术中全速率均衡器时序要求严格，设计成本和难度加大的问题，相关技术中出现了以下半速率判决反馈均衡器：
如图1所示，当有数据输入时，在奇(odd)、偶(even)通路的采样器(SA)对数据进行采样，其中，CKB是CK的反相相位，奇数据通路得到数据odd，偶数据通路得到数据even。
图2是图1的采样时序图，如图2所示，为了消除data1对data2的影响，在偶数据通路对data2采样前，利用奇数据通路对data1采样结果，来判决data2是加一个H1还是减一个H1(H1表示消除ISI影响的电压幅度)。
如果data1的采样结果是1，说明其对data2的影响是正的，会使data2的数据产生电压抬升的影响，在偶数据通路会通过数据选择器(MUX)选择带负H1的一路的SA。同理，data1的采样结果是0，说明其对data2的影响是负的，在偶数据通路会通过MUX选择带正H1的一路的SA。因而，相关技术中的半速率判决反馈均衡器采用4个SA，其功耗和面积变大。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其详细内容将在后续实施例中得以阐述。
实施例一
根据本申请的实施例一，提供了一种判决反馈均衡器。
图3是根据本申请实施例一的判决反馈均衡器的流程图。如图3所示，该判决均衡器包括：
第一判决采样电路。
第二判决采样电路，其中，第一判决采样电路和第二判决采样电路通过相反的采样时钟信号进行采样。
其中，第一判决采样电路的输入端接收采样数据，第一判决采样电路的输入端还与第二判决采样电路的输出端连接，被配置为接收第二判决采样电路在上一采样周期输出的第一采样结果，以通过第一采样结果确定采样数据的第一校正方式，并通过第一校正方式对采样数据进行校正；
第二判决采样电路的输入端接收采样数据，第二判决采样电路的输入端还与第一判决采样电路的输出端连接，被配置为接收第一判决采样电路在上一采样周期输出的第二采样结果，以通过第二采样结果确定采样数据的第二校正方式，并通过第二校正方式对采样数据进行校正。
如图3所示，在采用本申请实施例中的判决反馈均衡器采集采样数据时，可以采用采样时钟的上升沿信号CK、通过偶通路的第一判决采样电路采集偶数序列的数据，相反的，采用采样时钟的下降沿信号CKB、通过奇通路的第二判决采样电路采集奇数序列的数据，从而完成对采样数据的采集。
需要说明的是，第一判决采样电路和第二判决采样电路分别为奇通路和偶通路中虚线框内的电路，虚线框内的电路集成了一个MUX和一个SA的功能，在接收采样数据的同时，接收另一通路在上一个采样周期采集到的采样结果(对于偶通路来说，接收的是奇通路的采样结果odd，对于奇通路来说，接收的是偶通路的采样结果even)，MUX先基于采样结果确定校正方式，SA再采集校正后的采样数据，相对于相关技术中的半速率判决反馈均衡器，减少了采样器的使用数量，从而降低了接近一半的功耗和面积。
此外，需要说明的是，将MUX加入到SA内部，相对于相关技术中的半速率判决反馈均衡器T SA+Tmux<1UI的时序约束(T SA是指SA采到数据传到MUX的时间，Tmux是指数据从mux输入端到输出端的时间，1UI是指采样时钟高电平和低电平的时长的和)，其时序约束相当于放宽一个Tmux的时间，从而可以采样更高的数据流，提升了判决反馈均衡器的采样速率。
第一校正方式和第二校正方式均用于消除采样数据的码间干扰，可选地，在本申请实施例提供的判决反馈均衡器中，第一校正方式为以下之一：将采样数据与第一采样校正数据叠加，或将采样数据与第一采样校正数据相减：第二校正方式为以下之一：将采样数据与第二采样校正数据叠加，或将采样数据与第二采样校正数据相减。
本申请实施例提供的判决反馈均衡器，通过第一判决采样电路；第二判决采样电路，其中，第一判决采样电路和第二判决采样电路通过相反的采样时钟信号进行采样；其中，第一判决采样电路的输入端接收采样数据，第一判决采样电路的输入端还与第二判决采样电路的输出端连接，被配置为接收第二判决采样电路在上一采样周期输出的第一采样结果，以通过第一采样结果确定采样数据的第一校正方式，并通过第一校正方式对采样数据进行校正；第二判决采样电路的输入端接收采样数据，第二判决采样电路的输入端还与第一判决采样电路的输出端连接，被配置为接收第一判决采样电路在上一采样周期输出的第二采样结果，以通过第二采样结果确定采样数据的第二校正方式，并通过第二校正方式对采样数据进行校正，解决了相关技术中半速率判决反 馈均衡器采用多个采集器，导致电路功耗大、尺寸大的问题。通过第一判决采样电路和第二判决采样电路先确定采样数据的校正方式，再校正并采集采样数据，减少了采集器的使用，进而达到了减少电路功耗、降低电路尺寸的效果。
如图3所示，第一校正方式为在偶通路的采样数据的基础上加H1，或在偶通路的采样数据的基础上减H1。同理，第二校正方式为在奇通路的采样数据的基础上加H1，或在奇通路的采样数据的基础上减H1。
第一判决采样电路和第二判决采样电路的电路结构相同，可选地，在本申请实施例提供的判决反馈均衡器中，第一判决采样电路或第二判决采样电路中包括：选择采样电路，选择采样电路的输入端接收采样数据，以及接收上一采样周期内采集到的采样结果，通过采样结果确定采样数据的校正方式，并对采样数据进行校正以及放大，输出第一采样数据；放大比较电路，放大比较电路的输入端与选择采样电路的输出端连接，被配置为对第一采样数据进行放大，并根据放大结果进行正负判决，输出判决结果；保持电路，保持电路的输入端与放大比较电路的输出端连接，被配置为对判决结果进行保持，并将所保持的判决结果确定为当前采样周期的采样结果。
具体地，选择采样电路用于实现先选择后采样的功能，采样的数据即为校正后的数据，放大比较电路用于将校正后的数据判决出来，保持电路用于保持判决结果，以便于判决结果的读取。
选择采样电路在功能上为带有mux选择功能的采样预放大电路，可选地，在本申请实施例提供的判决反馈均衡器中，选择采样电路包括：第一差分放大电路；第二差分放大电路，其中，第一差分放大电路和第二差分放大电路分别接入相同的采样时钟信号；其中，第一差分放大电路的第一输入端接收上一采样周期内采集到的采样结果，并通过采样结果确定接通或断开第一差分放大电路，第一差分放大电路的两个差分输入端分别接收采样数据与采样校正数据叠加的结果，并对叠加的结果进行放大处理，输出两个第一差分输出信号；第二差分放大电路的第一输入端接收上一采样周期内采集到的采样结果，并通过采样结果确定接通或断开第二差分放大电路，第二差分放大电路的两个差分输入端分别接收采样数据与采样校正数据相减的结果，并对相减的结果进行放大处理，输出两个第二差分输出信号。
如图4所示，本实施例以偶通路的第一判决采样电路为例，介绍选择采样电路的结构，第一差分放大电路由开关管M3L、M4L、M1L、M2L以及M01L构成，第二差分放大电路由开关管M3、M4、M1、M2以及M01构成，第一差分放大电路和第二差分放大电路分别接入相同的采样时钟信号CK。
具体地，第一差分放大电路的第一输入端，也即M01L的G管脚，接收奇通路上 一采样周期内采集到的采样结果，由于M01L为NMOS管，在采样结果为0，也即是低电平信号TAPL时，接通第一差分放大电路，第一差分放大电路的两个差分输入端，也即M1L和M2L的G管脚，分别接收采样数据与采样校正数据相减的结果IPL和INL，并对相减的结果进行放大处理，输出两个第一差分输出信号ONL和OPL。
第二差分放大电路的第一输入端，也即M01的G管脚，接收奇通路上一采样周期内采集到的采样结果，由于M01L为NMOS管，在采样结果为1，也即是高电平信号TAPH时，接通第二差分放大电路，第二差分放大电路的两个差分输入端，也即M1和M2的G管脚，分别接收采样数据与采样校正数据叠加的结果IPH和INH，并对叠加的结果进行放大处理，输出两个第二差分输出信号ONH和OPH。
放大比较电路用于对选择采样电路输出的两个第一差分输出信号或两个第二差分输出信号进行放大与判决，从而使得采样结果可读取，可选地，在本申请实施例提供的判决反馈均衡器中，放大比较电路包括：第三差分放大电路，接入采样时钟信号，被配置为对两个第一差分输出信号或两个第二差分输出信号进行放大，得到两个第三差分输出信号；比较电路，接入采样时钟信号，被配置为接收两个第三差分输出信号，并对两个第三差分输出信号进行比较，得到第一判决信号和第二判决信号。
如图5所示，第三差分放大电路由开关管M33、M44、M111、M222、M11、M22以及M02构成，与选择采样电路相同，接入采样时钟信号CK。第三差分放大电路在第一差分放大电路接通、第二差分放大电路断开的情况下，对两个第一差分输出信号ONL和OPL进行放大，得到两个第三差分输出信号SP和SN；在第二差分放大电路接通、第一差分放大电路断开的情况下，对两个第二差分输出信号ONH和OPH进行放大，得到两个第三差分输出信号SP和SN。
可选地，在本申请实施例提供的判决反馈均衡器中，第三差分放大电路包括两组差分输入端，其中，第一组差分输入端，分别与第一差分放大电路的两个差分输出端连接，被配置为在断开第二差分放大电路，且第二组差分输入端导通的情况下，对两个第一差分输出信号进行放大，输出两个第三差分输出信号；第二组差分输入端，分别与第二差分放大电路的两个差分输出端连接，被配置为在断开第一差分放大电路，且第一组差分输入端导通的情况下，对两个第二差分输出信号进行放大，得到两个第三差分输出信号。
如图5所示，第一组差分输入端M111、M222与第一差分放大电路的输出端M1L、M2L连接，第二组差分输入端M11、M22与第二差分放大电路的输出端M1、M2连接，在对两个第一差分输出信号ONL和OPL进行放大时，为了避免第二差分放大电路的影响，控制第二组差分输入端M11、M22导通，M11、M22导通后相当于导线，避免了对两个第一差分输出信号进行放大时第二差分放大电路的影响。在对两个第二 差分输出信号ONH和OPH进行放大时，为了避免第一差分放大电路的影响，控制第二组差分输入端M111、M222导通，M111、M222导通后相当于导线，避免了对两个第二差分输出信号进行放大时第一差分放大电路的影响。
采用选择采样电路的功能电路控制第一组差分输入端以及第二组差分输入端的导通与关断，可选地，在本申请实施例提供的判决反馈均衡器中，选择采样电路还包括：第一功能电路；第二功能电路，其中，第一功能电路和第二功能电路的输入端分别接入上一周期内的采样结果；其中，第一功能电路的输出端与第三差分放大电路的第一组差分输入端连接，被配置为通过采样结果判断第一组差分输入端是否导通：第二功能电路的输出端与第三差分放大电路的第二组差分输入端连接，被配置为通过采样结果判断第二组差分输入端是否导通。
如图4所示，第一功能电路由开关管ML0和ML1构成，第二功能电路由开关管MH0和MH1构成，ML0、ML1、MH0以及MH1为PMOS管，在奇通路的第二判决采样器输出结果为0时，也即低电平TAPL时，ONL和OPL为1，第一组差分输入端M111、M222导通，在第三差分放大电路对两个第二差分输出信号ONH和OPH进行放大时，M111、M222相当于导线，避免了第一差分放大电路的影响。
相反的，第二判决采样器输出结果为1时，也即高电平TAPL时，ONH和OPH为1，第二组差分输入端M11、M22导通，在第三差分放大电路对两个第一差分输出信号ONL和OPL进行放大时，M11、M22相当于导线，避免了第二差分放大电路的影响。
放大判决电路除了第三差分放大电路，还包括比较电路，可选地，在本申请实施例提供的判决反馈均衡器中，比较电路包括：第一反相器；第二反相器，其中，第一反相器和第二反相器分别接入采样时钟信号；第一反相器的输入端和第二反相器的输出端相连，第二反相器的输入端和第一反相器的输出端相连，第一反相器的输入端和第二反相器的输入端分别接收两个第三差分输出信号，第一反相器的输出端和第二反相器的输出端分别输出第一判决信号和第二判决信号。
如图6所示，比较电路同样接入采样时钟信号CK，比较电路包括M6、M8、M5、M7、M9、M03，其中，M6和M5构成第一反相器，M8和M7构成第二反相器，第一反相器的输入端和第二反相器的输出端相连，第二反相器的输入端和第一反相器的输出端相连，第一反相器的输入端接第三差分输出信号SN，第二反相器的输入端接第三差分输出信号SP。
需要说明的是，ONL和OPL、ONH和OPH，为斜率不同的上升沿信号或斜率不同的下降沿信号，SP和SN为通过第三差分放大电路放大后的斜率信号，也即两个斜 率不同的斜率信号，为了判决出可读取的校正后的采样数据，采用比较电路对SP和SN的斜率进行比较，得到第一判决信号和第二判决信号。
具体地，对于上升沿信号，将斜率大的信号判决为1，将斜率小的信号判决为0。对于下降沿信号，将斜率大的信号判决为0，将斜率小的信号判决为1，从而实现对采样数据的判决。
为了稳定输出判决信号，可选地，在本申请实施例提供的判决反馈均衡器中，保持电路为锁存器。
具体的，如图7所示，保持电路可以为锁存器，输入判决结果SP和SN，得到保持的判决结果OUP和OUTN，可以在一段时间内保持判决结果，方便了后续电路对采集到的校正后的采样数据的读取。
实施例二
本申请实施例二还提供了一种数据的采集与校正方法，需要说明的是，本申请实施例的数据的采集与校正方法可以应用于本申请实施例所提供的用于判决反馈均衡器。以下对本申请实施例提供的数据的采集与校正方法进行介绍。
图8是根据本申请实施例二的数据的采集与校正方法的流程图。如图8所示，该方法包括以下步骤：
步骤S802，获取上一采样周期内对采样数据进行采集得到的采样结果，并通过采样结果确定采样数据的校正方式，其中，校正方式为将采样数据与采样校正数据叠加，或将采样数据与采样校正数据相减。
步骤S804，采用校正方式对采样数据进行校正，得到校正后的数据。
步骤S806，对校正后的数据进行采集，并输出采集结果。
具体地，上一采样周期内的采样结果即为上一个采样数据的采样结果，根据当前采样数据以及上一个采样数据确定校正方式，例如，传输的数据是为001，上一个采样数据为0，当前采样数据为1，上一个采样数据0对当前采样数据1影响为负，将采样数据1与采样校正数据叠加，从而实现采样数据的校正。
再例如，传输的数据是为011，上一个采样数据为1，当前采样数据为1，上一个采样数据1对当前采样数据1影响为正，将采样数据1与采样校正数据相减，从而实现采样数据的校正。
需要说明的是，先确定校正方式，再对采样数据进行校正并采集，一方面，相对于相关技术中的半速率判决反馈均衡器，减少了采样器的使用数量，从而降低了接近 一半的功耗和面积。另一方面，相对于相关技术中的半速率判决反馈均衡器T SA+Tmux<1UI的时序约束，其时序约束相当于放宽一个Tmux的时间，从而可以采样更高的数据流，提升了判决反馈均衡器的采样速率。
本申请实施例提供的数据的采集与校正方法，通过获取上一采样周期内对采样数据进行采集得到的采样结果，并通过采样结果确定采样数据的校正方式，其中，校正方式为将采样数据与采样校正数据叠加，或将采样数据与采样校正数据相减；采用校正方式对采样数据进行校正，得到校正后的数据；对校正后的数据进行采集，并输出采集结果，解决了相关技术中半速率判决反馈均衡器采用多个采集器，导致电路功耗大、尺寸大的问题，通过先确定采样数据的校正方式，再校正并采集采样数据，减少了采集器的使用，进而达到了减少电路功耗、降低电路尺寸的效果。
需要说明的是，在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行，并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、商品或者设备中还存在另外的相同要素。
本领域技术人员应明白，本申请的实施例可提供为方法、系统或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
以上仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。
工业实用性
本发明实施例提供的方案可应用于数据传输技术技术领域。在本发明实施例中，判决均衡器包括：第一判决采样电路；第二判决采样电路；第一判决采样电路的输入端接收采样数据，并接收第二判决采样电路在上一采样周期输出的第一采样结果，以通过第一采样结果确定采样数据的第一校正方式，并通过第一校正方式对采样数据进 行校正；第二判决采样电路的输入端接收采样数据，并接收第一判决采样电路在上一采样周期输出的第二采样结果，以通过第二采样结果确定采样数据的第二校正方式，并通过第二校正方式对采样数据进行校正。通过第一判决采样电路和第二判决采样电路先确定采样数据的校正方式，再校正并采集采样数据，减少了采集器的使用，解决了相关技术中半速率判决反馈均衡器采用多个采集器，导致电路功耗大、尺寸大的问题。

Claims (10)

  1. 一种判决反馈均衡器，包括：
    第一判决采样电路；
    第二判决采样电路，其中，所述第一判决采样电路和所述第二判决采样电路通过相反的采样时钟信号进行采样；
    其中，所述第一判决采样电路的输入端接收采样数据，所述第一判决采样电路的输入端还与所述第二判决采样电路的输出端连接，被配置为接收所述第二判决采样电路在上一采样周期输出的第一采样结果，以通过所述第一采样结果确定所述采样数据的第一校正方式，并通过所述第一校正方式对所述采样数据进行校正；
    所述第二判决采样电路的输入端接收所述采样数据，所述第二判决采样电路的输入端还与所述第一判决采样电路的输出端连接，被配置为接收所述第一判决采样电路在上一采样周期输出的第二采样结果，以通过所述第二采样结果确定所述采样数据的第二校正方式，并通过所述第二校正方式对所述采样数据进行校正。
  2. 根据权利要求1所述的判决反馈均衡器，其中，所述第一校正方式为以下之一：将所述采样数据与第一采样校正数据叠加，或将所述采样数据与所述第一采样校正数据相减：
    所述第二校正方式为以下之一：将所述采样数据与第二采样校正数据叠加，或将所述采样数据与所述第二采样校正数据相减。
  3. 根据权利要求2所述的判决反馈均衡器，其中，所述第一判决采样电路或所述第二判决采样电路中包括：
    选择采样电路，所述选择采样电路的输入端接收所述采样数据，以及接收上一采样周期内采集到的采样结果，通过所述采样结果确定所述采样数据的所述校正方式，并对所述采样数据进行校正以及放大，输出第一采样数据；
    放大比较电路，所述放大比较电路的输入端与所述选择采样电路的输出端连接，被配置为对所述第一采样数据进行放大，并根据放大结果进行正负判决，输出判决结果；
    保持电路，所述保持电路的输入端与所述放大比较电路的输出端连接，被配置为对所述判决结果进行保持，并将所保持的判决结果确定为当前采样周期的采样结果。
  4. 根据权利要求3所述的判决反馈均衡器，其中，所述选择采样电路包括：
    第一差分放大电路；
    第二差分放大电路，其中，所述第一差分放大电路和所述第二差分放大电路分别接入相同的采样时钟信号；
    其中，所述第一差分放大电路的第一输入端接收上一采样周期内采集到的采样结果，并通过所述采样结果确定接通或断开所述第一差分放大电路，所述第一差分放大电路的两个差分输入端分别接收所述采样数据与采样校正数据叠加的结果，并对所述叠加的结果进行放大处理，输出两个第一差分输出信号；
    所述第二差分放大电路的第一输入端接收上一采样周期内采集到的采样结果，并通过所述采样结果确定接通或断开所述第二差分放大电路，所述第二差分放大电路的两个差分输入端分别接收所述采样数据与所述采样校正数据相减的结果，并对所述相减的结果进行放大处理，输出两个第二差分输出信号。
  5. 根据权利要求4所述的判决反馈均衡器，其中，所述放大比较电路包括：
    第三差分放大电路，接入所述采样时钟信号，被配置为对两个所述第一差分输出信号或两个所述第二差分输出信号进行放大，得到两个第三差分输出信号；
    比较电路，接入所述采样时钟信号，被配置为接收所述两个第三差分输出信号，并对所述两个第三差分输出信号进行比较，得到第一判决信号和第二判决信号。
  6. 根据权利要求5所述的判决反馈均衡器，其中，所述第三差分放大电路包括两组差分输入端，其中，第一组差分输入端，分别与所述第一差分放大电路的两个差分输出端连接，被配置为在断开所述第二差分放大电路，且第二组差分输入端导通的情况下，对两个所述第一差分输出信号进行放大，输出两个所述第三差分输出信号；
    第二组差分输入端，分别与所述第二差分放大电路的两个差分输出端连接，被配置为在断开所述第一差分放大电路，且所述第一组差分输入端导通的情况下，对两个所述第二差分输出信号进行放大，得到两个所述第三差分输出信号。
  7. 根据权利要求6所述的判决反馈均衡器，其中，所述选择采样电路还包括：
    第一功能电路；
    第二功能电路，其中，所述第一功能电路和所述第二功能电路的输入端分别接入上一周期内的采样结果；
    其中，所述第一功能电路的输出端与所述第三差分放大电路的所述第一组差 分输入端连接，被配置为通过所述采样结果判断所述第一组差分输入端是否导通：
    所述第二功能电路的输出端与所述第三差分放大电路的所述第二组差分输入端连接，被配置为通过所述采样结果判断所述第二组差分输入端是否导通。
  8. 根据权利要求5所述的判决反馈均衡器，其中，所述比较电路包括：
    第一反相器；
    第二反相器，其中，所述第一反相器和所述第二反相器分别接入所述采样时钟信号；
    所述第一反相器的输入端和所述第二反相器的输出端相连，所述第二反相器的输入端和所述第一反相器的输出端相连，所述第一反相器的输入端和所述第二反相器的输入端分别接收所述两个第三差分输出信号，所述第一反相器的输出端和所述第二反相器的输出端分别输出所述第一判决信号和所述第二判决信号。
  9. 根据权利要求3所述的判决反馈均衡器，其中，所述保持电路为锁存器。
  10. 一种数据的采集与校正方法，应用于权利要求1到9任意一项所述的判决反馈均衡器，包括：
    获取上一采样周期内对采样数据进行采集得到的采样结果，并通过所述采样结果确定所述采样数据的校正方式，其中，所述校正方式为将所述采样数据与采样校正数据叠加，或将所述采样数据与所述采样校正数据相减；
    采用所述校正方式对所述采样数据进行校正，得到校正后的数据；
    对所述校正后的数据进行采集，并输出采集结果。
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