WO2022088595A1 - 边界扫描测试方法 - Google Patents

边界扫描测试方法 Download PDF

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Publication number
WO2022088595A1
WO2022088595A1 PCT/CN2021/082537 CN2021082537W WO2022088595A1 WO 2022088595 A1 WO2022088595 A1 WO 2022088595A1 CN 2021082537 W CN2021082537 W CN 2021082537W WO 2022088595 A1 WO2022088595 A1 WO 2022088595A1
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fpga
pad
tested
boundary scan
test
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PCT/CN2021/082537
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English (en)
French (fr)
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赵世赟
刘蒲霞
傅启攀
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深圳市紫光同创电子有限公司
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Priority to JP2023515556A priority Critical patent/JP2023539923A/ja
Publication of WO2022088595A1 publication Critical patent/WO2022088595A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318597—JTAG or boundary scan test of memory devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns

Definitions

  • the present application relates to the field of chip testing, and in particular, to a boundary scan testing method.
  • JTAG Joint Test Action Group, Joint Test Working Group
  • JTAG test refers to applying test stimulus and analyzing test response through JTAG pins, so as to realize fault diagnosis of the circuit under test.
  • Boundary scan test refers to the test of digital circuits by using the boundary scan unit of the chip pin (PAD) through the JTAG bus. Boundary scan testing has the advantages of simplicity and speed, which can cover the entire product cycle of R&D, production, and maintenance, and can greatly reduce product testing costs.
  • the boundary scan unit is placed on the input port, output port, bidirectional port and tri-state port of the device signal; the boundary scan unit is connected together to form a boundary scan chain.
  • boundary scan testing is implemented by hardware; however, implementing boundary scan by hardware has a relatively large disadvantage. First, since the boundary scan test needs to be performed on all PADs, the test time is long; secondly, the test arrangement is inflexible, and the PADs to be tested cannot be configured.
  • the present application provides a boundary scan test method, so as to complete the boundary scan test more quickly, test only the PADs that need to be tested, and skip the PADs that do not need to be tested.
  • the present application provides a boundary scan test method for testing the connectivity of the first device to the second device PAD, which is characterized by comprising the following steps:
  • the loading test instruction is to test the connectivity of the output PAD to be tested to the input PAD to be tested;
  • the first device is the upper-level device of the FPGA
  • the second device is the FPGA
  • the output PAD to be tested is the output PAD of the upper-level device of the FPGA to be tested
  • the input PAD to be tested is the Describe the input PAD of the FPGA to be tested
  • the step S10 includes: configuring the FPGA to enter a test mode through a JTAG daisy chain, and editing a user logic function so that the FPGA to be tested input PAD is connected to the last multiplexing or general PAD on the boundary scan chain of the FPGA;
  • the step S30 includes: inputting a test stimulus, entering the EXTEST instruction, moving the test stimulus into and updating the boundary scan register of the output PAD of the upper-level device of the FPGA to be tested; updating the test stimulus to the input of the FPGA to be tested In the boundary scan register of the PAD; enter the INTEST instruction, and move the test stimulus to the last multiplexed or general PAD on the boundary scan chain of the FPGA through the bypass circuit.
  • the first device is the upper-level device of the FPGA
  • the second device is the lower-level device of the FPGA
  • the output PAD to be tested is the output PAD of the upper-level device of the FPGA to be tested
  • the input PAD to be tested Input PAD for the FPGA lower-level device to be tested
  • the step S30 includes: inputting a test stimulus, entering the EXTEST instruction, moving and updating the test stimulus into the boundary scan register of the PAD output PAD of the upper-level device of the FPGA; updating the test stimulus to the lower-level device of the FPGA Input PAD to be tested.
  • the first device is the FPGA
  • the second device is the upper-level device of the FPGA
  • the output PAD to be tested is the output PAD to be tested of the FPGA
  • the input PAD to be tested is the FPGA The input PAD of the upper-level device to be tested
  • the step S10 includes: configuring the FPGA to enter the test mode through a JTAG daisy chain, and editing the user logic function to connect the first multiplexed or general PAD on the boundary scan chain of the FPGA to the FPGA to be tested output PAD and the FPGA The last multiplexed or general-purpose PAD on the boundary scan chain;
  • the step S30 includes: inputting a test stimulus, entering the INTEST instruction, moving and updating the test stimulus into the boundary scan register of the first multiplexed or general-purpose PAD on the boundary scan chain of the FPGA;
  • the bypass circuit is updated to the boundary scan register of the output PAD of the FPGA to be tested;
  • the EXTEST instruction is entered, and the test stimulus is moved into the boundary scan register of the input PAD of the upper-level device of the FPGA to be tested;
  • the test stimulus is Move into the boundary scan register of the first multiplexing or general-purpose PAD on the boundary scan chain of the FPGA; enter the INTEST instruction, and capture the test excitation to the last complex boundary scan chain of the FPGA through the bypass circuit.
  • Use or Universal PAD Use or Universal PAD.
  • the first device is the FPGA
  • the second device is the lower-level device of the FPGA
  • the output PAD to be tested is the output PAD to be tested of the FPGA
  • the input PAD to be tested is the FPGA The input PAD of the lower-level device to be tested
  • the step S10 includes: configuring the FPGA to enter a test mode through a JTAG daisy chain, and editing a user logic function to connect the first multiplexed or general PAD on the boundary scan chain of the FPGA to the output PAD to be tested on the FPGA;
  • the step S30 includes: inputting a test stimulus, entering the INTEST instruction, moving and updating the test stimulus into the boundary register of the first multiplexing or general-purpose PAD on the boundary scan chain of the FPGA; passing the test stimulus through The bypass circuit is updated into the boundary scan register of the output PAD to be tested of the FPGA; the EXTEST instruction is entered to capture the test stimulus into the input PAD of the lower-level device of the FPGA to be tested.
  • the first device is the FPGA lower-level device
  • the second device is the FPGA upper-level device
  • the output PAD to be tested is the output PAD of the FPGA lower-level device to be tested
  • the input PAD to be tested Input PAD for the FPGA upper-level device to be tested
  • the step S10 includes: configuring the FPGA to enter the test mode through the JTAG daisy chain, and editing the user logic function to connect the first multiplexer on the boundary scan chain of the FPGA or the last multiplexer on the boundary scan chain of the FPGA to the general PAD. Use or generic PAD;
  • the step S30 includes: inputting a test stimulus, entering the INTEST instruction, moving and updating the test stimulus into the boundary scan register of the first multiplexed or general-purpose PAD on the boundary scan chain of the FPGA; Capture into the boundary scan register of the last multiplexed or general-purpose PAD on the boundary scan chain of the FPGA through the bypass circuit; move and update the test stimulus to the output PAD of the FPGA lower-level device to be tested; enter the EXTEST instruction , the test stimulus is captured in the boundary scan register of the input PAD of the upper-level device of the FPGA to be tested; the test stimulus is moved into and updated to the boundary of the first multiplexing or general-purpose PAD on the boundary scan chain of the FPGA In the scan register; enter the INTEST instruction, and capture the test stimulus through the bypass circuit into the boundary scan register of the last multiplexing or general PAD on the boundary scan chain of the FPGA.
  • the first device is the lower-level device of the FPGA
  • the second device is the FPGA
  • the output PAD to be tested is the output PAD of the lower-level device of the FPGA to be tested
  • the input PAD to be tested is the Describe the input PAD of the FPGA to be tested
  • the step S10 includes: configuring the FPGA to enter the test mode through the JTAG daisy chain, and editing the user logic function to connect the first multiplexing or general PAD on the boundary scan chain of the FPGA to the last one on the boundary scan chain of the FPGA.
  • a multiplexing or general-purpose PAD, the input PAD to be tested of the FPGA is connected to the penultimate multiplexing or general-purpose PAD on the boundary scan chain of the FPGA;
  • the step S30 includes: inputting test excitation; entering the INTEST instruction, moving and updating the test excitation into the boundary scan register of the first multiplexing or general-purpose PAD on the boundary scan chain of the FPGA; passing the bypass circuit Capture the test excitation into the last multiplexing or general-purpose PAD on the boundary scan chain of the FPGA; move the test excitation into and update it into the boundary scan register of the output PAD of the FPGA lower-level device to be tested; enter the EXTEST instruction , capture and update the test stimulus into the boundary scan register of the input PAD to be tested in the FPGA; enter the INTEST instruction to capture the test stimulus into the boundary scanner of the penultimate multiplexing or general-purpose PAD of the FPGA.
  • the present application provides a boundary scan test method.
  • the boundary scan test method performs function editing in the FPGA user logic, sets a bypass circuit, and removes the PAD that is not to be tested through the bypass circuit.
  • the present application shortens the boundary scan chain to achieve faster and more flexible boundary scan testing and improve testing efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.
  • Fig. 1 is the flow chart of the boundary scan test method of the present application
  • Fig. 3 is the schematic diagram of the second embodiment of the application.
  • Fig. 5 is the schematic diagram of the fourth embodiment of the application.
  • Embodiment 5 of the application is a schematic diagram of Embodiment 5 of the application.
  • FIG. 7 is a schematic diagram of Embodiment 6 of the present application.
  • FIG. 1 is a flowchart of the boundary scan testing method of the present application.
  • the present application provides a boundary scan test method for testing the connectivity of a first device to a second device PAD, including the following steps:
  • the loading test instruction is to test the connectivity of the output PAD to be tested to the input PAD to be tested;
  • FIG. 2 is a schematic diagram of a boundary scan testing method according to Embodiment 1 of the present application.
  • the first device is an FPGA upper-level device
  • the second device is an FPGA; test the connection between the output PAD (output PAD S) of the upper-level device of the FPGA to be tested and the input PAD (input PAD D) of the FPGA to be tested sex.
  • the boundary scan test is implemented through the following steps:
  • PAD E is the last multiplexed or general PAD on the boundary scan chain of the FPGA.
  • the loading test instruction is to test the connectivity of the output PAD S of the upper-level device of the FPGA to the FPGA input PAD D;
  • Input the test stimulus enter the EXTEST (external test) command, enter the SHIFT-DR (shift) state, move the test stimulus to the boundary scan register of the output PAD S, enter the UPDATE-DR (data update) state, and change the test
  • the stimulus is updated to the boundary scan register of the output PAD S; enter the CAPTURE-DR (data acquisition) state, capture the test stimulus into the boundary scan register of the input PAD D, enter the UPDATE-DR state, and update the test stimulus to the input PAD D
  • enter the INTEST instruction enter the SHIFT-DR state from the CAPTURE-DR state, and move the test stimulus to the boundary scan chain output PAD E of the FPGA through the bypass circuit.
  • the EXTEST instruction is used to realize the interconnection test between the PADs of different devices. Before executing the EXTEST command, it is necessary to perform the PRELOAD (preload) command operation to preload the test stimulus. Once the EXTEST command is in effect, the preloaded test stimulus is moved to the output PAD, ensuring that the output PAD state is controllable.
  • PRELOAD preload
  • the INTEST instruction uses the boundary scan register as the input and output of the device to implement static testing of the system logic. Before executing the INTEST command, it is necessary to perform the PRELOAD command operation to pre-install the test stimulus. Once the INTEST command is in effect, the preloaded test stimulus is moved to the input PAD, ensuring that the input PAD state is controllable.
  • This embodiment edits the user logic function in the FPGA to connect the input PAD D to the output PAD E, set a bypass circuit, and remove the PAD that is not to be tested through the bypass circuit.
  • the boundary scan chain is shortened, so as to realize a faster and more flexible boundary scan test and improve the test efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.
  • FIG. 3 is a boundary scan test method according to Embodiment 2 of the present application.
  • the first device is an FPGA upper-level device
  • the second device is an FPGA lower-level device
  • the test output PAD (output PAD S) of the FPGA upper-level device is tested to the under-test input PAD (input PAD S) of the FPGA lower-level device D) connectivity.
  • the boundary scan test is implemented through the following steps:
  • the load test instruction is to test the connectivity of the output PAD S of the upper-level device of the FPGA to the input PAD D of the lower-level device of the FPGA;
  • test stimulus input the test stimulus; enter the EXTEST instruction, enter the SHIFT-DR state, move the test stimulus to the boundary scan register of the output PAD S, enter the UPDATE-DR state, and update the test stimulus to the boundary scan register of the output PAD S; Enter the CAPTURE-DR (data acquisition) state, capture the test stimulus to the input pad D, enter the UPDATE-DR state, and update the test stimulus to the boundary scan register of the input pad D;
  • the boundary scan chain is shortened, so as to realize a faster and more flexible boundary scan test and improve the test efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.
  • the first device is an FPGA
  • the second device is an upper-level device of the FPGA
  • the output PAD (output PAD S) of the FPGA to be tested is tested to the input PAD (input PAD D) of the upper-level device of the FPGA to be tested.
  • Connectivity is a boundary scan test method according to Embodiment 3 of the present application.
  • the boundary scan test is implemented through the following steps:
  • PAD H is the first multiplexing or general PAD on the boundary scan chain of the FPGA
  • PAD E is the last multiplexing or general PAD on the boundary scan chain of the FPGA.
  • the load test instruction is to test the connectivity of the FPGA output PAD S to the FPGA upper-level device input PAD D;
  • the editing user logic function is to connect the input PAD H to the output PAD S and PAD E, set up a bypass circuit, and remove the PAD that is not to be tested through the bypass circuit.
  • the boundary scan chain is shortened, so as to realize a faster and more flexible boundary scan test and improve the test efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.
  • the first device is an FPGA
  • the second device is a subordinate device of the FPGA
  • the output PAD (output PAD S) of the FPGA to be tested is tested to the input PAD (input PAD D) of the subordinate device of the FPGA to be tested.
  • Connectivity is a boundary scan test method according to Embodiment 4 of the present application.
  • the boundary scan test is implemented through the following steps:
  • PAD H is the first multiplexed or general-purpose PAD on the boundary scan chain of the FPGA.
  • the load test command is to test the connectivity of the FPGA output PAD S to the FPGA lower-level device input PAD D;
  • the editing user logic function is that the input PAD H is connected to the output PAD S, a bypass circuit is set, and the PAD that does not need to be tested is removed through the bypass circuit.
  • the boundary scan chain is shortened, so as to realize a faster and more flexible boundary scan test and improve the test efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.
  • the first device is an FPGA lower-level device
  • the second device is an FPGA upper-level device
  • the test output PAD (output PAD S) of the FPGA lower-level device is tested to the under-test input PAD (input PAD S) of the FPGA upper-level device PAD D) connectivity.
  • the boundary scan test is implemented through the following steps:
  • PAD H is the first multiplexing or general PAD on the boundary scan chain of the FPGA
  • PAD E is the last multiplexing or general PAD on the boundary scan chain of the FPGA.
  • the loading test instruction is to test the connectivity of the output PAD S of the lower-level device of the FPGA to the input PAD D of the upper-level device of the FPGA;
  • the editing user logic function is that the input PAD H is connected to the output PAD E, a bypass circuit is set, and the PAD that does not need to be tested is removed through the bypass circuit.
  • the boundary scan chain is shortened, so as to realize a faster and more flexible boundary scan test and improve the test efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.
  • the first device is an FPGA lower-level device
  • the second device is an FPGA
  • the output PAD (output PAD S) of the FPGA lower-level device to be tested is tested to the under-tested input PAD (input PAD D) of the FPGA.
  • Connectivity is a boundary scan test method according to Embodiment 6 of the present application.
  • the first device is an FPGA lower-level device
  • the second device is an FPGA
  • the output PAD (output PAD S) of the FPGA lower-level device to be tested is tested to the under-tested input PAD (input PAD D) of the FPGA.
  • Connectivity is a boundary scan test method according to Embodiment 6 of the present application.
  • the boundary scan test is implemented through the following steps:
  • PAD H is the first multiplexed or general PAD on the boundary scan chain of the FPGA
  • PAD E is the last multiplexed or general PAD on the boundary scan chain of the FPGA
  • PAD E1 is the reciprocal of the boundary scan chain of the FPGA A second multiplexed or general PAD.
  • the load test instruction is to test the connectivity of the output PAD S of the lower-level device of the FPGA to the FPGA input PAD D;
  • the editing user logic function is that the input PAD H is connected to the output PAD E, the input PAD D is connected to the output PAD E1, and the PAD that does not need to be tested is removed through the bypass circuit.
  • the boundary scan chain is shortened, so as to realize a faster and more flexible boundary scan test and improve the test efficiency. And it can be flexibly arranged to test the PAD without having to test all the PADs.

Abstract

一种边界扫描测试方法，用于测试第一器件到第二器件PAD的连通性，包括以下步骤：配置FPGA进入测试模式，编辑用户逻辑功能，设置旁路电路(S10)；选择待测PAD，载入测试指令为测试待测输出PAD到待测输入PAD的连通性(S20)；输入测试激励(S30)；将测试激励通过FPGA下级器件的TDO移出(S40)；进行响应分析和故障诊断(S50)。通过编辑用户逻辑功能，设置旁路电路，将不需要测试的PAD旁路，缩短了测试扫描链，加快测试速度，提高了测试灵活性。

Description

边界扫描测试方法 技术领域
本申请涉及芯片测试领域，特别是涉及一种边界扫描测试方法。
背景技术
JTAG(Joint Test Action Group，联合测试工作组)是一种国际标准测试协议(IEEE 1149.1兼容)，主要用于芯片内部测试。目前大多数的高级器件都支持JTAG协议，如DSP、FPGA器件等。JTAG测试，指通过JTAG管脚，施加测试激励和分析测试响应，从而实现待测电路的故障诊断。边界扫描测试(BST)，指通过JTAG总线，利用芯片管脚(PAD)的边界扫描单元，实现对数字电路的测试。边界扫描测试具有简便快捷的优点，可实现研发、生产、维护整个产品周期的覆盖，可大大降低产品的测试成本。边界扫描单元放置于器件信号的输入端口、输出端口、双向端口、三态端口；将边界扫描单元连接在一起，构成边界扫描链。目前，边界扫描测试由硬件实现；但是，通过硬件实现边界扫描有比较大的缺点。首先，由于需要对所有PAD均进行边界扫描测试，导致测试时间长；其次，测试安排不灵活，无法配置需要测试的PAD。
鉴于此，亟需一种新的边界扫描测试方法来解决上述问题，以实现更加快速、灵活的边界扫描测试，提高测试效率。
申请内容
基于此，本申请提供一种边界扫描测试方法，以实现更加快速地完成边界扫描测试，仅对需要测试的PAD进行测试，跳过不需要测试的PAD。
为达到上述目的，本申请提供了一种边界扫描测试方法，用于测试第一器件到第二器件PAD的连通性，其特征在于，包括以下步骤：
S10、配置FPGA进入测试模式，通过编辑用户逻辑功能设置旁路电路；
S20、载入测试指令为测试待测输出PAD到待测输入PAD的连通性；
S30、输入测试激励；
S40、将所述测试激励通过所述FPGA下级器件的TDO移出；
S50、进行响应分析和故障诊断。
优选地，所述第一器件为所述FPGA上级器件，所述第二器件为所述FPGA，所述待测输出PAD为所述FPGA上级器件待测输出PAD，所述待测输入PAD为所述FPGA待测输入PAD；
所述S10步骤包括：通过JTAG菊花链配置所述FPGA进入测试模式，编辑用户逻辑功能为所述FPGA待测输入PAD连接到所述FPGA的边界扫描链上最后一个复用或通用PAD；
所述S30步骤包括：输入测试激励，进入EXTEST指令，将所述测试激励移入并更新到所述FPGA上级器件待测输出PAD的边界扫描寄存器；将所述测试激励更新到所述FPGA待测输入PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励通过旁路电路移至所述FPGA的边界扫描链上最后一个复用或通用PAD。
优选地，所述第一器件为所述FPGA上级器件，所述第二器件为所述FPGA下级器件，所述待测输出PAD为所述FPGA上级器件待测输出PAD，所述待测输入PAD为所述FPGA下级器件待测输入PAD；
所述S30步骤包括：输入测试激励，进入EXTEST指令，将所述测试激励移入并更新到所述FPGA上级器件待测输出PAD的边界扫描寄存器中；将所述 测试激励更新到所述FPGA下级器件待测输入PAD。
优选地，所述第一器件为所述FPGA，所述第二器件为所述FPGA上级器件，所述待测输出PAD为所述FPGA待测输出PAD，所述待测输入PAD为所述FPGA上级器件待测输入PAD；
所述S10步骤包括：通过JTAG菊花链配置所述FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上第一个复用或通用PAD连接到所述FPGA待测输出PAD和FPGA的边界扫描链上最后一个复用或通用PAD；
所述S30步骤包括：输入测试激励，进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；将所述测试激励通过旁路电路更新到所述FPGA待测输出PAD的边界扫描寄存器中；进入EXTEST指令，将所述测试激励移入到所述FPGA上级器件待测输入PAD的边界扫描寄存器中；将所述测试激励移入到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励通过旁路电路捕获到所述FPGA的边界扫描链上最后一个复用或通用PAD。
优选地，所述第一器件为所述FPGA，所述第二器件为所述FPGA下级器件，所述待测输出PAD为所述FPGA待测输出PAD，所述待测输入PAD为所述FPGA下级器件待测输入PAD；
所述S10步骤包括：通过JTAG菊花链配置所述FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上第一个复用或通用PAD连接到所述FPGA待测输出PAD；
所述S30步骤包括：输入测试激励，进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界寄存器 中；将所述测试激励通过旁路电路更新到所述FPGA待测输出PAD的边界扫描寄存器中；进入EXTEST指令，将所述测试激励捕获到所述FPGA下级器件待测输入PAD中。
优选地，所述第一器件为所述FPGA下级器件，所述第二器件为所述FPGA上级器件，所述待测输出PAD为所述FPGA下级器件待测输出PAD，所述待测输入PAD为所述FPGA上级器件待测输入PAD；
所述S10步骤包括：通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上第一个复用或通用PAD连接到所述FPGA的边界扫描链上最后一个复用或通用PAD；
所述S30步骤包括：输入测试激励，进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；将所述测试激励通过旁路电路捕获到所述FPGA的边界扫描链上最后一个复用或通用PAD的边界扫描寄存器中；将所述测试激励移入并更新到所述FPGA下级器件待测输出PAD中；进入EXTEST指令，将所述测试激励捕获到所述FPGA上级器件待测输入PAD的边界扫描寄存器中；将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励通过旁路电路捕获到所述FPGA的边界扫描链上最后一个复用或通用PAD的边界扫描寄存器中。
优选地，所述第一器件为所述FPGA下级器件，所述第二器件为所述FPGA，所述待测输出PAD为所述FPGA下级器件待测输出PAD，所述待测输入PAD为所述FPGA待测输入PAD；
所述S10步骤包括：通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上的第一个复用或通用PAD连接到所述 FPGA的边界扫描链上的最后一个复用或通用PAD，所述FPGA待测输入PAD连接到所述FPGA的边界扫描链上的倒数第二个复用或通用PAD；
所述S30步骤包括：输入测试激励；进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上的第一个复用或通用PAD的边界扫描寄存器中；通过旁路电路将所述测试激励捕获到FPGA的边界扫描链上的最后一个复用或通用PAD中；将所述测试激励移入并更新到所述FPGA下级器件待测输出PAD的边界扫描寄存器中；进入EXTEST指令，将所述测试激励捕获并更新到所述FPGA待测输入PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励捕获到FPGA倒数第二个复用或通用PAD的边界扫描器中。
本申请的有益效果在于：本申请提供了一种边界扫描测试方法，该边界扫描测试方法通过在FPGA用户逻辑进行功能编辑，设置旁路电路，将不用测试的PAD通过旁路电路去掉。本申请缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
附图说明
图1为本申请的边界扫描测试方法的流程图；
图2为本申请实施例一的示意图；
图3为本申请实施例二的示意图；
图4为本申请实施例三的示意图；
图5为本申请实施例四的示意图；
图6为本申请实施例五的示意图；
图7为本申请实施例六的示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
请参见图1，为本申请边界扫描测试方法的流程图。本申请提供了一种边界扫描测试方法，用于测试第一器件到第二器件PAD的连通性，包括以下步骤：
S10、配置FPGA进入测试模式，编辑用户逻辑功能，设置旁路电路；
S20、载入测试指令为测试待测输出PAD到待测输入PAD的连通性；
S30、通过TDI(测试数据输入)输入测试激励；
S40、将测试激励通过FPGA下级器件的TDO(测试数据输出)移出；
S50、进行响应分析和故障诊断。
本申请通过编辑用户逻辑功能连接测试所需的PAD，将不需要测试的PAD通过旁路电路跳过，缩短了边界扫描测试的扫描链，加快了测试的速度和灵活性。下面将结合更加具体的实施例对本申请的步骤进更深一步的阐述。
实施例一
请参见图2，为本申请实施例一的边界扫描测试方法示意图。具体地，本实施例中，第一器件为FPGA上级器件，第二器件为FPGA；测试FPGA上级器件的待测输出PAD(输出PAD S)到FPGA的待测输入PAD(输入PAD D)的连 通性。
具体地，通过以下步骤来实现边界扫描测试：
S10、通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为输入PAD D连接输出PAD E，设置旁路电路。其中，PAD E为FPGA的边界扫描链上的最后一个复用或通用PAD。
S20、载入测试指令为测试FPGA上级器件输出PAD S到FPGA输入PAD D的连通性；
S30、输入测试激励，进入EXTEST(外测试)指令，进入SHIFT-DR(移位)状态，将测试激励移到输出PAD S的边界扫描寄存器后，进入UPDATE-DR(数据更新)状态，将测试激励更新到输出PAD S的边界扫描寄存器中；进入CAPTURE-DR(数据采集)状态，将测试激励捕获到输入PAD D的边界扫描寄存器中，进入UPDATE-DR状态，将测试激励更新到输入PAD D的边界扫描寄存器中；进入INTEST指令，从CAPTURE-DR状态进入SHIFT-DR状态，通过旁路电路将测试激励移至FPGA的边界扫描链输出PAD E。
其中，EXTEST指令用于实现不同器件PAD间的互连测试。在进行EXTEST指令之前，需要进行PRELOAD(预装)指令操作，预装测试激励。一旦EXTEST指令生效，预装的测试激励就会被移到输出PAD，从而确保输出PAD状态可控。
INTEST指令将边界扫描寄存器作为器件的输入和输出，实现对系统逻辑的静态测试。在进行INTEST指令之前，需要进行PRELOAD指令操作，预装测试激励。一旦INTEST指令生效，预装的测试激励就会被移到输入PAD，从而确保输入PAD状态可控。
S40、进入SHIFT-DR状态，将测试激励通过FPGA下级器件的TDO移出；
S50、进行响应分析和故障诊断。
本实施例在FPGA编辑用户逻辑功能为输入PAD D连接输出PAD E，设置旁路电路，将不用测试的PAD通过旁路电路去掉。本实施例缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
实施例二
请参见图3，为本申请实施例二的边界扫描测试方法。具体地，本实施例中，第一器件为FPGA上级器件，第二器件为FPGA下级器件；测试FPGA上级器件的待测输出PAD(输出PAD S)到FPGA下级器件的待测输入PAD(输入PAD D)的连通性。
具体地，通过以下步骤来实现边界扫描测试：
S10、配置FPGA进入测试模式，
S20、载入测试指令为测试FPGA上级器件输出PAD S到FPGA下级器件输入PAD D的连通性；
S30、输入测试激励；进入EXTEST指令，进入SHIFT-DR状态，将测试激励移到输出PAD S的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输出PAD S的边界扫描寄存器中；进入CAPTURE-DR(数据采集)状态，将测试激励捕获到输入PAD D，进入UPDATE-DR状态，将测试激励更新到输入PAD D的边界扫描寄存器中；
S40、进入SHIFT-DR状态，将测试激励通过FPGA下级器件的TDO移出；
S50、进行响应分析和故障诊断。
本实施例缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
实施例三
请参见图4，为本申请实施例三的边界扫描测试方法。具体地，在本实施例中，第一器件为FPGA，第二器件为FPGA上级器件；测试FPGA的待测输出PAD(输出PAD S)到FPGA上级器件的待测输入PAD(输入PAD D)的连通性。
具体地，通过以下步骤来实现边界扫描测试：
S10、通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为输入PAD H连接输出PAD S和PAD E，设置旁路电路。其中，PAD H为FPGA的边界扫描链上的第一个复用或通用PAD，PAD E为FPGA的边界扫描链上的最后一个复用或通用PAD。
S20、载入测试指令为测试FPGA输出PAD S到FPGA上级器件输入PAD D的连通性；
S30、输入测试激励；进入INTEST指令，进入SHIFT-DR状态，将测试激励移到输入PAD H的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输入PAD H的边界扫描寄存器中；通过旁路电路将测试激励更新到输出PAD S的边界扫描寄存器中；进入EXTEST指令，将测试激励移入到PAD D的边界扫描寄存器中；将测试激励移到输入PAD H的边界扫描寄存器；进入INTEST指令，进入UPDATE-DR状态，将测试激励更新到输入PAD H的边界扫描寄存器中；进入CAPTURE-DR状态，通过旁路电路将测试激励捕获到输出PAD E的边界扫描寄存器中；
S40、进入SHIFT-DR状态，将测试激励通过FPGA下级器件的TDO移出；
S50、进行响应分析和故障诊断。
本实施例在编辑用户逻辑功能为输入PAD H连接输出PAD S和PAD E，设置旁路电路，将不用测试的PAD通过旁路电路去掉。本实施例缩短了边界扫 描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
实施例四
请参见图5，为本申请实施例四的边界扫描测试方法。具体地，在本实施例中，第一器件为FPGA，第二器件为FPGA下级器件；测试FPGA的待测输出PAD(输出PAD S)到FPGA下级器件的待测输入PAD(输入PAD D)的连通性。
具体地，通过以下步骤来实现边界扫描测试：
S10、通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为输入PAD H连接输出PAD S，设置旁路电路。其中，PAD H为FPGA的边界扫描链上的第一个复用或通用PAD。
S20、载入测试指令为测试FPGA输出PAD S到FPGA下级器件输入PAD D的连通性；
S30、输入测试激励；进入INTEST指令，进入SHIFT-DR状态，将测试激励移到输入PAD H的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输入PAD H的边界扫描寄存器中；进入CAPTURE-DR状态，通过旁路电路将测试激励捕获到输出PAD S的边界扫描寄存器中；进入UPDATE-DR状态，将测试激励更新到输出PAD S的边界扫描寄存器中；进入EXTEST指令，进入CAPTURE-DR状态，将测试激励捕获到输入PAD D的边界扫描寄存器中。
S40、进入SHIFT-DR状态，通过FPGA下级器件的TDO移出；
S50、进行响应分析和故障诊断。
本实施例在编辑用户逻辑功能为输入PAD H连接输出PAD S，设置旁路 电路，将不用测试的PAD通过旁路电路去掉。本实施例缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
实施例五
请参见图6，为本申请实施例五的边界扫描测试方法。具体地，在本实施例中，第一器件为FPGA下级器件，第二器件为FPGA上级器件；测试FPGA下级器件的待测输出PAD(输出PAD S)到FPGA上级器件的待测输入PAD(输入PAD D)的连通性。
具体地，通过以下步骤来实现边界扫描测试：
S10、通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为输入PAD H连接输出PAD E，设置旁路电路。其中，PAD H为FPGA的边界扫描链上的第一个复用或通用PAD，PAD E为FPGA的边界扫描链上的最后一个复用或通用PAD。
S20、载入测试指令为测试FPGA下级器件输出PAD S到FPGA上级器件输入PAD D的连通性；
S30、输入测试激励；进入INTEST指令，进入SHIFT-DR状态，将测试激励移到输入PAD H的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输入PAD H的边界扫描寄存器中；进入CAPTURE-DR状态，通过旁路电路将测试激励捕获到输出PAD E的边界扫描寄存器中；进入SHIFT-DR状态，将测试激励移到输出PAD S的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输出PAD S的边界扫描寄存器中；进入EXTEST指令，进入CAPTURE-DR状态，将测试激励捕获到输入PAD D的边界扫描寄存器中；进入SHIFT-DR状态，将测试激励移到输入PAD H的边界扫描寄存器后， 进入UPDATE-DR状态，将测试激励更新到输入PAD H的边界扫描寄存器中；进入INTEST指令，进入CAPTURE-DR状态，通过旁路电路将测试激励捕获到输出PAD E的边界扫描寄存器中；
S40、进入SHIFT-DR状态，将测试激励通过FPGA下级器件的TDO移出；
S50、进行响应分析和故障诊断。
本实施例在编辑用户逻辑功能为输入PAD H连接输出PAD E，设置旁路电路，将不用测试的PAD通过旁路电路去掉。本实施例缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
实施例六
请参见图7，为本申请实施例六的边界扫描测试方法。具体地，在本实施例中，第一器件为FPGA下级器件，第二器件为FPGA；测试FPGA下级器件的待测输出PAD(输出PAD S)到FPGA的待测输入PAD(输入PAD D)的连通性。
具体地，通过以下步骤来实现边界扫描测试：
S10、通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为输入PAD H连接输出PAD E，输入PAD D连接输出PAD E1。其中，PAD H为FPGA的边界扫描链上的第一个复用或通用PAD，PAD E为FPGA的边界扫描链上的最后一个复用或通用PAD，PAD E1为FPGA的边界扫描链上的倒数第二个复用或通用PAD。
S20、载入测试指令为测试FPGA下级器件输出PAD S到FPGA输入PAD D的连通性；
S30、输入测试激励；进入INTEST指令，进入SHIFT-DR状态，将测试激 励移到输入PAD H的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输入PAD H的边界扫描寄存器中；进入CAPTURE-DR状态，通过旁路电路将测试激励捕获到输出PAD E的边界扫描寄存器中，进入SHIFT-DR状态，将测试激励移到输出PAD S的边界扫描寄存器后，进入UPDATE-DR状态，将测试激励更新到输出PAD S的边界扫描寄存器中；进入EXTEST指令，进入CAPTURE-DR状态，将测试激励捕获到输入PAD D的边界扫描寄存器中，进入UPDATE-DR状态，将测试激励更新到输入PAD D的边界扫描寄存器中；进入INTEST指令，进入CAPTURE-DR状态，通过旁路电路将测试激励捕获到输出PAD E1的边界扫描寄存器中；
S40、进入SHIFT-DR状态，将测试激励通过下级器件的TDO移出；
S50、进行响应分析和故障诊断。
本实施例在编辑用户逻辑功能为输入PAD H连接输出PAD E，输入PAD D连接输出PAD E1，将不用测试的PAD通过旁路电路去掉。本实施例缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。而且能灵活安排测试PAD，无需对所有的PAD进行测试。
以上实施例仅表达了本申请的优选的实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (7)

  1. 一种边界扫描测试方法，用于测试第一器件到第二器件PAD的连通性，其特征在于，包括以下步骤：
    S10、配置FPGA进入测试模式，通过编辑用户逻辑功能设置旁路电路，；
    S20、载入测试指令为测试待测输出PAD到待测输入PAD的连通性；
    S30、输入测试激励；
    S40、将所述测试激励通过所述FPGA下级器件的TDO移出；
    S50、进行响应分析和故障诊断。
  2. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述第一器件为所述FPGA上级器件，所述第二器件为所述FPGA，所述待测输出PAD为所述FPGA上级器件待测输出PAD，所述待测输入PAD为所述FPGA待测输入PAD；
    所述S10步骤包括：通过JTAG菊花链配置所述FPGA进入测试模式，编辑用户逻辑功能为所述FPGA待测输入PAD连接到所述FPGA的边界扫描链上最后一个复用或通用PAD；
    所述S30步骤包括：输入测试激励，进入EXTEST指令，将所述测试激励移入并更新到所述FPGA上级器件待测输出PAD的边界扫描寄存器；将所述测试激励更新到所述FPGA待测输入PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励通过旁路电路移至所述FPGA的边界扫描链上最后一个复用或通用PAD。
  3. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述第一器件为所述FPGA上级器件，所述第二器件为所述FPGA下级器件，所述待测输出PAD为所述FPGA上级器件待测输出PAD，所述待测输入PAD为所述FPGA下级器件待测输入PAD；
    所述S30步骤包括：输入测试激励，进入EXTEST指令，将所述测试激励移入并更新到所述FPGA上级器件待测输出PAD的边界扫描寄存器中；将所述测试激励更新到所述FPGA下级器件待测输入PAD。
  4. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述第一器件为所述FPGA，所述第二器件为所述FPGA上级器件，所述待测输出PAD为所述FPGA待测输出PAD，所述待测输入PAD为所述FPGA上级器件待测输入PAD；
    所述S10步骤包括：通过JTAG菊花链配置所述FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上第一个复用或通用PAD连接到所述FPGA待测输出PAD和FPGA的边界扫描链上最后一个复用或通用PAD；
    所述S30步骤包括：输入测试激励，进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；将所述测试激励通过旁路电路更新到所述FPGA待测输出PAD的边界扫描寄存器中；进入EXTEST指令，将所述测试激励移入到所述FPGA上级器件待测输入PAD的边界扫描寄存器中；将所述测试激励移入到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励通过旁路电路捕获到所述FPGA的边界扫描链上最后一个复用或通用PAD。
  5. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述第一器件为所述FPGA，所述第二器件为所述FPGA下级器件，所述待测输出PAD为所述FPGA待测输出PAD，所述待测输入PAD为所述FPGA下级器件待测输入PAD；
    所述S10步骤包括：通过JTAG菊花链配置所述FPGA进入测试模式，编 辑用户逻辑功能为所述FPGA的边界扫描链上第一个复用或通用PAD连接到所述FPGA待测输出PAD；
    所述S30步骤包括：输入测试激励，进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界寄存器中；将所述测试激励通过旁路电路更新到所述FPGA待测输出PAD的边界扫描寄存器中；进入EXTEST指令，将所述测试激励捕获到所述FPGA下级器件待测输入PAD中。
  6. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述第一器件为所述FPGA下级器件，所述第二器件为所述FPGA上级器件，所述待测输出PAD为所述FPGA下级器件待测输出PAD，所述待测输入PAD为所述FPGA上级器件待测输入PAD；
    所述S10步骤包括：通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上第一个复用或通用PAD连接到所述FPGA的边界扫描链上最后一个复用或通用PAD；
    所述S30步骤包括：输入测试激励，进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；将所述测试激励通过旁路电路捕获到所述FPGA的边界扫描链上最后一个复用或通用PAD的边界扫描寄存器中；将所述测试激励移入并更新到所述FPGA下级器件待测输出PAD中；进入EXTEST指令，将所述测试激励捕获到所述FPGA上级器件待测输入PAD的边界扫描寄存器中；将所述测试激励移入并更新到所述FPGA的边界扫描链上第一个复用或通用PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励通过旁路电路捕获到所述FPGA的边界扫描链上最后一个复用或通用PAD的边界扫描寄存器中。
  7. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述第一器件为所述FPGA下级器件，所述第二器件为所述FPGA，所述待测输出PAD为所述FPGA下级器件待测输出PAD，所述待测输入PAD为所述FPGA待测输入PAD；
    所述S10步骤包括：通过JTAG菊花链配置FPGA进入测试模式，编辑用户逻辑功能为所述FPGA的边界扫描链上的第一个复用或通用PAD连接到所述FPGA的边界扫描链上的最后一个复用或通用PAD，所述FPGA待测输入PAD连接到所述FPGA的边界扫描链上的倒数第二个复用或通用PAD；
    所述S30步骤包括：输入测试激励；进入INTEST指令，将所述测试激励移入并更新到所述FPGA的边界扫描链上的第一个复用或通用PAD的边界扫描寄存器中；通过旁路电路将所述测试激励捕获到FPGA的边界扫描链上的最后一个复用或通用PAD中；将所述测试激励移入并更新到所述FPGA下级器件待测输出PAD的边界扫描寄存器中；进入EXTEST指令，将所述测试激励捕获并更新到所述FPGA待测输入PAD的边界扫描寄存器中；进入INTEST指令，将所述测试激励捕获到FPGA倒数第二个复用或通用PAD的边界扫描器中。
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