WO2022088594A1 - 边界扫描测试方法及存储介质 - Google Patents

边界扫描测试方法及存储介质 Download PDF

Info

Publication number
WO2022088594A1
WO2022088594A1 PCT/CN2021/082534 CN2021082534W WO2022088594A1 WO 2022088594 A1 WO2022088594 A1 WO 2022088594A1 CN 2021082534 W CN2021082534 W CN 2021082534W WO 2022088594 A1 WO2022088594 A1 WO 2022088594A1
Authority
WO
WIPO (PCT)
Prior art keywords
boundary scan
test
pad
tested
scan chain
Prior art date
Application number
PCT/CN2021/082534
Other languages
English (en)
French (fr)
Inventor
赵世赟
刘蒲霞
傅启攀
Original Assignee
深圳市紫光同创电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市紫光同创电子有限公司 filed Critical 深圳市紫光同创电子有限公司
Priority to US17/906,980 priority Critical patent/US11933845B2/en
Publication of WO2022088594A1 publication Critical patent/WO2022088594A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318597—JTAG or boundary scan test of memory devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318569—Error indication, logging circuits

Definitions

  • the present application relates to the field of chip testing, and in particular, to a boundary scan testing method and a storage medium.
  • JTAG Joint Test Action Group, Joint Test Working Group
  • JTAG test refers to applying test stimulus and analyzing test response through JTAG pins, so as to realize fault diagnosis of the circuit under test.
  • Boundary scan test refers to the test of digital circuits by using the boundary scan unit of the chip pin (PAD) through the JTAG bus. Boundary scan testing has the advantages of simplicity and speed, which can cover the entire product cycle of R&D, production, and maintenance, and can greatly reduce product testing costs.
  • the boundary scan unit is placed on the input port, output port, bidirectional port and tri-state port of the device signal; the boundary scan unit is connected together to form a boundary scan chain.
  • boundary scan testing is implemented by hardware; however, implementing boundary scan by hardware has a relatively large disadvantage. First, since the boundary scan test needs to be performed on all PADs, the test time is long; secondly, the test arrangement is inflexible, and the PADs to be tested cannot be configured.
  • the present application provides a boundary scan test method to complete the boundary scan test more quickly.
  • the application provides a boundary scan test method for testing the connectivity of the PAD that is directly connected to the user logic, comprising the following steps:
  • the boundary scan chain includes a plurality of scan chain units, and a plurality of the scan chain units are connected in series to form a scan chain.
  • the boundary scan chain includes m scan chain units, and the FPGA includes n PADs, where m ⁇ n.
  • the step of "S10, configuring the FPGA to enter the test mode” further includes:
  • the boundary scan chain test interface is called to open the channel connecting the FPGA and the user logic.
  • the step of "S20, generating a boundary scan chain for boundary scan testing through the user logic” includes:
  • a boundary scan chain corresponding to the PAD to be tested one-to-one is generated by the user logic.
  • the step of "S40, sending the first test vector to the PAD to be tested through the TDI port” includes:
  • the step of "S50, perform boundary scan test, and load the EXTEST instruction to the device for which the PAD connectivity is to be tested” further includes:
  • the "S60, remove the first response data from the TDO port, and perform response analysis and fault diagnosis” further includes:
  • the first response data is removed from the TDO port, and the next test vector is sent to the next PAD to be tested at the same time.
  • the step of "removing the first response data from the TDO port and simultaneously sending the next test vector to the next PAD to be tested” further includes:
  • the present application also provides a storage medium, where the storage medium stores at least one computer program, and when the at least one computer program is executed by the processor, implements the foregoing boundary scan testing method.
  • the beneficial effects of the present application are: a boundary scan testing method and a storage medium are provided, wherein the boundary scan testing method generates a boundary scan chain for boundary scan testing through user logic.
  • the boundary scan test method of the present application does not require hardware upgrade, and by performing software settings on the PAD to be tested in the FPGA user logic, the PAD to be tested can be tested according to the settings, and the PAD that does not need to be tested can be tested.
  • the present application shortens the boundary scan chain to achieve faster and more flexible boundary scan testing and improve testing efficiency.
  • FIG. 2 is a flowchart of step S40 of the boundary scan test method shown in FIG. 1;
  • FIG. 4 is a flowchart of step S60 of the boundary scan testing method shown in FIG. 1 .
  • FIG. 1 to FIG. 4 the boundary scan testing method according to the embodiment of the present application is shown.
  • the boundary scan test method is used to test the connectivity of the PAD that has a direct path with user logic. As shown in Figure 1, the boundary scan test method includes the following steps:
  • SCAN CHAIN GTP is the interface between the FPGA and the user logic. Call this interface to open the channel connecting the FPGA and the user logic, and configure the FPGA to enter the test mode;
  • step S20 generating a boundary scan chain for boundary scan testing by the user logic, specifically including: generating a one-to-one correspondence with the PAD to be tested according to the position and quantity of the PAD to be tested the boundary scan chain.
  • the boundary scan chain is composed of several scan chain units connected in series, and each scan chain unit includes a data unit and a control unit.
  • the SI (shift input) of the first scan chain unit of the boundary scan chain is connected to TDI
  • the SO (shift output) of the first scan chain unit is connected to the SI of the second scan chain unit
  • the SO of the second scan chain unit The SI of the third scan chain unit is connected, and so on, the SO of the mth (last) scan chain unit is connected to TDO.
  • the boundary scan chain includes m scan chain units, and the FPGA includes n PADs, where m ⁇ n. Since the boundary scan chains are generated in a one-to-one correspondence according to the PAD to be tested, the number m of scan chain units is less than or equal to n. In an optional embodiment, if the FPGA has 500 PADs, and the number of PADs to be tested is 300, it is only necessary to correspondingly generate a boundary scan chain corresponding to the PADs to be tested. That is, the number of generated scan chain units is 300. During the boundary scan test, the test vector is directly moved into the PAD to be tested by the boundary scan chain generated by the user logic, which greatly shortens the length of the boundary scan chain, saves the test time, and has higher flexibility.
  • the PAD to be tested is controlled to be an input state or an output state by the control unit.
  • the input PAD in the CAPTURE-DR (data acquisition) state, the input value is captured to the data unit, and in the UPDATE-DR (data update) state, the value of the shift register in the control unit is updated to the second-level register; for Output PAD, in the UPDATE-DR state, update the value of the shift register in the data unit and the control unit to the second-level register.
  • step S30 loads the boundary scan test instruction to the FPGA, and loads the PRELOAD instruction to the device of the PAD connectivity to be tested; wherein the device of the PAD connectivity to be tested is the device of the PAD of the PAD connectivity test of the FPGA to be tested. It is an FPGA, or it can be an upper-level device of the FPGA, a lower-level device of the FPGA, and the like.
  • step S40 sending the first test vector to the PAD under test through the TDI port includes:
  • S41 enter the SHIFT-DR (shift) state, and serially shift the first test vector into the PAD to be tested through the TDI port;
  • the test vector in the SHIFT-DR state, is moved into the boundary scan register through the boundary scan chain.
  • the test data register placed on the TDI to TDO boundary scan link is shifted one bit in the direction of TDO; the test data register is selected by the current test command, but not placed on the TDI to TDO boundary scan link , it will keep the original state.
  • step S50 performs boundary scan test, and loading the EXTEST instruction to the connected device of the PAD to be tested also includes:
  • the EXTEST instruction is used to realize the boundary scan external test, and the external test is used for the interconnection test between the PADs.
  • the PRELOAD instruction operation needs to be performed to pre-install the test vector. Once the external test instruction takes effect, the pre-installed test vector will be moved to the output PAD to ensure that the output PAD state is controllable.
  • step S60 of the boundary scan test method of this embodiment removes the first response data from the TDO (test data output) port, and performs response analysis and fault diagnosis; it also includes removing the first response data from the TDO port, and simultaneously Send the second test vector to the second PAD to be tested.
  • step S60 specifically includes:
  • S62 enter the SHIFT-DR state, serially move out the first response data, and simultaneously move in the second test vector serially, and perform data analysis and fault diagnosis on the first response data;
  • the N+1th test vector is sent for response analysis and fault diagnosis, and the test mode is ended after all the tests of the PAD to be tested are completed.
  • the boundary scan testing method of the present application can also be used for board level interconnect testing.
  • there are three test chips including an FPGA, an upper-level device, and a lower-level device; wherein the TDO of the upper-level device is connected to the TDI of the FPGA, and the TDO of the FPGA is connected to the TDI of the lower-level device; a total of 6 kinds of board-level interconnection tests Combination, including: FPGA to lower-level device, FPAG to upper-level device, lower-level device to upper-level device, lower-level device to FPGA, upper-level device to lower-level device, upper-level device to FPGA.
  • there are five test chips including FPGA1, FPGA2, device 1, device 2, and device 3; there are a total of 20 board-level interconnection test combinations.
  • a boundary scan chain corresponding to the PAD to be tested one-to-one is generated through user logic.
  • the number of PADs to be tested is 300, so it is only necessary to generate a boundary scan chain corresponding to the number of PADs to be tested. That is, the number of generated scan chain units is 300.
  • the test vector is moved into the PAD under test through the boundary scan chain generated by the user logic.
  • the load test instruction is the connectivity of the output PAD to be tested from the FPGA to the input PAD to be tested of the lower-level device, and the PRELOAD instruction is loaded to the lower-level device.
  • S60 remove the first response data from the lower-level device port, and perform response analysis and fault analysis; at the same time, send the next test vector to perform boundary scan testing until all response data output and analysis are completed.
  • the boundary scan testing method of the embodiment of the present application by performing software settings on the PAD to be tested in the FPGA user logic, the PAD to be tested can be tested according to the settings, and the PAD that does not need to be tested can be tested.
  • the present application shortens the boundary scan chain to achieve faster and more flexible boundary scan testing and improve testing efficiency.
  • the present application also provides a storage medium, where the storage medium stores at least one computer program.
  • the computer program is used to implement the boundary scan testing method described above.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

一种边界扫描测试方法，用于测试与用户逻辑有直连通路的PAD的连通性，包括以下步骤：配置FPGA进入测试模式（S10）；通过用户逻辑生成用于边界扫描测试的边界扫描链（S20）；载入边界扫描测试指令到FPGA，载入PRELOAD指令到待测PAD连通性的器件（S30）；通过TDI端口发送第一测试矢量到待测PAD（S40）；进行边界扫描测试，载入EXTEST指令到待测PAD连通的器件（S50）；从TDO端口移出第一响应数据，进行响应分析和故障诊断（S60）。通过在FPGA用户逻辑里面对待测PAD进行软件设置，即可根据设置对待测PAD进行测试，而不测试和经过不需要测试的PAD。该方法缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。

Description

边界扫描测试方法及存储介质 技术领域
本申请涉及芯片测试领域，特别是涉及一种边界扫描测试方法及存储介质。
背景技术
JTAG(Joint Test Action Group，联合测试工作组)是一种国际标准测试协议(IEEE 1149.1兼容)，主要用于芯片内部测试。目前大多数的高级器件都支持JTAG协议，如DSP、FPGA器件等。JTAG测试，指通过JTAG管脚，施加测试激励和分析测试响应，从而实现待测电路的故障诊断。边界扫描测试(BST)，指通过JTAG总线，利用芯片管脚(PAD)的边界扫描单元，实现对数字电路的测试。边界扫描测试具有简便快捷的优点，可实现研发、生产、维护整个产品周期的覆盖，可大大降低产品的测试成本。边界扫描单元放置于器件信号的输入端口、输出端口、双向端口、三态端口；将边界扫描单元连接在一起，构成边界扫描链。目前，边界扫描测试由硬件实现；但是，通过硬件实现边界扫描有比较大的缺点。首先，由于需要对所有PAD均进行边界扫描测试，导致测试时间长；其次，测试安排不灵活，无法配置需要测试的PAD。
鉴于此，亟需一种新的边界扫描测试方法来解决上述问题，以实现更加快速、灵活的边界扫描测试，提高测试效率。
申请内容
基于此，本申请提供一种边界扫描测试方法，以实现更加快速地完成边界扫描测试。
为达到上述目的，本申请提供了一种边界扫描测试方法，用于测试与用户逻辑有直连通路的PAD的连通性，包括以下步骤：
S10、配置所述FPGA进入测试模式；
S20、通过所述用户逻辑生成用于边界扫描测试的边界扫描链；
S30、载入边界扫描测试指令到所述FPGA，载入PRELOAD指令到待测PAD连通性的器件；
S40、通过TDI端口发送第一测试矢量到所述待测PAD；
S50、进行边界扫描测试，载入EXTEST指令到所述待测PAD连通的器件；
S60、从TDO端口移出第一响应数据，进行响应分析和故障诊断。
优选的，所述边界扫描链包括若干个扫描链单元，若干个所述扫描链单元串联组成扫描链。
优选的，所述边界扫描链包括m个所述扫描链单元，所述FPGA包括n个PAD，其中，m≤n。
优选的，所述“S10、配置所述FPGA进入测试模式”步骤还包括：
调用边界扫描链测试接口，打开所述FPGA与所述用户逻辑连接的通道。
优选的，所述“S20、通过所述用户逻辑生成用于边界扫描测试的边界扫描链”步骤包括：
根据所述待测PAD的位置和数量，通过所述用户逻辑生成一条与所述待测PAD一一对应的边界扫描链。
优选的，所述“S40、通过TDI端口发送第一测试矢量到所述待测PAD”步骤包括：
进入SHIFT-DR状态，通过TDI端口串行移入所述第一测试矢量；
进入UPDATE-DR状态，将所述第一测试矢量并行更新到所述边界扫描链 的边界扫描寄存器中。
优选的，所述“S50、进行边界扫描测试，载入EXTEST指令到所述待测PAD连通性的器件”步骤还包括：
载入EXTEST指令到所述待测连通性的器件；
加载第一测试矢量，进行外测试。
优选的，所述“S60、从TDO端口移出第一响应数据，进行响应分析和故障诊断”还包括：
从所述TDO端口移出所述第一响应数据，同时发送下一测试矢量至下一待测PAD。
优选的，所述“从所述TDO端口移出所述第一响应数据，同时发送下一测试矢量至所述下一待测PAD”步骤还包括：
进入CAPTURE-DR状态，将所述第一响应数据并行捕获到所述边界扫描链的边界扫描寄存器中；
进入SHIFT-DR状态，将所述第一响应数据串行移出，同时将所述下一测试矢量串行移入所述下一待测PAD；
进入UPDATE-DR状态，将所述下一测试矢量并行更新到所述边界扫描链的边界扫描寄存器中。
本申请还提供了一种存储介质，所述存储介质存储有至少一个计算机程序，所述至少一个计算机程序被处理器执行时实现上述的边界扫描测试方法。
本申请的有益效果在于：提供了一种边界扫描测试方法和存储介质，该边界扫描测试方法通过用户逻辑生成用于边界扫描测试的边界扫描链。本申请的边界扫描测试方法不需要进行硬件升级，通过在FPGA用户逻辑里面对待测PAD进行软件设置，即可根据设置对待测PAD进行测试，而不测试和经过不需要测 试的PAD。本申请缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。
附图说明
图1为本申请实施例的边界扫描测试流程图；
图2为图1所示的边界扫描测试方法步骤S40的流程图；
图3为图1所示的边界扫描测试方法步骤S50的流程图；
图4为图1所示的边界扫描测试方法步骤S60的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
如图1至图4所示，为本申请实施例的边界扫描测试方法。
该边界扫描测试方法用于测试与用户逻辑有直接通路的PAD的连通性，如图1所示，该边界扫描测试方法包括以下步骤：
S10、调用SCAN CHAIN GTP接口，SCAN CHAIN GTP为FPGA与用户逻辑之间的接口，调用该接口，即可打开FPGA与用户逻辑相连接的通道，配置FPGA进入测试模式；
S20、通过用户逻辑生成用于边界扫描测试的边界扫描链；
S30、载入边界扫描测试指令到FPGA，载入PRELOAD(预装)指令到待测PAD连通性的器件；
S40、通过TDI(测试数据输入)端口发送第一测试矢量到待测PAD；
S50、进行边界扫描测试，载入EXTEST(外测试)指令到所述待测PAD连通性的器件，将第一测试矢量移入连通性测试的器件PAD上；
S60、从TDO(测试数据输出)端口移出第一响应数据，进行响应分析和故障诊断。
进一步地，步骤S20、通过所述用户逻辑生成用于边界扫描测试的边界扫描链，具体包括：根据所述待测PAD的位置和数量，通过用户逻辑生成一条与所述待测PAD一一对应的边界扫描链。边界扫描链由若干扫描链单元串联组成，每一个扫描链单元包括一个数据单元和一个控制单元。边界扫描链第一个扫描链单元的SI(移位输入)连接TDI，第一个扫描链单元的SO(移位输出)连接第二个扫描链单元的SI，第二个扫描链单元的SO连接第三个扫描链单元的SI，以此类推，第m个(最后一个)扫描链单元的SO连接TDO。
进一步地，所述边界扫描链包括m个扫描链单元，FPGA包括n个PAD，其中，m≤n。由于边界扫描链根据待测PAD一一对应生成，所以扫描链单元数量m小于等于n。在一可选实施例中，FPGA有500个PAD，其中待测的PAD数量为300个，则仅需要对应生成与待测PAD对应的边界扫描链。即，生成的扫描链单元数量为300个。进行边界扫描测试时，将测试矢量通过用户逻辑生成的边界扫描链直接移入待测PAD，从而大大缩短边界扫描链的长度，节约了测试时间，并且具有更高的灵活度。
进一步地，通过控制单元控制待测PAD为输入状态或输出状态。对于输入 PAD，在CAPTURE-DR(数据采集)状态，将输入值捕获到数据单元，在UPDATE-DR(数据更新)状态，将控制单元中移位寄存器的值更新到第二级寄存器中；对于输出PAD，在UPDATE-DR状态，将数据单元和控制单元中移位寄存器的值更新到第二级寄存器中。
进一步地，步骤S30载入边界扫描测试指令到FPGA，载入PRELOAD指令到待测PAD连通性的器件；其中待测PAD连通性的器件为FPGA待测PAD连通性测试的PAD所在的器件，可以是FPGA，也可以是FPGA的上级器件、FPGA的下级器件等。
进一步地，请参照图2，步骤S40通过TDI端口发送第一测试矢量到待测PAD包括：
S41、进入SHIFT-DR(移位)状态，通过TDI端口串行移入第一测试矢量到待测PAD；
S42、进入UPDATE-DR状态，将第一测试矢量并行更新到边界扫描链的边界扫描寄存器中。
其中，在SHIFT-DR状态下，通过边界扫描链将测试矢量移入边界扫描寄存器。当TCK上升沿时，放置于TDI到TDO边界扫描链路上的测试数据寄存器向TDO方向移一位；测试数据寄存器由当前测试指令选定，但没有放置于TDI到TDO的边界扫描链路上时，将保持原状态不变。
在UPDATE-DR状态下，在TCK下降沿，来自于移位寄存器路径的数据，被锁存到测试数据寄存器的并行输出端。
进一步地，请参照图3，步骤S50进行边界扫描测试，载入EXTEST指令到所述待测PAD连通的器件还包括：
S51、载入EXTEST指令到所述待测连通性的器件；
S52、加载第一测试矢量，进行外测试。
其中，EXTEST指令用于实现边界扫描外测试，外测试用于PAD间的互连测试。在进行EXTEST指令之前，需要进行PRELOAD指令操作，预装测试矢量，一旦外测试指令生效，预装的测试矢量就会被移到输出PAD，从而确保输出PAD状态可控。
进一步地，本实施例的边界扫描测试方法步骤S60从TDO(测试数据输出)端口移出第一响应数据，进行响应分析和故障诊断；还包括从所述TDO端口移出所述第一响应数据，同时发送第二测试矢量至第二待测PAD。
请参照图4，步骤S60具体包括：
S61、进入CAPTURE-DR状态，将第一响应数据并行捕获到边界扫描链的边界扫描寄存器中；
S62、进入SHIFT-DR状态，将第一响应数据串行移出，同时第二测试矢量串行移入，对第一响应数据进行数据分析和故障诊断；
S63、进入UPDATE-DR状态，将第二测试矢量并行更新到所述边界扫描链的边界扫描寄存器中，重复步骤S10-S60。
从TDO端口移出第N次响应数据的同时，发送第N+1次测试矢量，进行响应分析和故障诊断，直至完成所有待测PAD的测试后结束测试模式。
本申请的边界扫描测试方法还可用于板级互连测试。在一可选实施例中，测试芯片有三块，包括FPGA、上级器件、下级器件；其中上级器件的TDO连接FPGA的TDI，FPGA的TDO连接下级器件的TDI；一共有6种板级互连测试组合，包括：FPGA到下级器件、FPAG到上级器件、下级器件到上级器件、下级器件到FPGA、上级器件到下级器件、上级器件到FPGA。在另一可选实施例中，测试芯片有五块，包括FPGA1、FPGA2、器件1、器件2、器件3；一共有 20种板级互连测试组合。
下面使用三块测试芯片，测试FPGA的待测PAD到下级器件的PAD连通性的例子进一步阐述。
S10、调用SCAN CHAIN GTP接口，打开FPGA与用户逻辑的连接通道，配置FPGA进入测试模式。
S20、根据待测PAD的位置和数量，通过用户逻辑生成一条与所述待测PAD一一对应的边界扫描链。FPGA上共有500个PAD，待测的PAD数量为300个，则仅需要对应生成与待测PAD数量对应的边界扫描链。即，生成的扫描链单元数量为300个。进行测试时，将测试矢量通过用户逻辑生成的边界扫描链移入待测PAD。
S30、载入测试指令为FPGA待测输出PAD到下级器件待测输入PAD的连通性，载入PRELOAD指令到下级器件。
S40、通过TDI端口经过生成的边界扫描链发送第一次测试矢量到待测输出PAD；
S50、载入EXTEST指令到下级器件，将第一次测试矢量从待测输出PAD移入到待测输入PAD；
S60、从下级器件端口移出第一次响应数据，进行响应分析和故障分析；同时发送下一次测试矢量进行边界扫描测试，直至完成所有响应数据输出和分析。
本申请实施例的边界扫描测试方法，通过在FPGA用户逻辑里面对待测PAD进行软件设置，即可根据设置对待测PAD进行测试，而不测试和经过不需要测试的PAD。本申请缩短了边界扫描链，以实现更加快速、灵活的边界扫描测试，提高测试效率。
本申请在此基础上还提供了一种存储介质，存储介质存储有至少一个计算 机程序。该计算机程序用于实现上述的边界扫描测试方法。
以上实施例仅表达了本申请的优选的实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种边界扫描测试方法，用于测试与用户逻辑有直连通路的PAD的连通性，其特征在于，包括以下步骤：
    S10、配置FPGA进入测试模式；
    S20、通过所述用户逻辑生成用于边界扫描测试的边界扫描链；
    S30、载入边界扫描测试指令到所述FPGA，载入PRELOAD指令到待测PAD连通性的器件；
    S40、通过TDI端口发送第一测试矢量到所述待测PAD；
    S50、进行边界扫描测试，载入EXTEST指令到所述待测PAD连通性的器件；
    S60、从TDO端口移出第一响应数据，进行响应分析和故障诊断。
  2. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述边界扫描链包括若干个扫描链单元，若干个所述扫描链单元串联组成扫描链。
  3. 根据权利要求2所述的边界扫描测试方法，其特征在于，所述边界扫描链包括m个所述扫描链单元，所述FPGA包括n个PAD，其中，m≤n。
  4. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述“S10、配置所述FPGA进入测试模式”步骤还包括：
    调用所述边界扫描链测试接口，打开所述FPGA与所述用户逻辑连接的通道,进入测试模式。
  5. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述“S20、通过所述用户逻辑生成用于边界扫描测试的边界扫描链”步骤包括：
    根据所述待测PAD的位置和数量，通过所述用户逻辑生成一条与所述待测PAD一一对应的边界扫描链。
  6. 根据权利要求1所述边界扫描测试方法，其特征在于，所述“S40、通过 TDI端口发送第一测试矢量到所述待测PAD”步骤包括：
    进入SHIFT-DR状态，通过TDI端口串行移入所述第一测试矢量到所述待测PAD；
    进入UPDATE-DR状态，将所述第一测试矢量并行更新到所述边界扫描链的边界扫描寄存器中。
  7. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述“S50、进行边界扫描测试，载入EXTEST指令到所述待测PAD连通性的器件”步骤还包括：
    载入EXTEST指令到所述待测PAD连通性的器件；
    加载所述第一测试矢量，进行外测试。
  8. 根据权利要求1所述的边界扫描测试方法，其特征在于，所述“S60、从TDO端口移出第一响应数据，进行响应分析和故障诊断”还包括：
    从所述TDO端口移出所述第一响应数据，同时发送下一测试矢量至下一待测PAD。
  9. 根据权利要求8所述的边界扫描测试方法，其特征在于，所述“从所述TDO端口移出所述第一响应数据，同时发送下一测试矢量至下一待测PAD”步骤还包括：
    进入CAPTURE-DR状态，将所述第一响应数据并行捕获到所述边界扫描链的边界扫描寄存器中；
    进入SHIFT-DR状态，将所述第一响应数据串行移出，同时将所述下一测试矢量串行移入所述下一待测PAD；
    进入UPDATE-DR状态，将所述下一测试矢量并行更新到所述边界扫描链的边界扫描寄存器中。
  10. 一种存储介质，其特征在于，所述存储介质存储有至少一个计算机程序，所述至少一个计算机程序被处理器执行时实现如权利要求1至9中任一项所述的边界扫描测试方法。
PCT/CN2021/082534 2020-10-28 2021-03-24 边界扫描测试方法及存储介质 WO2022088594A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/906,980 US11933845B2 (en) 2020-10-28 2021-03-24 Boundary scan test method and storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011171203.9A CN112526327B (zh) 2020-10-28 2020-10-28 边界扫描测试方法及存储介质
CN202011171203.9 2020-10-28

Publications (1)

Publication Number Publication Date
WO2022088594A1 true WO2022088594A1 (zh) 2022-05-05

Family

ID=74979660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/082534 WO2022088594A1 (zh) 2020-10-28 2021-03-24 边界扫描测试方法及存储介质

Country Status (3)

Country Link
US (1) US11933845B2 (zh)
CN (1) CN112526327B (zh)
WO (1) WO2022088594A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112526327B (zh) * 2020-10-28 2022-07-08 深圳市紫光同创电子有限公司 边界扫描测试方法及存储介质
CN113702816B (zh) * 2021-08-26 2024-05-10 中国电子科技集团公司第五十八研究所 一种基于边界扫描的寄存器单元设计方法

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5644580A (en) * 1993-11-29 1997-07-01 Motorola, Inc. Boundary-scan testable system and method
US5701308A (en) * 1996-10-29 1997-12-23 Lockheed Martin Corporation Fast bist architecture with flexible standard interface
US6012155A (en) * 1997-10-30 2000-01-04 Synopsys, Inc. Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist
US6163864A (en) * 1998-06-10 2000-12-19 Compaq Computer Corporation Method for cost-effective production testing of input voltage levels of the forwarded clock interface of high performance integrated circuits
JP2001194422A (ja) * 2000-01-05 2001-07-19 Matsushita Electric Ind Co Ltd 集積回路
WO2002071567A1 (en) * 2001-03-01 2002-09-12 Syntest Technologies, Inc. Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques
US6539491B1 (en) * 1999-11-08 2003-03-25 International Business Machines Corporation Method and apparatus for implementing IEEE 1149.1 compliant boundary scan
EP2749894A1 (en) * 2012-12-31 2014-07-02 Testonica Lab Oü System and method for optimized board test and configuration
CN109459684A (zh) * 2018-12-20 2019-03-12 中国航空综合技术研究所 基于数据重构的边界扫描故障注入方法
CN111579974A (zh) * 2020-06-09 2020-08-25 中国电子科技集团公司第十四研究所 实现边界扫描测试的被测模块、嵌入式系统及测试方法
CN112526327A (zh) * 2020-10-28 2021-03-19 深圳市紫光同创电子有限公司 边界扫描测试方法及存储介质
CN112526328A (zh) * 2020-10-28 2021-03-19 深圳市紫光同创电子有限公司 边界扫描测试方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US20030163773A1 (en) * 2002-02-26 2003-08-28 O'brien James J. Multi-core controller
US20030217306A1 (en) * 2002-05-17 2003-11-20 Harthcock Jerry D. Self-programmable microcomputer and method of remotely programming same
JP3484181B1 (ja) * 2002-09-02 2004-01-06 沖電気工業株式会社 半導体テスト回路
US7506210B1 (en) * 2003-06-26 2009-03-17 Xilinx, Inc. Method of debugging PLD configuration using boundary scan
US7480843B1 (en) * 2004-09-29 2009-01-20 Xilinx, Inc. Configuration access from a boundary-scannable device
US7308656B1 (en) * 2005-10-04 2007-12-11 Xilinx, Inc. Method and apparatus for generating a boundary scan description and model
US9110142B2 (en) * 2011-09-30 2015-08-18 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
US9728273B2 (en) * 2014-05-21 2017-08-08 Lattice Semiconductor Corporation Embedded memory testing using back-to-back write/read operations
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan
CN106597250A (zh) * 2016-11-24 2017-04-26 深圳市紫光同创电子有限公司 一种可编程逻辑器件测试方法及设备
CN108693466B (zh) * 2017-04-12 2020-09-11 上海鹏武电子科技有限公司 一种边界扫描器件、装置及控制方法和扫描方法

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5644580A (en) * 1993-11-29 1997-07-01 Motorola, Inc. Boundary-scan testable system and method
US5701308A (en) * 1996-10-29 1997-12-23 Lockheed Martin Corporation Fast bist architecture with flexible standard interface
US6012155A (en) * 1997-10-30 2000-01-04 Synopsys, Inc. Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist
US6163864A (en) * 1998-06-10 2000-12-19 Compaq Computer Corporation Method for cost-effective production testing of input voltage levels of the forwarded clock interface of high performance integrated circuits
US6539491B1 (en) * 1999-11-08 2003-03-25 International Business Machines Corporation Method and apparatus for implementing IEEE 1149.1 compliant boundary scan
JP2001194422A (ja) * 2000-01-05 2001-07-19 Matsushita Electric Ind Co Ltd 集積回路
WO2002071567A1 (en) * 2001-03-01 2002-09-12 Syntest Technologies, Inc. Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques
EP2749894A1 (en) * 2012-12-31 2014-07-02 Testonica Lab Oü System and method for optimized board test and configuration
CN109459684A (zh) * 2018-12-20 2019-03-12 中国航空综合技术研究所 基于数据重构的边界扫描故障注入方法
CN111579974A (zh) * 2020-06-09 2020-08-25 中国电子科技集团公司第十四研究所 实现边界扫描测试的被测模块、嵌入式系统及测试方法
CN112526327A (zh) * 2020-10-28 2021-03-19 深圳市紫光同创电子有限公司 边界扫描测试方法及存储介质
CN112526328A (zh) * 2020-10-28 2021-03-19 深圳市紫光同创电子有限公司 边界扫描测试方法

Also Published As

Publication number Publication date
US20230120955A1 (en) 2023-04-20
CN112526327B (zh) 2022-07-08
CN112526327A (zh) 2021-03-19
US11933845B2 (en) 2024-03-19

Similar Documents

Publication Publication Date Title
CA2249088C (en) Method and apparatus for high-speed interconnect testing
WO2022088594A1 (zh) 边界扫描测试方法及存储介质
WO2022088595A1 (zh) 边界扫描测试方法
US6813738B2 (en) IC test cell with memory output connected to input multiplexer
US5631911A (en) Integrated test circuit
US6983441B2 (en) Embedding a JTAG host controller into an FPGA design
US5495487A (en) Testing buffer/register
KR102065813B1 (ko) 아날로그 블록 및 아날로그 블록을 테스트하는 테스트 블록
US20160349320A1 (en) Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniques
US20020035442A1 (en) Hierarchical test circuit structure for chips with multiple circuit blocks
US7181705B2 (en) Hierarchical test circuit structure for chips with multiple circuit blocks
US10234505B1 (en) Clock generation for integrated circuit testing
KR100505662B1 (ko) 칩 사이즈를 감소시키는 스캔 테스트 회로를 구비한반도체 장치, 및 그 테스트 방법
US20140298125A1 (en) System and method for optimized board test and configuration
US8914689B2 (en) Controlled toggle rate of non-test signals during modular scan testing of an integrated circuit
US5617431A (en) Method and apparatus to reuse existing test patterns to test a single integrated circuit containing previously existing cores
CN104903736B (zh) 用于动态分配扫描测试资源的电路和方法
US8788895B2 (en) Testing system for integrated circuits including components for receiving clock signals corresponding to different clock domains
KR20070059327A (ko) 보드를 점검하는 제이택 데이지 체인 장치
US8826087B2 (en) Scan circuitry for testing input and output functional paths of an integrated circuit
JPH05180911A (ja) Ｊｔａｇアーキテクチャのための回路
EP0358371B1 (en) Enhanced test circuit
US7188277B2 (en) Integrated circuit
JPH07209381A (ja) 回路ネットワークにおけるバウンダリ・スキャン検査システム及び方法
JP4610919B2 (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21884338

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25/09/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21884338

Country of ref document: EP

Kind code of ref document: A1