WO2022087989A1 - 信号延迟方法、装置、系统及医疗挂号设备 - Google Patents

信号延迟方法、装置、系统及医疗挂号设备 Download PDF

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Publication number
WO2022087989A1
WO2022087989A1 PCT/CN2020/124950 CN2020124950W WO2022087989A1 WO 2022087989 A1 WO2022087989 A1 WO 2022087989A1 CN 2020124950 W CN2020124950 W CN 2020124950W WO 2022087989 A1 WO2022087989 A1 WO 2022087989A1
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Prior art keywords
delay
signal
clock signal
stage
delayed clock
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PCT/CN2020/124950
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English (en)
French (fr)
Inventor
黄继景
唐大伟
杨志明
吴琼
刘宗民
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002541.1A priority Critical patent/CN115136099A/zh
Priority to PCT/CN2020/124950 priority patent/WO2022087989A1/zh
Priority to US17/599,490 priority patent/US11720138B2/en
Publication of WO2022087989A1 publication Critical patent/WO2022087989A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/043—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using propagating acoustic waves
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10K—SOUND-PRODUCING DEVICES; METHODS OR DEVICES FOR PROTECTING AGAINST, OR FOR DAMPING, NOISE OR OTHER ACOUSTIC WAVES IN GENERAL; ACOUSTICS NOT OTHERWISE PROVIDED FOR
    • G10K11/00—Methods or devices for transmitting, conducting or directing sound in general; Methods or devices for protecting against, or for damping, noise or other acoustic waves in general
    • G10K11/18—Methods or devices for transmitting, conducting or directing sound
    • G10K11/26—Sound-focusing or directing, e.g. scanning
    • G10K11/34—Sound-focusing or directing, e.g. scanning using electrical steering of transducer arrays, e.g. beam steering
    • G10K11/341—Circuits therefor
    • G10K11/345—Circuits therefor using energy switching from one active element to another
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/0207—Driving circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B2201/00—Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
    • B06B2201/70—Specific application
    • B06B2201/76—Medical, dental
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
    • G01S15/8909—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration
    • G01S15/8915—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration using a transducer array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a signal delay method, device, system, and medical registration equipment.
  • Delaying the driving signal is one of the necessary steps to drive some devices to work normally.
  • a register is generally used to buffer the driving signal to be delayed, and the driving signal is output at a specified time, so as to realize the delay processing of the driving signal.
  • the application provides a signal delay method, device, system and medical registration equipment, and the technical solutions are as follows:
  • a signal delay method comprising:
  • the number of clock cycles of the delayed clock signal of each stage is used in turn, and the driving signal is delayed and then output.
  • the multi-stage delayed clock signal is generated based on a master clock signal; the multi-stage delayed clock signal is determined according to the clock period of each stage of the delayed clock signal in the multi-stage delayed clock signal, each time required to delay the total delay bits.
  • the number of clock cycles of the first stage of the delayed clock signal including:
  • the candidate delay bit corresponding to the delayed clock signal is determined, and the candidate delay bit Refers to the number of delay bits that can be completed by one clock cycle of the delayed clock signal;
  • For each stage of the delayed clock signal determine the number of clock cycles of the delayed clock signal required to delay the total delay bits according to the reference delay bits and the candidate delay bits corresponding to the delayed clock signal;
  • the reference delay bit is the total delay bit
  • the reference The number of delay bits is the remaining delay bits after the driving signal is delayed by the number of clock cycles of the delayed clock signal of the previous stage.
  • the candidate delay bits corresponding to the delayed clock signal including: :
  • a quotient obtained by dividing the clock frequency of the main clock signal by the clock frequency of the delayed clock signal is determined as the candidate delay bits corresponding to the delayed clock signal.
  • the delay clock required for delaying the total delay bits is determined according to the reference delay bits and the candidate delay bits corresponding to the delay clock signal for each stage of the delay clock signal.
  • the number of clock cycles of the signal including:
  • the quotient obtained by dividing the reference delay bits by the candidate delay bits corresponding to the delayed clock signal is rounded down to obtain the required delay for the total delay bits The number of clock cycles of the delayed clock signal.
  • the driving signal transitions at the first transition edge of the delayed clock signal, and the second transition edge of the delayed clock signal in the first stage is used to delay the driving signal, the first transition Among the first transition edge and the second transition edge, one is a rising edge and the other is a falling edge; then for the first stage of the delayed clock signal, the reference delay bit and the corresponding delay clock signal
  • the number of alternate delay bits to determine the number of clock cycles of the delayed clock signal required to delay the total delay bits including:
  • the sum of the number of candidate clock cycles and 1/2 is determined as the number of clock cycles of the first stage of the delayed clock signal required to delay the total number of delay bits.
  • the number of stages of the multi-stage delayed clock signal is 4; wherein, the clock cycle of the delayed clock signal in the third stage is 8 times the clock cycle of the delayed clock signal in the fourth stage, and the second stage
  • the clock period of the delayed clock signal is 10 times the clock period of the delayed clock signal in the third stage
  • the clock period of the delayed clock signal in the first stage is 5 times the clock period of the delayed clock signal in the second stage.
  • the determining the total delay bits required to delay the driving signal includes:
  • a total number of delay bits required to delay the drive signal is determined.
  • the method before the determining of the total number of delay bits required to delay the driving signal, the method further includes: generating the driving signal.
  • the signal delay circuit is a field programmable logic gate array FPGA.
  • a signal delay system in yet another aspect, includes: a target device, a drive circuit, and the signal delay circuit according to the above aspect;
  • the signal delay circuit is connected to the drive circuit, and the signal delay circuit is used for delaying the drive signal by a total delay number of bits and then outputting it to the drive circuit;
  • the driving circuit is connected to the target device, and the driving circuit is used for driving the target device to work in response to the received driving signal.
  • the system further includes: a communication module, the communication module is connected to the signal delay circuit, the communication module is configured to receive delay reference information and output the delay reference information to the signal delay circuit .
  • the target device is an ultrasonic transducer
  • the system includes a transducer array composed of a plurality of the ultrasonic transducers
  • the driving circuit is used for driving the ultrasonic transducer to emit ultrasonic waves in response to the received driving signal, so as to form a virtual key.
  • a medical registration device in another aspect, includes: a computer, a printer, a medical insurance card reading component, a camera component, and a virtual key generation system that are sequentially connected in communication, and the virtual key generation system includes the above aspects. the described signal delay system;
  • the medical insurance card reading component is used for reading medical insurance card information, and sending the medical insurance card information to the computer;
  • the camera assembly is configured to photograph the area where the transducer array is located in the virtual button generation system if a touch operation for any ultrasonic transducer in the virtual button generation system is detected, and record the images. sending the resulting image to the computer;
  • the computer is configured to determine, based on the image, the target ultrasonic transducer targeted by the touch operation, and after determining that the mapping position of the target ultrasonic transducer in the display interface of the computer is located in the key area, sending delay reference information to the virtual key generation system, and generating registration information in response to a registration trigger operation, and controlling the printer to print the registration information;
  • the virtual key generation system is configured to form virtual keys based on the delay reference information
  • the delay reference information includes: the position of the target ultrasonic transducer in the transducer array.
  • FIG. 1 is a schematic structural diagram of a signal delay system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another signal delay system provided by an embodiment of the present application.
  • FIG. 3 is an internal program frame diagram of a signal delay circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a delay sequence of a multi-stage delayed clock signal provided by an embodiment of the present application.
  • FIG. 7 is a simulation diagram of a delayed clock signal at all levels provided by an embodiment of the present application.
  • Fig. 8 is a partial enlarged view of the simulation diagram shown in Fig. 7;
  • FIG. 9 is a timing simulation diagram of a driving signal before and after a delay provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a medical registration device provided by an embodiment of the present application.
  • Delaying the signal with a signal delay circuit is one of the necessary steps to drive some systems to work properly.
  • the signal delay can be understood as when a signal (eg, a driving signal) required by a device in the system is received or generated, the signal is delayed for a fixed period of time before being output to the corresponding device.
  • a signal eg, a driving signal
  • the system includes an array composed of a plurality of identical devices, signals output to different devices in the array can be flexibly delayed, so that the array can perform some specific functions, that is, the array can work reliably.
  • FIG. 1 shows a schematic structural diagram of a signal delay system.
  • the signal delay system may include: a target device 01 , a driving circuit 02 and a signal delay circuit 03 .
  • the signal delay circuit 03 can be connected to the drive circuit 02 , and the signal delay circuit 03 can be used to generate a drive signal, and output the generated drive signal to the drive circuit 02 after delaying the generated drive signal by a total number of delay bits.
  • the driving circuit 02 can be connected to the target device 01, and the driving circuit 02 can drive the target device 01 to work based on the received driving signal.
  • the total delay bits can be used to determine the duration of the signal delay, and the total delay bits can be flexibly generated by the signal delay circuit 03 based on the received delay reference information.
  • the signal delay circuit The delay reference information received by 03 may be different, and the delay reference information may be sent by a computer device that has established a communication connection with the system.
  • FIG. 2 shows a schematic structural diagram of another signal delay system.
  • the target device 01 may be an ultrasonic transducer, and the system may further include: a transducer array 00 composed of a plurality of ultrasonic transducers.
  • the delay reference information may include: the position of the ultrasonic transducer in the transducer array 00 .
  • the driving circuit 02 driving the target device 01 to work in response to the driving signal can be understood as: the driving circuit 02 drives the ultrasonic transducer to emit ultrasonic waves, that is, the ultrasonic transducer can emit ultrasonic waves under the control of the received driving signal.
  • the driving circuit 02 drives the ultrasonic transducer to emit ultrasonic waves, that is, the ultrasonic transducer can emit ultrasonic waves under the control of the received driving signal.
  • different ultrasonic transducers in the transducer array 00 can emit ultrasonic waves at different times, that is, different ultrasonic transducers can vibrate at different times.
  • the system may further include: a communication module 04 .
  • the communication module 04 can be connected to the signal delay circuit 03 .
  • the communication module 04 can be used for receiving the delay reference information and outputting the delay reference information to the signal delay circuit 03 .
  • the signal delay circuit 03 in the system can be a field programmable gate array (field programmable gate Array, FPGA).
  • FIG. 3 shows the internal program frame diagram of the FPGA.
  • the program framework may include: a PS terminal and a PL terminal. Both the PS terminal and the PL terminal can be used to directly establish a communication connection with the communication module 04, and data exchange transmission can be performed between the PS terminal and the PL terminal.
  • Fig. 3 takes the PL end and the communication module 04 as an example to establish a communication connection, and further shows the optional program frame diagram included in the PL end.
  • the PL end can include a network port communication module, a PS-PL communication module, a drive signal Generate block and delay block.
  • the driving signal generating module may be used to generate a driving signal (also referred to as an excitation signal).
  • the network port communication module can be used to receive the delay reference information output by the communication module 04 and send it to the PS-PL communication module.
  • the PS-PL communication module can further transmit the delay reference information to the PS side.
  • the PS terminal can be used to determine the total delay bits required to delay the driving signal based on the received delay reference information, and transmit the total delay bits to the PL terminal through the PS-PL communication module.
  • the delay module in the PL terminal can be used to delay the driving signal generated by the driving signal generating module based on the total delay bits and output it to the driving circuit 02 .
  • the signal delay circuit 03 is not limited to an FPGA, and may also be other devices capable of delaying signals, such as a single-chip microcomputer.
  • the target device 01 is not limited to an ultrasonic transducer, and can be any other device that needs to work in response to a delayed drive signal.
  • FIG. 4 is a schematic flowchart of a signal delay method provided by an embodiment of the present disclosure, which may be applied to the signal delay circuit 03 shown in FIG. 1 or FIG. 2 . As shown in Figure 4, the method may include:
  • Step 401 Determine the total delay bits required to delay the drive signal.
  • the signal delay circuit 03 can further determine the total delay bits required to delay the driving signal based on the received delay reference information, and the total delay bits determines the number of delays in the driving signal. The total amount of time to delay.
  • Step 402 Determine the number of clock cycles of each stage of the delayed clock signal required to delay the total number of delay bits according to the clock cycle of each stage of the multistage delayed clock signal.
  • the clock cycles of the various stages of the delayed clock signal can be sequentially reduced. In this way, the step-by-step refinement delay of the drive signal can be facilitated.
  • the signal delay circuit can first determine the number of delay bits that can be delayed by each stage of the delayed clock signal in one clock cycle based on the clock cycle of each stage of the delayed clock signal, and then based on the delay of each stage of the clock signal.
  • the number of delay bits that can be delayed by one clock cycle determines the number of clock cycles of each stage of the delayed clock signal required to delay the total delay bits. That is, for each stage of the delayed clock signal, the number of clock cycles required to delay the total number of delay bits is determined for that stage of the delayed clock signal.
  • Step 403 according to the order of the clock cycles from large to small, sequentially adopt the number of clock cycles of each stage of the delayed clock signal, delay the driving signal and then output it.
  • the signal delay circuit can first delay the driving signal by a first-stage delayed clock signal of 4 clock cycles, and then delay the driving signal by a second-stage delayed clock signal by 2 clock cycles before outputting. In this way, even the driving signal is delayed by the total number of delay bits before output.
  • the embodiments of the present disclosure provide a signal delay method. Because it is based on the clock cycles of the delayed clock signals at all levels, the number of clock cycles of the delayed clock signals at all levels required to delay the total number of delay bits of the driving signal is determined, and then based on the determined number of clock cycles of the delayed clock signals at each level, the driving signal
  • the delays are performed in sequence, so on the premise that the data amount of the drive signal to be delayed is constant, compared with directly using the register to delay the signal, this method can reliably realize the signal delay while effectively reducing the number of registers that need to be set.
  • FIG. 5 is a schematic flowchart of another signal delay method provided by an embodiment of the present disclosure, which can be applied to the signal delay circuit 03 shown in FIG. 1 or FIG. 2 . As shown in Figure 5, the method may include:
  • Step 501 generating a driving signal.
  • the signal delay circuit 03 generally includes a drive signal generation module for generating a drive signal, and the drive signal generation module can be used to generate a drive target. drive signal required by the device.
  • the generated driving signal may be a signal capable of driving the ultrasonic transducer to emit ultrasonic waves, and may also be referred to as an excitation signal.
  • Step 502 Receive delay reference information.
  • the signal delay circuit 03 may receive delay reference information sent to it by a computer device with which a communication connection is established, and the delay reference information may be used by the signal delay circuit 03 to further determine the delay driving signal.
  • the delay reference information may include: the position of the target ultrasonic transducer in the transducer array (represented by coordinates),
  • the target ultrasonic transducer may refer to the transducer currently to be driven in the transducer array.
  • Step 503 based on the delay reference information, determine the total number of delay bits required to delay the driving signal.
  • the signal delay circuit 03 may first determine, based on the received delay reference information, how long the target device needs to work in response to the drive signal after the current moment, and then further based on the determined time duration. Calculate the total number of delay bits required to obtain the delayed drive signal. In this way, after delaying the total number of delay bits of the driving signal, the target device can receive the driving signal at the corresponding moment (ie, after a specified time period from the current moment), and work in response to the driving signal.
  • the target ultrasonic transducer is the first ultrasonic transducer on the upper left of the transducer array.
  • the signal delay circuit 03 can determine the distance between the target ultrasonic transducer and the ultrasonic transducer at the center of the transducer array based on the position of the target ultrasonic transducer. Then, the target duration from the moment when the target ultrasonic transducer sends out ultrasonic waves to the current moment is determined based on the distance, that is, how long before the target ultrasonic transducer needs to emit ultrasonic waves. Finally, based on the target duration, determine the total delay bits of the drive signal that delays driving the target ultrasonic transducer, so that the target ultrasonic transducer can respond to the delayed drive signal and emit ultrasonic waves after the target duration at the current moment.
  • Step 504 For each stage of the delayed clock signal, determine the candidate delay bits corresponding to the delayed clock signal according to the clock frequency of the main clock signal and the clock frequency of the delayed clock signal.
  • the multi-stage delayed clock signal may be generated based on a master clock signal. That is, the signal delay circuit 03 can actually only be connected to a clock signal terminal capable of providing a master clock signal, the clock signal terminal can be used to generate the master clock signal, and the signal delay circuit 03 can respond to the master clock signal to generate the signal delay required by the signal.
  • the multi-stage delayed clock signal is generated, and the number of stages of the generated delayed clock signal can be proportional to the total number of delay bits. That is, the larger the total number of delay bits, the greater the number of stages of the generated delayed clock signal; conversely, the smaller the total number of delay bits, the less the number of stages of the generated delayed clock signal.
  • the first stage delay clock signal to the last stage delay clock signal, and the clock cycles of the delay clock signals at each stage can be sequentially reduced.
  • the clock frequencies of the delayed clock signals at each stage can be sequentially increased.
  • the signal delay circuit 03 may adopt a clock frequency division technique to divide the main clock signal CLK into four-stage delayed clock signals.
  • the clock period of the fourth-stage delayed clock signal CLK and the main clock signal CLK may be the same (so, indicated by the same symbol)
  • the clock period of the third-stage delayed clock signal CLKB may be the clock period of the fourth-stage delayed clock signal CLK 8 times
  • the clock period of the second-stage delayed clock signal CLKC can be 10 times the clock period of the third-stage delayed clock signal CLKB
  • the clock period of the first-stage delayed clock signal CLKD can be 10 times the clock period of the second-stage delayed clock signal CLKC 5 times the clock period.
  • the clock frequency of the first-stage delayed clock signal CLKD may be divided by 5 (ie, 1/5) of the clock frequency of the second-stage delayed clock signal CLKC
  • the clock frequency of the second-stage delayed clock signal CLKC may be the third
  • the clock frequency of the stage delay clock signal CLKB is divided by 10
  • the clock frequency of the third stage delay clock signal CLKB can be divided by 8 of the clock frequency of the fourth stage delay clock signal CLK
  • the clock frequency of the fourth stage delay clock signal CLK The same as the main clock signal CLK.
  • FIG. 7 schematically shows a simulation diagram of the four-stage delayed clock signal
  • FIG. 8 is a partial enlarged diagram of the simulation diagram shown in FIG. 7 .
  • the embodiments of the present disclosure do not limit the number of stages of the generated delayed clock signals and the frequency of each stage to be the contents described in the above-mentioned embodiments, that is, more or less stages of delayed clock signals may also be included, and The frequency and period of each stage of the delayed clock signal may satisfy other conditions, which will not be repeated here.
  • the candidate delay bits may refer to the delay bits that can be completed by one clock cycle of the delayed clock signal. That is, for each stage of the delayed clock signal, using one clock cycle of the delayed clock signal to delay the driving signal, the number of delay bits that can be delayed.
  • one clock cycle may refer to a stage from one rising edge to another adjacent rising edge; or, a stage from one falling edge to another adjacent falling edge.
  • T0 represents one clock cycle of the third-stage delayed clock signal CLKB, and the same is true for other delayed clock signals.
  • the signal delay circuit 03 may determine the quotient obtained by dividing the clock frequency of the main clock signal by the clock frequency of the delayed clock signal as the delayed clock signal of this stage.
  • the corresponding alternate delay bits since the clock period and the clock frequency are inversely proportional, the clock period may also be used to calculate the number of alternative delay bits, which will not be described further herein.
  • the clock frequency of the main clock signal CLK is 32 megahertz (MHz) and the clock frequency of the first-stage delayed clock signal CLKD is 80 kilohertz (KHz)
  • Step 505 For each stage of the delayed clock signal, determine the number of clock cycles of the delayed clock signal required to delay the total delay bits according to the reference delay bits and the candidate delay bits corresponding to the delayed clock signal.
  • the reference delay bits may be the total delay bits.
  • the reference delay bits may be the remaining delay bits after the driving signal is delayed by the number of clock cycles of the previous stage of delayed clock signals.
  • the signal delay circuit 03 may round down the quotient obtained by dividing the reference delay bits by the alternative delay bits corresponding to the delayed clock signal, to Get the number of clock cycles of the delayed clock signal required to delay the total number of bits of delay. Rounding down can refer to: regardless of the rounding rules, as long as there are decimals behind, the decimals are ignored.
  • the total number of delay bits is 2025
  • the number of candidate delay bits corresponding to the first-stage delayed clock signal CLKD is 400
  • the driving signal can be set to jump at the first transition edge of the first-stage delayed clock signal CLKD, and the first-stage delayed clock signal CLKD can be set to jump.
  • the second transition edge of the stage-delayed clock signal CLKD delays the driving signal, and one of the first transition edge and the second transition edge is a rising edge and the other is a falling edge. That is, if a signal transition occurs on the rising edge of the driving signal, the falling edge of the first-stage delayed clock signal CLKD is used to delay the driving signal.
  • the driving signal when delaying the driving signal, the driving signal is first delayed by 1/2 clock cycle of CLKD, and then the driving signal is delayed by CLKD of every complete clock cycle.
  • the delay bit number that can be delayed is 1/2 of the alternative delay bit number of CLKD of one clock cycle.
  • the quotient obtained by dividing the total number of delay bits by the number of alternative delay bits may be rounded down to obtain the first stage required to delay the total number of delay bits.
  • the number of candidate clock cycles of the delayed clock signal; then the sum of the number of candidate clock cycles and 1/2 is determined as the final number of clock cycles of the delayed clock signal CLKD required to delay the driving signal of the total delay bits.
  • the number of candidate clock cycles required for the first-stage delayed clock signal CLKD is 4, it can be known that the final number of clock cycles of the delayed clock signal CLKD required to delay a drive signal of 2025 digits is actually: 4.5.
  • the candidate delay bits of the first-stage delayed clock signal CLKD are 400, it can be known that the delay bits that can be delayed by 1/2 clock cycle CLKD is 200.
  • 2025-400*4-200 225. That is, there are still 225 bits left, and the delay clock signals of other stages after the first stage delay clock signal CLKD need to be used for further delay.
  • Step 506 According to the order of clock cycles from large to small, sequentially adopt the number of clock cycles of the delayed clock signal of each stage to delay the driving signal and then output it.
  • the signal delay circuit 03 can use the number of clock cycles of each stage of the delay clock signal to process the drive signal. output after a delay.
  • the signal delay circuit 03 can first use 4.5 clock cycles of CLKD to perform the first-stage delay on the drive signal (data_D) to be delayed, Obtain the delayed first-level delay signal (data_C); then use 2 clock cycles of CLKC to perform second-level delay on the first-level delay signal to obtain the delayed second-level delay signal (data_B); then use 1 clock Periodic CLKB performs third-level delay on the second-level delay signal to obtain the delayed third-level delay signal (data); finally, 0.5 clock cycles of CLK are used to perform fourth-level delay on the third-level delay signal to obtain the final delay.
  • the driving signal is output to the driving circuit 02
  • FIG. 9 shows a timing simulation diagram of the driving signal data_D before the delay and the driving signal data_C after the delay. It can be further seen with reference to FIG. 9 that the delayed driving signal data_C and the pre-delayed driving signal data_D differ from the delayed clock signal CLKD by 4.5 clock cycles T0.
  • the last delay can also be directly performed by means of register buffer delay.
  • the first stage delay can be the delay executed by the program module D (Module D) in the signal delay circuit 03
  • the second stage delay can be the program module C (Module C) in the signal delay circuit 03 delay
  • the delay of execution, the third stage delay can be the delay executed by the program module B (Module B) in the signal delay circuit 03
  • the fourth stage delay can be the delay executed by the program module A (Module A) in the signal delay circuit 03.
  • Module A to Module D are all program virtual modules.
  • the driving signal can be first buffered in the first-stage delay, so as to be delayed with the multi-stage delayed clock signal (including the first-stage delayed clock signal CLKD, the second-stage delayed clock signal CLKC and the third-stage delayed clock signal CLKC)
  • the multi-stage delayed clock signal including the first-stage delayed clock signal CLKD, the second-stage delayed clock signal CLKC and the third-stage delayed clock signal CLKC
  • the transition edges of the clock signal CLKB) are aligned, so that errors generated in the subsequent delay process due to misalignment of the transition edges can be reliably avoided.
  • step 501 and step 502 can be reversed. Any person skilled in the art can easily think of a changed method within the technical scope disclosed by the embodiments of the present disclosure, which should be covered within the protection scope of the invention, and therefore no longer Repeat.
  • the embodiments of the present disclosure provide a signal delay method. Because it is based on the clock cycles of the delayed clock signals at all levels, the number of clock cycles of the delayed clock signals at all levels required to delay the total number of delay bits of the driving signal is determined, and then based on the determined number of clock cycles of the delayed clock signals at each level, the driving signal
  • the delays are performed in sequence, so on the premise that the data amount of the drive signal to be delayed is constant, compared with directly using the register to delay the signal, this method can reliably realize the signal delay while effectively reducing the number of registers that need to be set.
  • the embodiment of the present disclosure further provides a medical registration device.
  • the medical registration device may include: a virtual key generation system 10 , a computer 20 , a printer 30 , a medical insurance card reading component 40 and a camera component 50 , which are sequentially connected in communication.
  • the virtual key generation system 10 may include the signal delay system 100 shown in any one of FIG. 1 to FIG. 3 .
  • the signal delay system 100 may include a transducer array 00 and a control circuit for controlling the operation of the transducer array 00 .
  • the control circuit may include: a communication module 04, a signal delay circuit 03 and a drive circuit 02 (not shown in FIG. 10).
  • the medical insurance card reading component 40 can be used to read the medical insurance card information and send the medical insurance card information to the computer 20 .
  • the medical insurance card information can be the information of the medical insurance card placed on the medical insurance card reading component 40 by the user to be registered, that is, when registering, the user can directly place the medical insurance card on the medical insurance card reading component 40 for the medical insurance card
  • the reading component 40 reads the information in the medical insurance card (referred to as medical insurance card information).
  • the camera assembly 50 can be used to photograph the area where the transducer array 00 in the virtual button generation system 10 is located if a touch operation for any ultrasonic transducer in the virtual button generation system 10 is detected, and obtain the result of the photographing.
  • the image is sent to the computer 20.
  • the user can perform touch operations on the virtual key generation system 10 , and the touch operations can be mapped on the display interface of the computer 20 . That is, a series of operations performed by the user on the virtual key generation system 10 can be mapped to operations performed on the computer 20 .
  • the medical registration device can also be called a non-contact registration device.
  • the photographing component 50 can capture the image of the area where the transducer array 00 in the virtual key generating system 10 is located in real time, and send the image to the computer 20 .
  • the camera assembly 50 may be a depth camera.
  • the computer 20 can be used to determine the target ultrasonic transducer for the touch operation based on the received image, and after determining that the mapping position of the target ultrasonic transducer in the display interface of the computer 20 is located in the key area, delay the reference
  • the information is sent to the virtual key generation system 10, and can be used to generate registration information in response to a registration trigger operation, and to control the printer 40 to print the registration information.
  • the virtual key generation system 10 may be used to form virtual keys based on the received delay reference information.
  • the key area refers to the area where the key controls are located in the display interface of the computer 20 .
  • the computer 20 can flexibly determine the position of the user's touch operation on the virtual key generation system 10 based on the image captured by the camera assembly 50 , that is, determine the target ultrasonic transducer targeted by the user's touch operation s position. And after determining that the target ultrasonic transducer is located in the key area, the computer 20 can further send the delay reference information to the virtual key generation system 10, so that the virtual key generation system 10 drives the ultrasonic transducer based on the delay reference information to emit at a specified time.
  • the virtual key may include various ultrasonic transducers that vibrate at different times, and the user can determine whether the touch operation is located in the key area at the moment through the tactile sense of vibration.
  • the delay reference information may include: the position of the target ultrasonic transducer in the transducer array.
  • the delay reference information may also include: the center position of the key area, the current position of the touch operation on the display interface, and any other information that can be used to estimate the total delay bits.
  • the computer 20 can receive the registration trigger operation. At this time, the computer can perform the next operation, such as generating registration information, and driving the printer 40 to print the registration information, and the whole registration process ends.
  • the number of ultrasonic transducers targeted by the touch operation is not only one. If there are more than one, the target ultrasonic transducer may refer to the ultrasonic transducer with the largest overlapping area with the touch operation.
  • the signal delay system and the combined signal delay method described in the embodiments of the present disclosure are not limited to be applied to the medical registration scenario shown in FIG. 10 . For example, it can also be applied to other scenarios such as radar imaging.

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Abstract

一种信号延迟方法、装置、系统及医疗挂号设备，该方法包括：先基于各级延迟时钟信号的时钟周期，确定延迟驱动信号总延迟位数所需各级延迟时钟信号的时钟周期数量，然后再基于确定的各级延迟时钟信号的时钟周期数量对驱动信号依次进行延迟；该方法在所需延迟的驱动信号的数据量一定的前提下，相对于直接采用寄存器延迟信号，在可靠实现信号延迟的同时，还有效减少了所需设置的寄存器数量。

Description

信号延迟方法、装置、系统及医疗挂号设备 技术领域
本申请涉及通信技术领域，特别涉及一种信号延迟方法、装置、系统及医疗挂号设备。
背景技术
对驱动信号进行延迟处理(简称信号延迟)是驱动一些设备正常工作必不可少的步骤之一。
相关技术中，一般采用寄存器缓存待延迟的驱动信号，并在指定时刻输出该驱动信号，以实现对驱动信号的延迟处理。
但是，若待延迟的驱动信号数据量较大，则所需设置的寄存器数量也会相应的增多，占用信号延迟电路较多存储空间。
发明内容
本申请提供了一种信号延迟方法、装置、系统及医疗挂号设备，所述技术方案如下：
一方面，提供了一种信号延迟方法，所述方法包括：
确定驱动信号所需延迟的总延迟位数；
根据多级延迟时钟信号中每一级所述延迟时钟信号的时钟周期，确定延迟所述总延迟位数所需的每一级所述延迟时钟信号的时钟周期数量，其中，自第一级所述延迟时钟信号至最后一级所述延迟时钟信号，各级所述延迟时钟信号的时钟周期依次减小；
按照时钟周期由大到小的顺序，依次采用每一级所述延迟时钟信号的时钟周期数量，对所述驱动信号进行延迟后输出。
可选的，所述多级延迟时钟信号基于主时钟信号生成；所述根据多级延迟时钟信号中每一级所述延迟时钟信号的时钟周期，确定延迟所述总延迟位数所需的每一级所述延迟时钟信号的时钟周期数量，包括：
对于每一级所述延迟时钟信号，根据所述主时钟信号的时钟频率和所述延迟时钟信号的时钟频率，确定所述延迟时钟信号对应的备选延迟位数，所述备选延迟位数是指所述延迟时钟信号的一个时钟周期所能完成的延迟位数；
对于每一级所述延迟时钟信号，根据参考延迟位数以及所述延迟时钟信号对应的备选延迟位数，确定延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量；
其中，对于第一级所述延迟时钟信号，所述参考延迟位数为所述总延迟位数，对于除第一级所述延迟时钟信号之外的其他级所述延迟时钟信号，所述参考延迟位数为采用前一级所述延迟时钟信号的时钟周期数量对所述驱动信号进行延迟后的剩余延迟位数。
可选的，所述对于每一级所述延迟时钟信号，根据所述主时钟信号的时钟频率和所述延迟时钟信号的时钟频率，确定所述延迟时钟信号对应的备选延迟位数，包括：
对于每一级所述延迟时钟信号，将所述主时钟信号的时钟频率除以所述延迟时钟信号的时钟频率得到的商值确定为所述延迟时钟信号对应的备选延迟位数。
可选的，所述对于每一级所述延迟时钟信号，根据参考延迟位数以及所述延迟时钟信号对应的备选延迟位数，确定延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量，包括：
对于每一级所述延迟时钟信号，对参考延迟位数除以所述延迟时钟信号对应的备选延迟位数得到的商值进行向下取整，得到延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量。
可选的，若所述驱动信号在所述延迟时钟信号的第一跳变沿发生跳变，且采用第一级所述延迟时钟信号的第二跳变沿延迟所述驱动信号，所述第一跳变沿和所述第二跳变沿中，一个为上升沿，一个为下降沿；则对于第一级所述延迟时钟信号，所述根据参考延迟位数以及所述延迟时钟信号对应的备选延迟位数，确定延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量，包括：
对参考延迟位数除以第一级所述延迟时钟信号对应的备选延迟位数得到的商值进行向下取整，得到延迟所述总延迟位数所需的第一级所述延迟时钟信号的备选时钟周期数量；
将所述备选时钟周期数量与1/2之和确定为延迟所述总延迟位数所需的第一级所述延迟时钟信号的时钟周期数量。
可选的，所述多级延迟时钟信号的级数为4；其中，第三级所述延迟时钟信号的时钟周期为第四级所述延迟时钟信号的时钟周期的8倍，第二级所述延迟时钟信号的时钟周期为第三级所述延迟时钟信号的时钟周期的10倍，第一级所述延迟时钟信号的时钟周期为第二级所述延迟时钟信号的时钟周期的5倍。
可选的，所述确定驱动信号所需延迟的总延迟位数，包括：
接收延迟参考信息；
基于所述延迟参考信息，确定驱动信号所需延迟的总延迟位数。
可选的，在所述确定驱动信号所需延迟的总延迟位数之前，所述方法还包括：生成所述驱动信号。
另一方面，提供了一种信号延迟电路，所述信号延迟电路用于执行如上述方面所述的信号延迟方法。
可选的，所述信号延迟电路为现场可编程逻辑门阵列FPGA。
又一方面，提供了一种信号延迟系统，所述系统包括：目标器件、驱动电路以及如上述方面所述的信号延迟电路；
所述信号延迟电路与所述驱动电路连接，所述信号延迟电路用于将驱动信号延迟总延迟位数后输出至所述驱动电路；
所述驱动电路与所述目标器件连接，所述驱动电路用于响应于接收到的所述驱动信号驱动所述目标器件工作。
可选的，所述系统还包括：通讯模块，所述通讯模块与所述信号延迟电路连接，所述通讯模块用于接收延迟参考信息，并将所述延迟参考信息输出至所述信号延迟电路。
可选的，所述目标器件为超声波换能器，所述系统包括多个所述超声波换能器组成的换能器阵列；
其中，所述驱动电路用于响应于接收到的所述驱动信号，驱动所述超声波换能器发出超声波，以形成虚拟按键。
再一方面，提供了一种医疗挂号设备，所述设备包括：依次通信连接的计算机、打印机、医保卡读取组件、摄像组件以及虚拟按键产生系统，所述虚拟按键产生系统包括如上述方面所述的信号延迟系统；
所述医保卡读取组件用于读取医保卡信息，并将所述医保卡信息发送至所述计算机；
所述摄像组件用于若检测到针对所述虚拟按键产生系统中任一超声波换能器的触控操作，则对所述虚拟按键产生系统中换能器阵列所在的区域进行拍摄，并将拍摄得到的图像发送至所述计算机；
所述计算机用于基于所述图像确定所述触控操作所针对的目标超声波换能器，并在确定所述目标超声波换能器在所述计算机的显示界面中的映射位置位于按键区域后，将延迟参考信息发送至所述虚拟按键产生系统，以及用于响应于挂号触发操作生成挂号信息，并控制所述打印机打印所述挂号信息；
所述虚拟按键产生系统用于基于所述延迟参考信息形成虚拟按键；
其中，所述延迟参考信息包括：所述目标超声波换能器在所述换能器阵列中的位置。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种信号延迟系统的结构示意图；
图2是本申请实施例提供的另一种信号延迟系统的结构示意图；
图3是本申请实施例提供的一种信号延迟电路的内部程序框架图；
图4是本申请实施例提供的一种信号延迟方法的流程图；
图5是本申请实施例提供的另一种信号延迟方法的流程图；
图6是本申请实施例提供的一种多级延迟时钟信号的延迟顺序示意图；
图7是本申请实施例提供的一种各级延迟时钟信号的仿真图；
图8是图7所示仿真图的局部放大图；
图9是本申请实施例提供的一种延迟前后驱动信号的时序仿真图；
图10是本申请实施例提供的一种医疗挂号设备的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
采用信号延迟电路对信号进行延迟是驱动一些系统正常工作必不可少的步骤之一。其中，信号延迟可以理解为在接收到或是产生系统中某器件所需的信号(例如，驱动信号)时，将信号延迟固定时长后再输出至对应的器件。如此，在系统包括由多个相同的器件组成的阵列时，可以通过灵活延迟向该阵列中不同器件输出的信号，使得该阵列完成一些特定功能，即使得该阵列可靠工作。
示例的，图1示出了一种信号延迟系统的结构示意图。如图1所示，该信号延迟系统可以包括：目标器件01、驱动电路02和一个信号延迟电路03。
信号延迟电路03可以与驱动电路02连接，该信号延迟电路03可以用于生成驱动信号，并将生成的驱动信号延迟总延迟位数后输出至驱动电路02。
驱动电路02可以与目标器件01连接，驱动电路02可以基于接收到的驱动信号驱动目标器件01工作。
可选的，总延迟位数可以用于决定信号延迟的时长，且总延迟位数可以为信号延迟电路03基于接收到的延迟参考信息灵活生成的，对于不同的信号延迟应用场景，信号延迟电路03接收到的延迟参考信息可以不同，且该延迟参考信息可以由与该系统建立有通信连接的计算机设备发送。
为了对总延迟位数进行示意性说明，结合图1所示信号延迟系统，图2示出了另一种信号延迟系统的结构示意图。如图2所示，目标器件01可以为超声波换能器，且该系统还可以包括：由多个超声波换能器组成的换能器阵列00。
相应的，延迟参考信息可以包括：超声波换能器在换能器阵列00中的位置。驱动电路02响应于驱动信号驱动目标器件01工作可以理解为：驱动电路02驱动超声波换能器发出超声波，即超声波换能器在接收到的驱动信号的控制下可以发出超声波。如此，通过灵活延迟向不同超声波换能器输出的驱动信号，可以使得换能器阵列00中不同超声波换能器在不同时刻发出超声波，即使得不同超声波换能器在不同时刻振动。可选的，在将图2所示的系统应用于生成虚拟按键的场景下时，可以通过控制不同超声波换能器在不同时刻发出振动，以聚焦形成虚拟按键。形成虚拟按键也可以理解为：形成虚拟按键的触觉，以供用户感知其手当前所在位置处具有按键控件。
可选的，再结合图2所示信号延迟系统，该系统还可以包括：通讯模块04。该通讯模块04可以与信号延迟电路03连接。该通讯模块04可以用于接收延迟参考信息，并将延迟参考信息输出至信号延迟电路03。
可选的，再结合图2所示信号延迟系统，该系统中的信号延迟电路03可以为现场可编程逻辑门阵列(field programmable gate Array，FPGA)。示例的，图3示出了FPGA内部程序框架图。如图3所示，该程序框架可以包括：PS端和PL端，PS端和PL端均可以用于与通讯模块04直接建立通讯连接，且PS端和PL端之间可以进行数据交互传输。图3以PL端与通讯模块04建立通讯连接为例，进一步示出PL端所包括的可选程序框架图，参考图3，PL端可以包括网口通讯模块、PS-PL通讯模块、驱动信号产生模块和延迟模块。
其中，驱动信号产生模块可以用于产生驱动信号(也可以称为激励信号)。网口通讯模块可以用于接收通讯模块04输出的延迟参考信息并发送至PS-PL通讯模块。PS-PL通讯模块可以将延迟参考信息进一步传输至PS端。PS端可以用于基于接收到的延迟参考信息确定延迟驱动信号所需的总延迟位数，并将总延迟位数通过PS-PL通讯模块传输至PL端。PL端中的延迟模块可以用于基于总延迟位数对驱动信号产生模块产生的驱动信号进行延迟后输出至驱动电路02。
需要说明的是，信号延迟电路03并不限于为FPGA，也可以为其他能够对信号进行延迟的设备，如单片机。目标器件01也并不限于超声波换能器，可以为其他任何需要响应于延迟后的驱动信号工作的器件。
图4是本公开实施例提供的一种信号延迟方法的流程示意图，可以应用于图1或图2所示的信号延迟电路03中。如图4所示，该方法可以包括：
步骤401、确定驱动信号所需延迟的总延迟位数。
结合上述实施例可知，在本公开实施例中，可以由信号延迟电路03直接基于接收到的延迟参考信息进一步确定驱动信号所需延迟的总延迟位数，该总延迟位数决定了驱动信号所需延迟的总时长。
步骤402、根据多级延迟时钟信号中每一级延迟时钟信号的时钟周期，确定延迟总延迟位数所需的每一级延迟时钟信号的时钟周期数量。
其中，自第一级延迟时钟信号至最后一级延迟时钟信号，各级延迟时钟信号的时钟周期可以依次减小。如此，可以便于对驱动信号进行逐步精细化延迟。
可选的，可以由信号延迟电路先基于每一级延迟时钟信号的时钟周期，确定一个时钟周期的每一级延迟时钟信号所能延迟的延迟位数，然后再基于每一级延迟时钟信号每个时钟周期所能延迟的延迟位数，确定延迟总延迟位数所需的每一级延迟时钟信号的时钟周期数量。即，对于每一级延迟时钟信号而言，确定延迟总延迟位数所需几个时钟周期的该级延迟时钟信号。
步骤403、按照时钟周期由大到小的顺序，依次采用每一级延迟时钟信号的时钟周期数量，对驱动信号进行延迟后输出。
示例的，假设总延迟位数为2000，且共包括2级延迟时钟信号，延迟总延迟位数的驱动信号所需第一级延迟时钟信号的时钟周期数量为4，第二级延迟时钟信号的时钟周期数量为2。则信号延迟电路可以先将驱动信号延迟4个时钟周期的第一级延迟时钟信号，再将驱动信号延迟2个时钟周期的第二级延迟时钟信号后输出。如此，即使得驱动信号共被延迟总延迟位数后才输出。
基于上述示例可知，采用本公开实施例的信号延迟方法，延迟2000个总延迟位数，可能共需用到6个寄存器即可(一个时钟周期的延迟时钟信号对应1个寄存器)。而若采用相关技术中的方法对其延迟，一般需要几百甚至几千个寄存器。由此可以看出，在延迟的驱动信号一致的前提下，本公开实施例的信号延迟方法有效减少了所需的寄存器数量，且不会影响延迟效果。
综上所述，本公开实施例提供了一种信号延迟方法。由于是先基于各级延迟时钟信号的时钟周期，确定延迟驱动信号总延迟位数所需各级延迟时钟信号的时钟周期数量，然后再基于确定的各级延迟时钟信号的时钟周期数量对驱动信号依次进行延迟，因此在所需延迟的驱动信号的数据量一定的前提下，相对于直接采用寄存器延迟信号，该方法在可靠实现信号延迟的同时，还有效减少了所需设置的寄存器数量。
图5是本公开实施例提供的另一种信号延迟方法的流程示意图，可以应用于图1或图2所示的信号延迟电路03中。如图5所示，该方法可以包括：
步骤501、生成驱动信号。
可选的，结合图2所示信号延迟系统可知，在本公开实施例中，信号延迟电路03中一般包括用于生成驱动信号的驱动信号产生模块，该驱动信号产生模块可以用于产生驱动目标器件所需的驱动信号。
例如，结合图2，假设目标器件为超声波换能器，则生成的驱动信号即可以为能够驱动超声波换能器发出超声波的信号，也可以称为激励信号。
步骤502、接收延迟参考信息。
可选的，在本公开实施例中，信号延迟电路03可以接收与其建立有通信连接的计算机设备向其发送的延迟参考信息，该延迟参考信息可以用于信号延迟电路03进一步确定延迟驱动信号所需的总延迟位数。
例如，结合图2，假设目标器件为超声波换能器，系统还包括换能器阵列，那么该延迟参考信息可以包括：目标超声波换能器在换能器阵列中的位置(可用坐标表示)，目标超声波换能器可以是指换能器阵列中当前待驱动的换能器。
步骤503、基于延迟参考信息，确定驱动信号所需延迟的总延迟位数。
可选的，信号延迟电路03在接收到延迟参考信息后，可以先基于接收到的延迟参考信息确定目标器件在当前时刻的多长时间后需要响应于驱动信号工作，然后再基于确定的时长进一步计算得到延迟驱动信号所需的总延迟位数。如此，即可以使得在延迟驱动信号总延迟位数后，目标器件恰好能够在对应时刻(即距当前时刻的指定时长后)接收到驱动信号，并响应于驱动信号工作。
例如，结合图2，假设目标超声波换能器为换能器阵列左上方的第一个超声波换能器。则首先，信号延迟电路03可以基于该目标超声波换能器的位置，确定该目标超声波换能器与换能器阵列中心位置处的超声波换能器的距离。然后，再基于距离确定该目标超声波换能器发出超声波的时刻距当前时刻的目标时长，即确定目标超声波换能器需要在多久后发出超声波。最后，再基于目标时长确定延迟驱动目标超声波换能器的驱动信号的总延迟位数，以使得目标超声波换能器可以响应于延迟后的驱动信号，在当前时刻的目标时长后发出超声波。
步骤504、对于每一级延迟时钟信号，根据主时钟信号的时钟频率和延迟时钟信号的时钟频率，确定延迟时钟信号对应的备选延迟位数。
需要说明的是，多级延迟时钟信号可以基于一主时钟信号生成。即，信号延迟电路03其实可以仅连接至一能够提供主时钟信号的时钟信号端，该时钟信号端可以用于生成主时钟信号，信号延迟电路03可以响应于该主时钟信号生成信号延迟所需的多级延迟时钟信号，且生成的延迟时钟信号的级数与总延迟位数可以成正比。即，总延迟位数越大，生成的延迟时钟信号的级数越多；反之，总延迟位数越小，生成的延迟时钟信号的级数越少。
此外，在本公开实施例中，信号延迟电路03生成的多级延迟时钟信号中，第一级延迟时钟信号至最后一级延迟时钟信号，各级延迟时钟信号的时钟周期可以依次减小。换言之，各级延迟时钟信号的时钟频率可以依次变大。
示例的，结合图6，信号延迟电路03可以采用时钟分频技术，将主时钟信号CLK分为4级延迟时钟信号。其中，第四级延迟时钟信号CLK的时钟周期与主时钟信号CLK可以相同(故，用相同标识表明)，第三级延迟时钟信号CLKB的时钟周期可以为第四级延迟时钟信号CLK的时钟周期的8倍，第二级延迟时钟信号CLKC的时钟周期可以为第三级延迟时钟信号CLKB的时钟周期的10倍，第一级延迟时钟信号CLKD的时钟周期可以为第二级延迟时钟信号CLKC的时钟周期的5倍。换言之，第一级延迟时钟信号CLKD的时钟频率可以为第二级延迟时钟信号CLKC的时钟频率的5分频(即，1/5)，第二级延迟时钟信号CLKC的时钟频率可以为第三级延迟时钟信号CLKB的时钟频率的10分频，第三级延迟时钟信号CLKB的时钟频率可以为第四级延迟时钟信号CLK的时钟频率的8分频，第四级延迟时钟信号CLK的时钟频率与主时钟信号CLK相同。
可选的，图7示意性的示出了该四级延迟时钟信号的仿真图，图8为图7所示仿真图的局部放大图。
需要说明的是，本公开实施例并不限定生成的延迟时钟信号的级数和每级的频率为上述实施例记载的内容，即还可以包括更多或更少级数的延迟时钟信号，且每级延迟时钟信号的频率和周期可以满足其他条件，在此不再一一赘述。
可选的，备选延迟位数可以是指延迟时钟信号的一个时钟周期所能完成的延迟位数。即，对于每一级延迟时钟信号而言，采用该延迟时钟信号的一个时钟周期对驱动信号进行延迟，所能延迟的延迟位数。且，一个时钟周期可以是指由一个上升沿至相邻的另一个上升沿这一阶段；或者，由一个下降沿至相邻的另一个下降沿这一阶段。如，结合上述图8所示仿真图，T0即代表第三级延迟时钟信号CLKB的一个时钟周期，其他延迟时钟信号同理。
可选的，在本公开实施例中，对于每一级延迟时钟信号，信号延迟电路03可以将主时钟信号的时钟频率除以延迟时钟信号的时钟频率得到的商值确定为该级延迟时钟信号对应的备选延迟位数。另，因时钟周期和时钟频率成反比，故也可以采用时钟周期计算备选延迟位数，在此不再进一步赘述。
示例的，假设主时钟信号CLK的时钟频率为32兆赫兹(MHz)，第一级 延迟时钟信号CLKD的时钟频率为80千赫兹(KHz)，则基于确定备选延迟位数的方法可知，第一级延迟时钟信号CLKD的备选延迟位数(也可以称为延迟数据)Num_subD可以为32MHz/80KHz＝400。即，一个时钟周期的第一级延迟时钟信号CLKD能够将驱动信号延迟400位数。
步骤505、对于每一级延迟时钟信号，根据参考延迟位数以及延迟时钟信号对应的备选延迟位数，确定延迟总延迟位数所需的延迟时钟信号的时钟周期数量。
其中，对于第一级延迟时钟信号，参考延迟位数可以为总延迟位数。对于除第一级延迟时钟信号之外的其他级延迟时钟信号，参考延迟位数可以为采用前一级延迟时钟信号的时钟周期数量对驱动信号进行延迟后的剩余延迟位数。
例如，假设总延迟位数为2025，则对于第一级延迟时钟信号CLKD而言，参考延迟位数即为2025。再假设第一级延迟时钟信号CLKD共将驱动信号延迟了1025位，则可知剩余延迟位数即为：2025-1025＝1000。相应的。对于第二级延迟时钟信号CLKC而言，参考延迟位数即为1000。以此类推，不再赘述。
为了确保对驱动信号的有效延迟，对于每一级延迟时钟信号，信号延迟电路03可以对参考延迟位数除以延迟时钟信号对应的备选延迟位数得到的商值进行向下取整，以得到延迟总延迟位数所需的延迟时钟信号的时钟周期数量。向下取整可以是指：不参考四舍五入的规则，只要后面有小数则忽略小数。
示例的，假设总延迟位数为2025，第一级延迟时钟信号CLKD对应的备选延迟位数为400，即一个时钟周期的第一级延迟时钟信号CLKD可以延迟400位数，则相应的，可以计算得到延迟总延迟位数所需该级延迟时钟信号CLKD的时钟周期数量NumD为：2025/400＝4.56，向下取整即为4。也即是，将驱动信号延迟2025位数，需要采用4个时钟周期的第一级延迟时钟信号CLKD。
需要说明的是，为了避免驱动信号与第一级延迟时钟信号出现同沿竞争的问题，可以设置驱动信号在第一级延迟时钟信号CLKD的第一跳变沿发生跳变，且设置采用第一级延迟时钟信号CLKD的第二跳变沿延迟驱动信号，第一跳变沿和第二跳变沿中，一个为上升沿，一个为下降沿。即，假设驱动信号在上升沿发生信号跳变，则采用第一级延迟时钟信号CLKD的下降沿延迟驱动信号。
如此，对于第一级延迟时钟信号CLKD而言，在延迟驱动信号时，首先采用1/2个时钟周期的CLKD延迟驱动信号，之后，采用每完整的一个时钟周期 的CLKD延迟驱动信号。且，对于1/2个时钟周期的CLKD延迟驱动信号而言，其所能延迟的延迟位数即为一个时钟周期的CLKD的备选延迟位数的1/2。相应的，对于第一级延迟时钟信号CLKD而言，可以先对总延迟位数除以备选延迟位数得到的商值进行向下取整，得到延迟总延迟位数所需的第一级延迟时钟信号的备选时钟周期数量；然后再将该备选时钟周期数量与1/2之和，确定为延迟总延迟位数的驱动信号所需该延迟时钟信号CLKD最终的时钟周期数量。
示例的，假设延迟2025位数，所需第一级延迟时钟信号CLKD的备选时钟周期数量为4，则可知延迟2025位数的驱动信号所需该延迟时钟信号CLKD最终的时钟周期数量其实为4.5。再假设第一级延迟时钟信号CLKD的备选延迟位数为400，则可知1/2个时钟周期的CLKD所能延迟的延迟位数为200。经第一级延迟时钟信号CLKD延迟后，还剩余：2025-400*4-200＝225。即，还剩余225位数，需采用第一级延迟时钟信号CLKD之后的其他级延迟时钟信号继续延迟。在该情况下，对于第二级延迟时钟信号CLKC而言，其参考延迟位数NumC即为225。若驱动信号data_D经第一级延迟时钟信号CLKD延迟后变为data_C，则data_C和data_D之间即相差400*4+200＝1800位数，4.5个时钟周期的CLKD。
步骤506、按照时钟周期由大到小的顺序，依次采用每一级延迟时钟信号的时钟周期数量，对驱动信号进行延迟后输出。
在本公开实施例中，在确定出延迟总延迟位数所需各级延迟时钟信号的时钟周期数量后，信号延迟电路03即可以采用每一级延迟时钟信号的时钟周期数量，对驱动信号进行延迟后输出。
例如，假设共包括图6所示的四级延迟时钟信号，第一级延迟时钟信号CLKD的时钟周期数量为4.5，第二级延迟时钟信号CLKC的时钟周期数量为2，第三级延迟时钟信号CLKB的时钟周期数量为1，第一级延迟时钟信号CLK的时钟周期数量为0.5，则信号延迟电路03可以先采用4.5个时钟周期的CLKD对待延迟的驱动信号(data_D)进行第一级延迟，得到延迟后的一级延迟信号(data_C)；然后再采用2个时钟周期的CLKC对一级延迟信号进行第二级延迟，得到延迟后的二级延迟信号(data_B)；然后再采用1个时钟周期的CLKB对二级延迟信号进行第三级延迟，得到延迟后的三级延迟信号(data)；最后再采用0.5个时钟周期的CLK对三级延迟信号进行第四级延迟得到最终延迟好的驱动信号，并输出至驱动电路02。
示例的，图9示出了延迟前的驱动信号data_D和延迟后的驱动信号data_C的时序仿真图。结合图9可以进一步看出，延迟后的驱动信号data_C和延迟前的驱动信号data_D相差4.5个时钟周期T0的延迟时钟信号CLKD。
可选的，对于第四级延迟而言，还可以直接采用寄存器缓存延迟的方式进行最后一次延迟。且结合图3和图6，第一级延迟可以为信号延迟电路03中的程序模块D(Module D)执行的延迟，第二级延迟可以为信号延迟电路03中的程序模块C(Module C)执行的延迟，第三级延迟可以为信号延迟电路03中的程序模块B(Module B)执行的延迟，第四级延迟可以为信号延迟电路03中的程序模块A(Module A)执行的延迟。Module A至Module D均为程序虚拟模块。
需要说明的是，结合图6，驱动信号可以先缓存于第一级延迟中，以与多级延迟时钟信号(包括第一级延迟时钟信号CLKD、第二级延迟时钟信号CLKC和第三级延迟时钟信号CLKB)的跳变沿对齐，从而可以可靠避免因跳变沿不对齐而在后续延迟过程中产生的误差。
还需要说明的是，本公开实施例提供的信号延迟方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。如步骤501和步骤502的顺序可以调换，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内可轻易想到变化的方法，都应涵盖在发明的保护范围之内，因此不再赘述。
综上所述，本公开实施例提供了一种信号延迟方法。由于是先基于各级延迟时钟信号的时钟周期，确定延迟驱动信号总延迟位数所需各级延迟时钟信号的时钟周期数量，然后再基于确定的各级延迟时钟信号的时钟周期数量对驱动信号依次进行延迟，因此在所需延迟的驱动信号的数据量一定的前提下，相对于直接采用寄存器延迟信号，该方法在可靠实现信号延迟的同时，还有效减少了所需设置的寄存器数量。
可选的，本公开实施例还提供了一种医疗挂号设备。如图10所示，该医疗挂号设备可以包括：依次通信连接的虚拟按键产生系统10、计算机20、打印机30、医保卡读取组件40和摄像组件50。
其中，该虚拟按键产生系统10可以包括图1至图3任一所示的信号延迟系统100。此外，结合图10，该信号延迟系统100可以包括换能器阵列00，以及控制该换能器阵列00工作的控制电路。结合上述实施例可知，该控制电路可以 包括：通讯模块04、信号延迟电路03和驱动电路02(图10未示出)。
可选的，医保卡读取组件40可以用于读取医保卡信息，并将医保卡信息发送至计算机20。该医保卡信息可以为待挂号的用户放置于医保卡读取组件40上的医保卡的信息，即在进行挂号时，用户可以直接将医保卡置于医保卡读取组件40上，供医保卡读取组件40读取其医保卡内的信息(简称医保卡信息)。
摄像组件50可以用于若检测到针对虚拟按键产生系统10中任一超声波换能器的触控操作，则对虚拟按键产生系统10中换能器阵列00所在的区域进行拍摄，并将拍摄得到的图像发送至计算机20。
示例的，用户可以在虚拟按键产生系统10上进行触控操作，且触控操作可以映射于计算机20的显示界面上。即，用户在虚拟按键产生系统10上执行的一系列操作均可以映射为：在计算机20上执行的操作。如此，因用户未直接触控计算机20执行任何操作，故该医疗挂号设备也可以称为非接触式挂号设备。当用户触控虚拟按键产生系统10时，拍摄组件50可以实时拍摄以抓取虚拟按键产生系统10中换能器阵列00所在区域的图像，并发送至计算机20。可选的，该摄像组件50可以为深度摄像机。
该计算机20可以用于基于接收到的图像确定触控操作所针对的目标超声波换能器，并在确定目标超声波换能器在计算机20的显示界面中的映射位置位于按键区域后，将延迟参考信息发送至虚拟按键产生系统10，以及可以用于响应于挂号触发操作生成挂号信息，并控制打印机40打印挂号信息。虚拟按键产生系统10可以用于基于接收到的延迟参考信息形成虚拟按键。
可选的，按键区域是指：计算机20的显示界面中按键控件所处区域。在本公开实施例中，计算机20可以基于摄像组件50拍摄到的图像灵活确定用户的触控操作于虚拟按键产生系统10上的位置，即确定用户的触控操作所针对的目标超声波换能器的位置。且在确定目标超声波换能器位于按键区域后，计算机20可以进一步将延迟参考信息发送至虚拟按键产生系统10，以供虚拟按键产生系统10基于该延迟参考信息驱动超声波换能器在指定时刻发出超声波，从而使得换能器阵列聚焦形成虚拟按键，该虚拟按键即对应计算机20显示界面显示的按键区域的按键控件。虚拟按键可以包括在不同时刻发出振动的各个超声波换能器，用户通过振动这一感知触觉可以确定其触控操作此刻是否位于按键区域。
可选的，在本公开实施例中，该延迟参考信息可以包括：目标超声波换能 器在换能器阵列中的位置。此外，延迟参考信息还可以包括：按键区域的中心位置，触控操作在显示界面的当前位置等任何可以用于推算总延迟位数的信息。
当用户进一步在虚拟按键处进行了点击操作后，计算机20即可以接收到挂号触发操作。此时，计算机可以进行下一步操作，如生成挂号信息，并驱动打印机40打印挂号信息，整个挂号处理结束。
需要说明的是，触控操作所针对的超声波换能器的数量不仅为一个。若为多个时，目标超声波换能器可以是指与触控操作重叠面积最大的一个超声波换能器。此外，本公开实施例记载的信号延迟系统及结合的信号延迟方法并不限于应用于上述图10所示的医疗挂号场景下。例如，还可以应用于雷达成像等其他场景。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种信号延迟方法，其中，所述方法包括：
    确定驱动信号所需延迟的总延迟位数；
    根据多级延迟时钟信号中每一级所述延迟时钟信号的时钟周期，确定延迟所述总延迟位数所需的每一级所述延迟时钟信号的时钟周期数量，其中，自第一级所述延迟时钟信号至最后一级所述延迟时钟信号，各级所述延迟时钟信号的时钟周期依次减小；
    按照时钟周期由大到小的顺序，依次采用每一级所述延迟时钟信号的时钟周期数量，对所述驱动信号进行延迟后输出。
  2. 根据权利要求1所述的方法，其中，所述多级延迟时钟信号基于主时钟信号生成；所述根据多级延迟时钟信号中每一级所述延迟时钟信号的时钟周期，确定延迟所述总延迟位数所需的每一级所述延迟时钟信号的时钟周期数量，包括：
    对于每一级所述延迟时钟信号，根据所述主时钟信号的时钟频率和所述延迟时钟信号的时钟频率，确定所述延迟时钟信号对应的备选延迟位数，所述备选延迟位数是指所述延迟时钟信号的一个时钟周期所能完成的延迟位数；
    对于每一级所述延迟时钟信号，根据参考延迟位数以及所述延迟时钟信号对应的备选延迟位数，确定延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量；
    其中，对于第一级所述延迟时钟信号，所述参考延迟位数为所述总延迟位数，对于除第一级所述延迟时钟信号之外的其他级所述延迟时钟信号，所述参考延迟位数为采用前一级所述延迟时钟信号的时钟周期数量对所述驱动信号进行延迟后的剩余延迟位数。
  3. 根据权利要求2所述的方法，其中，所述对于每一级所述延迟时钟信号，根据所述主时钟信号的时钟频率和所述延迟时钟信号的时钟频率，确定所述延迟时钟信号对应的备选延迟位数，包括：
    对于每一级所述延迟时钟信号，将所述主时钟信号的时钟频率除以所述延 迟时钟信号的时钟频率得到的商值确定为所述延迟时钟信号对应的备选延迟位数。
  4. 根据权利要求2所述的方法，其中，所述对于每一级所述延迟时钟信号，根据参考延迟位数以及所述延迟时钟信号对应的备选延迟位数，确定延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量，包括：
    对于每一级所述延迟时钟信号，对参考延迟位数除以所述延迟时钟信号对应的备选延迟位数得到的商值进行向下取整，得到延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量。
  5. 根据权利要求2所述的方法，其中，若所述驱动信号在所述延迟时钟信号的第一跳变沿发生跳变，且采用第一级所述延迟时钟信号的第二跳变沿延迟所述驱动信号，所述第一跳变沿和所述第二跳变沿中，一个为上升沿，一个为下降沿；则对于第一级所述延迟时钟信号，所述根据参考延迟位数以及所述延迟时钟信号对应的备选延迟位数，确定延迟所述总延迟位数所需的所述延迟时钟信号的时钟周期数量，包括：
    对参考延迟位数除以第一级所述延迟时钟信号对应的备选延迟位数得到的商值进行向下取整，得到延迟所述总延迟位数所需的第一级所述延迟时钟信号的备选时钟周期数量；
    将所述备选时钟周期数量与1/2之和确定为延迟所述总延迟位数所需的第一级所述延迟时钟信号的时钟周期数量。
  6. 根据权利要求1至5任一所述的方法，其中，所述多级延迟时钟信号的级数为4；其中，第三级所述延迟时钟信号的时钟周期为第四级所述延迟时钟信号的时钟周期的8倍，第二级所述延迟时钟信号的时钟周期为第三级所述延迟时钟信号的时钟周期的10倍，第一级所述延迟时钟信号的时钟周期为第二级所述延迟时钟信号的时钟周期的5倍。
  7. 根据权利要求1至6任一所述的方法，其中，所述确定驱动信号所需延迟的总延迟位数，包括：
    接收延迟参考信息；
    基于所述延迟参考信息，确定驱动信号所需延迟的总延迟位数。
  8. 根据权利要求1至7任一所述的方法，其中，在所述确定驱动信号所需延迟的总延迟位数之前，所述方法还包括：生成所述驱动信号。
  9. 根据权利要求4所述的方法，其中，所述对于每一级所述延迟时钟信号，根据所述主时钟信号的时钟频率和所述延迟时钟信号的时钟频率，确定所述延迟时钟信号对应的备选延迟位数，包括：对于每一级所述延迟时钟信号，将所述主时钟信号的时钟频率除以所述延迟时钟信号的时钟频率得到的商值确定为所述延迟时钟信号对应的备选延迟位数；
    所述多级延迟时钟信号的级数为4；其中，第三级所述延迟时钟信号的时钟周期为第四级所述延迟时钟信号的时钟周期的8倍，第二级所述延迟时钟信号的时钟周期为第三级所述延迟时钟信号的时钟周期的10倍，第一级所述延迟时钟信号的时钟周期为第二级所述延迟时钟信号的时钟周期的5倍；
    所述确定驱动信号所需延迟的总延迟位数，包括：接收延迟参考信息；基于所述延迟参考信息，确定驱动信号所需延迟的总延迟位数；
    在所述确定驱动信号所需延迟的总延迟位数之前，所述方法还包括：生成所述驱动信号。
  10. 一种信号延迟电路，其中，所述信号延迟电路用于执行如权利要求1至9任一所述的信号延迟方法。
  11. 根据权利要求10所述的信号延迟电路，其中，所述信号延迟电路为现场可编程逻辑门阵列FPGA。
  12. 一种信号延迟系统，其中，所述系统包括：目标器件、驱动电路以及如权利要求10或11所述的信号延迟电路；
    所述信号延迟电路与所述驱动电路连接，所述信号延迟电路用于将驱动信号延迟总延迟位数后输出至所述驱动电路；
    所述驱动电路与所述目标器件连接，所述驱动电路用于响应于接收到的所述驱动信号驱动所述目标器件工作。
  13. 根据权利要求12所述的系统，其中，所述系统还包括：通讯模块，所述通讯模块与所述信号延迟电路连接，所述通讯模块用于接收延迟参考信息，并将所述延迟参考信息输出至所述信号延迟电路。
  14. 根据权利要求12或13所述的系统，其中，所述目标器件为超声波换能器，所述系统包括多个所述超声波换能器组成的换能器阵列；
    其中，所述驱动电路用于响应于接收到的所述驱动信号，驱动所述超声波换能器发出超声波，以形成虚拟按键。
  15. 一种医疗挂号设备，其中，所述设备包括：依次通信连接的计算机、打印机、医保卡读取组件、摄像组件以及虚拟按键产生系统，所述虚拟按键产生系统包括如权利要求14所述的信号延迟系统；
    所述医保卡读取组件用于读取医保卡信息，并将所述医保卡信息发送至所述计算机；
    所述摄像组件用于若检测到针对所述虚拟按键产生系统中任一超声波换能器的触控操作，则对所述虚拟按键产生系统中换能器阵列所在的区域进行拍摄，并将拍摄得到的图像发送至所述计算机；
    所述计算机用于基于所述图像确定所述触控操作所针对的目标超声波换能器，并在确定所述目标超声波换能器在所述计算机的显示界面中的映射位置位于按键区域后，将延迟参考信息发送至所述虚拟按键产生系统，以及用于响应于挂号触发操作生成挂号信息，并控制所述打印机打印所述挂号信息；
    所述虚拟按键产生系统用于基于所述延迟参考信息形成虚拟按键；
    其中，所述延迟参考信息包括：所述目标超声波换能器在所述换能器阵列中的位置。
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EP2242178A1 (en) * 2009-04-15 2010-10-20 Nxp B.V. Digital phase shifting for imparting a target delay on an input signal to generate an output signal
WO2013121698A1 (ja) * 2012-02-15 2013-08-22 パナソニック株式会社 時間積分器およびδς型時間デジタル変換器
CN104113342A (zh) * 2013-11-28 2014-10-22 西安电子科技大学 用于高速数模转换器的高速数据同步电路
CN105634474A (zh) * 2014-10-31 2016-06-01 天钰科技股份有限公司 多相位延迟锁定回路
CN107066096A (zh) * 2017-04-10 2017-08-18 苏春 一种基于超声相控阵的触觉感知装置及方法
CN111198835A (zh) * 2018-11-16 2020-05-26 瑞昱半导体股份有限公司 时钟产生装置及时钟产生方法
CN110673731A (zh) * 2019-09-26 2020-01-10 吉林大学 基于可变长度移位寄存器的多通道超声波聚焦延时控制方法
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CN111429826A (zh) * 2020-04-15 2020-07-17 京东方科技集团股份有限公司 一种同步电路及其同步方法、显示装置

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