WO2022078076A1 - 像素驱动电路及显示设备、驱动方法 - Google Patents

像素驱动电路及显示设备、驱动方法 Download PDF

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Publication number
WO2022078076A1
WO2022078076A1 PCT/CN2021/114326 CN2021114326W WO2022078076A1 WO 2022078076 A1 WO2022078076 A1 WO 2022078076A1 CN 2021114326 W CN2021114326 W CN 2021114326W WO 2022078076 A1 WO2022078076 A1 WO 2022078076A1
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Prior art keywords
transistor
light
signal
emitting element
circuit
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PCT/CN2021/114326
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English (en)
French (fr)
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贾玉虎
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Oppo广东移动通信有限公司
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Publication of WO2022078076A1 publication Critical patent/WO2022078076A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the present application relates to electronic technology, and relates to, but is not limited to, a pixel driving circuit, a display device, and a driving method.
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light Emitting Diode, organic light-emitting diode display
  • an OLED display is a display that emits light by electrically exciting fluorescent organic components, and displays an image by driving each organic light-emitting unit with a voltage or current.
  • the pixel driving circuit plays a very important role, and how to design a high-quality, high-performance pixel driving circuit has become the focus of research by those skilled in the art.
  • embodiments of the present application provide a pixel driving circuit, a display device, and a driving method.
  • an embodiment of the present application provides a pixel drive circuit
  • the pixel drive circuit includes: a first transistor, a storage capacitor, a data transmission path, a second transistor, a light-emitting element, and a third transistor, wherein:
  • the first transistor for writing a data signal representing an image into the storage capacitor
  • the storage capacitor for storing the data signal
  • the data transmission path used for transmitting the data signal stored in the storage capacitor to the light-emitting element
  • the second transistor for providing current to the light-emitting element to drive the light-emitting element to emit light
  • the light-emitting element is used for emitting an optical signal corresponding to the data signal under the driving of the current;
  • the third transistor is configured to initialize the potential of the anode of the light-emitting element when the second transistor drives the light-emitting element to emit light.
  • an embodiment of the present application provides a display device, where the display device includes the pixel driving circuit described above.
  • an embodiment of the present application provides a pixel driving method, which is applied to a pixel driving circuit, and the method includes:
  • the light-emitting element is driven to emit light by the current provided by the second transistor in the circuit, so that the light-emitting element emits a light signal corresponding to the data signal;
  • the potential of the anode of the light-emitting element is initialized by the third transistor in the circuit.
  • Embodiments of the present application provide a pixel driving circuit, a display device, and a driving method.
  • the pixel driving circuit includes: a first transistor, a storage capacitor, a data transmission path, a second transistor, a light-emitting element, and a third transistor, wherein: the The first transistor is used to write the data signal representing the image into the storage capacitor; the storage capacitor is used to store the data signal; the data transmission path is used to transmit the data signal stored in the storage capacitor to the light-emitting element; the second transistor is used to provide current to the light-emitting element to drive the light-emitting element to emit light; the light-emitting element is used to emit the data signal corresponding to the data signal driven by the current
  • the third transistor is used to initialize the potential of the anode of the light-emitting element when the second transistor drives the light-emitting element to emit light.
  • FIG. 1A is a schematic diagram 1 of a circuit structure of a pixel driving circuit in the related art
  • FIG. 1B is a schematic diagram 1 of a working sequence of a pixel driving circuit in the related art
  • FIG. 2A is a schematic diagram 2 of a circuit structure of a pixel driving circuit in the related art
  • 2B is a second schematic diagram of a working sequence of a pixel driving circuit in the related art
  • FIG. 3 is a schematic diagram 1 of a circuit structure of a pixel driving circuit according to an embodiment of the present application
  • FIG. 4 is a schematic diagram 2 of a circuit structure of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the luminance change of the light-emitting element of the LTPO pixel drive circuit in the related art
  • 6A is a third schematic diagram of a circuit structure of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 6B is a schematic diagram 1 of a working sequence of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 7A is a schematic diagram of a connection structure of an EOA signal unit according to an embodiment of the present application.
  • FIG. 7B is a second working timing diagram of the pixel driving circuit according to the embodiment of the present application.
  • FIG. 8 is a schematic diagram of luminance variation of a light-emitting element of an LTPO pixel driving circuit according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an implementation flowchart of a pixel driving method according to an embodiment of the present application.
  • FIG. 1A is a schematic diagram 1 of the circuit structure of a pixel driving circuit in the related art.
  • the pixel driving circuit is 7T1C of LTPS (Low Temperature Poly Crystalline Silicon, low temperature polysilicon) (that is, 7 thin film transistors plus 1 storage unit).
  • Capacitance) circuit the 7T1C circuit requires two sets of GOA (Gate Driver On Array, array integrated gate drive) drive circuits, wherein the first scan signal (Scan1), the second scan signal (Scan2) and the third scan signal (Scan3 ) share 1 set of GOA drive circuit, and control signal (ie EM (Emission) signal) uses a set of GOA drive circuit.
  • GOA Gate Driver On Array, array integrated gate drive
  • the pixel circuit Due to the large leakage of the T3 transistor and the T4 transistor in the LTPS driving circuit, the pixel circuit cannot maintain a good charge on the storage capacitor Cst when the pixel circuit is driven at a low frequency, that is, when the frequency is 1 to 30 Hz (Hertz), so the screen is prone to appear. Problems such as flicker caused by changes in brightness. Moreover, the pixel driving circuit shown in FIG. 1A can only initialize point G, that is, the gate of the driving transistor T1.
  • FIG. 1B is a schematic diagram 1 of the operation timing of the pixel driving circuit in the related art.
  • the waveform 11 is the signal waveform diagram of the first scan signal (Scan1)
  • the waveform 12 is the second scan signal (Scan2) and the third scan signal.
  • the waveform 13 is the signal waveform diagram of the control signal (EM)
  • the waveforms of the second scan signal and the third scan signal are the same.
  • FIG. 2A is a schematic diagram 2 of the circuit structure of a pixel driving circuit in the related art.
  • the current LTPO Low Temperature Poly Crystalline Silicon and Oxide, low temperature polysilicon and oxide
  • the T3 transistor and T4 transistor are replaced with oxide TFT (Thin Film Transistor, thin film field effect transistor). That is, the T3 transistor and the T4 transistor in FIG. 1A are replaced from LTPS to LTPO (other transistors are still LTPS, and the connection structure of the circuit remains unchanged) to achieve the purpose of controlling leakage.
  • oxide TFT Thin Film Transistor, thin film field effect transistor
  • the working state of the pixel driving circuit shown in FIG. 2A is divided into the following three stages.
  • the light-emitting stage the T1 transistor, the T5 transistor and the T6 transistor are on, the rest of the tubes are off, and the OLED emits light.
  • FIG. 2B is a second working timing diagram of the pixel driving circuit in the related art.
  • the waveform 21 is the signal waveform diagram of the first scan signal (Scan1)
  • the waveform 22 is the signal waveform diagram of the second scan signal (Scan2).
  • the waveform 23 is the signal waveform diagram of the third scan signal (Scan3)
  • the waveform 24 is the signal waveform diagram of the control signal (EM).
  • the LTPO pixel driving circuit in FIG. 2A needs to add a set of GOA driving circuit. That is, three sets of GOA drive circuits are required, the first scan signal and the second scan signal share one set of GOA drive circuits, the third scan signal uses one set of GOA drive circuits, and the EM signal uses one set of GOA drive circuits Drive circuit. In this way, it cannot be guaranteed that the frame of the screen when the LTPO technology is used is the same as the frame of the original screen when the LTPS technology is used, so the shape and size of the screen may be affected.
  • the embodiments of the present application provide a pixel driving circuit, which not only introduces LTPO (Low Temperature Polysilicon and Oxide, Low Temperature Poly Crystalline Silicon and Oxide) transistors, but also designs a new circuit structure.
  • LTPO Low Temperature Polysilicon and Oxide, Low Temperature Poly Crystalline Silicon and Oxide
  • the following technical effects can be achieved: (1) The anode of the light-emitting element can be initialized in the data retention stage, thereby improving the problems of screen flicker and smear during low-frequency driving. (2) Both the drain and the gate of the drive tube can be initialized, thereby improving the short-term afterimage problem of the panel due to the hysteresis effect of the drive tube.
  • the drive signal is exactly the same as the GOA drive signal of the LTPS 7T1C pixel drive circuit in the prior art, so no need A new GOA drive circuit is added to ensure that the frame of the screen body can be consistent and unaffected when LTPO technology is used.
  • first ⁇ second ⁇ third involved in the embodiments of the present application is only to distinguish similar objects, and does not represent a specific ordering of objects. It is understandable that “first ⁇ second ⁇ third” "Where permitted, the specific order or sequence may be interchanged to enable the embodiments of the application described herein to be practiced in sequences other than those illustrated or described herein.
  • FIG. 3 is a schematic diagram 1 of the circuit structure of the pixel driving circuit according to the embodiment of the present application.
  • the pixel driving circuit 300 includes: a first transistor 301 , a storage capacitor 302 , The data transmission path 303, the second transistor 304, the light-emitting element 305 and the third transistor 306, wherein:
  • the first transistor 301 is used to write the data signal representing the image into the storage capacitor 302;
  • the storage capacitor 302 for storing the data signal
  • the data transmission path 303 is used to transmit the data signal stored in the storage capacitor 302 to the light-emitting element 305;
  • the second transistor 304 is used to provide current to the light-emitting element 305 to drive the light-emitting element 305 to emit light;
  • the light-emitting element 305 is used for emitting the light signal corresponding to the data signal under the driving of the current;
  • the light-emitting element may be a light-emitting diode OLED.
  • the third transistor 306 is used to initialize the potential of the anode of the light-emitting element 305 when the second transistor 304 drives the light-emitting element 305 to emit light.
  • the third transistor is used to initialize the potential of the anode of the light-emitting element when the second transistor drives the light-emitting element to emit light (that is, to emit light during the data retention stage).
  • the anode of the component is initialized), so it can improve the screen flicker, smear and other problems when driving at low frequency.
  • the embodiments of the present application further provide a pixel driving circuit
  • the pixel driving circuit includes: a first transistor, a storage capacitor, a data transmission path, a second transistor, a light-emitting element and a third transistor, wherein:
  • the first transistor for writing a data signal representing an image into the storage capacitor
  • the source of the first transistor is connected to the data signal, the gate of the first transistor is connected to the second scan signal, and the drain of the first transistor is connected to the source of the second transistor;
  • the storage capacitor for storing the data signal
  • the data transmission path used for transmitting the data signal stored in the storage capacitor to the light-emitting element
  • the second transistor for providing current to the light-emitting element to drive the light-emitting element to emit light
  • the gate of the second transistor is connected to the lower electrode of the storage capacitor; the upper electrode of the storage capacitor is connected to a working voltage;
  • the light-emitting element is used for emitting an optical signal corresponding to the data signal under the driving of the current;
  • the third transistor for initializing the potential of the anode of the light-emitting element when the second transistor drives the light-emitting element to emit light
  • the source of the third transistor is connected to the reference signal, the gate of the third transistor is connected to the control signal, the drain of the third transistor is connected to the anode of the light-emitting element; the cathode of the light-emitting element is connected Access to the ground terminal voltage;
  • the source of the third transistor is connected to the reference signal, and the drain of the third transistor is connected to the anode of the light-emitting element, so that the potential of the anode of the light-emitting element can be initialized.
  • the second scan signal is used to control the switch of the first transistor to write the data signal row by row
  • the reference signal is used to initialize the potential
  • the control signal is used to control the light emitting element. working status.
  • an embodiment of the present application further provides a pixel driving circuit
  • the pixel driving circuit includes: a first transistor, a storage capacitor, a second transistor, a light-emitting element, a third transistor, a fifth transistor, and a sixth transistor ,in:
  • the first transistor for writing a data signal representing an image into the storage capacitor
  • the source of the first transistor is connected to the data signal, the gate of the first transistor is connected to the second scan signal, and the drain of the first transistor is connected to the source of the second transistor;
  • the storage capacitor for storing the data signal
  • the fifth transistor and the sixth transistor are used to switch the light-emitting element between different working states, the different working states include an on state and an off state, wherein the light-emitting element is in a In the case of an on state, transmitting the data signal in the storage capacitor to the light-emitting element;
  • the drain of the fifth transistor is connected to the source of the second transistor, the gate of the fifth transistor is connected to the control signal, and the source of the fifth transistor is connected to the working voltage;
  • the source of the sixth transistor is connected to the drain of the second transistor, the gate of the sixth transistor is connected to the control signal, and the drain of the sixth transistor is connected to the anode of the light-emitting element connected;
  • the fifth transistor and the sixth transistor together constitute the data transmission path, and are used for switching the light-emitting element between different working states under the action of the control signal, and When the light-emitting element is in an on state, the data signal in the storage capacitor is transmitted to the light-emitting element.
  • the second transistor for providing current to the light-emitting element to drive the light-emitting element to emit light
  • the gate of the second transistor is connected to the lower electrode of the storage capacitor; the upper electrode of the storage capacitor is connected to a working voltage;
  • the light-emitting element is used for emitting an optical signal corresponding to the data signal under the driving of the current;
  • the third transistor for initializing the potential of the anode of the light-emitting element when the second transistor drives the light-emitting element to emit light
  • the source of the third transistor is connected to the reference signal, the gate of the third transistor is connected to the control signal, the drain of the third transistor is connected to the anode of the light-emitting element; the cathode of the light-emitting element is connected Access to the ground terminal voltage;
  • the second scan signal is used to control the switch of the first transistor to write the data signal row by row
  • the reference signal is used to initialize the potential
  • the control signal is used to control the light emitting element. working status.
  • an embodiment of the present application further provides a pixel driving circuit
  • the pixel driving circuit includes: a first transistor, a storage capacitor, a second transistor, a light-emitting element, a third transistor, a fourth transistor, and a fifth transistor and the sixth transistor, where:
  • the first transistor for writing a data signal representing an image into the storage capacitor
  • the source of the first transistor is connected to the data signal, the gate of the first transistor is connected to the second scan signal, and the drain of the first transistor is connected to the source of the second transistor;
  • the storage capacitor for storing the data signal
  • the fourth transistor for initializing the potentials of the drain and the gate of the second transistor
  • the gate of the fourth transistor is connected to the first scan signal, the source of the fourth transistor is connected to the reference signal, and the drain of the fourth transistor is connected to the drain of the second transistor;
  • the gate of the fourth transistor is connected to the first scan signal
  • the source of the fourth transistor is connected to the reference signal
  • the drain of the fourth transistor and the drain of the second transistor connected to initialize the potentials of the drain and gate of the second transistor (that is, initialize both the drain and the gate of the driving transistor through the fourth transistor, so that the gap between the drain and the gate of the driving transistor is The voltage is zero), which can achieve the technical effect of improving the short-term afterimage problem caused by the hysteresis effect of the driving transistor (ie, the second transistor) on the panel.
  • the fifth transistor and the sixth transistor are used to switch the light-emitting element between different working states, the different working states include an on state and an off state, wherein the light-emitting element is in a In the case of an on state, transmitting the data signal in the storage capacitor to the light-emitting element;
  • the state of the light-emitting element includes an on state, an off state, a saturated state, and the like.
  • the drain of the fifth transistor is connected to the source of the second transistor, the gate of the fifth transistor is connected to the control signal, and the source of the fifth transistor is connected to the working voltage;
  • the source of the sixth transistor is connected to the drain of the second transistor, the gate of the sixth transistor is connected to the control signal, and the drain of the sixth transistor is connected to the anode of the light-emitting element connected;
  • the second transistor for providing current to the light-emitting element to drive the light-emitting element to emit light
  • the gate of the second transistor is connected to the lower electrode of the storage capacitor; the upper electrode of the storage capacitor is connected to a working voltage;
  • the light-emitting element is used for emitting an optical signal corresponding to the data signal under the driving of the current;
  • the source of the third transistor is connected to the reference signal, the gate of the third transistor is connected to the control signal, the drain of the third transistor is connected to the anode of the light-emitting element; the cathode of the light-emitting element is connected Access to the ground terminal voltage;
  • the first scan signal is used to control the switch of the fourth transistor to write the reference signal row by row; the second scan signal is used to control the switch of the first transistor to write row by row
  • the data signal is input; the reference signal is used for potential initialization; the control signal is used to control the working state of the light-emitting element.
  • the first scan signal, the second scan signal, and the third scan signal are all row selection signals.
  • FIG. 4 is a second schematic diagram of the circuit structure of the pixel driving circuit according to the embodiment of the present application.
  • the pixel driving circuit 400 includes: a first Transistor 401, storage capacitor 402, second transistor 403, light-emitting element 404, third transistor 405, fourth transistor 406, fifth transistor 407, sixth transistor 408 and seventh transistor 409, wherein:
  • the first transistor 401 is used to write the data signal representing the image into the storage capacitor 402;
  • the source of the first transistor 401 is connected to the data signal, the gate of the first transistor 401 is connected to the second scan signal, and the drain of the first transistor 401 is connected to the source of the second transistor 403 connect;
  • the storage capacitor 402 for storing the data signal
  • the fourth transistor 406, for initializing the potentials of the drain and the gate of the second transistor 403;
  • the gate of the fourth transistor 406 is connected to the first scan signal, the source of the fourth transistor 406 is connected to the reference signal, the drain of the fourth transistor 406 and the drain of the second transistor 403 poles connected;
  • the fourth transistor is paired with the seventh transistor to initialize the potentials of the gate and drain of the second transistor.
  • the fifth transistor 407 and the sixth transistor 408 are used to switch the light-emitting element 404 between different working states, and the different working states include an on state and an off state, wherein in the When the light-emitting element 404 is in an on state, the data signal in the storage capacitor 402 is transmitted to the light-emitting element 404;
  • the drain of the fifth transistor 407 is connected to the source of the second transistor 403, the gate of the fifth transistor 407 is connected to the control signal, and the source of the fifth transistor 407 is connected to the working voltage;
  • the source of the sixth transistor 408 is connected to the drain of the second transistor 403, the gate of the sixth transistor 408 is connected to the control signal, and the drain of the sixth transistor 408 is connected to the The anodes of the light-emitting elements 404 are connected;
  • the second transistor 403 is used for providing current to the light-emitting element 404 to drive the light-emitting element 404 to emit light;
  • the gate of the second transistor 403 is connected to the lower electrode of the storage capacitor 402; the upper electrode of the storage capacitor 402 is connected to the working voltage;
  • the light-emitting element 404 is used for emitting an optical signal corresponding to the data signal under the driving of the current;
  • the third transistor 405 is used to initialize the potential of the anode of the light-emitting element 404 when the second transistor 403 drives the light-emitting element 404 to emit light;
  • the source of the third transistor 405 is connected to the reference signal, the gate of the third transistor 405 is connected to the control signal, and the drain of the third transistor 405 is connected to the anode of the light-emitting element 404; the The cathode of the light-emitting element 404 is connected to the ground terminal voltage;
  • the seventh transistor 409 for compensating for the deviation of the threshold voltage of the second transistor 403;
  • the drain of the seventh transistor 409 is connected to the gate of the second transistor 403, the gate of the seventh transistor 409 is connected to the third scan signal, and the source of the seventh transistor 409 is connected to the gate of the seventh transistor 409.
  • the drain of the second transistor 403 is connected;
  • the first scan signal is used to control the switch of the fourth transistor to write the reference signal row by row; the second scan signal is used to control the switch of the first transistor to write row by row
  • the data signal is input; the third scan signal is used to control the switch of the seventh transistor.
  • the first scan signal, the second scan signal and the third scan signal are all row selection signals; the reference signal is used for potential initialization, and the control signal is used to control the working state of the light-emitting element.
  • the pulse widths of the first scan signal and the second scan signal are the same, but there is a timing dislocation relationship. Therefore, the first scan signal and the second scan signal may use the same GOA driving signal.
  • the pulse widths of the third scan signal and the control signal are the same, but there is a timing dislocation relationship. Therefore, the third scan signal and the control signal may also use the same GOA driving signal. That is, only two sets of GOA drive circuits are required.
  • the drive signals of the pixel drive circuits in the embodiments of the present application are exactly the same as the GOA drive signals of the LTPS 7T1C pixel drive circuit in the prior art, so there is no need to add a new GOA drive circuit. , so as to ensure that the frame of the screen body can be consistent and unaffected when using LTPO technology.
  • the first transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor in the circuit are low temperature polysilicon LTPS thin film transistors; the third transistor and the seventh transistor are Low temperature polysilicon and oxide LTPO thin film transistors.
  • the first transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor are PMOS low temperature polysilicon LTPS thin film transistors, so that the first transistor, the second transistor, the fourth transistor and the fifth transistor and the operating states of the sixth transistor are both active low.
  • Both the third transistor and the seventh transistor are NMOS low temperature polysilicon and oxide LTPO thin film transistors, so that the working states of the third transistor and the seventh transistor are active high.
  • the third transistor and the seventh transistor are LTPO thin film transistors, and the other transistors are LTPS thin film transistors.
  • the pixel driving circuit does not fluctuate in continuous reading during low-frequency driving. That is, it solves the problem that the pixel circuit in the prior art cannot keep the charge of the storage capacitor Cst well when the frequency is 1 to 30 Hz (Hertz), so the screen is prone to flicker caused by brightness changes.
  • LTPO technology has been applied in some wearable products. , a technology that integrates two TFTs together.
  • the LTPO pixel driving circuit in the prior art that is, the LTPO pixel driving circuit shown in FIG. 2A not only has the problem that a new set of GOA driving circuit needs to be added, but also has the following defects:
  • FIG. 5 is a schematic diagram of the brightness change of the light-emitting element of the LTPO pixel drive circuit in the related art.
  • the curve 51 is the change curve of the brightness of the OLED with time in the state of the EM signal being switched on and off in the data refresh stage.
  • the curve 52 is the change curve of the brightness of the OLED with time when the EM signal keeps switching on and off in the data holding stage.
  • the GOA driving signal and the EOA (Emission Driver On Array, array EM signal driving) driving signal act simultaneously, which can Initialize the anode potential of the OLED.
  • the anode point A of the OLED is not initialized due to only the EOA action.
  • the EM signal is turned off, the brightness of the OLED will increase and the average brightness will increase, so that the human eye can observe the screen. Flickering, smearing, etc.
  • GOA signal action no action EOA signal action action action OLED anode point A initialization Yes no
  • the three-stage working states of the pixel driving circuit (i.e. initialization stage; data writing, threshold voltage compensation, and OLED anode initialization stage; light-emitting stage) belong to the data refresh stage in FIG. 5 .
  • initialization stage data writing, threshold voltage compensation, and OLED anode initialization stage; light-emitting stage
  • Table 1 in the data refresh stage, both the GOA signal and the EOA signal are active. In this way, the OLED anode point A is initialized, so that in the data refresh stage, with the switching of the EM signal, the brightness of the OLED also follows. normal variation.
  • the EOA signal is active, and the GOA signal is inactive, so the OLED anode point A will not be initialized, so in the data hold phase, with the switching of the EM signal, the average brightness of the OLED increases.
  • GOA includes signals such as Scan1, Scan2 and Scan3, which are the signal units for controlling the initialization and signal writing of the internal compensation circuit.
  • the EOA includes the EM signal, which is a signal unit for controlling the light emission of the OLED.
  • the embodiments of the present application propose a new LTPO pixel driving circuit.
  • the LTPO pixel driving circuit in the embodiments of the present application can be compatible with the current GOA driving signals of LTPS without adding a new GOA driving circuit. , so as to ensure that the frame of the screen body is not affected when LTPO technology is used.
  • the driving tube and the anode of the OLED can be effectively initialized, thereby solving the problems of flicker, short-term afterimage, smear and the like of the LTPO pixel driving circuit in the prior art during low-frequency driving.
  • FIG. 6A is a schematic diagram 3 of the circuit structure of the pixel driving circuit according to the embodiment of the present application.
  • the T3 transistor and the T7 transistor are oxide TFTs (ie LTPO), and the rest of the transistors (ie the T1 tube, T2 tube, T4 tube, T5 tube and T6 tube) are both PMOS (Positive Channel Metal Oxide Semiconductor, P-channel enhancement type field effect transistor) TFTs in LTPS.
  • the T1 tube is a switch tube, which is mainly used for writing data signals.
  • the T2 tube is a driving tube, and is mainly used to control the lighting state of the OLED device.
  • the T3 tube is a switch tube, and is an NMOS (N-Metal-Oxide-Semiconductor, N-channel enhancement type field effect transistor) device of IGZO (Indium Gallium Zinc Oxide), which is mainly used to control OLED Initialization of anode potential.
  • the T4 tube is a switch tube, and is mainly used to control the initialization of the lower electrode potential of the storage capacitor Cst in cooperation with the T7 tube.
  • the T5 tube and the T6 tube are switch tubes, which are mainly used to control whether the OLED device is lit.
  • the T7 tube is a switch tube, and is an IGZO NMOS device, which is mainly used to control the writing of the data compensation signal.
  • the storage capacitor Cst is mainly used for storing data signals. Since the TFT connected to the capacitor and the TFT connected to the light-emitting element are replaced with oxide TFTs with lower leakage current (ie, LTPO), the leakage path of the pixel driving circuit can be effectively reduced.
  • the Scan1 signal and the Scan2 signal share a set of driving circuits, and the Scan3 signal and the EM signal share a set of driving circuits, that is, there is no need to add a new GOA driving circuit.
  • the working state of the pixel drive circuit shown in FIG. 6A during data refresh can be divided into the following three stages:
  • Capacitor and LED anode initialization stage T3, T4 and T7 tubes are turned on, and other transistors are turned off.
  • the lower electrode of the capacitor Cst and the anode of the light emitting diode OLED are initialized, that is, the initialization voltage V ref is written into the lower electrode of the capacitor Cst and the anode of the light emitting diode OLED.
  • the V gd of the T2 tube 0, that is, the gate and drain of the T2 tube at this time. The voltage between them is zero, so that the drive transistor T2 can be initialized.
  • the I oled is the current driving the light emitting diode OLED to emit light
  • the V dd is the voltage corresponding to ELVDD in FIG. 6A
  • the V data is the data signal voltage, that is, the input voltage of the data input port Data.
  • the working state of the pixel driving circuit shown in FIG. 6A during data retention includes:
  • the T3 transistor when the EM signal in the data retention stage is turned off, the T3 transistor is turned on to reset the anode, so as to ensure that the brightness will not increase during the data retention stage of low frequency driving. , so that there will be no problems such as screen flickering and smearing.
  • FIG. 6B is a schematic diagram 1 of the working timing of the pixel driving circuit according to the embodiment of the present application.
  • the working timing is the working timing of the pixel driving circuit in the data refresh stage.
  • the waveform 61 is the first scan signal (Scan1 )
  • waveform 62 is the signal waveform of the second scan signal (Scan2)
  • waveform 63 is the signal waveform of the third scan signal (Scan3)
  • waveform 64 is the signal waveform of the control signal (EM signal).
  • the waveform widths of the Scan1 signal and the Scan2 signal are consistent, which is only a timing dislocation relationship.
  • the waveform width of the Scan3 signal and the EM signal is the same, which is only a timing dislocation relationship.
  • the Scan1 signal and the Scan2 signal can share a set of GOA drive circuits
  • the Scan3 signal and the EM signal can share a set of GOA drive circuits. Therefore, the working timing (ie, the driving timing) of the pixel driving circuit in the embodiment of the present application can be consistent with the working timing of the LTPS 7T1C pixel driving circuit in the prior art. That is, in the pixel driving circuit, the GOA driving circuit and the GOA driving circuit corresponding to the existing LTPS 7T1C pixel driving circuit can be kept consistent.
  • FIG. 7A is a schematic diagram of a connection structure of an EOA signal unit according to an embodiment of the present application.
  • a display device may include multiple EOA units, and the multiple EOA units are equivalent to a shift register.
  • ESTV is the start signal
  • the first EOA unit 701 starts to work under the trigger of the ESTV signal
  • the output signal is used to trigger the second EOA unit 702 to work
  • the output signal of the second EOA unit 702 is used again. to trigger the third EOA unit 703 to work.
  • each Scan3 signal terminal 704 is connected to a TFT 705 (equivalent to a switch), and each EOA unit includes a Scan3 signal terminal 704 and an EM signal terminal 706.
  • the TFT 705 is turned on, and the Scan3 signal terminal 704 and the EM signal terminal 706 can use this output signal together.
  • the Scan3 control signal is a signal for controlling the switch of the TFT 705, and the Scan3 control signal and the Scan3 signal are different signals.
  • FIG. 7B is a second schematic diagram of the working timing of the pixel driving circuit according to the embodiment of the present application.
  • the working timing is the working timing of the pixel driving circuit in the data refresh stage and the data retention stage.
  • the waveform 71 is controlled by Scan3
  • the signal waveform diagram of the signal, waveform 72 is the signal waveform diagram of the EOA signal (ie the EM signal), wherein the Scan3 control signal is only turned on when the data is refreshed, and the Scan3 control signal is turned off in the data retention phase.
  • EOA signal ie the EM signal
  • FIG. 8 is a schematic diagram of the brightness change of the light-emitting element of the LTPO pixel drive circuit according to the embodiment of the present application.
  • the curve 81 is the change curve of the brightness of the OLED over time when the EM signal is constantly on and off during the data refresh stage.
  • the curve 82 is the change curve of the brightness of the OLED with time when the EM signal is kept on and off during the data retention phase.
  • the GOA driving signal and the EOA driving signal act simultaneously to initialize the anode potential of the OLED.
  • the anode point A of the OLED can still be initialized. In this way, it can be solved that if the EM signal is turned off, the The increase in the brightness of OLED leads to an increase in the average brightness, so that the human eye observes the appearance of problems such as screen flickering and smearing.
  • the three-stage working states of the pixel drive circuit (ie capacitor and LED anode initialization stage; data writing, threshold voltage compensation and anode initialization stage; light-emitting stage) belong to the data refresh stage in FIG. 8 .
  • Table 2 in the data refresh stage, both the GOA signal and the EOA signal are active. In this way, the OLED anode point A is initialized, so that in the data refresh stage, with the switch of the EM signal, the brightness of the OLED also follows. normal variation.
  • the OLED anode point A will still be initialized, so that in the data hold phase, with the switch of the EM signal, the brightness of the OLED is also normal. change, there will be no problem of average brightness rising. This avoids problems such as screen flickering and smearing.
  • the embodiment of the present application provides a new LTPO pixel drive circuit, which is exactly the same as the GOA drive signal of the current LTPS 7T1C pixel drive circuit, so there is no need to add a new GOA drive circuit, so as to ensure the screen body when the LTPO technology is adopted.
  • the gate of the drive tube T2 and the anode of the light-emitting diode OLED can be initialized, thereby effectively improving the low frequency or frequency cut of the LTPO screen. flickering, smearing, and short-term afterimages.
  • the embodiment of the present application proposes a brand-new LTPO drive circuit, which can initialize the drive tube T2 and the anode of the light-emitting element, thereby effectively improving the flicker, smear and short-term afterimage of the LTPO screen at low frequency or frequency cut.
  • the LTPO circuit in the related art ie the circuit shown in FIG. 2A
  • the T4 transistor has two leakage paths, and three sets of GOA drive circuits are required at the same time, which increases the frame of the screen.
  • the LTPO circuit in the embodiment of the present application ie the circuit shown in FIG.
  • the 6A can not only initialize the gate of the driving transistor, but also initialize the drain of the driving transistor, so that the gate and the drain of the driving transistor are connected between the gate and the drain.
  • the voltage difference between the two is zero, which optimizes the hysteresis effect of the device and significantly improves the short-term afterimage and smear.
  • the initialization action of the anode of the light-emitting element can also be performed synchronously during the off period of the EM signal, thereby significantly improving the low-frequency flickering phenomenon.
  • the leakage path is reduced to only one leakage path passing through the T7 transistor, and the pixel driving circuit only needs two sets of GOA driving circuits, which is the same as the existing LTPS pixel driving circuit.
  • an embodiment of the present application provides a display device including the above-mentioned pixel driving circuit.
  • FIG. 9 is a schematic diagram of the implementation flow of the pixel driving method according to the embodiment of the present application, as shown in FIG. 9 .
  • the method includes:
  • Step S901 using the first transistor in the circuit to write the acquired data signal representing the image into the storage capacitor of the circuit;
  • Step S902 using the data transmission path in the circuit to transmit the data signal stored in the storage capacitor to the light-emitting element in the circuit;
  • Step S903 driving the light-emitting element to emit light through the current provided by the second transistor in the circuit, so that the light-emitting element emits a light signal corresponding to the data signal;
  • Step S904 when the second transistor drives the light-emitting element to emit light, use the third transistor in the circuit to initialize the potential of the anode of the light-emitting element.
  • the acquired data signal representing the image is written into the storage capacitor of the circuit by using the first transistor in the circuit; the data stored in the storage capacitor is written by using the data transmission path in the circuit
  • the signal is transmitted to the light-emitting element in the circuit; the light-emitting element is driven to emit light by the current provided by the second transistor in the circuit, so that the light-emitting element emits the light signal corresponding to the data signal; when the first transistor When two transistors drive the light-emitting element to emit light, the third transistor in the circuit is used to initialize the potential of the anode of the light-emitting element, so that the light-emitting element can be lit (that is, where the light-emitting element emits light). After the optical signal corresponding to the data signal), the third transistor is used to initialize the potential of the anode of the light-emitting element in the data retention stage, thereby improving the problems of screen flicker and smear during low-frequency driving.
  • the embodiments of the present application further provide a pixel driving method.
  • the pixel driving method is applied to the above-mentioned pixel driving circuit, and the method includes:
  • Step S911 applying a voltage smaller than the first preset value to the first scan signal, applying a voltage larger than the second preset value to the control signal, and applying a voltage larger than the first preset value to the third scanning signal, so as to turning on the third transistor, the fourth transistor and the seventh transistor;
  • the fourth transistor is a PMOS LTPS, and the working state is active low. Therefore, when a voltage less than the first preset value is applied to the first scan signal, the fourth transistor is in an on state.
  • the third transistor and the seventh transistor are NMOS LTPO, and the working state is active high. Therefore, when a voltage greater than the second preset value is applied to the control signal, the third transistor In an open state, when a voltage greater than the first preset value is applied to the third scan signal, the seventh transistor is in an open state.
  • a voltage greater than the first preset value also needs to be applied to the second scan signal at the same time, so that the first transistor is in an off state.
  • the second transistor, the fifth transistor and the sixth transistor are PMOS LTPS, the working state is active low level, and further, they are also in the off state under the action of the control signal.
  • Step S912 using the fourth transistor and the seventh transistor, write a reference signal into the lower electrode of the storage capacitor and the drain of the second transistor, so that the gate potential of the second transistor corresponds to
  • the voltage corresponding to the reference signal is the voltage corresponding to the reference signal
  • the voltage corresponding to the drain potential of the second transistor is the voltage corresponding to the reference signal
  • Step S913 transmitting the reference signal to the anode of the light-emitting element through the third transistor, so that the voltage corresponding to the anode potential of the light-emitting element is the voltage corresponding to the reference signal;
  • Step S914 applying a voltage greater than the second preset value to the control signal, applying a voltage smaller than the first preset value to the second scan signal, and applying a voltage greater than the first preset value to the third scan signal. a voltage of a preset value to turn on the first transistor, the second transistor, the third transistor and the seventh transistor;
  • the first transistor and the second transistor are PMOS LTPS, and the working state is active low. Therefore, when a voltage less than the first preset value is applied to the second scan signal, the first The transistor and the second transistor are in an on state.
  • the third transistor and the seventh transistor are NMOS LTPO, and the working state is active high. Therefore, when a voltage greater than the second preset value is applied to the control signal, the third transistor In an open state, when a voltage greater than the first preset value is applied to the third scan signal, the seventh transistor is in an open state. Of course, at the same time, a voltage greater than the first preset value also needs to be applied to the first scan signal, so that the fourth transistor is in an off state.
  • the fifth transistor and the sixth transistor are PMOS LTPS, and the working state is active low, and further, they are also turned off under the action of the control signal.
  • Step S915 using the first transistor to obtain a data signal representing an image, and writing the data signal into the storage capacitor;
  • Step S916 using the seventh transistor to compensate the deviation of the threshold voltage of the second transistor, so that the voltage corresponding to the gate potential of the second transistor is the voltage corresponding to the data signal and the second transistor. the sum of the threshold voltages of the transistors;
  • Step S917 transmitting the reference signal to the anode of the light-emitting element through the third transistor, so that the voltage corresponding to the anode potential of the light-emitting element is the voltage corresponding to the reference signal;
  • step S916 may be performed first and then the step S917 may be performed, or the step S917 may be performed first and then the step S916 may be performed.
  • Step S918 applying a voltage smaller than the second preset value to the control signal, so that the second transistor, the fifth transistor and the sixth transistor are in an on state;
  • the second transistor, the fifth transistor, and the sixth transistor are PMOS LTPS, and the working state is active low. Therefore, when a voltage less than the second preset value is applied to the control signal, The second transistor, the fifth transistor, and the sixth transistor are in an on state. Of course, it is also necessary to apply a voltage greater than the first preset value to the first scan signal and the second scan signal, and apply a voltage less than the first preset value to the third scan signal, so that the first transistor, the third The transistor, the fourth transistor and the seventh transistor are in an off state.
  • Step S919 using the fifth transistor and the sixth transistor to transmit the data signal stored in the storage capacitor to the light-emitting element;
  • Step S921 driving the light-emitting element to emit light through the current, so that the light-emitting element emits an optical signal corresponding to the data signal;
  • the I is the current that drives the light-emitting element to emit light
  • the V dd is the working voltage
  • the V data is the data signal
  • the ⁇ is the offset ratio of the second transistor
  • the Cox is the capacitance per unit area of the storage capacitor
  • the W is the width of the second transistor
  • the L is the length of the second transistor
  • Step S922 when the second transistor drives the light-emitting element to emit light, set the port corresponding to the control signal to the working state, and set the port corresponding to the first scan signal and the port corresponding to the second scan signal The port corresponding to the third scan signal is set to a non-working state;
  • Step S923 transmitting the reference signal to the anode of the light-emitting element through the third transistor, so that the voltage corresponding to the anode potential of the light-emitting element is the voltage corresponding to the reference signal.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms. of.
  • the unit described above as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may all be integrated into one processing module, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above integration
  • the unit can be implemented either in the form of hardware or in the form of hardware plus software functional units.

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Abstract

本申请实施例公开了一种像素驱动电路及显示设备、驱动方法，其中，所述像素驱动电路包括：第一晶体管、存储电容、数据传输通路、第二晶体管、发光元件和第三晶体管；所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；所述存储电容，用于存储所述数据信号；所述数据传输通路，用于将所述存储电容存储的数据信号传输给所述发光元件；所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；所述第三晶体管，用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化。

Description

像素驱动电路及显示设备、驱动方法
相关申请的交叉引用
本申请基于申请号为202011083329.0、申请日为2020年10月12日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引用的方式引入本申请。
技术领域
本申请涉及电子技术，涉及但不限于一种像素驱动电路及显示设备、驱动方法。
背景技术
目前，电子设备在人们的工作和生活中占据越来越多的时间，电子设备显示器的改进也成为人们逐渐关注的重点。随着光学技术和半导体技术的发展，以LCD(Liquid Crystal Display，液晶显示器)和OLED(Organic Light Emitting Diode，有机发光二极管显示器)为代表的显示器具有轻薄、能耗低、反应速度快、色纯度佳、以及对比度高等特点，在显示领域占据了主导地位。
其中，OLED显示器是一种通过电激励荧光有机成分来发光、并且通过利用电压或电流驱动每个有机发光单元来显示图像的显示器。而在每个有机发光单元中，像素驱动电路起着非常重要的作用，如何设计出一种高质量、高性能的像素驱动电路，成为本领域技术人员研究的重点。
发明内容
有鉴于此，本申请实施例提供一种像素驱动电路及显示设备、驱动方法。
本申请实施例的技术方案是这样实现的：
第一方面，本申请实施例提供一种像素驱动电路，所述像素驱动电路包括：第一晶体管、存储电容、数据传输通路、第二晶体管、发光元件和第三晶体管，其中：
所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；
所述存储电容，用于存储所述数据信号；
所述数据传输通路，用于将所述存储电容存储的数据信号传输给所述发光元件；
所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；
所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；
所述第三晶体管，用于当所述第二晶体管驱动所述发光元件发光时，使所 述发光元件的阳极的电位初始化。
第二方面，本申请实施例提供一种显示设备，所述显示设备包括上述所述的像素驱动电路。
第三方面，本申请实施例提供一种像素驱动方法，应用于像素驱动电路，所述方法包括：
利用所述电路中的第一晶体管将获取的表示图像的数据信号写入所述电路的存储电容；
利用所述电路中的数据传输通路将所述存储电容存储的数据信号传输给所述电路中的发光元件；
通过所述电路中的第二晶体管提供的电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号；
当所述第二晶体管驱动所述发光元件发光时，利用所述电路中的第三晶体管对所述发光元件的阳极的电位进行初始化。
本申请实施例提供一种像素驱动电路及显示设备、驱动方法，所述像素驱动电路包括：第一晶体管、存储电容、数据传输通路、第二晶体管、发光元件和第三晶体管，其中：所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；所述存储电容，用于存储所述数据信号；所述数据传输通路，用于将所述存储电容存储的数据信号传输给所述发光元件；所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；所述第三晶体管，用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化。
附图说明
图1A为相关技术中像素驱动电路的电路结构示意图一；
图1B为相关技术中像素驱动电路的工作时序示意图一；
图2A为相关技术中像素驱动电路的电路结构示意图二；
图2B为相关技术中像素驱动电路的工作时序示意图二；
图3为本申请实施例像素驱动电路的电路结构示意图一；
图4为本申请实施例像素驱动电路的电路结构示意图二；
图5为相关技术中LTPO像素驱动电路发光元件的亮度变化示意图；
图6A为本申请实施例像素驱动电路的电路结构示意图三；
图6B为本申请实施例像素驱动电路的工作时序示意图一；
图7A为本申请实施例EOA信号单元的连接结构示意图；
图7B为本申请实施例像素驱动电路的工作时序示意图二；
图8为本申请实施例LTPO像素驱动电路发光元件的亮度变化示意图；
图9为本申请实施例像素驱动方法的实现流程示意图。
具体实施方式
图1A为相关技术中像素驱动电路的电路结构示意图一，如图1A所示，所述像素驱动电路为LTPS(Low Temperature Poly Crystalline Silicon，低温多晶硅)的7T1C(即7个薄膜晶体管加1个存储电容)电路，所述7T1C电路需要两套GOA(Gate Driver On Array，阵列集成栅极驱动)驱动电路，其中第一扫描信号(Scan1)、第二扫描信号(Scan2)和第三扫描信号(Scan3)共用1套GOA驱动电路，控制信号(即EM(Emission)信号)用一套GOA驱动电路。由于LTPS驱动电路中T3晶体管和T4晶体管的漏电较大，导致该像素电路在低频驱动，即频率为1至30Hz(赫兹)时不能对存储电容Cst进行很好的电荷保持，所以屏体易出现亮度变化导致的闪烁等问题。并且，图1A所示的像素驱动电路，只能对G点，即驱动管T1的栅极进行初始化。
图1B为相关技术中像素驱动电路的工作时序示意图一，如图1B所示，波形11为第一扫描信号(Scan1)的信号波形图，波形12为第二扫描信号(Scan2)和第三扫描信号(Scan3)的信号波形图，波形13为控制信号(EM)的信号波形图，且第二扫描信号和第三扫描信号的波形相同。
图2A为相关技术中像素驱动电路的电路结构示意图二，如图2A所示，目前的LTPO(Low Temperature Poly Crystalline Silicon and Oxide，低温多晶硅和氧化物)像素驱动电路主要是将图1A中影响漏电的T3晶体管和T4晶体管更换为氧化物TFT(Thin Film Transistor，薄膜场效应晶体管)。即，将图1A中的T3晶体管和T4晶体管从LTPS更换为LTPO(其它晶体管仍为LTPS，且电路的连接结构保持不变)从而达到控制漏电的目的。
其中，图2A所示的像素驱动电路的工作状态分为以下三个阶段。第一、初始化阶段：T4晶体管处于打开状态，对电容Cst进行初始化，并将初始化电压V ref写入所述电容的下电极，此时G点电位V g＝V ref。第二、数据写入、阈值电压补偿、以及OLED阳极初始化阶段：T1晶体管、T2晶体管、T3晶体管和T7晶体管处于打开状态，将数据信号电压写入并获取此时驱动管T1的阈值电压V th，此时G点电位V g＝V data+V th，A点电位V a＝V ref。第三、发光阶段：T1晶体管、T5晶体管和T6晶体管处于打开状态，其余管子关闭，OLED发光。
图2B为相关技术中像素驱动电路的工作时序示意图二，如图2B所示，波形21为第一扫描信号(Scan1)的信号波形图，波形22为第二扫描信号(Scan2)的信号波形图，波形23为第三扫描信号(Scan3)的信号波形图，波形24为控制信号(EM)的信号波形图。可以看出，将图1A中影响漏电的T3晶体管和T4晶体管更换为氧化物TFT后，所述第二扫描信号和所述第三扫描信号的波形完全不同了，且也不是时序错位关系。因此，图2A中的LTPO像素驱动电路与图1A中的原始LTPS像素驱动电路相比，需要新增一套GOA驱动电路。即，需要三套GOA驱动电路，所述第一扫描信号和所述第二扫描信号共用一套GOA驱动电路，所述第三扫描信号使用一套GOA驱动电路，所述EM信号使用一套GOA驱动电路。如此，就不能保证采用LTPO技术时屏体的边框与原始的采用LTPS技术时的屏体边框保持一致，从而屏体的形状、大小等可能会 受到影响。
因此，本申请实施例提供了一种像素驱动电路，所述像素驱动电路不但引入了LTPO(低温多晶硅和氧化物，Low Temperature Poly Crystalline Silicon and Oxide)晶体管，还设计了新的电路结构。如此，能够达到以下技术效果：(1)能够在数据保持阶段对发光元件的阳极进行初始化，从而改善在低频驱动时的屏幕闪烁、拖影等问题。(2)能够对驱动管的漏极和栅极都进行初始化，从而改善屏体由于驱动管迟滞效应导致的短期残像问题。(3)在采用LTPO晶体管以保证像素驱动电路在低频驱动时连读不会有波动的同时，实现了驱动信号与现有技术中LTPS的7T1C像素驱动电路的GOA驱动信号完全相同，因此不需要增加新的GOA驱动电路，从而保证采用LTPO技术时屏体的边框能够前后保持一致，不受影响。
下面结合附图和实施例对本申请的技术方案进一步详细阐述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本申请的说明，其本身没有特定的意义。因此，“模块”、“部件”或“单元”可以混合地使用。
需要指出，本申请实施例所涉及的术语“第一\第二\第三”仅仅是是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本申请实施例能够以除了在这里图示或描述的以外的顺序实施。
本申请实施例提供一种像素驱动电路，图3为本申请实施例像素驱动电路的电路结构示意图一，如图3所示，所述像素驱动电路300包括：第一晶体管301、存储电容302、数据传输通路303、第二晶体管304、发光元件305和第三晶体管306，其中：
所述第一晶体管301，用于使表示图像的数据信号写入所述存储电容302；
所述存储电容302，用于存储所述数据信号；
所述数据传输通路303，用于将所述存储电容302存储的数据信号传输给所述发光元件305；
所述第二晶体管304，用于提供电流至所述发光元件305，以驱动所述发光元件305发光；
所述发光元件305，用于在所述电流的驱动下发射所述数据信号对应的光信号；
这里，所述发光元件可以是发光二极管OLED。
所述第三晶体管306，用于当所述第二晶体管304驱动所述发光元件305 发光时，使所述发光元件305的阳极的电位初始化。
本申请实施例中提供的像素驱动电路，所述第三晶体管用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化(即在数据保持阶段对发光元件的阳极进行初始化)，如此，能够改善在低频驱动时的屏幕闪烁、拖影等问题。
基于前述的实施例，本申请实施例再提供一种像素驱动电路，所述像素驱动电路包括：第一晶体管、存储电容、数据传输通路、第二晶体管、发光元件和第三晶体管，其中：
所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；
所述第一晶体管的源极接入数据信号，所述第一晶体管的栅极接入第二扫描信号，所述第一晶体管的漏极与所述第二晶体管的源极相连接；
所述存储电容，用于存储所述数据信号；
所述数据传输通路，用于将所述存储电容存储的数据信号传输给所述发光元件；
所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；
所述第二晶体管的栅极与所述存储电容的下电极相连接；所述存储电容的上电极接入工作电压；
所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；
所述第三晶体管，用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化；
所述第三晶体管的源极接入参考信号，所述第三晶体管的栅极接入控制信号，所述第三晶体管的漏极与所述发光元件的阳极相连接；所述发光元件的阴极接入接地端电压；
这里，所述第三晶体管的源极接入参考信号，其漏极与发光元件的阳极相连接，从而能对所述发光元件的阳极电位进行初始化。
其中，所述第二扫描信号用于控制所述第一晶体管的开关，以逐行写入所述数据信号，所述参考信号用于电位初始化，所述控制信号用于控制所述发光元件的工作状态。
基于前述的实施例，本申请实施例再提供一种像素驱动电路，所述像素驱动电路包括：第一晶体管、存储电容、第二晶体管、发光元件、第三晶体管、第五晶体管和第六晶体管，其中：
所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；
所述第一晶体管的源极接入数据信号，所述第一晶体管的栅极接入第二扫描信号，所述第一晶体管的漏极与所述第二晶体管的源极相连接；
所述存储电容，用于存储所述数据信号；
所述第五晶体管和所述第六晶体管，用于使所述发光元件在不同的工作状态之间进行切换，所述不同的工作状态包括导通状态和截止状态，其中在所述 发光元件处于导通状态的情况下，将所述存储电容中的数据信号传输给所述发光元件；
所述第五晶体管的漏极与所述第二晶体管的源极相连接，所述第五晶体管的栅极接入控制信号，所述第五晶体管的源极接入工作电压；
所述第六晶体管的源极与所述第二晶体管的漏极相连接，所述第六晶体管的栅极接入所述控制信号，所述第六晶体管的漏极与所述发光元件的阳极相连接；
这里，所述第五晶体管和所述第六晶体管，一起构成了所述数据传输通路，用于在所述控制信号的作用下，使所述发光元件在不同的工作状态之间进行切换，并且在所述发光元件处于导通状态的情况下，将所述存储电容中的数据信号传输给所述发光元件。
所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；
所述第二晶体管的栅极与所述存储电容的下电极相连接；所述存储电容的上电极接入工作电压；
所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；
所述第三晶体管，用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化；
所述第三晶体管的源极接入参考信号，所述第三晶体管的栅极接入控制信号，所述第三晶体管的漏极与所述发光元件的阳极相连接；所述发光元件的阴极接入接地端电压；
其中，所述第二扫描信号用于控制所述第一晶体管的开关，以逐行写入所述数据信号，所述参考信号用于电位初始化，所述控制信号用于控制所述发光元件的工作状态。
基于前述的实施例，本申请实施例再提供一种像素驱动电路，所述像素驱动电路包括：第一晶体管、存储电容、第二晶体管、发光元件、第三晶体管、第四晶体管、第五晶体管和第六晶体管，其中：
所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；
所述第一晶体管的源极接入数据信号，所述第一晶体管的栅极接入第二扫描信号，所述第一晶体管的漏极与所述第二晶体管的源极相连接；
所述存储电容，用于存储所述数据信号；
所述第四晶体管，用于使所述第二晶体管的漏极和栅极的电位初始化；
所述第四晶体管的栅极接入第一扫描信号，所述第四晶体管的源极接入所述参考信号，所述第四晶体管的漏极与所述第二晶体管的漏极相连接；
这里，通过所述第四晶体管的栅极接入第一扫描信号，所述第四晶体管的源极接入所述参考信号，所述第四晶体管的漏极与所述第二晶体管的漏极相连接，用于使所述第二晶体管的漏极和栅极的电位初始化(即通过第四晶体管对驱动管的漏极和栅极都进行初始化，从而驱动管的漏极和栅极之间的电压为零)，能够达到改善屏体由于驱动管(即第二晶体管)迟滞效应导致的短期残像问题 的技术效果。
所述第五晶体管和所述第六晶体管，用于使所述发光元件在不同的工作状态之间进行切换，所述不同的工作状态包括导通状态和截止状态，其中在所述发光元件处于导通状态的情况下，将所述存储电容中的数据信号传输给所述发光元件；
这里，所述发光元件的状态包括导通状态、截止状态和饱和状态等。
所述第五晶体管的漏极与所述第二晶体管的源极相连接，所述第五晶体管的栅极接入控制信号，所述第五晶体管的源极接入工作电压；
所述第六晶体管的源极与所述第二晶体管的漏极相连接，所述第六晶体管的栅极接入所述控制信号，所述第六晶体管的漏极与所述发光元件的阳极相连接；
所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；
所述第二晶体管的栅极与所述存储电容的下电极相连接；所述存储电容的上电极接入工作电压；
所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；
用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化；
所述第三晶体管的源极接入参考信号，所述第三晶体管的栅极接入控制信号，所述第三晶体管的漏极与所述发光元件的阳极相连接；所述发光元件的阴极接入接地端电压；
其中，所述第一扫描信号用于控制所述第四晶体管的开关，以逐行写入所述参考信号；所述第二扫描信号用于控制所述第一晶体管的开关，以逐行写入所述数据信号；所述参考信号用于电位初始化；所述控制信号用于控制所述发光元件的工作状态。
本申请实施例中，所述第一扫描信号、第二扫描信号和第三扫描信号，都为行选信号。
基于前述的实施例，本申请实施例再提供一种像素驱动电路，图4为本申请实施例像素驱动电路的电路结构示意图二，如图4所示，所述像素驱动电路400包括：第一晶体管401、存储电容402、第二晶体管403、发光元件404、第三晶体管405、第四晶体管406、第五晶体管407、第六晶体管408和第七晶体管409，其中：
所述第一晶体管401，用于使表示图像的数据信号写入所述存储电容402；
所述第一晶体管401的源极接入数据信号，所述第一晶体管401的栅极接入第二扫描信号，所述第一晶体管401的漏极与所述第二晶体管403的源极相连接；
所述存储电容402，用于存储所述数据信号；
所述第四晶体管406，用于使所述第二晶体管403的漏极和栅极的电位初始化；
所述第四晶体管406的栅极接入第一扫描信号，所述第四晶体管406的源极接入所述参考信号，所述第四晶体管406的漏极与所述第二晶体管403的漏极相连接；
这里，所述第四晶体管与所述第七晶体管搭配使得所述第二晶体管的栅极和漏极的电位初始化。
所述第五晶体管407和所述第六晶体管408，用于使所述发光元件404在不同的工作状态之间进行切换，所述不同的工作状态包括导通状态和截止状态，其中在所述发光元件404处于导通状态的情况下，将所述存储电容402中的数据信号传输给所述发光元件404；
所述第五晶体管407的漏极与所述第二晶体管403的源极相连接，所述第五晶体管407的栅极接入控制信号，所述第五晶体管407的源极接入工作电压；
所述第六晶体管408的源极与所述第二晶体管403的漏极相连接，所述第六晶体管408的栅极接入所述控制信号，所述第六晶体管408的漏极与所述发光元件404的阳极相连接；
所述第二晶体管403，用于提供电流至所述发光元件404，以驱动所述发光元件404发光；
所述第二晶体管403的栅极与所述存储电容402的下电极相连接；所述存储电容402的上电极接入工作电压；
所述发光元件404，用于在所述电流的驱动下发射所述数据信号对应的光信号；
所述第三晶体管405，用于当所述第二晶体管403驱动所述发光元件404发光时，使所述发光元件404的阳极的电位初始化；
所述第三晶体管405的源极接入参考信号，所述第三晶体管405的栅极接入控制信号，所述第三晶体管405的漏极与所述发光元件404的阳极相连接；所述发光元件404的阴极接入接地端电压；
所述第七晶体管409，用于对所述第二晶体管403的阈值电压的偏差进行补偿；
所述第七晶体管409的漏极与所述第二晶体管403的栅极相连接，所述第七晶体管409的栅极接入第三扫描信号，所述第七晶体管409的源极与所述第二晶体管403的漏极相连接；
其中，所述第一扫描信号用于控制所述第四晶体管的开关，以逐行写入所述参考信号；所述第二扫描信号用于控制所述第一晶体管的开关，以逐行写入所述数据信号；所述第三扫描信号用于控制所述第七晶体管的开关。所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为行选信号；所述参考信号用于电位初始化，所述控制信号用于控制所述发光元件的工作状态。
这里，本申请实施例提供的像素驱动电路中，所述第一扫描信号和所述第二扫描信号的脉冲宽度相同，只是存在时序错位关系。因此，所述第一扫描信号和所述第二扫描信号可以采用同一GOA驱动信号。所述第三扫描信号和所述控制信号的脉冲宽度相同，只是存在时序错位关系。因此，所述第三扫描信号和所述控制信号也可以采用同一GOA驱动信号。即只需要两套GOA驱动电 路，如此，本申请实施例中的像素驱动电路的驱动信号与现有技术中LTPS的7T1C像素驱动电路的GOA驱动信号完全相同，因此不需要增加新的GOA驱动电路，从而保证采用LTPO技术时屏体的边框能够前后保持一致，不受影响。
在一些实施例中，所述电路中第一晶体管、第二晶体管、所述第四晶体管、第五晶体管和第六晶体管为低温多晶硅LTPS薄膜晶体管；所述第三晶体管和所述第七晶体管为低温多晶硅和氧化物LTPO薄膜晶体管。
这里，所述第一晶体管、第二晶体管、第四晶体管、第五晶体管和第六晶体管为PMOS的低温多晶硅LTPS薄膜晶体管，从而所述第一晶体管、第二晶体管、第四晶体管、第五晶体管和第六晶体管的工作状态都为低电平有效。所述第三晶体管和所述第七晶体管都为NMOS的低温多晶硅和氧化物LTPO薄膜晶体管，从而所述第三晶体管和所述第七晶体管的工作状态为高电平有效。
本申请实施例中提供的像素驱动电路，通过第三晶体管和第七晶体管为LTPO薄膜晶体管，其它晶体管为LTPS薄膜晶体管，如此，能够保证像素驱动电路在低频驱动时连读不会有波动。即，解决了现有技术中的像素电路在低频驱动，即频率为1至30Hz(赫兹)时不能对存储电容Cst进行很好的电荷保持，所以屏体易出现亮度变化导致的闪烁等问题。
目前如何降低手机显示屏的功耗已经成为业内研究的热点，LTPO技术作为其中一种实现方式已经在部分穿戴式产品上得到应用，LTPO技术是一种利用LTPS高迁移率与氧化物TFT低漏电的优势，将两种TFT整合到一起的一种技术。现有技术中的LTPO像素驱动电路，即图2A所示的LTPO像素驱动电路不仅存在需要新增一套GOA驱动电路的问题，还存在以下缺陷：
图5为相关技术中LTPO像素驱动电路发光元件的亮度变化示意图，如图5所示，曲线51为在数据刷新阶段，OLED的亮度在EM信号不停开关的状态下随时间的变化曲线，曲线52为在数据保持阶段，OLED的亮度在EM信号不停开关的状态下随时间的变化曲线。在图2A所示的像素驱动电路为低频驱动的情况下，当所述像素驱动电路处于数据刷新阶段时，GOA驱动信号与EOA(Emission Driver On Array，阵列EM信号驱动)驱动信号同时动作，可以对OLED的阳极电位进行初始化。当所述像素驱动电路处于数据保持阶段时，由于只有EOA动作使得OLED的阳极A点未进行初始化，此时如果EM信号关断则OLED的亮度升高导致平均亮度升高从而人眼观察到屏幕闪烁、拖影等现象。
表1 相关技术中LTPO像素驱动电路GOA信号与EOA信号的工作状态
阶段 数据刷新阶段 数据保持阶段
GOA信号 动作 不动作
EOA信号 动作 动作
OLED阳极A点初始化 是 否
所述像素驱动电路的三个阶段的工作状态(即初始化阶段；数据写入、阈值电压补偿、以及OLED阳极初始化阶段；发光阶段)属于图5中的数据刷新 阶段。如表1所示，在数据刷新阶段，GOA信号和EOA信号都是动作的，如此，OLED阳极A点进行了初始化，从而在数据刷新阶段，随着EM信号的开关，OLED的亮度也随之正常变化。但是在数据保持阶段，只有EOA信号是动作的，GOA信号是不动作的，如此，OLED阳极A点不会进行初始化，从而在数据保持阶段，随着EM信号的开关，OLED存在平均亮度升高的问题，这样会导致屏幕闪烁、拖影等问题的出现。其中，GOA包括Scan1、Scan2和Scan3等信号，为控制内部补偿电路初始化与信号写入的信号单元。EOA包括EM信号，为控制OLED发光的信号单元。
因此，基于前述的实施例，本申请实施例提出一种新的LTPO像素驱动电路，本申请实施例中的LTPO像素驱动电路可以兼容目前LTPS的GOA驱动信号，而不需要增加新的GOA驱动电路，从而保证采用LTPO技术时屏体的边框不受影响。另外采用该电路时可以对驱动管及OLED的阳极进行有效的初始化，从而解决现有技术中的LTPO像素驱动电路在低频驱动时的闪烁、短期残影、拖影等问题。图6A为本申请实施例像素驱动电路的电路结构示意图三，如图6A所示，T3晶体管和T7晶体管为氧化物TFT(即LTPO)，其余的晶体管(即T1管、T2管、T4管、T5管和T6管)均为LTPS中PMOS(Positive Channel Metal Oxide Semiconductor，P沟道增强型场效应晶体管)的TFT。其中，所述T1管为开关管，主要用于数据信号的写入。所述T2管为驱动管，主要用于控制OLED器件的点亮状态。所述T3管为开关管，且为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)的NMOS(N-Metal-Oxide-Semiconductor，N沟道增强型场效应晶体管)器件，主要用于控制OLED阳极电位的初始化。所述T4管为开关管，主要用于与所述T7管搭配控制所述存储电容Cst下电极电位的初始化。所述T5管和T6管为开关管，主要用于控制OLED器件是否点亮。所述T7管为开关管，且为IGZO的NMOS器件，主要用于控制数据补偿信号的写入。所述存储电容Cst，主要用于保存数据信号。由于与电容相连的TFT以及与发光元件相连的TFT更换为了漏电流更低的氧化物TFT(即LTPO)，因此可以有效的降低所述像素驱动电路的漏电途径。并且，Scan1信号和Scan2信号共用一套驱动电路，Scan3信号和EM信号共用一套驱动电路，即不需要增加新的GOA驱动电路。
其中，图6A所示的像素驱动电路在数据刷新时的工作状态可以分为以下三个阶段：
(1)电容及发光二极管阳极初始化阶段：T3、T4和T7管打开，其它晶体管关闭。对电容Cst的下电极及发光二极管OLED的阳极进行初始化，即将初始化电压V ref写入所述电容Cst的下电极及所述发光二极管OLED的阳极。此时G点电位V g＝V ref，A点电位V a＝V ref，且D点电位V d＝V ref，因此T2管的V gd＝0，即此时T2管的栅极和漏极之间的电压为零，从而可以对驱动管T2进行初始化处理。
(2)数据写入、阈值电压补偿及阳极初始化阶段：T1、T2、T3和T7管打开，其它晶体管关闭。将数据信号电压V data写入并获取此时驱动管T2的阈值 电压V th，此时G点电位V g＝V data+V th，即此时对驱动管T2的阈值电压的偏差进行了补偿。同时，对A点进行复位重置，此时A点电位V a＝V ref。
(3)发光阶段：T2、T5和T6管打开，其它晶体管关闭。此时控制发光二极管OLED发光，且驱动所述OLED发光的电流满足以下公式：I oled＝1/2K*(V dd-V data) 2。其中，所述I oled为驱动发光二极管OLED发光的电流，所述V dd为图6A中ELVDD对应的电压，所述V data为数据信号电压，即数据输入端口Data的输入电压。所述K由公式K＝μ*Cox*W/L获得，其中，μ为T1管的偏移率，所述Cox为所述存储电容Cst的单位面积电容，所述W为所述T1管的宽度，所述L为所述T1管的长度。
其中，图6A所示的像素驱动电路在数据保持时的工作状态包括：
(1)低频补偿阶段：Scan1信号、Scan2信号和Scan3信号关闭(即Scan1信号、Scan2信号和Scan3信号处于非工作状态)，EM信号打开(EM信号处于工作状态)。在驱动OLED点亮的同时对A点即OLED的阳极进行初始化，此时A点电位V a＝V ref。
也就是说，本申请实施例中的LTPO像素驱动电路，在数据保持阶段的EM信号关断时，打开了T3晶体管对阳极进行了复位，以保证在低频驱动的数据保持阶段亮度不会升高，从而不会出现屏幕闪烁、拖影等问题。
图6B为本申请实施例像素驱动电路的工作时序示意图一，所述工作时序为所述像素驱动电路在数据刷新阶段时的工作时序，如图6B所示，波形61为第一扫描信号(Scan1)的信号波形图，波形62为第二扫描信号(Scan2)的信号波形图，波形63为第三扫描信号(Scan3)的信号波形图，波形64为控制信号(EM信号)的信号波形图。可以看出，Scan1信号与Scan2信号的波形宽度一致，仅为时序错位关系。Scan3信号与EM信号的波形宽度一致，仅为时序错位关系，因此Scan1信号和Scan2信号可以共用一套GOA驱动电路，Scan3信号和EM信号可以共用一套GOA驱动电路。从而本申请实施例中像素驱动电路的工作时序(即驱动时序)与现有技术中的LTPS的7T1C像素驱动电路的工作时序可以保持一致。即，在该像素驱动电路中GOA驱动电路与现有LTPS的7T1C像素驱动电路对应的GOA驱动电路可以保持一致。
图7A为本申请实施例EOA信号单元的连接结构示意图，如图7A所示，显示设备可以包括多个EOA单元，并且所述多个EOA单元相当于一个移位的寄存器。ESTV为起始信号，所述第一EOA单元701在所述ESTV信号的触发下开始工作，其输出的信号又用于触发第二EOA单元702工作，同时第二EOA单元702的输出信号又用于触发第三EOA单元703工作。同时，Scan3信号和EOA信号(即EM信号)共用一个电路，这个电路输出的信号(即输出信号)即能给EM信号端使用也能给Scan3信号端使用。如图7A所示，每个Scan3信号端704都接了一个TFT 705(相当于一个开关)，且每一EOA单元都包括一个Scan3信号端704和一个EM信号端706。所述TFT 705打开，Scan3信号端704和EM信号端706可以一起使用这个输出信号。所述TFT 705关闭，则所述输出信号只给Scan3信号端704使用，或只给EM信号端706使用。其中， 所述Scan3控制信号为控制所述TFT 705管开关的信号，Scan3控制信号与Scan3信号为不同的信号。
图7B为本申请实施例像素驱动电路的工作时序示意图二，所述工作时序为所述像素驱动电路在数据刷新阶段和数据保持阶段时的工作时序，如图7B所示，波形71为Scan3控制信号的信号波形图，波形72为EOA信号(即EM信号)的信号波形图，其中，所述Scan3控制信号只在数据刷新时开启，在数据保持阶段Scan3控制信号是关闭的。
图8为本申请实施例LTPO像素驱动电路发光元件的亮度变化示意图，如图8所示，曲线81为在数据刷新阶段，OLED的亮度在EM信号不停开关的状态下随时间的变化曲线，曲线82为在数据保持阶段，OLED的亮度在EM信号不停开关的状态下随时间的变化曲线。在图6A所示的像素驱动电路为低频驱动的情况下，当所述像素驱动电路处于数据刷新阶段时，GOA驱动信号与EOA驱动信号同时动作，可以对OLED的阳极电位进行初始化。当所述像素驱动电路处于数据保持阶段时，在只有EOA信号动作，所述GOA信号不动作的情况下，所述OLED的阳极A点仍能进行初始化，如此，能够解决如果EM信号关断则OLED的亮度升高导致平均亮度升高从而人眼观察到屏幕闪烁、拖影等问题的出现。
表2 本申请实施例LTPO像素驱动电路GOA信号与EOA信号的工作状态
阶段 数据刷新阶段 数据保持阶段
GOA信号 动作 不动作
EOA信号 动作 动作
OLED阳极A点初始化 是 是
所述像素驱动电路的三个阶段的工作状态(即电容及发光二极管阳极初始化阶段；数据写入、阈值电压补偿及阳极初始化阶段；发光阶段)属于图8中的数据刷新阶段。如表2所示，在数据刷新阶段，GOA信号和EOA信号都是动作的，如此，OLED阳极A点进行了初始化，从而在数据刷新阶段，随着EM信号的开关，OLED的亮度也随之正常变化。并且，在数据保持阶段，在只有EOA信号动作，GOA信号不动作的情况下，OLED阳极A点仍会进行初始化，从而在数据保持阶段，随着EM信号的开关，OLED的亮度也随之正常变化，不会存在平均亮度升高的问题。从而避免了屏幕闪烁、拖影等问题的出现。
本申请实施例提供了一种新的LTPO像素驱动电路，该电路与目前LTPS的7T1C像素驱动电路的GOA驱动信号完全相同，因此不需要增加新的GOA驱动电路，从而保证采用LTPO技术时屏体的边框与LTPS的驱动屏体保持一致不受影响，另外采用该像素驱动电路时，可以对驱动管T2的栅极和发光二极管OLED的阳极进行初始化，从而有效改善LTPO屏体在低频或切频下存在的闪烁、拖影和短期残像等问题。
表3 本申请实施例中LTPO电路与相关技术中LTPO电路的对比
Figure PCTCN2021114326-appb-000001
Figure PCTCN2021114326-appb-000002
本申请实施例提出了一种全新的LTPO驱动电路，可以对驱动管T2以及发光元件的阳极进行初始化，进而有效改善LTPO屏体在低频或切频下的闪烁、拖影和短期残像等问题。从表3中可以看出，相关技术中的LTPO电路(即图2A所示的电路)只是对驱动管的栅极进行了初始化，不能将EM信号的关断时间完全利用，并且存在T3晶体管和T4晶体管两个漏电途径，同时需要三套GOA驱动电路，增加了屏体的边框。而本申请实施例中的LTPO电路(即图6A所示的电路)，不仅能对驱动管的栅极进行初始化，还能够对驱动管的漏极进行初始化，使得驱动管栅极和漏极之间的压差为零，从而优化器件的迟滞效应，显著改善了短期残像和拖影等问题。同时，还能在EM信号关断期间同步进行发光元件阳极的初始化动作，从而显著改善了低频闪烁现象。将漏电途径降低为只有经过T7晶体管的一个漏电途径，且所述像素驱动电路只需要两套GOA驱动电路，与现有的LTPS像素驱动电路相同。
基于前述的实施例，本申请实施例提供一种显示设备，所述显示设备包括上述的像素驱动电路。
基于前述的实施例，本申请实施例提供一种像素驱动方法，所述像素驱动方法应用于上述的像素驱动电路，图9为本申请实施例像素驱动方法的实现流程示意图，如图9所示，所述方法包括：
步骤S901、利用所述电路中的第一晶体管将获取的表示图像的数据信号写入所述电路的存储电容；
步骤S902、利用所述电路中的数据传输通路将所述存储电容存储的数据信号传输给所述电路中的发光元件；
步骤S903、通过所述电路中的第二晶体管提供的电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号；
步骤S904、当所述第二晶体管驱动所述发光元件发光时，利用所述电路中的第三晶体管对所述发光元件的阳极的电位进行初始化。
本申请实施例中，通过利用所述电路中的第一晶体管将获取的表示图像的 数据信号写入所述电路的存储电容；利用所述电路中的数据传输通路将所述存储电容存储的数据信号传输给所述电路中的发光元件；通过所述电路中的第二晶体管提供的电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号；当所述第二晶体管驱动所述发光元件发光时，利用所述电路中的第三晶体管对所述发光元件的阳极的电位进行初始化，如此，能够在所述发光元件被点亮(即所述发光元件发射所述数据信号对应的光信号)后，在数据保持阶段利用所述第三晶体管对所述发光元件的阳极的电位进行初始化，从而改善在低频驱动时的屏幕闪烁、拖影等问题。
基于前述的实施例，本申请实施例再提供一种像素驱动方法，所述像素驱动方法应用于上述的像素驱动电路，所述方法包括：
步骤S911、对第一扫描信号施加小于第一预设值的电压，对控制信号施加大于第二预设值的电压，并对第三扫描信号施加大于所述第一预设值的电压，以使所述第三晶体管、第四晶体管和第七晶体管处于打开状态；
这里，所述第四晶体管为PMOS的LTPS，工作状态为低电平有效，因此在对第一扫描信号施加小于第一预设值的电压的情况下，所述第四晶体管处于打开状态。所述第三晶体管和所述第七晶体管为NMOS的LTPO，工作状态为高电平有效，因此，在对所述控制信号施加大于第二预设值的电压的情况下，所述第三晶体管处于打开状态，在对所述第三扫描信号施加大于所述第一预设值的电压的情况下，所述第七晶体管处于打开状态。当然，同时还需要对第二扫描信号施加大于第一预设值的电压，以使所述第一晶体管处于关闭状态。所述第二晶体管、第五晶体管和第六晶体管为PMOS的LTPS，工作状态为低电平有效，进而在所述控制信号的作用下也处于关闭状态。
步骤S912、利用所述第四晶体管和所述第七晶体管，将参考信号写入所述存储电容的下电极和所述第二晶体管的漏极，以使所述第二晶体管的栅极电位对应的电压为所述参考信号对应的电压，所述第二晶体管的漏极电位对应的电压为所述参考信号对应的电压；
步骤S913、通过所述第三晶体管将所述参考信号传输至所述发光元件的阳极，以使所述发光元件的阳极电位对应的电压为所述参考信号对应的电压；
步骤S914、对所述控制信号施加大于所述第二预设值的电压，对第二扫描信号施加小于所述第一预设值的电压，并对所述第三扫描信号施加大于所述第一预设值的电压，以使所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第七晶体管处于打开状态；
这里，所述第一晶体管和所述第二晶体管为PMOS的LTPS，工作状态为低电平有效，因此在对第二扫描信号施加小于第一预设值的电压的情况下，所述第一晶体管和所述第二晶体管处于打开状态。所述第三晶体管和所述第七晶体管为NMOS的LTPO，工作状态为高电平有效，因此，在对所述控制信号施加大于第二预设值的电压的情况下，所述第三晶体管处于打开状态，在对所述第三扫描信号施加大于所述第一预设值的电压的情况下，所述第七晶体管处于打开状态。当然，同时还需要对第一扫描信号施加大于第一预设值的电压，以 使所述第四晶体管处于关闭状态。所述第五晶体管和第六晶体管为PMOS的LTPS，工作状态为低电平有效，进而在所述控制信号的作用下也处于关闭状态。
步骤S915、利用所述第一晶体管获取表示图像的数据信号，并将所述数据信号写入所述存储电容；
步骤S916、利用所述第七晶体管对所述第二晶体管的阈值电压的偏差进行补偿，以使所述第二晶体管的栅极电位对应的电压为所述数据信号对应的电压和所述第二晶体管的阈值电压的和；
步骤S917、通过所述第三晶体管将所述参考信号传输至所述发光元件的阳极，以使所述发光元件的阳极电位对应的电压为所述参考信号对应的电压；
这里，对所述步骤S916和所述步骤S917的执行顺序并没有具体要求。可以先执行所述步骤S916再执行所述步骤S917，也可以先执行所述步骤S917再执行所述步骤S916。
步骤S918、对所述控制信号施加小于所述第二预设值的电压，以使所述第二晶体管、第五晶体管和第六晶体管处于打开状态；
这里，所述第二晶体管、第五晶体管和所述第六晶体管为PMOS的LTPS，工作状态为低电平有效，因此在对所述控制信号施加小于第二预设值的电压的情况下，所述第二晶体管、第五晶体管和所述第六晶体管处于打开状态。当然，同时还需要对第一扫描信号和第二扫描信号施加大于第一预设值的电压，对第三扫描信号施加小于第一预设值的电压，以使所述第一晶体管、第三晶体管、第四晶体管和第七晶体管处于关闭状态。
步骤S919、利用所述第五晶体管和所述第六晶体管，将所述存储电容存储的数据信号传输给所述发光元件；
步骤S920、利用公式I＝1/2K*(V dd-V data) 2，确定所述第二晶体管提供的电流；
步骤S921、通过所述电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号；
其中，所述I为驱动所述发光元件发光的电流，所述V dd为工作电压，所述V data为所述数据信号，所述K由公式K＝μ*Cox*W/L确定，所述μ为所述第二晶体管的偏移率，所述Cox为所述存储电容的单位面积电容，所述W为所述第二晶体管的宽度，所述L为所述第二晶体管的长度；
步骤S922、当所述第二晶体管驱动所述发光元件发光时，将所述控制信号对应的端口设置为工作状态，将所述第一扫描信号对应的端口、所述第二扫描信号对应的端口和所述第三扫描信号对应的端口设置为非工作状态；
步骤S923、通过所述第三晶体管将所述参考信号传输至所述发光元件的阳极，以使所述发光元件的阳极电位对应的电压为所述参考信号对应的电压。
以上方法实施例的描述，与上述电路实施例的描述是类似的，具有同电路实施例相似的有益效果。对于本申请方法实施例中未披露的技术细节，请参照本申请电路实施例的描述而理解。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法， 可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。另外，在本申请各实施例中的各功能单元可以全部集成在一个处理模块中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤。
本申请所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素驱动电路，其中，所述像素驱动电路包括：第一晶体管、存储电容、数据传输通路、第二晶体管、发光元件和第三晶体管，其中：
    所述第一晶体管，用于使表示图像的数据信号写入所述存储电容；
    所述存储电容，用于存储所述数据信号；
    所述数据传输通路，用于将所述存储电容存储的数据信号传输给所述发光元件；
    所述第二晶体管，用于提供电流至所述发光元件，以驱动所述发光元件发光；
    所述发光元件，用于在所述电流的驱动下发射所述数据信号对应的光信号；
    所述第三晶体管，用于当所述第二晶体管驱动所述发光元件发光时，使所述发光元件的阳极的电位初始化。
  2. 根据权利要求1所述的电路，其中，
    所述第一晶体管的源极接入数据信号，所述第一晶体管的栅极接入第二扫描信号，所述第一晶体管的漏极与所述第二晶体管的源极相连接；
    所述第二晶体管的栅极与所述存储电容的下电极相连接；所述存储电容的上电极接入工作电压；
    所述第三晶体管的源极接入参考信号，所述第三晶体管的栅极接入控制信号，所述第三晶体管的漏极与所述发光元件的阳极相连接；所述发光元件的阴极接入接地端电压；
    其中，所述第二扫描信号用于控制所述第一晶体管的开关，以逐行写入所述数据信号，所述参考信号用于电位初始化，所述控制信号用于控制所述发光元件的工作状态。
  3. 根据权利要求2所述的电路，其中，所述数据传输通路包括：第五晶体管和第六晶体管，其中：
    所述第五晶体管和所述第六晶体管，用于使所述发光元件在不同的工作状态之间进行切换，所述不同的工作状态包括导通状态和截止状态，其中在所述发光元件处于导通状态的情况下，将所述存储电容中的数据信号传输给所述发光元件；
    所述第五晶体管的漏极与所述第二晶体管的源极相连接，所述第五晶体管的栅极接入控制信号，所述第五晶体管的源极接入工作电压；
    所述第六晶体管的源极与所述第二晶体管的漏极相连接，所述第六晶体管的栅极接入所述控制信号，所述第六晶体管的漏极与所述发光元件的阳极相连接。
  4. 根据权利要求3所述的电路，其中，所述电路还包括：第四晶体管， 其中：
    所述第四晶体管，用于使所述第二晶体管的漏极和栅极的电位初始化；
    所述第四晶体管的栅极接入第一扫描信号，所述第四晶体管的源极接入所述参考信号，所述第四晶体管的漏极与所述第二晶体管的漏极相连接；
    其中，所述第一扫描信号用于控制所述第四晶体管的开关，以逐行写入所述参考信号。
  5. 根据权利要求4所述的电路，其中，所述电路还包括：第七晶体管，其中：
    所述第七晶体管，用于对所述第二晶体管的阈值电压的偏差进行补偿；
    所述第七晶体管的漏极与所述第二晶体管的栅极相连接，所述第七晶体管的栅极接入第三扫描信号，所述第七晶体管的源极与所述第二晶体管的漏极相连接；
    其中，所述第三扫描信号用于控制所述第七晶体管的开关。
  6. 根据权利要求5所述的电路，其中，所述电路中第一晶体管、第二晶体管、所述第四晶体管、第五晶体管和第六晶体管为低温多晶硅薄膜晶体管；所述第三晶体管和所述第七晶体管为低温多晶硅和氧化物薄膜晶体管。
  7. 根据权利要求6所述的电路，其中，所述第一晶体管、第二晶体管、所述第四晶体管、第五晶体管和第六晶体管为PMOS的低温多晶硅薄膜晶体管。
  8. 根据权利要求7所述的电路，其中，所述第三晶体管和所述第七晶体管为NMOS的低温多晶硅和氧化物薄膜晶体管。
  9. 根据权利要求5所述的电路，其中，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为行选信号。
  10. 根据权利要求5所述的电路，其中，所述第一扫描信号和所述第二扫描信号的脉冲宽度相同，时序不同；所述第三扫描信号和所述控制信号的脉冲宽度相同，时序不同。
  11. 根据权利要求10所述的电路，其中，所述第一扫描信号和所述第二扫描信号采用第一GOA驱动电路产生的驱动信号，所述第三扫描信号和所述控制信号采用第二GOA驱动电路产生的驱动信号；其中，所述第一GOA驱动电路和所述第二GOA驱动电路为两套不同的GOA驱动电路。
  12. 一种显示设备，其中，所述显示设备包括权利要求1至6中任一项所述的像素驱动电路。
  13. 一种像素驱动方法，其中，应用于像素驱动电路，所述方法包括：
    利用所述电路中的第一晶体管将获取的表示图像的数据信号写入所述电路的存储电容；
    利用所述电路中的数据传输通路将所述存储电容存储的数据信号传输给所述电路中的发光元件；
    通过所述电路中的第二晶体管提供的电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号；
    当所述第二晶体管驱动所述发光元件发光时，利用所述电路中的第三晶体管对所述发光元件的阳极的电位进行初始化。
  14. 根据权利要求13所述的方法，其中，所述方法还包括：
    对第一扫描信号施加小于第一预设值的电压，对控制信号施加大于第二预设值的电压，并对第三扫描信号施加大于所述第一预设值的电压，以使所述第三晶体管、第四晶体管和第七晶体管处于打开状态；
    利用所述第四晶体管和所述第七晶体管，将参考信号写入所述存储电容的下电极和所述第二晶体管的漏极，以使所述第二晶体管的栅极电位对应的电压为所述参考信号对应的电压，所述第二晶体管的漏极电位对应的电压为所述参考信号对应的电压；
    通过所述第三晶体管将所述参考信号传输至所述发光元件的阳极，以使所述发光元件的阳极电位对应的电压为所述参考信号对应的电压。
  15. 根据权利要求14所述的方法，其中，所述利用所述电路中的第一晶体管将获取的表示图像的数据信号写入所述电路的存储电容，包括：
    对所述控制信号施加大于所述第二预设值的电压，对第二扫描信号施加小于所述第一预设值的电压，并对所述第三扫描信号施加大于所述第一预设值的电压，以使所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第七晶体管处于打开状态；
    利用所述第一晶体管获取表示图像的数据信号，并将所述数据信号写入所述存储电容。
  16. 根据权利要求15所述的方法，其中，所述利用所述第一晶体管获取表示图像的数据信号，并将所述数据信号写入所述存储电容之后，所述方法还包括：
    利用所述第七晶体管对所述第二晶体管的阈值电压的偏差进行补偿，以使所述第二晶体管的栅极电位对应的电压为所述数据信号对应的电压和所述第二晶体管的阈值电压的和。
  17. 根据权利要求15或16所述的方法，其中，所述利用所述第一晶体管获取表示图像的数据信号，并将所述数据信号写入所述存储电容之后，所述方法还包括：
    通过所述第三晶体管将所述参考信号传输至所述发光元件的阳极，以使所述发光元件的阳极电位对应的电压为所述参考信号对应的电压。
  18. 根据权利要求17所述的方法，其中，所述数据传输通路包括第五晶体管和第六晶体管；对应地，所述利用所述电路中的数据传输通路将所述存储电容存储的数据信号传输给所述电路中的发光元件，包括：
    对所述控制信号施加小于所述第二预设值的电压，以使所述第二晶体管、第五晶体管和第六晶体管处于打开状态；
    利用所述第五晶体管和所述第六晶体管，将所述存储电容存储的数据信号传输给所述发光元件。
  19. 根据权利要求18所述的方法，其中，所述通过所述电路中的第二晶体管提供的电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号，包括：
    利用公式I＝1/2K*(V dd-V data) 2，确定所述第二晶体管提供的电流；
    通过所述电流驱动所述发光元件发光，以使所述发光元件发射所述数据信号对应的光信号；
    其中，所述I为驱动所述发光元件发光的电流，所述V dd为工作电压，所述V data为所述数据信号，所述K由公式K＝μ*Cox*W/L确定，所述μ为所述第二晶体管的偏移率，所述Cox为所述存储电容的单位面积电容，所述W为所述第二晶体管的宽度，所述L为所述第二晶体管的长度。
  20. 根据权利要求19所述的方法，其中，所述当所述第二晶体管驱动所述发光元件发光时，利用所述电路中的第三晶体管对所述发光元件的阳极的电位进行初始化，包括：
    当所述第二晶体管驱动所述发光元件发光时，将所述控制信号对应的端口设置为工作状态，将所述第一扫描信号对应的端口、所述第二扫描信号对应的端口和所述第三扫描信号对应的端口设置为非工作状态；
    通过所述第三晶体管将所述参考信号传输至所述发光元件的阳极，以使所述发光元件的阳极电位对应的电压为所述参考信号对应的电压。
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