WO2022077940A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2022077940A1
WO2022077940A1 PCT/CN2021/100138 CN2021100138W WO2022077940A1 WO 2022077940 A1 WO2022077940 A1 WO 2022077940A1 CN 2021100138 W CN2021100138 W CN 2021100138W WO 2022077940 A1 WO2022077940 A1 WO 2022077940A1
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layer
word line
source
semiconductor device
drain
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English (en)
French (fr)
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吴公一
陆勇
辛欣
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/439,054 priority Critical patent/US12213309B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor device and a method for fabricating the same.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes transistors and storage nodes, and a plurality of memory cells are connected into a memory cell array through word lines and bit lines.
  • the word line voltage connected to the gate of the transistor can control the turning on and off of the transistor, so that the data information stored in the storage node can be read through the bit line, or the data information can be written into the capacitor.
  • the present disclosure provides a semiconductor device and a preparation method thereof.
  • the semiconductor device prepared by the preparation method of the semiconductor device can reduce the leakage current and the parasitic capacitance effect between the bit line structure and the capacitor, and has good performance and reliability. high.
  • a method for fabricating a semiconductor device includes: providing a semiconductor substrate formed with a trench isolation structure and a functional region between the trench isolation structures; forming a buried bit a line structure, the buried bit line structure is formed in the semiconductor substrate; a word line structure and an active region are formed, the word line structure and the active region are formed on the surface of the semiconductor substrate and located in above the ribbon.
  • the step of forming the word line structure includes: forming a stacked structure on the surface of the semiconductor substrate, the stacked structure including a passivation layer, a word line conductive layer and a top layer that are stacked in sequence word line barrier layer; patterning the stacked structure to form a primary word line structure pattern; forming a side word line barrier layer on the sidewall of the primary word line structure pattern, the side word line barrier layer and the top
  • the word line barrier layer together constitutes a word line barrier layer
  • the passivation layer, the word line conductive layer and the word line barrier layer together constitute the word line structure.
  • the method for fabricating the semiconductor device further includes: forming a dielectric layer on the surface of the word line structure; forming a channel layer on the surface of the dielectric layer; wherein, the dielectric layer Covering the word line structure, the channel layer covers the dielectric layer.
  • a dielectric layer is formed on the surface of the word line structure; the step of forming a channel layer on the surface of the dielectric layer includes: on the surface of the semiconductor substrate and the word line structure forming a primary dielectric layer on the surface; forming a primary channel layer on the surface of the primary dielectric layer; removing part of the primary dielectric layer and the primary channel layer located on the surface of the semiconductor substrate, leaving the top and the primary dielectric layer and the primary channel layer of the sidewalls to form the dielectric layer and the channel layer.
  • the method for fabricating the semiconductor device further includes: performing ion implantation into the channel layer to form a gate channel.
  • the step of forming an active region includes: forming a source-drain structure above the functional region on a surface of the semiconductor substrate as the active region.
  • forming the source-drain structure above the functional region on the surface of the semiconductor substrate includes the following step: filling and forming a cap between the surface of the semiconductor substrate and the gate channel.
  • the source and drain layers on the surface of the gate channel; the source and drain layers located above the gate channel and part of the source and drain layers located on the sidewalls of the word line channel are removed to form a source and drain structure, the word line channel Including a dielectric layer and a gate channel.
  • the step of filling and forming a source-drain layer covering the surface of the gate channel between the surface of the semiconductor substrate and the gate channel using a molecular epitaxy process to form the source Drain layer; in-situ doping is performed on the source and drain layers while the source and drain layers are formed, or ion implantation is performed on the source and drain layers after the source and drain layers are formed.
  • the height of the source-drain structure is 30 nm ⁇ 100 nm.
  • the step of forming the buried bit line structure includes: forming an insulating trench in the semiconductor substrate; forming a bottom wall covering the insulating trench and a bottom wall in the insulating trench; A bit line barrier layer on part of the sidewalls; a bit line conductive layer is formed on the surface of the bit line barrier layer and fills part of the insulating trench.
  • the step of forming the buried bit line structure further includes: forming an isolation layer on the surface of the bit line barrier layer, the surface of the bit line conductive layer and the sidewall of the insulating trench; A polysilicon layer is formed on the surface of the isolation layer and the insulating trench is filled.
  • the following step is performed: performing rapid heat treatment on the isolation layer.
  • the isolation layer material is cobalt or titanium.
  • the present disclosure also proposes a semiconductor device, comprising: a semiconductor substrate provided with a trench isolation structure and a functional region between the trench isolation structures; a buried bit line structure, the A buried bit line structure is arranged in the semiconductor substrate; a word line structure and a source-drain structure are arranged on the surface of the semiconductor substrate and above the functional region.
  • the semiconductor device further includes a channel layer covering at least a surface of the word line structure and a dielectric layer, the channel layer covering a surface of the dielectric layer .
  • the source-drain structure is disposed above the functional region and on sides of the channel layer and the dielectric layer.
  • the height of the source-drain structure is 30 nm ⁇ 100 nm.
  • a buried bit line structure is formed in a semiconductor substrate, a word line structure and a source-drain structure are formed above the semiconductor substrate, and subsequent capacitors are formed on the source-drain structure.
  • the distance between the buried bit line structure and the subsequently formed capacitor device is increased, the leakage current between the bit line structure and the capacitor is reduced, and the leakage current between the bit line structure and the capacitor is also reduced. Parasitic capacitance effects improve the performance and reliability of semiconductor devices.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the disclosure
  • 2-20 are cross-sectional views of structures formed in various steps in a method for fabricating a semiconductor device according to an embodiment of the disclosure.
  • bit line structure 21: insulating trench
  • 22 bit line barrier layer
  • 23 bit line conductive layer
  • 24 isolation layer
  • 25 polysilicon layer
  • 26 contact layer
  • word line structure 31: passivation layer, 32: word line conductive layer, 33: top word line barrier layer, 34: primary word line structure pattern, 35: side word line barrier layer, 36: word line barrier layer ;
  • 61 first mask layer
  • 62 second mask layer
  • 63 third mask layer
  • 64 fourth mask layer
  • 65 photoresist layer
  • 66 filling layer.
  • a method for fabricating a semiconductor device 100 may include: providing a semiconductor substrate 1 formed with a trench isolation structure 11 and located between the trench isolation structures 11 functional area 12 between; forming a buried bit line structure 2, the buried bit line structure 2 is formed in the semiconductor substrate 1; forming a word line structure 3 and an active region, the word line structure 3 and the active region is formed on the surface of the semiconductor substrate 1 and located above the functional region 12 .
  • FIGS. 2 to 20 are cross-sectional views of structures formed by various steps of a method for fabricating a semiconductor device 100 according to an embodiment of the present disclosure. The embodiments of the present disclosure are described with reference to the cross-sectional views of the structures formed by each of the steps shown in FIGS. 2 to 20 . The process flow of the preparation method.
  • a semiconductor substrate 1 is provided, and the material of the semiconductor substrate 1 can be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) ), germanium on insulator (GOI); or other materials, such as III-V group compounds such as gallium arsenide.
  • the semiconductor substrate 1 is formed with a trench isolation structure 11 and a functional region 12 located between the trench isolation structures 11.
  • the trench isolation structure 11 isolates a plurality of functional regions 12 in the semiconductor substrate 1.
  • the trench isolation structure 11 may It includes isolation trenches and insulating materials filled in the isolation trenches, and the insulating materials may be silicon oxide materials or the like.
  • a buried bit line structure 2 is formed, and the buried bit line structure 2 is formed in the semiconductor substrate 1 .
  • the steps of forming the buried bit line structure 2 include: as shown in FIG. 3 , forming an insulating trench 21 in the semiconductor substrate 1 ; as shown in FIGS. 4-6 , forming a covering insulating trench in the insulating trench 21 21 Bit line barrier layer 22 on the bottom wall and part of the sidewall; a bit line conductive layer 23 is formed on the surface of the bit line barrier layer 22 and fills part of the insulating trench 21 .
  • a first mask layer 61 is deposited on the surface of the semiconductor substrate 1 , the semiconductor substrate 1 is patterned by using the first mask layer 61 as a mask, and an insulating trench 21 is formed in the semiconductor substrate 1 .
  • the trenches 21 are formed in the functional regions 12 between the trench isolation structures 11, and the buried bit line structures 2 are formed in the insulating trenches 21, wherein the depth of the insulating trenches 21 may be 60 nm ⁇ 150 nm, for example, may be 80 nm , 100 nm, 120 nm, etc., the width of the insulating trench 21 may be 10 nm ⁇ 60 nm, for example, may be 20 nm, 30 nm, 40 nm, or 50 nm.
  • the bit line barrier layer 22 is formed on the surface of the first mask layer 61 and the inner wall surface of the insulating trench 21 , wherein the bit line barrier layer 22 can be formed by atomic layer deposition.
  • the material may be TiN (titanium nitride) material, and the thickness of the bit line barrier layer 22 may be 3 nm ⁇ 8 nm, for example, may be 4 nm, 5 nm, 6 nm, or 7 nm.
  • a bit line conductive layer 23 is formed on the surface of the bit line barrier layer 22 .
  • the bit line barrier layer 22 and the bit line conductive layer 23 fill the insulating trench 21 , and the bit line located in the insulating trench 21
  • the barrier layer 22 wraps the bit line conductive layer 23, the material of the bit line conductive layer 23 can be tungsten material, and the bit line conductive layer 23 can be formed by chemical vapor deposition or physical vapor deposition.
  • the surface of the bit line conductive layer 23 is processed so that the surface of the bit line conductive layer 23 is flattened.
  • part of the bit line barrier layer 22 and part of the bit line conductive layer 23 located above the first mask layer 61 are removed, and part of the bit line conductive layer 23 and part of the bit line located in the insulating trench 21 are removed
  • the depth of the engraving can be 30 nm to 120 nm.
  • the process of etching back the bit line barrier layer 22 and the bit line conductive layer 23 includes: dry etching the bit line barrier layer 22 and the bit line conductive layer 23 back, and using wet etching to remove the residual bits on the sidewalls of dry etching.
  • Line barrier layer 22 .
  • the surface of the remaining bit line barrier layer 22 is flush with the surface of the bit line conductive layer 23 and wraps the bit line conductive layer 23 to avoid ion migration in the bit line conductive layer 23 and to block isolation.
  • the isolation layer 24 is deposited on the surface of the first mask layer 61 , the inner wall surface of the insulating trench 21 and the surface of the bit line barrier layer 22 and the bit line conductive layer 23 , and polysilicon is formed on the surface of the isolation layer 24 layer 25 and fill the insulating trench 21, wherein the material of the isolation layer 24 can be cobalt material or titanium material, which can be formed by physical vapor deposition, and then deposited by chemical vapor deposition to form a polysilicon layer 25, which is flattened by chemical mechanical polishing process The surface of the polysilicon layer 25 is cured.
  • the polysilicon layer 25 can be doped with elements, for example, the polysilicon layer 25 can be doped with P element, so as to increase the conductivity of the polysilicon layer 25 and improve the electrical connection of the buried bit line structure 2 Effect.
  • the polysilicon layer 25 , the isolation layer 24 and the first mask layer 61 on the surface of the semiconductor substrate 1 can be removed, and part of the polysilicon layer 25 and the isolation layer 24 located in the insulating trench 21 are retained, and the isolation layer The surfaces of the polysilicon layer 24 and the polysilicon layer 25 are flush with the surface of the semiconductor substrate 1 .
  • the polysilicon layer 25 , the isolation layer 24 and the first mask layer 61 located on the surface of the semiconductor substrate 1 are removed by an etching process, and the remaining etching pairs on the surface of the semiconductor substrate 1 are removed by wet cleaning product. Then, rapid heat treatment can be performed to make the contact part of the isolation layer 24 and the semiconductor substrate 1 react to form the contact layer 26.
  • the material of the contact layer 26 formed after the reaction can be a silicon-cobalt compound CoSix or a silicon-titanium compound TiSix , thereby forming The ohmic contact can thereby reduce the contact resistance between the bit line conductive layer 23 and the polysilicon layer 25 on the one hand.
  • the contact layer 26 formed on the sidewall can also prevent the ion implantation element P from diffusing into the functional region 12 .
  • FIG. 9-13 are cross-sectional views of the structures formed by each step of the process flow of forming the word line structure 3 and the active region on the surface of the semiconductor substrate 1.
  • the steps of forming the word line structure 3 include: as shown in FIG. 9 As shown, a stacked structure is formed on the surface of the semiconductor substrate 1, and the stacked structure includes a passivation layer 31, a word line conductive layer 32 and a top word line barrier layer 33 that are stacked in sequence; as shown in FIG. 11, the patterned stacked structure to form the primary word line structure pattern 34; as shown in FIG.
  • a side word line barrier layer 35 is formed on the sidewall of the primary word line structure pattern 34, and the side word line barrier layer 35 and the top word line barrier layer 33 together form the word line
  • the line barrier layer 36 , the passivation layer 31 , the word line conductive layer 32 and the word line barrier layer 36 together constitute the word line structure 3 .
  • a stacked structure is formed on the surface of the semiconductor substrate 1.
  • the stacked structure sequentially includes a passivation layer 31, a word line conductive layer 32 and a top word line barrier layer. 33.
  • a mask structure is formed on the surface of the top word line barrier layer 33.
  • the stacked structure is patterned through the mask structure to form a preliminary word line structure pattern.
  • the mask structure may include a second mask layer 62 formed on the surface of the top word line barrier layer 33 and a word line pattern formed on the surface of the second mask layer 62
  • a word line pattern can be formed on the third mask layer 63 by using the pitch multiplication technology after thin film deposition.
  • the second mask layer 62 may be formed as an organic carbon layer
  • the third mask layer 63 may be formed as a hard mask layer
  • the material of the third mask layer 63 may be a silicon oxide material.
  • a side word line barrier layer 35 is deposited on the sidewall surface of the primary word line structure pattern 34 and the surface of the semiconductor substrate 1.
  • the side word line barrier layer 35 is made of the same material as the top word line barrier layer 33.
  • the material of the side word line barrier layer 35 and the top word line barrier layer 33 can be titanium nitride material, and the deposition process of the side word line barrier layer 35 can be made by atomic layer deposition.
  • an etching process such as dry etching is used to remove part of the side word line barrier layer 35 on the surface of the semiconductor substrate 1 , leaving the side word line barrier layer 35 located on the sidewall of the primary word line structure pattern 34 .
  • the thickness of the word line barrier layer 36 can be 2nm-7nm
  • the word line barrier layer 36 wraps the passivation layer 31 and the word line conductive layer 32, so The passivation layer 31 , the word line conductive layer 32 and the word line barrier layer 36 together constitute the word line structure 3 .
  • a primary dielectric layer 41 is formed on the surface of the semiconductor substrate 1 and the surface of the word line structure 3, and a primary channel layer 42 is formed on the surface of the primary dielectric layer 41, and a deposition process (for example, atomic layer deposition) can be used.
  • a primary dielectric layer 41 is formed, and then a primary channel layer 42 is formed by a low pressure vapor deposition method (eg, physical vapor deposition or chemical vapor deposition), wherein the material of the primary dielectric layer 41 may be a high-node material such as hafnium dioxide (HfO 2 ), the material of the primary channel layer 42 may be silicon material, and the thickness of the primary channel layer 42 may be 2 nm ⁇ 10 nm.
  • HfO 2 hafnium dioxide
  • part of the primary dielectric layer 41 and the primary channel layer 42 located on the surface of the semiconductor substrate 1 are removed, and the primary dielectric layer located on the top and sidewalls of the word line structure 3 remains.
  • a filling layer 66 is formed on the surface of the primary channel layer 42 , the filling layer 66 fills the primary channel layer 42 and the surface of the filling layer 66 is higher than the surface of the primary channel layer 42 , and is deposited on the surface of the filling layer 66 to form
  • the fourth mask layer 64 is coated with photoresist on the surface of the fourth mask layer 64 to form a photoresist layer 65 .
  • the filling layer 66 can be formed by backfilling by thin film deposition, the filling layer 66 can be an organic carbon layer, and the fourth mask layer 64 can form a silicon oxynitride hard mask layer, and the filling layer 66 can be patterned by applying glue, exposing, and developing. , the primary channel layer 42 and the primary dielectric layer 41 .
  • part of the primary channel layer 42 and the primary dielectric layer 41 on the surface of the semiconductor substrate 1 are removed, and the primary channel layer 42 and the primary dielectric layer 41 located on the sidewall of the word line structure 3 are retained to form a word line
  • the dielectric layer 43 and the channel layer 44 of the structure 3 the channel layer 44 is formed on the surface of the dielectric layer 43, the sidewall of the dielectric layer 43 formed on the bottom part of the surface of the semiconductor substrate 1 and the channel layer 44.
  • the sidewalls are flush.
  • a dry etching process can be used to etch, and the surface of the semiconductor substrate 1 is formed as a stop layer.
  • the surface of the channel layer 44 after etching has a portion of the partially filled layer 66 remaining.
  • hydrogen gas, oxygen gas or a mixed gas of hydrogen gas and oxygen gas can be used to perform a plasma bath to remove the residual filling layer 66 .
  • ion implantation is performed on the channel layer 44 to form the gate channel 45.
  • the implanted atomic species can be selected according to the requirements of different devices.
  • N element implantation can be performed, such as phosphorus atom or arsenic atom input.
  • P element boron atoms, etc. can be performed, specifically, low energy (eg, 1k-15k) and low dose (eg, 0.5-10E13) implantation can be used to perform ion implantation.
  • the active region is formed on the surface of the semiconductor substrate 1 and located above the functional region 12 .
  • the step of forming the active region includes: forming on the surface of the semiconductor substrate 1 and located above the functional region 12 .
  • the source-drain structure 46 is used as an active region and includes the following steps:
  • a source-drain layer 47 covering the surface of the gate channel is filled between the surface of the semiconductor substrate 1 and the gate channel 45 ; molecular epitaxy can be used to form the surface of the semiconductor substrate 1 and the gate channel.
  • the source and drain layers 47 are epitaxially formed on the surface of the channel 45. Further, the source and drain layers 47 can be epitaxially produced by SiGe layers or SiC layers according to the requirements of different MOS (metal-oxide-semiconductor) devices.
  • the source-drain layer 47 is doped in-situ at the same time as the source-drain layer 47 is formed, or ion implantation is performed on the source-drain layer 47 after the source-drain layer 47 is formed.
  • the source-drain layer 47 located above the gate channel 45 and part of the source-drain layer 47 located on the sidewall of the word line channel are removed to form a source-drain structure 46 , and the word line channel includes the dielectric layer 43 and Gate channel 45 .
  • part of the source/drain layer 47 may be selectively removed by wet etching or dry etching, and part of the source/drain layer 47 may be retained to form a drain source region.
  • the drain source region may include a drain region and a source region, wherein the source region and the buried
  • the buried bit line structures 2 are connected, formed between adjacent gate channels 45 and located above the buried bit line structures 2 , and the drain region is formed on the other side of the word line structures 3 .
  • the thickness of the source-drain layer 47 that is finally retained, that is, the source-drain structure 46 may be 30-100 nm.
  • the source-drain structure 46 may be partially located above the trench isolation structure 11 , and a source-drain isolation structure (not shown) is provided between adjacent source-drain structures 46 to isolate each memory cell device
  • the material of the source-drain isolation structure (not shown) can be one or more of spin-on insulating dielectric (SOD), ethyl orthosilicate (TEOS), silicon nitride (SiN) and silicon oxynitride (SiON). kind.
  • an insulating layer 5 covering the source and drain regions and the surface of the gate channel 45 is deposited on the surface of the semiconductor substrate 1.
  • the insulating layer 5 not only the structure of the semiconductor device 100 can be protected, but also the structure of the semiconductor device 100 can be protected by forming the insulating layer 5 on the surface of the gate channel.
  • the insulating layer 5 is formed above the track 45 , which can also greatly reduce the leakage in the direction of the substrate and enhance the reliability of the semiconductor device 100 .
  • the material of the insulating layer 5 may be one or more of spin-on insulating dielectric (SOD), tetraethyl orthosilicate (TEOS), silicon nitride (SiN) and silicon oxynitride (SiON).
  • SOD spin-on insulating dielectric
  • TEOS tetraethyl orthosilicate
  • SiN silicon nitride
  • SiON silicon oxynitride
  • the buried bit line structure 2 is formed in the semiconductor substrate 1 , the word line structure 3 and the source-drain structure 46 are formed above the semiconductor substrate 1 , and the subsequent The capacitors are formed on both sides of the source-drain structure 46, so that the distance between the buried bit line structure 2 and the capacitor device formed subsequently is increased, and the leakage current between the buried bit line structure 2 and the capacitor is reduced, The parasitic capacitance effect between the buried bit line structure 2 and the capacitor is also reduced, and the performance and reliability of the semiconductor device 100 are improved.
  • the present disclosure also proposes a semiconductor device 100 .
  • the semiconductor device 100 can be formed by using the manufacturing method of the semiconductor device in the above-mentioned embodiments.
  • a semiconductor device 100 includes a semiconductor substrate 1 provided with trench isolation structures 11 and functional regions 12 between the trench isolation structures 11 ; a buried bit line structure 2 , which is embedded The type bit line structure 2 is disposed in the semiconductor substrate 1 ; the word line structure 3 and the source-drain structure 46 are disposed on the surface of the semiconductor substrate 1 and above the functional region 12 .
  • the semiconductor device 100 further includes a channel layer 44 and a dielectric layer 43, the dielectric layer 43 is disposed to cover at least the surface of the word line structure 3, and the channel layer 44 is disposed to cover the dielectric layer 43 surface.
  • the source-drain structure 46 is disposed over the functional region 12 and on the sides of the channel layer 44 and the dielectric layer 43 .
  • the height of the source-drain structure 46 is 30 nm ⁇ 100 nm.
  • the semiconductor device prepared according to the preparation method of the semiconductor device of the present disclosure can reduce the leakage current and the parasitic capacitance effect between the bit line structure and the capacitor, and has good performance and high reliability.
  • the present disclosure provides a semiconductor device and a method for fabricating the same.
  • the method for fabricating the semiconductor device includes: providing a semiconductor substrate formed with a trench isolation structure and a function between the trench isolation structures regions; forming buried bit line structures; forming word line structures and active regions.
  • the semiconductor device prepared according to the preparation method of the semiconductor device can reduce the leakage current and the parasitic capacitance effect between the bit line structure and the capacitor, and has good performance and high reliability.

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Abstract

本公开提供了一种半导体器件及其制备方法，所述半导体器件的制备方法包括：提供半导体衬底，所述半导体衬底形成有沟槽隔离结构和位于所述沟槽隔离结构之间的功能区；形成埋入式位线结构，所述埋入式位线结构形成在所述半导体衬底内；形成字线结构和有源区，所述字线结构和所述有源区形成在所述半导体衬底表面且位于所述功能区的上方。

Description

半导体器件及其制备方法
本公开要求在2020年10月15日提交中国专利局、申请号为202011100761.6、发明名称为“半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体器件及其制备方法。
背景技术
现有动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，包括用于存储数据的存储单元阵列，以及位于存储单元阵列外围的外围电路组成.存储单元阵列中每个存储单元通常包括晶体管和存储节点，并通过字线和位线将多个存储单元连接成存储单元阵列。所述晶体管栅极连接的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在存储节点中的数据信息，或者将数据信息写入到电容器中。
随着晶体管密度不断增加，字线、位线以及不同器件间的隔离结构尺寸都会不断缩小。一方面位线与位线之间，位线与存储节点接触(storage node contact)的寄生电容问题也变得越来越严重，会导致RC delay问题越来越严重，导致数据信息传输的延迟，严重时甚至造成感应放大器工作失效；另一方面，字线晶体管亚阈值漏电流问题变得日益严重，影响器件的性能以及可靠性。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体器件及其制备方法，所述半导体器件的制备方法制备的半导体器件能够减小漏电流，并减小位线结构和电容器之间的寄生电容效应，性能好且可靠性高。
本公开中提供的一种半导体器件的制备方法，包括：提供半导体衬底，所述半导体衬底形成有沟槽隔离结构和位于所述沟槽隔离结构之间的功能区；形成埋入式位线结构，所述埋入式位线结构形成在所述半导体衬底内；形成字线结构和有源区，所述字线结构和所述有源区形成在所述半导体衬底表面且位于所述功能区的上方。
根据本公开的一些实施例，在形成字线结构的步骤中包括：于所述半导体衬底表面形成叠层结构，所述叠层结构包括依次层叠设置的钝化层、字线导电层和顶部字线阻挡层；图形化所述叠层结构以形成初级字线结构图案；于所述初级字线结构图案侧壁形成侧部字线阻挡层，所述侧部字线阻挡层与所述顶部字线阻挡层共同构成字线阻挡层，所述钝化层、所述字线导电层和所述字线阻挡层共同构成所述字线结构。
根据本公开的一些实施例，所述半导体器件的制备方法还包括：于所述字线结构的表面形成介电层；于所述介电层表面形成沟道层；其中，所述介电层覆盖所述字线结构，所述沟道层覆盖所述介电层。
根据本公开的一些实施例，在于所述字线结构的表面形成介电层；于所述介电层表面形成沟道层的步骤中包括：于所述半导体衬底表面和所述字线结构表面形成初级介电层；于所述初级介电层表面形成初级沟道层；去除位于所述半导体衬底表面的部分初级介电层和初级沟道层，保留位于所述字线结构顶部和侧壁的所述初级介电层和所述初级沟道层以形成所述介电层和所述沟道层。
根据本公开的一些实施例，所述半导体器件的制备方法还包括：向所述沟道层进行离子植入以形成栅极沟道。
根据本公开的一些实施例，在形成有源区的步骤中包括：于所述半导体衬底表面形成位于所述功能区上方的源漏结构作为所述有源区。
根据本公开的一些实施例，在于所述半导体衬底表面形成位于所述功能区上方的源漏结构中包括以下步骤：于所述半导体衬底表面和所述栅极沟道之间填充形成覆盖所述栅极沟道表面的源漏层；去除位于所述栅极沟道上方的源漏层和部分位于字线沟道侧壁的源漏层以形成源漏结构，所述字线沟道包括介电层和栅极沟道。
根据本公开的一些实施例，在于所述半导体衬底表面和所述栅极沟道之间 填充形成覆盖所述栅极沟道表面的源漏层的步骤中：采用分子外延工艺形成所述源漏层；在形成所述源漏层的同时对所述源漏层进行原位掺杂，或在形成所述源漏层之后对所述源漏层进行离子注入。
根据本公开的一些实施例，所述源漏结构的高度为30nm～100nm。
根据本公开的一些实施例，在形成埋入式位线结构的步骤中包括：于所述半导体衬底内形成绝缘沟槽；于所述绝缘沟槽内形成覆盖所述绝缘沟槽底壁和部分侧壁的位线阻挡层；于所述位线阻挡层表面形成位线导电层且填充部分所述绝缘沟槽。
根据本公开的一些实施例，所述形成埋入式位线结构的步骤还包括：于所述位线阻挡层表面和所述位线导电层表面以及所述绝缘沟槽侧壁形成隔离层；于所述隔离层表面形成多晶硅层且填充所述绝缘沟槽。
根据本公开的一些实施例，在于所述隔离层表面形成多晶硅层且填充所述沟槽后，执行以下步骤：对所述隔离层进行快速热处理。
根据本公开的一些实施例，所述隔离层材料为钴或钛。
本公开还提出了一种半导体器件，包括：半导体衬底，所述半导体衬底设置有沟槽隔离结构和位于所述沟槽隔离结构之间的功能区；埋入式位线结构，所述埋入式位线结构设置在所述半导体衬底内；字线结构和源漏结构，所述字线结构和所述源漏结构设置在所述半导体衬底表面且位于所述功能区上方。
根据本公开的一些实施例，所述半导体器件还包括沟道层和介电层，所述介电层至少覆盖所述字线结构的表面，所述沟道层覆盖所述介电层的表面。
根据本公开的一些实施例，所述源漏结构设置在所述功能区上方且设置在所述沟道层和所述介电层的侧部。
根据本公开的一些实施例，所述源漏结构的高度为30nm～100nm。
由此根据本公开实施例的半导体器件的制备方法，通过在半导体衬底内形成埋入式位线结构，在半导体衬底的上方形成字线结构和源漏结构，后续电容器形成在源漏结构的两侧，从而使得埋入式位线结构与后续形成的电容器件之间的距离增大，减小位线结构与电容器之间的漏电流，也减小了位线结构与电容器之间的寄生电容效应，提高和半导体器件的性能和可靠性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开实施例的半导体器件的制备方法的流程图；
图2-图20为本公开实施例的半导体器件的制备方法中各步骤所形成的结构的剖视图。
附图标记：
100：半导体器件；
1：半导体衬底，11：沟槽隔离结构，12：功能区；
2：埋入式位线结构，21：绝缘沟槽，22：位线阻挡层，23：位线导电层，24：隔离层，25：多晶硅层；26：接触层；
3：字线结构，31：钝化层，32：字线导电层，33：顶部字线阻挡层，34：初级字线结构图案，35：侧部字线阻挡层，36：字线阻挡层；
41：初级介电层，42：初级沟道层，43：介电层，44：沟道层，45：栅极沟道，46：源漏结构，47：源漏层；
5：绝缘层；
61：第一掩膜层，62：第二掩膜层，63：第三掩膜层，64：第四掩膜层，65：光刻胶层；66：填充层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然， 所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
以下结合附图和具体实施方式对本公开提出的一种半导体器件及其制备方法作进一步详细说明。
下面结合附图描述根据本公开实施例的半导体器件100的制备方法。
如图1所示，根据本公开实施例的半导体器件100的制备方法可以包括：提供半导体衬底1，所述半导体衬底1形成有沟槽隔离结构11和位于所述沟槽隔离结构11之间的功能区12；形成埋入式位线结构2，所述埋入式位线结构2形成在所述半导体衬底1内；形成字线结构3和有源区，所述字线结构3和所述有源区形成在所述半导体衬底1表面且位于所述功能区12的上方。
图2-图20为根据本公开实施例的半导体器件100的制备方法的各步骤所形成的结构的剖视图，结合图2-图20所示的各步骤所形成的结构的剖视图描述本公开实施例的制备方法的工艺流程。
如图2所示，提供半导体衬底1，半导体衬底1材料可以为硅(Si)、锗(Ge)、硅锗(GeSi)、或碳化硅(SiC)；也可以是绝缘体上硅(SOI)、绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。半导体衬底1形成有沟槽隔离结构11和位于沟槽隔离结构11之间的功能区12，沟槽隔离结构11于半导体衬底1内隔离出多个功能区12，沟槽隔离结构11可以包括隔离沟槽和填充在隔离沟槽内的绝缘材料，绝缘材料可以为氧化硅材料等。
如图3-图8所示，形成埋入式位线结构2，埋入式位线结构2形成在半导体衬底1内。形成埋入式位线结构2的步骤包括：如图3所示，于半导体衬底1内形成绝缘沟槽21；如图4-图6所示，于绝缘沟槽21内形成覆盖绝缘沟槽21底壁和部分侧壁的位线阻挡层22；于位线阻挡层22表面形成位线导电层23且填充部分绝缘沟槽21。
参见图3，在半导体衬底1表面沉积形成有第一掩膜层61，以第一掩膜层61为掩膜图形化半导体衬底1，于半导体衬底1内形成绝缘沟槽21，绝缘沟槽 21形成在沟槽隔离结构11之间的功能区12内，埋入式位线结构2形成在绝缘沟槽21内，其中绝缘沟槽21的深度可以为60nm～150nm，例如可以为80nm、100nm、120nm等，绝缘沟槽21的宽度可以为10nm～60nm，例如可以为20nm、30nm、40nm或50nm等。
如图4所示，在第一掩膜层61表面和绝缘沟槽21的内壁面形成位线阻挡层22，其中，位线阻挡层22可采用原子层沉积法形成，位线阻挡层22的材料可以为TiN(氮化钛)材料，位线阻挡层22的厚度可以为3nm～8nm，例如可以为4nm、5nm、6nm或7nm等。
如图5所示，于位线阻挡层22的表面形成位线导电层23，此时位线阻挡层22和位线导电层23填满绝缘沟槽21，位于绝缘沟槽21内的位线阻挡层22包裹位于位线导电层23，位线导电层23的材料可以为钨材料，可采用化学气相沉积法或物理气相沉积法形成位线导电层23，沉积后可采用化学机械研磨设备对位线导电层23的表面进行处理，使得位线导电层23表面平坦化。
如图6所示，去除位于第一掩膜层61上方的部分位线阻挡层22和部分位线导电层23，并去除部分位于绝缘沟槽21内的部分位线导电层23和部分位线阻挡层22，保留位于绝缘沟槽21下部的部分位线阻挡层22和位线导电层23，即可对绝缘沟槽21内的位线阻挡层22和位线导电层23进行回刻，回刻的深度可以为30nm～120nm。回刻位线阻挡层22和位线导电层23的工艺包括：可采用干法蚀刻回刻位线阻挡层22和位线导电层23，并搭配湿法蚀刻去除干法蚀刻侧壁残余的位线阻挡层22。其中剩余位线阻挡层22的表面与位线导电层23的表面平齐且包裹位线导电层23，以避免位线导电层23发生离子迁移，起到阻挡隔离的效果。
如图7所示，在第一掩膜层61表面和绝缘沟槽21的内壁面以及位线阻挡层22和位线导电层23的表面沉积形成隔离层24，在隔离层24的表面形成多晶硅层25且填满绝缘沟槽21，其中隔离层24材料可以为钴材料或者钛材料，可通过物理气相沉积法沉积形成，然后通过化学气相沉积法沉积形成多晶硅层25，通过化学机械研磨工艺平坦化多晶硅层25的表面。
如图8所示，可对多晶硅层25进行元素掺杂，例如可对多晶硅层25进行P元素掺杂，从而可增加多晶硅层25的导电性，提高埋入式位线结构2的电性连接效果。如图8所示，可去除位于半导体衬底1表面的多晶硅层25、隔离 层24和第一掩膜层61，保留位于绝缘沟槽21内的部分多晶硅层25和隔离层24，且隔离层24和多晶硅层25的表面与半导体衬底1的表面相平齐。
在本公开的一些实施例中，通过蚀刻工艺去除位于半导体衬底1表面的多晶硅层25、隔离层24和第一掩膜层61，并采用湿法清洗去除半导体衬底1表面残留的蚀刻副产物。然后可进行快速热处理，使得隔离层24与半导体衬底1接触的部位发生反应，形成接触层26，反应后形成的接触层26材料可以为硅钴化合物CoSi x或硅钛化合物TiSi x，从而形成欧姆接触，由此一方面能够降低位线导电层23与多晶硅层25之间的接触电阻。另一方面侧壁形成的接触层26硅钴化合物CoSi x或硅钛化合物TiSi x也能够防止离子植入元素P向功能区12扩散。
如图9-图13所示为在半导体衬底1表面形成字线结构3和有源区的工艺流程的各步骤所形成的结构的剖视图，形成字线结构3的步骤包括：如图9所示，于半导体衬底1表面形成叠层结构，叠层结构包括依次层叠设置的钝化层31、字线导电层32和顶部字线阻挡层33；如图11所示，图形化叠层结构以形成初级字线结构图案34；如图12所示，于初级字线结构图案34侧壁形成侧部字线阻挡层35，侧部字线阻挡层35与顶部字线阻挡层33共同构成字线阻挡层36，钝化层31、字线导电层32和字线阻挡层36共同构成字线结构3。
参见图9，在半导体衬底1表面形成层叠设置叠层结构，在从半导体衬底1表面向上的方向上，叠层结构依次包括钝化层31、字线导电层32和顶部字线阻挡层33，在顶部字线阻挡层33的表面形成掩膜结构，如图10所示，通过掩膜结构图形化叠层结构以形成初步字线结构图案。
在本公开的一些实施例中，如图10所示，掩膜结构可以包括形成在顶部字线阻挡层33表面的第二掩膜层62和形成在第二掩膜层62表面形成字线图形的第三掩膜层63，具体可采用薄膜沉积后通过间距倍增技术，在第三掩膜层63上形成字线图形。第二掩膜层62可以形成为有机碳层，第三掩膜层63可以形成硬掩模层，第三掩膜层63的材料可以为氧化硅材料。
如图11所示，在初级字线结构图案34的侧壁表面和半导体衬底1表面沉积形成侧部字线阻挡层35，侧部字线阻挡层35与顶部字线阻挡层33材料相同，例如侧部字线阻挡层35和顶部字线阻挡层33的材料均可以为氮化钛材料，对于侧部字线阻挡层35的沉积工艺，可采用原子层沉积法。
如图12所示，采用刻蚀工艺例如干法刻蚀，去除半导体衬底1表面的部分侧部字线阻挡层35，保留位于初级字线结构图案34侧壁的侧部字线阻挡层35，以与顶部字线阻挡层33共同构成字线阻挡层36，字线阻挡层36的厚度可以为2nm～7nm，所述字线阻挡层36包裹钝化层31和字线导电层32，所述钝化层31、字线导电层32与字线阻挡层36共同构成字线结构3。
如图13所示，在半导体衬底1表面和字线结构3表面形成初级介电层41，在初级介电层41表面形成初级沟道层42，可采用沉积工艺(例如，原子层沉积)形成初级介电层41，然后通过低压气相沉积法(例如，物理气相沉积法或化学气相沉积法)形成初级沟道层42，其中初级介电层41的材料可以为高节点材料例如二氧化铪(HfO 2)，初级沟道层42的材料可为硅材料，初级沟道层42的厚度可以为2nm～10nm。
如图14-图16所示，去除位于所述半导体衬底1表面的部分初级介电层41和初级沟道层42，保留位于所述字线结构3顶部和侧壁的所述初级介电层41和所述初级沟道层42以形成介电层43和沟道层44，介电层43覆盖字线结构3，沟道层44覆盖介电层43。
参见图14，在初级沟道层42的表面形成填充层66，填充层66填满初级沟道层42且填充层66的表面高于初级沟道层42的表面，在填充层66表面沉积形成第四掩膜层64，在第四掩膜层64表面涂布光刻胶以形成光刻胶层65。可采用薄膜沉积的方法回填形成填充层66，填充层66可以为有机碳层，第四掩膜层64可以形成氮氧化硅硬掩模层，通过涂胶、曝光、显影以图形化填充层66、初级沟道层42和初级介电层41。
如图15所示，去除半导体衬底1表面的部分初级沟道层42和初级介电层41，保留位于字线结构3侧壁的初级沟道层42和初级介电层41以形成字线结构3的介电层43和沟道层44，沟道层44形成在介电层43的表面，介电层43的形成在半导体衬底1表面的底部部分的侧壁与沟道层44的侧壁相平齐，在此步骤中可采用干法刻蚀工艺进行刻蚀，半导体衬底1表面形成为停止层。刻蚀后沟道层44的表面具有部分残余的部分填充层66。如图16所示，去除沟道层44表面的残余填充层66，例如可采用氢气、氧气或者氢气和氧气的混合气体进行等离子浴来去除残留的填充层66。
如图17所示，向沟道层44进行离子植入以形成栅极沟道45，具体可根据 不同器件需求选择注入的原子种类，例如可进行N元素注入，如磷原子或者砷原子输入，或者可以进行P元素硼原子等，具体可采用低能量(例如1k-15k)低剂量(例如0.5～10E13)注入，注入进行离子注入。
如图18-图20所示，有源区形成在半导体衬底1表面且位于在功能区12的上方，形成有源区的步骤中包括：于半导体衬底1表面形成位于功能区12上方的源漏结构46作为有源区，包括以下步骤：
如图18所示，于半导体衬底1表面和栅极沟道45之间填充形成覆盖栅极沟道表面的源漏层47；可采用分子外延技术在半导体衬底1的表面和栅极沟道45的表面外延形成源漏层47，进一步地，源漏层47可根据不同MOS(金属-氧化物-半导体)器件需求可外延生产SiGe层或SiC层。在形成源漏层47的同时对源漏层47进行原位掺杂，或在形成源漏层47之后对源漏层47进行离子注入。
如图19所示，去除位于栅极沟道45上方的源漏层47和部分位于字线沟道侧壁的源漏层47以形成源漏结构46，字线沟道包括介电层43和栅极沟道45。在此步骤中可通过湿法蚀刻或干法蚀刻选择性去除部分源漏层47，保留部分源漏层47以形成漏源区，漏源区可以包括漏区和源区，其中源区与埋入式位线结构2相连，形成在相邻栅极沟道45之间且位于埋入式位线结构2上方，漏区形成在字线结构3的另一侧。最终保留的源漏层47即源漏结构46的厚度可以为30～100nm。
在另一实施例中，源漏结构46可以部分位于沟槽隔离结构11上方，且相邻源漏结构46之间具有源漏隔离结构(未图示)起到各存储单元器件之间的隔离作用，源漏隔离结构(未图示)材料可以为旋涂绝缘介质(SOD)、正硅酸乙酯(TEOS)、氮化硅(SiN)和氮氧化硅(SiON)中的一种或者多种。
如图20所示，在半导体衬底1表面沉积形成覆盖源漏区和栅极沟道45表面的绝缘层5，通过形成绝缘层5不仅能够保护半导体器件100的结构，而且通过在栅极沟道45的上方形成绝缘层5，也能够大大减小衬底方向的漏电，增强半导体器件100的可靠性。绝缘层5材料可以为旋涂绝缘介质(SOD)、正硅酸乙酯(TEOS)、氮化硅(SiN)和氮氧化硅(SiON)中的一种或者多种。
由此根据本公开实施例的半导体器件100的制备方法，通过在半导体衬底 1内形成埋入式位线结构2，在半导体衬底1的上方形成字线结构3和源漏结构46，后续电容器形成在源漏结构46的两侧，从而使得埋入式位线结构2与后续形成的电容器件之间的距离增大，减小埋入式位线结构2与电容器之间的漏电流，也减小了埋入式位线结构2与电容器之间的寄生电容效应，提高和半导体器件100的性能和可靠性。
本公开还提出了一种半导体器件100。所述半导体器件100可采用上述实施例的半导体器件的制备方法形成。
根据本公开实施例的半导体器件100包括半导体衬底1，半导体衬底1设置有沟槽隔离结构11和位于沟槽隔离结构11之间的功能区12；埋入式位线结构2，埋入式位线结构2设置在半导体衬底1内；字线结构3和源漏结构46，字线结构3和源漏结构46设置在半导体衬底1表面且位于功能区12上方。
根据本公开的一些实施例，所述半导体器件100还包括沟道层44和介电层43，介电层43设置为至少覆盖字线结构3的表面，沟道层44设置为覆盖介电层43的表面。
根据本公开的一些实施例，源漏结构46设置在功能区12上方且位于沟道层44和介电层43的侧部。
源漏结构46的高度为30nm～100nm。
根据本公开的半导体器件的制备方法所制备的半导体器件，能够减小漏电流，并减小位线结构和电容器之间的寄生电容效应，性能好且可靠性高。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开提供了一种半导体器件及其制备方法，所述半导体器件的制备方法包括：提供半导体衬底，所述半导体衬底形成有沟槽隔离结构和位于所述沟槽隔离结构之间的功能区；形成埋入式位线结构；形成字线结构和有源区。根据半导体器件的制备方法制备的半导体器件能够减小漏电流，并减小位线结构和电容器之间的寄生电容效应，性能好且可靠性高。

Claims (17)

  1. 一种半导体器件的制备方法，其中，所述半导体器件的制备方法包括：
    提供半导体衬底(1)，所述半导体衬底(1)形成有沟槽隔离结构(11)和位于所述沟槽隔离结构(11)之间的功能区(12)；
    形成埋入式位线结构(2)，所述埋入式位线结构(2)形成在所述半导体衬底(1)内；
    形成字线结构(3)和有源区，所述字线结构(3)和所述有源区形成在所述半导体衬底(1)表面且位于所述功能区(12)的上方。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，在形成字线结构(3)的步骤中包括：
    于所述半导体衬底(1)表面形成叠层结构，所述叠层结构包括依次层叠设置的钝化层(31)、字线导电层(32)和顶部字线阻挡层(33)；
    图形化所述叠层结构以形成初级字线结构图案(34)；
    于所述初级字线结构图案(34)侧壁形成侧部字线阻挡层(35)，所述侧部字线阻挡层(35)与所述顶部字线阻挡层(33)共同构成字线阻挡层(36)，所述钝化层(31)、所述字线导电层(32)和所述字线阻挡层(36)共同构成所述字线结构(3)。
  3. 根据权利要求2所述的半导体器件的制备方法，还包括：
    于所述字线结构(3)的表面形成介电层(43)；
    于所述介电层(43)表面形成沟道层(44)；
    其中，所述介电层(43)覆盖所述字线结构(3)，所述沟道层(44)覆盖所述介电层(43)。
  4. 根据权利要求3所述的半导体器件的制备方法，其中，在于所述字线结构(3)的表面形成介电层(43)；于所述介电层(43)表面形成沟道层(44)的步骤中包括：
    于所述半导体衬底(1)表面和所述字线结构(3)表面形成初级介电层(41)；
    于所述初级介电层(41)表面形成初级沟道层(42)；
    去除位于所述半导体衬底(1)表面的部分初级介电层(41)和初级沟道层(42)，保留位于所述字线结构(3)顶部和侧壁的所述初级介电层(41)和所述初级沟道层(42)以形成所述介电层(43)和所述沟道层(44)。
  5. 根据权利要求3所述的半导体器件的制备方法，还包括：向所述沟道层(44)进行离子植入以形成栅极沟道(45)。
  6. 根据权利要求5所述的半导体器件的制备方法，其中，在形成有源区的步骤中包括：于所述半导体衬底(1)表面形成位于所述功能区(12)上方的源漏结构(46)作为所述有源区。
  7. 根据权利要求6所述的半导体器件的制备方法，其中，在于所述半导体衬底(1)表面形成位于所述功能区(12)上方的源漏结构(46)中包括以下步骤：
    于所述半导体衬底(1)表面和所述栅极沟道(45)之间填充形成覆盖所述栅极沟道(45)表面的源漏层(47)；
    去除位于所述栅极沟道(45)上方的源漏层(47)和部分位于字线沟道侧壁的源漏层(47)以形成源漏结构(46)，所述字线沟道包括介电层(43)和栅极沟道(45)。
  8. 根据权利要求7所述的半导体器件的制备方法，其中，在于所述半导体衬底(1)表面和所述栅极沟道(45)之间填充形成覆盖所述栅极沟道(45)表面的源漏层(47)的步骤中：
    采用分子外延工艺形成所述源漏层(47)；
    在形成所述源漏层(47)的同时对所述源漏层(47)进行原位掺杂，或在形成所述源漏层(47)之后对所述源漏层(47)进行离子注入。
  9. 根据权利要求6所述的半导体器件的制备方法，其中，所述源漏结构(46)的高度为30nm～100nm。
  10. 根据权利要求1所述的半导体器件的制备方法，其中，在形成埋入式位线结构(2)的步骤中包括：
    于所述半导体衬底(1)内形成绝缘沟槽(21)；
    于所述绝缘沟槽(21)内形成覆盖所述绝缘沟槽(21)底壁和部分侧壁的 位线阻挡层(22)；
    于所述位线阻挡层(22)表面形成位线导电层(23)且填充部分所述绝缘沟槽(21)。
  11. 根据权利要求10所述的半导体器件的制备方法，还包括：
    于所述位线阻挡层(22)表面和所述位线导电层(23)表面以及所述绝缘沟槽(21)侧壁形成隔离层(24)；
    于所述隔离层(24)表面形成多晶硅层(25)且填充所述绝缘沟槽(21)。
  12. 根据权利要求11所述的半导体器件的制备方法，其中，在于所述隔离层(24)表面形成多晶硅层(25)且填充所述沟槽后，执行以下步骤：对所述隔离层(24)进行快速热处理。
  13. 根据权利要求11所述的半导体器件的制备方法，其中，所述隔离层(24)材料为钴或钛。
  14. 一种半导体器件，其中，包括：
    半导体衬底(1)，所述半导体衬底(1)设置有沟槽隔离结构(11)和位于所述沟槽隔离结构(11)之间的功能区(12)；
    埋入式位线结构(2)，所述埋入式位线结构(2)设置在所述半导体衬底(1)内；
    字线结构(3)和源漏结构(46)，所述字线结构(3)和所述源漏结构(46)设置在所述半导体衬底(1)表面且位于所述功能区(12)上方。
  15. 根据权利要求14所述的半导体器件，还包括沟道层(44)和介电层(43)，所述介电层(43)至少覆盖所述字线结构(3)的表面，所述沟道层(44)覆盖所述介电层(43)的表面。
  16. 根据权利要求15所述的半导体器件，其中，所述源漏结构(46)设置在所述功能区(12)上方且设置在所述沟道层(44)和所述介电层(43)的侧部。
  17. 根据权利要求14所述的半导体器件，所述源漏结构(46)的高度为30nm～100nm。
PCT/CN2021/100138 2020-10-15 2021-06-15 半导体器件及其制备方法 Ceased WO2022077940A1 (zh)

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