WO2022071430A1 - 配線基板の製造方法、半導体装置の製造方法、及び樹脂シート - Google Patents
配線基板の製造方法、半導体装置の製造方法、及び樹脂シート Download PDFInfo
- Publication number
- WO2022071430A1 WO2022071430A1 PCT/JP2021/035957 JP2021035957W WO2022071430A1 WO 2022071430 A1 WO2022071430 A1 WO 2022071430A1 JP 2021035957 W JP2021035957 W JP 2021035957W WO 2022071430 A1 WO2022071430 A1 WO 2022071430A1
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- Prior art keywords
- layer
- resin
- wiring
- resin sheet
- manufacturing
- Prior art date
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- 229920005989 resin Polymers 0.000 title claims abstract description 263
- 239000011347 resin Substances 0.000 title claims abstract description 263
- 238000000034 method Methods 0.000 title claims abstract description 100
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 87
- 239000004065 semiconductor Substances 0.000 title claims description 61
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 77
- 229910052802 copper Inorganic materials 0.000 claims abstract description 77
- 239000010949 copper Substances 0.000 claims abstract description 77
- 239000011521 glass Substances 0.000 claims abstract description 33
- 239000004744 fabric Substances 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 427
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 229910052763 palladium Inorganic materials 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 29
- -1 polyethylene Polymers 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 21
- 238000007772 electroless plating Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 239000000835 fiber Substances 0.000 claims description 12
- 239000003054 catalyst Substances 0.000 claims description 8
- 229920000049 Carbon (fiber) Polymers 0.000 claims description 7
- 239000004917 carbon fiber Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 7
- 239000012784 inorganic fiber Substances 0.000 claims description 6
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011247 coating layer Substances 0.000 claims description 5
- 239000006103 coloring component Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000003365 glass fiber Substances 0.000 claims description 5
- 229910052784 alkaline earth metal Inorganic materials 0.000 claims description 4
- 239000006229 carbon black Substances 0.000 claims description 4
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 4
- 239000002041 carbon nanotube Substances 0.000 claims description 4
- 150000004696 coordination complex Chemical class 0.000 claims description 4
- 229910021389 graphene Inorganic materials 0.000 claims description 4
- 229910002804 graphite Inorganic materials 0.000 claims description 4
- 239000010439 graphite Substances 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 4
- 239000012860 organic pigment Substances 0.000 claims description 4
- IEQIEDJGQAUEQZ-UHFFFAOYSA-N phthalocyanine Chemical compound N1C(N=C2C3=CC=CC=C3C(N=C3C4=CC=CC=C4C(=N4)N3)=N2)=C(C=CC=C2)C2=C1N=C1C2=CC=CC=C2C4=N1 IEQIEDJGQAUEQZ-UHFFFAOYSA-N 0.000 claims description 4
- ANRHNWWPFJCPAZ-UHFFFAOYSA-M thionine Chemical compound [Cl-].C1=CC(N)=CC2=[S+]C3=CC(N)=CC=C3N=C21 ANRHNWWPFJCPAZ-UHFFFAOYSA-M 0.000 claims description 4
- 239000004698 Polyethylene Substances 0.000 claims description 3
- 150000001342 alkaline earth metals Chemical class 0.000 claims description 3
- 229920006231 aramid fiber Polymers 0.000 claims description 3
- 239000012964 benzotriazole Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 claims description 3
- 229920000573 polyethylene Polymers 0.000 claims description 3
- 125000003118 aryl group Chemical group 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 150000004699 copper complex Chemical class 0.000 claims description 2
- 239000001023 inorganic pigment Substances 0.000 claims description 2
- 239000007788 liquid Substances 0.000 description 23
- 238000007747 plating Methods 0.000 description 20
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 18
- 238000001179 sorption measurement Methods 0.000 description 13
- 229920001187 thermosetting polymer Polymers 0.000 description 12
- 238000005498 polishing Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000000243 solution Substances 0.000 description 10
- 239000007864 aqueous solution Substances 0.000 description 9
- 238000007654 immersion Methods 0.000 description 8
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- 206010042674 Swelling Diseases 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 239000003960 organic solvent Substances 0.000 description 5
- 238000012536 packaging technology Methods 0.000 description 5
- MUJIDPITZJWBSW-UHFFFAOYSA-N palladium(2+) Chemical compound [Pd+2] MUJIDPITZJWBSW-UHFFFAOYSA-N 0.000 description 5
- 230000008961 swelling Effects 0.000 description 5
- 230000002378 acidificating effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011888 foil Substances 0.000 description 4
- 238000006386 neutralization reaction Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910021642 ultra pure water Inorganic materials 0.000 description 4
- 239000012498 ultrapure water Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012190 activator Substances 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 241001641958 Desmia Species 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 229910001096 P alloy Inorganic materials 0.000 description 2
- 239000004696 Poly ether ether ketone Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 125000001072 heteroaryl group Chemical group 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000000049 pigment Substances 0.000 description 2
- 229920002530 polyetherether ketone Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012756 surface treatment agent Substances 0.000 description 2
- 239000012815 thermoplastic material Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- 241001050985 Disco Species 0.000 description 1
- JUWOETZNAMLKMG-UHFFFAOYSA-N [P].[Ni].[Cu] Chemical compound [P].[Ni].[Cu] JUWOETZNAMLKMG-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000002940 palladium Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Definitions
- the present invention relates to a method for manufacturing a wiring board, a method for manufacturing a semiconductor device, and a resin sheet. More specifically, the present invention relates to a manufacturing method for efficiently and at low cost to manufacture a wiring board and a semiconductor device, which are highly required to be miniaturized or have a high density.
- Non-Patent Document 1 and Non-Patent Document 2 are widely used in smartphones and tablet terminals (see, for example, Non-Patent Document 1 and Non-Patent Document 2).
- a packaging technology organic interposer
- FO-WLP fan-out type packaging technology
- TSV through mold via
- TSV through silicon via
- TSV through silicon via
- TMV Through Mold Via
- ECTC Electronics Components and Technology Conference
- eWLB-PoP Embedded Wafer Level PoP
- the formation of the above-mentioned fine wiring layer requires steps of seed layer formation by sputtering, resist formation, electroplating, resist removal, and seed layer removal, which complicates the manufacturing process. Therefore, a simpler method for forming a fine wiring layer is desired.
- an object of the present invention is to provide a simplified method for forming a fine wiring layer.
- the present invention relates to a method for manufacturing a wiring board as one aspect.
- a structure in which a resin sheet in which a glass cloth is arranged in an organic resin is attached on a support having a metal layer on the surface or on a built-in wiring layer provided in the support is prepared.
- a step of forming a wiring layer and a step of forming a wiring layer in the recess and the opening are provided.
- a resin sheet in which a glass cloth is arranged in an organic resin is used, and a recess is formed in the first resin layer region where the glass cloth does not exist in the resin sheet by an excimer laser, and wiring is performed in the recess or the like.
- the excimer laser can be used to finely process the concave portion, and the fine wiring layer can be easily formed.
- the step of forming the recess and the step of forming the opening may be performed first, or may be performed at the same time. Further, in this manufacturing method, in order to form the wiring layer in the recess and the opening, a plating treatment may be used, or another method may be used.
- the present invention relates to another method for manufacturing a wiring board as another aspect.
- This method of manufacturing a wiring board has a higher elastic modulus than the first resin layer region and the first resin layer region located outside on a support provided with a metal layer on the surface or on a built-in wiring layer provided on the support.
- a step of preparing a structure to which a resin sheet in which a highly elastic layer region located inside is formed in order is prepared, and a recess is formed in the first resin layer region on the surface side of the resin sheet by laser or imprint.
- a step of forming an opening extending from the surface of the resin sheet to the metal layer on the support, and a step of forming a wiring layer in the recess and the opening are provided.
- a resin sheet provided with a first resin layer region and a highly elastic layer region located on the outside is used, and a recess is formed in the first resin layer region of the resin sheet by laser or imprint.
- a wiring layer is formed in the recesses and the like.
- the concave portion can be finely machined by laser or imprint, and the fine wiring layer can be easily formed.
- the step of forming the recess and the step of forming the opening may be performed first, or may be performed at the same time. Further, in this manufacturing method, in order to form the wiring layer in the recess and the opening, a plating treatment may be used, or another method may be used.
- the highly elastic layer region may be formed by arranging at least one of the inorganic fiber and the organic fiber in the organic resin material.
- the inorganic fiber may be at least one of glass fiber, ceramic fiber, and carbon fiber
- the organic fiber may be at least one of aramid fiber and polyethylene fiber.
- the thickness of the first resin layer region on the surface side of the resin sheet may be 20 ⁇ m or less.
- the layer region forming the fine wiring layer can be thinned to reduce the height of the manufactured wiring board.
- the thickness of the first resin layer region may be 5 ⁇ m or more.
- the line width of the recess formed in the first resin layer region may be 0.5 ⁇ m or more and 5 ⁇ m or less. In this case, it is possible to form a fine wiring layer having excellent conductivity.
- the resin sheet has a second resin layer region on the opposite side of the first resin layer region, and in the step of preparing the structure, wiring is performed on the support or built-in wiring.
- a resin sheet may be attached on the layer by the second resin layer region to prepare a structure.
- the structure can be prepared by a simple method such as laminating, and the manufacturing method can be simplified.
- a structure in which the resin sheet is preliminarily attached on the support or the built-in wiring layer may be prepared and used in the subsequent steps.
- the pulse width of the excimer laser may be 10 nanoseconds or more and 50 nanoseconds or less, and the output of the excimer laser may be formed. May be 10 mJ / pulse or more and 1000 mJ / pulse or less. In this case, finer recesses can be easily formed.
- a plated metal layer is formed in the recesses and openings to form the wiring layer, and the resin sheet is a seed for forming the plated metal layer.
- It may contain a component consisting of a heteroaromatic ring capable of coordinating with the metal material constituting the layer. In this case, it becomes easier to form a finer wiring layer.
- the component consisting of a heteroaromatic ring capable of coordination bond with the metal material constituting the seed layer is composed of, for example, a group consisting of a maleimide compound, a bismaleimide compound, a triazole compound, a benzotriazole compound, and a benzoxazole compound. It may be at least one compound of choice.
- the resin sheet or the coating layer covering the resin sheet may contain a laser light-absorbing coloring component consisting of an inorganic dye, an inorganic pigment, an organic dye, and at least one of the organic pigments. ..
- the concave portion can be machined more reliably by the laser.
- the laser light-absorbing coloring component may be, for example, at least one of graphite, graphene, carbon nanotubes, carbon fibers, carbon black, phthalocyanine, cyanine, alkaline earth metal, and a metal complex.
- a seed layer by electroless plating is provided in the recess and the opening to form a plated metal layer to form the wiring layer, and the resin sheet is formed by the resin sheet.
- It may contain a catalyst for forming electroless plating. In this case, it becomes easier to form a finer wiring layer.
- the catalyst for forming the electroless plating may be at least one of palladium particles, a palladium complex, copper particles, and a copper complex.
- the concave portion and the opening are filled with the conductive material, and the conductive material is applied on the surface of the first resin layer region excluding the concave portion and the opening. It may have a step of forming a conductive layer and a step of flattening the conductivity. In the flattening step, at least the first portion of the conductive layer provided on the surface of the first resin layer region is polished, and the second portion of the conductive layer formed from the conductive material filled in the recesses and openings.
- the wiring layer may be formed from. In this case, the fine wiring layer can be formed more efficiently.
- the method for manufacturing any of the above wiring boards may further include a step of forming a built-in wiring portion having at least one built-in wiring layer on the support, and a step of preparing a structure is on the built-in wiring portion.
- the structure may be prepared by attaching the resin sheet to the wiring.
- the built-in wiring layer is composed of a build-up material
- the fine wiring layer on the surface is composed of an organic resin material such as prepreg. be able to.
- the degree of freedom in designing the wiring board can be increased.
- another resin sheet is attached on a resin sheet on which a wiring layer is formed, and another recess is formed by a laser with respect to a first resin layer region of the other resin sheet.
- a step of forming another wiring layer, a step of attaching another resin sheet, a step of forming another recess, a step of forming another opening, and a step of forming another wiring layer are further provided.
- the process may be repeated at least once. In this case, it is possible to simplify the method of manufacturing a wiring board provided with two or more fine wiring layers.
- the steps for forming the wiring layer are at least a step of performing desmear treatment on the openings and recesses and forming a seed layer on at least the openings and recesses by electroless plating.
- the present invention relates to a method for manufacturing a semiconductor device as yet another aspect.
- the method for manufacturing this semiconductor device includes a step of preparing a wiring board manufactured by any of the above methods for manufacturing a wiring board, mounting a semiconductor element on a wiring layer or another wiring layer, and mounting the semiconductor element on the wiring layer or. A process of electrically connecting to another wiring layer is provided.
- a semiconductor device having a wiring board provided with a fine wiring layer can be manufactured by a simplified method.
- it is manufactured by a simplified method it is possible to improve the manufacturing yield or reduce the cost of manufactured products.
- the semiconductor elements when a plurality of semiconductor elements (chips) are mounted (especially when mounted at a high density), the semiconductor elements can be connected to each other by a fine wiring layer having excellent transmissibility. , It becomes possible to provide a small semiconductor device having better performance.
- the present invention relates to a resin sheet as yet another aspect.
- This resin sheet is a resin sheet used in any of the above methods for manufacturing a wiring substrate, and has a higher elastic modulus than the first resin layer region located on the outside and the first resin layer region and is located on the inside. It comprises a high elastic layer region or a high elastic layer region having a glass cloth and located inside.
- the above resin sheet may further include a second resin layer region located on the opposite side of the first resin layer region via the highly elastic layer region, and the second resin layer region has adhesiveness. May be good.
- the structure including the resin sheet can be formed more easily, and the above-mentioned method for manufacturing the wiring board and the method for manufacturing the semiconductor device can be further simplified.
- FIG. 1 (a) to 1 (d) are views showing a part of a method for manufacturing a wiring board according to an embodiment of the present invention.
- 2 (a) to 2 (c) are views showing a part of a method for manufacturing a wiring board according to an embodiment of the present invention, and are views showing steps performed after the step of FIG. 1. ..
- FIG. 3 is a diagram showing an example of a semiconductor device in which a semiconductor element is mounted on a wiring board manufactured by the manufacturing methods shown in FIGS. 1 and 2.
- FIG. 4A is a diagram showing a wiring board according to a modified example
- FIG. 4B is a diagram showing a semiconductor device according to a modified example.
- the term “layer” includes not only a structure having a shape formed on the entire surface but also a structure having a shape partially formed when observed as a plan view.
- the term “process” is used not only as an independent process but also as long as the intended action of the process is achieved even if it cannot be clearly distinguished from other processes. included.
- the numerical range indicated by using “-” indicates a range including the numerical values before and after "-" as the minimum value and the maximum value, respectively.
- a method for manufacturing a wiring board and a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.
- the method for manufacturing a wiring board and the method for manufacturing a semiconductor device according to the present embodiment are preferably applied to, but are not limited to, a form in which miniaturization and multi-pinning are required.
- the manufacturing method according to the present embodiment is preferably applied to a package form that requires an interposer for mixedly mounting different types of chips, but is not limited to this.
- the case where one semiconductor element is mounted is described, but the same applies to the form in which two or more (or two or more types) of semiconductor elements are mounted.
- ⁇ Structure preparation process> 1 and 2 are diagrams showing a method of manufacturing a wiring board according to the present embodiment.
- a structure 1a in which a resin sheet 3 is attached is prepared on a support 1 having a copper layer 2 (metal layer) on its surface.
- the resin sheet 3 is, for example, a sheet obtained by impregnating a glass cloth with an organic resin, and has a first resin layer region 4 on the surface side where the glass sheet does not exist and a height located inside the first resin layer region 4. It has an elastic layer region 5 and a second resin layer region 6 located on the opposite side of the first resin layer region 4 via a highly elastic layer region 5 (glass cloth).
- the resin sheet 3 may have a structure in which a highly elastic body such as a glass cloth is arranged in an organic resin, for example, and may have a structure in which both sides of the glass cloth are laminated with a resin sheet.
- the second resin layer region 6 has adhesiveness, for example, and is attached by attaching the resin sheet 3 to the copper layer 2 of the support 1 via the second resin layer region 6.
- the resin sheet 3 may be attached to the copper layer 2 on the support 1, or the resin sheet 3 may be attached to the structure 1a in advance on the support 1 via the copper layer 2. May be prepared and used.
- the support 1 is not particularly limited, but is, for example, a silicon plate, a glass plate, a SUS plate, a substrate containing a glass cloth, a sealing resin substrate containing a semiconductor element, or the like, and is a substrate having high rigidity.
- the thickness of the support 1 may be 0.2 mm or more and 2.0 mm or less. When the support 1 is 0.2 mm or more, the handling property can be improved, and when the support 1 is 2.0 mm or less, the wiring board can be easily lowered and the material cost can be reduced. It is possible to reduce costs.
- the support 1 may have either a wafer shape or a panel shape, and the size of the support 1 is not particularly limited.
- the support 1 may be a wafer having a diameter of 200 mm, a diameter of 300 mm or a diameter of 450 mm, or a rectangular panel having a side of 300 mm or more and 700 mm or less.
- the resin sheet 3 is a semi-cured film-like member such as a prepreg.
- the organic resin material contained in the resin sheet 3 may contain at least one of a thermosetting material and a thermoplastic material in order to ensure electrical insulation.
- the thermosetting material used here is, for example, an epoxy resin, and the thermoplastic resin is, for example, an acrylic resin, but the present invention is not limited thereto.
- the organic resin material contained in the resin sheet 3 may be a film-like composite from the viewpoint of film thickness flatness and cost. Further, the organic resin material may contain a thermosetting material in that fine recesses can be formed.
- the size of the filler (filler) contained in the thermosetting material may have an average particle size of 500 nm or less. The thermosetting material does not have to contain a filler.
- the first resin layer region 4 and the second resin layer region 6 of the resin sheet 3 are formed of such an organic resin material and are regions in which the glass cloth does not exist. Since the first resin layer region 4 forms a fine trench structure in the recess forming step described later, the film thickness of the first resin layer region 4 may be 20 ⁇ m or less or 10 ⁇ m or less. The film thickness of the first resin layer region 4 may be 5 ⁇ m or more in order to ensure conductivity in the fine wiring structure.
- the glass cloth contained in the resin sheet 3 is composed of a woven fabric or a non-woven fabric containing glass fibers.
- the glass fiber may be, for example, E glass, S glass, or quartz glass.
- the thickness of the glass cloth may be, for example, 0.01 ⁇ m or more and 0.2 ⁇ m or less.
- Such a glass cloth is impregnated with the above-mentioned organic resin material to form the highly elastic layer region 5. That is, the highly elastic layer region 5 is composed of a glass cloth and an organic resin material impregnated or penetrated into the glass cloth. Since the highly elastic layer region 5 contains a rigid material such as glass, it is configured to have a higher elastic modulus, specifically, Young's modulus than the first resin layer region 4 and the second resin layer region 6.
- the other inorganic fiber and the organic fiber may be impregnated into the organic resin material to form the highly elastic layer region 5.
- the inorganic fiber is, for example, a ceramic fiber or a carbon fiber
- the organic fiber is, for example, an aramid fiber or a polyethylene fiber.
- the organic resin material contained in the resin sheet 3 is arranged with a metal such as a maleimide compound, a bismaleimide compound, a triazole compound, a benzotriazole compound, or a benzoxazole compound in order to enhance the adhesion to the seed layer formed in a later step. It may contain a component consisting of a complex aromatic ring capable of coordinating.
- the metal referred to here is a metal material constituting the seed layer. This component may be included in the filler surface treatment agent.
- the resin sheet 3 may contain palladium particles, palladium complexes, copper particles, and copper complexes that serve as catalysts by electroless plating.
- the resin sheet 3 has an inorganic dye or pigment such as graphite, graphene, carbon nanotube, carbon fiber, carbon black, or a phthalocyanine-based, cyanine-based, alkaline earth metal salt, for example, in order to enhance the absorption with laser light. It may contain a laser light-absorbing coloring component composed of an organic dye such as a metal complex or an organic pigment. This component may be included in the filler surface treatment agent.
- an inorganic dye or pigment such as graphite, graphene, carbon nanotube, carbon fiber, carbon black, or a phthalocyanine-based, cyanine-based, alkaline earth metal salt, for example, in order to enhance the absorption with laser light.
- It may contain a laser light-absorbing coloring component composed of an organic dye such as a metal complex or an organic pigment. This component may be included in the filler surface treatment agent.
- the resin sheet 3 has the above-mentioned configuration, and may have a thickness of, for example, 10 ⁇ m or more and 100 ⁇ m or less. When the thickness of the resin sheet 3 is 10 ⁇ m or more, the handleability can be improved. Further, when the thickness of the resin sheet 3 is 100 ⁇ m or less, the manufactured wiring board or semiconductor device can be made into a thin package.
- the resin sheet 3 may be formed, for example, by impregnating an organic resin (varnish) with glass cloth to form a structure having a first resin layer region 4, a highly elastic layer region 5, and a second resin layer region 6.
- the glass cloth may be arranged between the resin layer corresponding to the first resin layer region 4 and the resin layer corresponding to the second resin layer region 6 and laminated or pressed.
- a vacuum laminating, a roll laminating, a vacuum roll laminating, an atmospheric pressure press, a vacuum press or the like can be used.
- the temperature at the time of forming the resin sheet 3 may be a temperature at which the thermosetting material contained in the resin sheet 3 is thermally cured, and may be, for example, 100 ° C. or higher and 250 ° C. or lower.
- the formation temperature By setting the formation temperature to 100 ° C. or higher, the tackiness of the organic resin material of the resin sheet 3 can be weakened and the handleability can be improved.
- the formation temperature By setting the formation temperature to 250 ° C. or lower, the warp of the resin sheet 3 can be suppressed.
- Examples of such a resin sheet 3 include "MCL-E-705G, thickness 0.4 mm or 0.6 mm, 255 mm square (manufactured by Hitachi Chemical Co., Ltd.)” or “R-1766 thickness 0.4 mm or 0. "6 mm, 255 mm square", “R-5715ES thickness 0.4 mm or 0.6 mm, 255 mm square", “R-5670Kj thickness 0.4 mm or 0.6 mm, 255 mm square (all manufactured by Panasonic Corporation)", or "GHPL830NS Thickness 0.4mm or 0.6mm 255mm Square", “830NS Thickness 0.4mm or 0.6mm, 255mm Square”, “830NSF Thickness 0.4mm or 0.6mm, 255mm Square” (above, Mitsubishi Gas Chemical Company Limited) Made) ”can be used.
- a coating layer can be provided on the surface of the resin sheet 3 (the side where the recess is formed).
- the coating layer may be, for example, an organic resin film containing a polyethylene terephthalate (PET) resin, a polyethylene naphthalate (PEN) resin, a polyetheretherketone (PEEK) resin, a polyimide (PI) resin, or a Cu foil or Ni foil. It may be a metal foil such as SUS foil.
- the organic resin film constituting the coating layer is an inorganic dye or pigment such as graphite, graphene, carbon nanotube, carbon fiber, carbon black, or a phthalocyanine-based, cyanine-based, alkaline earth metal. It may contain a laser light-absorbing coloring component composed of an organic dye such as a salt or a metal complex or an organic pigment. Further, the surface of the metal foil may be blackened.
- the recess 7 refers to a portion recessed in the thickness direction of the first resin layer region 4 with respect to the surface of the first resin layer region 4, and includes an inner wall (side wall, bottom wall, etc.) of the recessed portion. ..
- the recess 7 has a width along the left-right direction shown in the figure, is formed like a groove extending in the vertical direction shown in the figure, and has a shape corresponding to fine wiring in the plane direction.
- an excimer laser may be used for processing from the viewpoint of miniaturization, but a carbon dioxide laser or UV-YAG may be used. Processing using a laser or imprint may be used.
- the recess 7 may be formed so that the opening width is 0.5 ⁇ m or more and 20 ⁇ m or less, and from the viewpoint of miniaturization, the recess 7 is formed so that the opening width is 0.5 ⁇ m or more and 5 ⁇ m or less. May be formed. This makes it possible to provide a semiconductor device having a high density by forming a fine wiring layer. An excimer laser may be used to form a recess having such a fine opening width as described above.
- the medium of the excimer laser used is argon / fluorine (ArF) or krypton / fluorine (KrF), and from the viewpoint of versatility, an excimer laser using KrF as a medium may be used.
- the pulse energy may be 20 mJ or more and 100 mJ or less.
- the pulse repetition frequency may be 1 Hz or more and 4000 Hz or less.
- the pulse width may be 10 nanoseconds or more and 50 nanoseconds or less.
- the laser irradiation amount may be greater than 0 and 1000 mJ / cm 2 or less.
- the output of the excimer laser may be 10 mJ / pulse or more and 1000 mJ / pulse or less.
- the resin sheet 3 including the first resin layer region 4 may be further heat-cured.
- the heating temperature at this time may be 100 ° C. or higher and 250 ° C. or lower, and the heating time may be 30 minutes or longer and 3 hours or lower.
- the recess 7 is configured so as not to reach the highly elastic layer region 5.
- an opening 8 is formed from the surface of the resin sheet 3 to the copper layer 2 of the support 1.
- the highly elastic layer region 5 including the glass cloth in the resin sheet 3 and the first resin layer region 4 and the second resin layer region 6 made of the organic resin material are put together.
- the opening 8 is formed through the penetration.
- a method for forming the opening 8 for example, carbon dioxide laser processing or drilling can be used, but from the viewpoint of miniaturization, a carbon dioxide laser may be used.
- an opening 8 having an opening diameter of 30 ⁇ m or more and 200 ⁇ m or less is formed.
- the opening step may be performed before, after, or at the same time as the recess forming step described above, and the order thereof is not particularly limited.
- a step of desmearing is performed for the purpose of removing the smear formed by the laser opening.
- a commercially available pretreatment liquid and a desmear liquid may be used.
- a swelling liquid manufactured by Atotech Japan Co., Ltd., trade name: Swering Dip Securigant
- a roughening liquid manufactured by Atotech Japan Co., Ltd., trade name: Concentrate Compact CP
- a chemical solution used for neutralization after desmia for example, a neutralizing solution (manufactured by Atotech Japan Co., Ltd., trade name: reduction securigant) can be used.
- the temperature of the swelling liquid may be 50 ° C. or higher and 80 ° C. or lower, and the immersion time may be 1 minute or longer and 30 minutes or lower.
- the recess 7 and the opening 8 and the like may be washed with pure water or city water.
- a step of roughening treatment with a desmear liquid is carried out.
- the temperature of the desmear liquid is 30 ° C. or higher and 80 ° C. or lower, and the immersion time may be 1 minute or longer and 30 minutes or shorter. After the desmear treatment, it may be washed with pure water or city water.
- a drag-out process is carried out with pure water or city water.
- the drag-out temperature may be 25 ° C. or higher and 50 ° C. or lower, and the immersion time may be 1 minute or longer and 5 minutes or lower.
- a neutralization step is carried out.
- the neutralization temperature may be 25 ° C. or higher and 50 ° C. or lower, and the immersion time may be 1 minute or longer and 10 minutes or shorter.
- the neutralization treatment it may be washed with pure water or city water. With the above, the desmear processing is completed.
- the seed layer 9 can be formed by using a method using a copper paste, a sputtering method, or an electroless plating method. As a method suitable for paneling, an electroless plating method can be used.
- the seed layer 9 In order to form the seed layer 9, first, palladium, which is a catalyst for electroless copper plating, is applied to the surface of the first resin layer region 4, the side wall and bottom wall of the recess 7, the side wall of the opening 8, and the opening.
- the surface of the first resin layer region 4 and the like are washed with a pretreatment liquid in order to be adsorbed on the surface of the copper layer 2 exposed to 8 (hereinafter, also referred to as “the surface of the first resin layer region 4 and the like”).
- the pretreatment liquid is a commercially available alkaline pretreatment liquid containing, for example, sodium hydroxide or potassium hydroxide.
- the pretreatment may be carried out when the concentration of sodium hydroxide or potassium hydroxide is 1% or more and 30% or less, or the immersion time in the pretreatment liquid is 1 minute or more and 60 minutes or less. It may be carried out while the immersion temperature in the pretreatment liquid is 25 ° C. or higher and 80 ° C. or lower. After the pretreatment, it may be washed with city water, pure water, ultrapure water or an organic solvent in order to remove excess pretreatment liquid.
- the pretreatment liquid After removing the pretreatment liquid, it is immersed and washed with an acidic aqueous solution in order to remove alkaline ions from the surface of the first resin layer region 4 and the like.
- the immersion washing may be carried out using a sulfuric acid aqueous solution as an acidic aqueous solution, or may be carried out while the concentration is 1% or more and 20% or less, and the soaking time is 1 minute or more and 60 minutes or less.
- the acidic aqueous solution it may be washed with city water, pure water, ultrapure water or an organic solvent. Then, palladium is attached to the first resin layer region 4 and the like after being immersed and washed with an acidic aqueous solution.
- a commercially available palladium sol colloidal solution, an aqueous solution containing palladium ions, a palladium ion suspension, or the like may be used for adhering palladium, but an aqueous solution containing palladium ions that effectively adsorbs to the modified layer is used. You may.
- the temperature of the aqueous solution containing palladium ions may be 25 ° C. or higher and 80 ° C. or lower, and the immersion time for adsorption may be 1 minute or longer and 60 minutes or shorter.
- After adsorbing the palladium ions it may be washed with city water, pure water, ultrapure water or an organic solvent in order to remove excess palladium ions.
- activation is performed so that the palladium ion acts as a catalyst.
- a commercially available activator activation treatment liquid
- the temperature of the activator soaked to activate the palladium ions is between 25 ° C and 80 ° C, and the soaking time to activate is between 1 minute and 60 minutes or less. good.
- the seed layer 9 is formed by electroless plating using palladium as a catalyst.
- the seed layer 9 is an electroless plating layer selected from the group consisting of, for example, a copper layer, a nickel layer, a copper nickel alloy layer, a nickel phosphorus alloy layer, and a copper nickel phosphorus alloy layer. From the viewpoint of cost, the material of the seed layer 9 may be a copper layer.
- a commercially available plating solution may be used as the electroless plating solution.
- an electroless copper plating solution manufactured by Atotech Japan Co., Ltd., trade name: Copper Solution Print Gantt MSK
- the formation of electroless copper plating is carried out in an electroless copper plating solution at a temperature of 20 ° C. or higher and 40 ° C. or lower.
- the thickness of the seed layer 9 may be 0.1 nm or more and 500 nm or less, 0.1 nm or more and 400 nm or less, or 0.1 nm or more and 300 nm or less.
- the thickness of the seed layer 9 By setting the thickness of the seed layer 9 to 0.1 nm or more, it becomes easy to form wiring with a uniform thickness in the subsequent electrolytic plating. On the other hand, by setting the thickness of the seed layer 9 to 500 nm or less, it is possible to prevent excessive etching of the wiring in the etching process of the seed layer 9, and it is possible to form fine wiring with good yield.
- thermosetting temperature 80 ° C. or higher and 200 ° C. or lower.
- the thermosetting temperature may be heated to 120 ° C. or higher and 200 ° C. or lower, or the thermosetting temperature may be heated to 120 ° C. or higher and 180 ° C. or lower.
- the thermosetting time may be 5 minutes or more and 60 minutes or less, 10 minutes or more and 60 minutes or less, or 20 minutes or more and 60 minutes or less.
- ⁇ Copper layer forming process> When the step of forming the seed layer is completed, as shown in FIG. 2A, copper layers 10, 11 and 12 (plated metal layer, conductive layer) are formed on the seed layer 9 by electrolytic copper plating (conductive material). Perform the forming step. More specifically, the copper layer formed by electroless copper plating is used as the seed layer 9, and the copper layers 10 to 12 are formed on the seed layer 9 by electrolytic copper plating. In the present embodiment, electrolytic copper plating is used as a method for forming the copper layers 10 to 12, but in addition to this, for example, electroless plating may be used.
- the copper layer 10 (second portion) is filled in the recess 7 provided on the surface of the first resin layer region 4, and the copper layer 11 (second portion) is the first resin layer region 4.
- the inside of the opening 8 provided so as to reach the copper layer 2 from the surface of the copper layer 12 is filled, and the copper layer 12 (first portion) is formed on the surface of the first resin layer region 4 excluding the recess 7 and the opening 8.
- the surface of the first resin layer region 4 excluding the recess 7 and the opening 8 in the subsequent step can be used.
- Copper formed on the surface of the first resin layer region 4, the recess 7, and the opening 8 by simply removing the copper layer 12, the seed layer, and the palladium adsorption layer without scraping the surface of the first resin layer region 4. It becomes possible to flatten the layers 10 to 12. After removing the copper layer, the seed layer, and the palladium adsorption layer, the surface of the first resin layer region 4 is further scraped, and the copper layer formed on the surface of the first resin layer region 4, the recess 7 and the opening 8 respectively. 10 and 11 may be flattened.
- the inside of the recess 7 and the opening 8 are compared with the surface of the first resin layer region 4. So-called filled plating, in which the amount of electrolytic copper plating deposited on the surface (plating thickness) is large, may be used.
- the copper layers 10 and 11 may not be filled in the recess 7 or the opening 8, and may be formed along the inner wall (bottom wall and side wall) of the recess 7 or the opening 8.
- the main portion of the wiring layer 13 is formed of a copper layer 10 formed in a plurality of recesses 7.
- the wiring layer 13 is connected to the connection terminal of the semiconductor element 22 described later.
- the surface of the first resin layer region 4 excluding the recess 7 are separated. It may be flattened. Further, when removing the copper layer 12, the seed layer, and the palladium adsorption layer on the upper part of the first resin layer region 4, a part in the thickness direction is removed from the upper (surface) side of the first resin layer region 4. You may. A back grind method, a fly-cut method, or chemical mechanical polishing (CMP) is used as a method for removing the copper layer 12, the seed layer, the palladium adsorption layer, and the first resin layer region 4 above the first resin layer region 4.
- CMP chemical mechanical polishing
- a plurality of removal methods may be used in combination.
- a grinding device with a diamond bite is used.
- an automatic surface planar (manufactured by Disco Corporation, trade name "DAS8930”) compatible with a 300 mm wafer can be used.
- the removal of the metal layer and the palladium adsorption layer by the fly-cut method is a flattening process because the entire surface is uniformly polished from the upper side (surface side) of the first resin layer region 4, so that the polished surface becomes flat. It can be said that.
- CMP chemical mechanical polishing
- a CMP polishing device compatible with a 300 mm wafer manufactured by Applied Materials, trade name "F-REX300X"
- polishing can be performed using a polishing liquid containing abrasive grain components such as silica, alumina, and ceria. Further, a plurality of polishing liquids may be used in combination, or the polishing liquids may be sequentially used. After polishing, polishing debris and excess abrasive grains may be removed with a cleaning liquid such as pure water or a solvent.
- the copper layer 12 the seed layer, the palladium adsorption layer and the upper part of the first resin layer region 4
- the exposed seed layer and the surfaces of the copper layers 10 and 11 may be chemically or physically roughened.
- the exposed seed layer, the copper layers 10 and 11 (wiring layer 13), and the palladium adsorption layer are cap-plated by electroless plating. 14, 15 may be formed.
- the metal type of the cap platings 14 and 15 a metal containing any one of Cu, Ni, Cr, and W may be used.
- the wiring board 20 having the fine wiring layer 13 is manufactured.
- the semiconductor element 22 is mounted on the wiring layer 13 on the wiring board 20, and the connection terminals of the semiconductor element 22 are electrically connected to the wiring layer 13. As a result, the semiconductor device 25 connected by the fine wiring layer 13 is manufactured.
- the resin sheet 3 in which the glass cloth is arranged in the organic resin is used, and the excimer laser is used in the first resin layer region 4 in which the glass cloth does not exist in the resin sheet 3. 7 is formed, and the wiring layer 13 is formed in the recess 7 and the like.
- the concave portion 7 can be finely machined by a laser, and the fine wiring layer can be easily formed.
- the thickness of the first resin layer region 4 on the surface side of the resin sheet 3 may be 20 ⁇ m or less.
- the layer region forming the fine wiring layer 13 can be thinned to reduce the height of the manufactured wiring board 20.
- the thickness of the first resin layer region 4 may be 5 ⁇ m or more.
- the line width of the recess 7 formed in the first resin layer region 4 may be 0.5 ⁇ m or more and 5 ⁇ m or less. In this case, it is possible to form a fine wiring layer 13 having excellent conductivity.
- the resin sheet 3 has a second resin layer region 6 on the opposite side of the first resin layer region 4, and in the step of preparing the structure, the resin sheet 3 has a second resin layer region 6.
- the structure 1a is prepared by attaching the resin sheet 3 on the support 1 by the second resin layer region 6.
- the structure 1a can be prepared by a simple method such as laminating, and the manufacturing method can be simplified.
- the steps for forming the plating layer include a step of performing desmear treatment on the recess 7 and the opening 8 and the surface of the first resin layer region, and the recess 7.
- the conductive portion of the fine wiring layer 13 can be formed more reliably.
- the semiconductor device 25 having the wiring board 20 provided with the fine wiring layer 13 can be manufactured by a simplified method by the various methods described above. In addition, since it is manufactured by a simplified method, it is possible to improve the manufacturing yield or reduce the cost of manufactured products. Further, but not limited to this, when a plurality of semiconductor elements (chips) are mounted (especially when mounted at a high density), the semiconductor elements can be connected to each other by a fine wiring layer having excellent transmissibility. , It becomes possible to provide a small semiconductor device having better performance.
- the resin sheet 3 according to the present embodiment includes a first resin layer region 4 located on the outer side and a highly elastic layer region 5 having a higher elastic modulus than the first resin layer region 4 and located on the inner side.
- the resin sheet 3 according to the present embodiment further includes a second resin layer region 6 located on the opposite side of the first resin layer region 4 via the highly elastic layer region 5, and the second resin layer region 6 is provided. It has adhesiveness. Therefore, the structure 1a including the resin sheet 3 can be formed more easily, and the above-mentioned manufacturing method of the wiring board 20 and the manufacturing method of the semiconductor device 25 can be further simplified.
- one wiring layer 13 is provided and a semiconductor element 22 is arranged on the wiring layer 13 to manufacture a semiconductor device 25.
- the wiring layer 13 has two layers. It may be the above.
- another resin sheet 3 is further attached to the first resin layer region 4 on which the wiring layer 13 is formed by sticking or the like. The step, the step of forming another recess 7 in the first resin layer region 4 of another resin sheet 3, the step of forming another opening 8 in another resin sheet 3, and another wiring layer 13 are separated.
- the wiring layer 13 may be multi-layered by repeating the process of forming the recess 7 and the other opening 8 one or more times. When the number of layers is increased, another opening 8 is formed so as to reach the copper layer 11 or the wiring layer 13 of the inner opening 8 from the surface side of another resin sheet 3. As a result, it is possible to obtain a wiring board and a semiconductor device in which the fine wiring layer 13 is multi-layered.
- one or more built-in wiring layers 31 are provided on the support 1 to form a built-in wiring portion, and a resin sheet 3 is attached on the built-in wiring layer 3 by sticking or the like to form a recess. 7 may be formed, an opening 8 may be formed, and a wiring layer 13 may be formed to form a multilayer wiring board 30.
- the semiconductor element 32 may be mounted on the multilayer wiring board 30 to form the semiconductor device 35.
- the built-in wiring layer 31 can be formed by using the build-up method.
- the built-in wiring layer 31 can be multi-layered by using a conventional method, and only the wiring layer 13 on the surface layer (that is, the connection portion with the semiconductor element) can be made into a finer wiring layer.
- the built-in wiring layer 31 is composed of a build-up material, and the fine wiring layer 13 on the surface is optimally configured by using different materials such as laser processing an organic resin material such as prepreg to form recesses.
- Wiring board can be manufactured. Further, according to the manufacturing method according to such a modification, it is possible to increase the degree of freedom in designing the wiring board.
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Abstract
Description
図1及び図2は、本実施形態に係る配線基板の製造方法を示す図である。図1の(a)に示すように、まず、表面に銅層2(金属層)を設けた支持体1上に樹脂シート3が取り付けられた構造体1aを準備する。樹脂シート3は、例えば、ガラスクロスに有機樹脂を含浸させたシートであり、表面側であってガラスシートが存在しない第1樹脂層領域4と、第1樹脂層領域4の内側に位置する高弾性層領域5と、第1樹脂層領域4とは高弾性層領域5(ガラスクロス)を介して反対側に位置する第2樹脂層領域6とを、有している。樹脂シート3は、例えば有機樹脂中にガラスクロス等の高弾性体が配置されている構成であればよく、ガラスクロスの両面を樹脂シートでラミネートした構成のものであってもよい。第2樹脂層領域6は、例えば粘着性を有しており、第2樹脂層領域6を介して支持体1の銅層2に樹脂シート3が貼り付けられることで取り付けられる。構造体1aの準備工程では、支持体1上の銅層2に樹脂シート3を貼り付けてもよいし、樹脂シート3が銅層2を介して支持体1上に予め取り付けられた構造体1aを用意しておき、それを用いてもよい。
次に、構造体1aの準備工程が終了すると、図1の(b)に示すように、樹脂シート3の表面側であってガラスクロスが存在しない第1樹脂層領域4に対してエキシマレーザにより複数の凹部7を形成する。凹部7は、第1樹脂層領域4の表面に対して、第1樹脂層領域4の厚さ方向に凹んだ部位をいい、この凹んだ部位の内壁(側壁及び底壁等)を含んでいる。凹部7は、図示の左右方向に沿った幅で、図示垂直方向等に伸びる溝のように形成されており、平面方向において微細配線に対応する形状を有している。熱硬化性材料又は熱可塑性材料から形成される第1樹脂層領域4に凹部を形成するには、微細化の観点からはエキシマレーザを用いて加工してもよいが、炭酸ガスレーザ若しくはUV-YAGレーザを用いた加工、又は、インプリントを用いてもよい。
次に、凹部7の形成が終了すると、図1の(c)に示すように、樹脂シート3の表面から支持体1の銅層2に到る開口部8を形成する。開口部の形成工程では、樹脂シート3においてガラスクロスを含んで構成される高弾性層領域5と、有機樹脂材料から構成される第1樹脂層領域4及び第2樹脂層領域6とをまとめて貫通して開口部8が形成される。開口部8を形成する方法としては、例えば、炭酸ガスレーザ加工又はドリル加工を用いることができるが、微細化の観点からは、炭酸ガスレーザを用いてもよい。
次に、凹部7及び開口部8の形成が終了すると、レーザ開口で形成されたスミアを除去する目的で、デスミアする工程を行う。デスミア液は、市販の前処理液及びデスミア液を用いてもよい。前処理液としては、例えば膨潤液(株式会社アトテックジャパン製、商品名:スウェリングディップセキュリガント)を用いることができる。デスミア液として、例えば粗化液(株式会社アトテックジャパン製、商品名:コンセントレートコンパクトCP)を用いることができる。デスミア後の中和に使用する薬液として、例えば中和液(株式会社アトテックジャパン製、商品名:リダクションセキュリガント)を用いることができる。
デスミア処理が終了すると、図1(d)に示すように、第1樹脂層領域4の表面と、凹部7の側壁及び底壁と、開口部8の側壁と、開口部8に露出する銅層2の表面とにシード層9を形成する工程を行う。シード層の形成工程では、銅ペーストを用いた方法、スパッタリング方法、又は無電解めっき法を用いて、シード層9を形成することができる。パネル化に適した方法としては、無電解めっき法を用いることができる。
シード層の形成工程が終了すると、図2の(a)に示すように、シード層9上に電解銅めっき(導電性材料)により銅層10,11,12(めっき金属層、導電層)を形成する工程を行う。より具体的には、無電解銅めっきで形成した銅層をシード層9として、その上に電解銅めっきにより、銅層10~12を形成する。なお、本実施形態では、銅層10~12を形成する方法として、電解銅めっきを用いるが、これ以外に、例えば、無電解めっきを用いてもよい。
次に、銅層の形成が終了すると、図2の(b)に示すように、第1樹脂層領域4の凹部7及び開口部8を除く表面から、銅層12、シード層及びパラジウム触媒を除去することによって、凹部7に形成された銅層10及び開口部8に形成された銅層11からなる配線層13を形成する工程を行う。すなわち、第1樹脂層領域4の表面の銅層12、シード層、パラジウム吸着層を除去することによって、第1樹脂層領域4の凹部7等を含む表面においては、凹部7及び開口部8にのみ銅層10,11(詳細には、銅層10,11に対応するシード層、パラジウム吸着層を含む)が残され、凹部7及び開口部8の銅層10、11等が配線層13を形成する。配線層13の主要部は、複数の凹部7に形成された銅層10から形成される。配線層13は、後述する半導体素子22の接続端子に接続される。
次に、配線層の形成工程が終了すると、図2(c)に示すように、露出したシード層、銅層10、11(配線層13)、パラジウム吸着層上に、無電解めっきによってキャップめっき14,15を形成してもよい。キャップめっき14,15の金属種としては、Cu、Ni,Cr,Wのいずれか一種類を含む金属を用いてもよい。以上により、微細な配線層13を有する配線基板20が作製される。
次に、図3に示すように、配線基板20上の配線層13上に半導体素子22を実装し、半導体素子22の接続端子を配線層13に電気的に接続する。これにより、微細な配線層13によって接続された半導体装置25が作製される。
Claims (22)
- 表面に金属層を設けた支持体上に又は前記支持体に設けた内蔵配線層上に有機樹脂中にガラスクロスを配置した樹脂シートが取り付けられた構造体を準備する工程と、
前記樹脂シートの表面側であって前記ガラスクロスが存在しない第1樹脂層領域に対してエキシマレーザにより凹部を形成する工程と、
前記樹脂シートの表面から前記支持体上の前記金属層に到る開口部を形成する工程と、
前記凹部及び前記開口部に配線層を形成する工程と、
を備える、配線基板の製造方法。 - 表面に金属層を設けた支持体上に又は前記支持体に設けた内蔵配線層上に外側に位置する第1樹脂層領域と前記第1樹脂層領域より弾性率が高く内側に位置する高弾性層領域とが順に形成された樹脂シートが取り付けられた構造体を準備する工程と、
前記樹脂シートの表面側であって前記第1樹脂層領域にレーザ又はインプリントにより凹部を形成する工程と、
前記樹脂シートの表面から前記支持体上の前記金属層に到る開口部を形成する工程と、
前記凹部及び前記開口部に配線層を形成する工程と、
を備える、配線基板の製造方法。 - 前記高弾性層領域は、無機繊維及び有機繊維の少なくとも一方が有機樹脂材料中に配置されることにより形成されている、
請求項2に記載の配線基板の製造方法。 - 前記無機繊維は、ガラス繊維、セラミック繊維、及び炭素繊維の少なくとも1つであり、前記有機繊維は、アラミド繊維、及びポリエチレン繊維の少なくとも1つである、
請求項3に記載の配線基板の製造方法。 - 前記樹脂シートの表面側における前記第1樹脂層領域の厚みが5μm以上20μm以下である、
請求項1~4の何れか一項に記載の配線基板の製造方法。 - 前記第1樹脂層領域に形成される前記凹部のライン幅が0.5μm以上5μm以下である、
請求項1~5の何れか一項に記載の配線基板の製造方法。 - 前記樹脂シートは、前記第1樹脂層領域とは逆側に第2樹脂層領域を有しており、
前記構造体を準備する工程では、前記支持体上又は前記内蔵配線層上に前記樹脂シートを前記第2樹脂層領域によって貼り付けて、前記構造体を準備する、
請求項1~6の何れか一項に記載の配線基板の製造方法。 - 前記第1樹脂層領域にエキシマレーザにより前記凹部を形成する場合において、前記エキシマレーザのパルス幅が10ナノ秒以上50ナノ秒以下であり、前記エキシマレーザの出力が10mJ/パルス以上1000mJ/パルス以下である、
請求項1~7の何れか一項に記載の配線基板の製造方法。 - 前記配線層を形成する工程では、前記凹部及び前記開口部にめっき金属層を形成して前記配線層を形成し、
前記樹脂シートは、前記めっき金属層を形成するためのシード層を構成する金属材料と配位結合が可能な複素芳香族環からなる成分を含む、
請求項1~8の何れか一項に記載の配線基板の製造方法。 - 前記樹脂シート又は前記樹脂シートを覆う被覆層は、無機染料、無機顔料、有機染料、及び有機顔料の少なくとも1つからなるレーザ光吸収性着色成分を含む、
請求項1~9の何れか一項に記載の配線基板の製造方法。 - 前記配線層を形成する工程では、前記凹部及び前記開口部に無電解めっきによるシード層を設けてめっき金属層を形成して前記配線層を形成し、
前記樹脂シートは、前記無電解めっきを形成するための触媒を含む、
請求項1~10の何れか一項に記載の配線基板の製造方法。 - 前記配線層を形成する工程は、
前記凹部及び前記開口部に導電性材料を充填すると共に前記凹部及び前記開口部を除く前記第1樹脂層領域の表面上に導電性材料を設けて、導電層を形成する工程と、
前記導電性を平坦化する工程と、を有し、
前記平坦化する工程では、前記第1樹脂層領域の表面上に設けられた前記導電層の第1部分を少なくとも研磨し、前記凹部及び前記開口部に充填された前記導電性材料から形成される前記導電層の第2部分から前記配線層を形成する、
請求項1~11の何れか一項に記載の配線基板の製造方法。 - 前記支持体上に、前記内蔵配線層を少なくとも一層有する内蔵配線部を形成する工程を更に備え、
前記構造体を準備する工程は、当該内蔵配線部上に前記樹脂シートを貼り付けることにより取り付けを行い、前記構造体を準備する、
請求項1~12の何れか一項に記載の配線基板の製造方法。 - 前記配線層が形成された前記樹脂シートの上に別の樹脂シートを取り付ける工程と、
前記別の樹脂シートの第1樹脂層領域に対してレーザにより別の凹部を形成する工程と、
前記別の樹脂シートの表面から前記開口部の前記めっき金属層又は前記配線層に到る別の開口部を形成する工程と、
前記別の凹部及び前記別の開口部に別のめっき金属層を形成して別の配線層を形成する工程と、を更に備え、
前記別の樹脂シートを取り付ける工程、前記別の凹部を形成する工程、前記別の開口部を形成する工程、及び、前記別の配線層を形成する工程を少なくとも1回以上繰り返す、
請求項1~13の何れか一項に記載の配線基板の製造方法。 - 前記配線層を形成する工程は、
少なくとも前記開口部及び前記凹部に対してデスミア処理を行う工程と、
少なくとも前記開口部及び前記凹部に対して無電解めっきによりシード層を形成する工程と、
前記シード層上に電解めっきを施してめっき金属層を形成する工程と、
前記第1樹脂層領域の表面と前記シード層と前記めっき金属層とが平坦化するように前記第1樹脂層領域の表面上の前記シード層及び前記めっき金属層を除去する工程と、を有する、
請求項1~14の何れか一項に記載の配線基板の製造方法。 - 請求項1~15の何れか一項に記載の配線基板の製造方法によって製造される配線基板を準備する工程と、
前記配線層又は前記別の配線層上に半導体素子を実装し、前記半導体素子を前記配線層又は前記別の配線層に電気的に接続する工程と、
備える、半導体装置の製造方法。 - 請求項16に記載の製造方法を用いて製造される構造を有する、半導体装置。
- 請求項1~15の何れか一項に記載の配線基板の製造方法に使用される樹脂シートであって、外側に位置する第1樹脂層領域と、前記第1樹脂層領域より弾性率が高く内側に位置する高弾性層領域又はガラスクロスを有し内側に位置する高弾性層領域と、を備える樹脂シート。
- 前記第1樹脂層領域とは前記高弾性層領域を介して反対側に位置する第2樹脂層領域を更に備え、前記第2樹脂層領域が粘着性を有している、
請求項15に記載の樹脂シート。 - 前記第1樹脂層領域は、マレイミド化合物、ビスマレイミド化合物、トリアゾール化合物、ベンゾトリアゾール化合物、及び、ベンゾオキサゾール化合物からなる群から選ばれる少なくとも1つの化合物を含む、
請求項18又は19に記載の樹脂シート。 - 前記第1樹脂層領域は、黒鉛、グラフェン、カーボンナノチューブ、カーボンファイバー、カーボンブラック、フタロシアニン、シアニン、アルカリ土類金属、及び、金属錯体の少なくとも1つを含む、
請求項18~20の何れか一項に記載の樹脂シート。 - 前記第1樹脂層領域は、パラジウム粒子、パラジウム錯体、銅粒子、及び、銅錯体の少なくとも1つを含む、
請求項18~21の何れか一項に記載の樹脂シート。
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JPH0936522A (ja) * | 1995-07-14 | 1997-02-07 | Fuji Kiko Denshi Kk | プリント配線板における回路形成方法 |
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JP2011100796A (ja) * | 2009-11-04 | 2011-05-19 | Panasonic Electric Works Co Ltd | 回路基板 |
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