1291847 (1) 九、發明說明 【發明所屬之技術領域】 本發明係有關一種多層電路基板及其製造方、法。 【先前技術】 以往，舉出特開平1卜274 72 3號公報所揭示者爲例作 爲多層電路基板。該電路基板爲了提升導體配線層間之@ 孔孔連接的品値信賴性，藉由電鍍法以金屬導體塡充通子L 。根據該公報，這種電路基板係將絕緣層與導體配，線層$ 雙層形成設爲一循環，藉由反覆進行此之沉積法所製造。 然而，在該沉積法中，於中間循環中，於絕緣層或導 體配線層產生不良處所時，要僅除去其不良絕緣層或不良 導體配線層甚爲困難，迄今形成的良好絕緣層以及導體配 線層結果亦成爲廢棄，引起所謂浪費的問題。 避免這種問題的辦法有下述一體沖壓之製造法（「一 體沖壓法」）。在一體沖壓法中，首先，事先個別製造： 在具有以導體物質塡充的通孔之基板的兩面形成圖案之基 板（兩面基板）；以及具有以導體物質塡充之通孔的薄片（ 通孔薄片）。然後，交互重疊兩面基板與通孔薄片特定的 片數，在兩側重疊最外層用來形成電路之銅箔，一舉進行 沖壓（熱壓等），同時使之接著，然後以蝕刻法形成最外層 的電路，製造多層電路基板。 在一體沖壓法中，藉由預先檢查除掉不良基板、不良 薄片，由於僅使用檢查結束的基板以及薄片，因此在上述 -4 - 1291847 (2) 的中間循環不會產生所謂不良絕緣層或不良導體配線層， 可降低不良率以及製造成本。 藉由一體沖壓法製造的多層電路基板列舉有特開 . 2 0 0 1 - 7 5 3 0號公報所記載者。該電路基板係具有以導體塡 · 充的通孔之聚酯膠片（Prepreg)重疊在兩面電路基板的兩表 面上，進行熱壓所製造。 ^ --------然基板銅等的金屬塡充通 孔之聚酯膠片（Prepreg)進行熱壓時，金屬層間例如通孔的 φ 銅與電路圖案之連接不充分，使連接信賴性產生問題。 [發明內容】 [發明所欲解決之課題] 有鑒於上述情況，本發明之目的在於：可抑制不良率’ 且以低成本製造一種導體配線層（電路圖案）之通孔連接的 品質信賴性優良，且難以引起層間剝離之多層電路基板。 [周以解決課題之方案] 爲了解決上述課題，本發明者精闢的檢討結果，發現 ; 交互重疊電鍍塡充通孔的金屬之表面所製作的通孔薄片以 · 及電鍍電路圖案的表面所製作的圖案薄片特定片數之後’ 可達從該層積體的兩面整體進行熱壓之功效，可達成本發 明。 亦即，本發明提供一種多層電路基板，其係交互積層 有導體配線層，並介以貫通絕緣層之通孔，電性連接導體 1291847 (3) 配線層間’係以導體物質塡充通孔，且以合金使所塡充的 導體物質與導體配線層接合。 再者’本發明提供一種多層電路基板的製造方法，其 係藉由父互重豐需要數量之以下構件作爲層積體，且從層 積體的兩表面進行熱壓加以製造：通孔形成基材，係藉由 在絕緣基板形成通孔，以導體物質塡充通孔，使已塡充的 導體物質表面平坦化’且電鍍該已平坦化的表面所製作； 以及電路圖案形成基材，係藉由在絕緣基板進行電路圖案 用的開孔，在導體物質塡充電路圖案用孔，平坦化已塡充 的導體物質之表面以形成電路圖案，以上述電鍍與可生成 合金的金屬電鍍電路圖案表面所製作。 【實施方式】 以下，使用添附的圖面詳述本發明。 本發明之多層電路基板係交互積層有導體配線層（電 路圖案）與絕緣層。積層數沒有限定，依據期望適當選擇 。例如，第1圖係導體配線層5與6挾住絕緣層7而積層的三 層構造之多層電路基板。通孔4貫通絕緣層7，以導體物質 3塡充。藉由以導體物質3塡充通孔4，使導體配線層5與6 之間的通孔連接之品質信賴性提升。 如第1圖所示，例如在三層構造之本發明的多層電路 基板中，其特徵在於藉由合金1使導體物質3與導體配線層 5接合，且藉由合金2使導體物質3與導體配線層6接合。藉 此’在可確實使導體配線層5與6之間的通孔連接的同時， 1291847 (4) 使層間剝離強度提升。 這種本發明之多層電路基板係交互重疊需要數量之通 孔形成基材與電路圖案形成基材作爲層積體，藉由從層積 體的兩面熱壓而製造。例如，以如下所示之方法製造第1 圖所示之本發明的多層電路基板。 如第2圖所示，以如下之方式作成通孔形成基材1 2。 亦即，首先，在絕緣基板（絕緣層）7形成通孔4(第2圖a)。 亦可以單·一層基板、積層板任一種作爲絕緣基板7。積層 板可爲單一基材、複合基材之任一種構成。具體而言，絕 緣基板7係列舉有：由樹脂「酚醛樹脂、環氧樹脂、聚亞 醯胺、B T樹脂、聚酯、工程塑料（p p 〇、p p S等）」構成的 絕緣性塑膠膜（或是薄片）；將此等樹脂浸漬於補強劑（玻 璃布、紙等）者；以及此等的層積體。從薄片的強度、耐 熱性等觀點來看，以環氧樹脂、聚亞醯胺、工程塑料較爲 理想。 通孔4的形成：例如以雷射（C〇2雷射、Nd : YAG雷射 、YAG雷射、準分子雷射等）加工法；使用感光性絕緣材 料曝光、顯影之方法；電漿加工法；機械（通孔機、鑽孔 等）加工法；微影加工法；乾鈾刻加工法等進行亦可。從 生產性等的觀點來看，以使用感光性絕緣材料曝光、顯影 之方法最佳。 然後，以導體物質3塡充通孔4(第2圖b)。舉出金屬、 導體性組成物作爲導體物質3。金屬係有：金、銀、銅、 鎳、銦、錫、鉛、鋅等純金屬，或是此等合金（錫-銀、銲 -Ί - (5) 1291847 劑等）。導體組成物係舉出混練上述金屬的粉末與樹脂（環 氧樹脂、聚亞醯胺樹脂等）者等。導體物質3從導電性、成 本等觀點來看以銅最佳。 將金屬塡充入通孔4作爲導體物質3，可藉由濕式電鍍 法（電解電鍍、無電解電鍍等）、乾式電鍍法（蒸鍍、濺鍍 、噴鍍、銲劑覆蓋等）進行。從成本的觀點來看，以濕式 電鍍法最佳。 然後，平坦化所塡充的導體物質3之表面（第2圖c)。 藉由平坦化，可降低信號雜訊，使接著、氣泡的除去性等 良好。平坦化係藉由包含硏磨材（陶瓷等）、硏磨紙等之磨 光、刷洗、振動等機械硏磨等進行。 繼而，電鍍上述平坦化的表面，形成電鍍層]0、1 1 ( 第2圖d)。鍍著金屬係以上述導體物質3例示的金屬爲例 。具體而言，電鍍列舉有：合金鍍（銀-錫鍍、銲劑電鍍等 )、純金屬電鍍（錫鍍、銅電鍍等）。從連接信賴性的觀點 來看，以鎳-金鑛、銅電鍍最佳。表面電鍍係利用在上述 通孔4的肩充中例示的濕式電鍍法、乾式電鍍法等進行。 從成本的觀點來看以濕式電鍍法較佳。電鍍層1 0、1 1的m 鍍厚度例如以〇 . 〇 1至2 0 //較佳。 此外，電鍍層1 〇與1 1可進行一樣的電鍍或不一樣的電 鍍。例如進行無電解電鍍，可在電鍍層1 〇與1 1進行相同的 電鍍。又，若進行兩次電鍍，可在電鍍層1 0與1 1進行不同 的電鍍。 另外，電路圖案形成基材1 6如第3圖所示，以如下之 -8- 1291847 (6) 方式作成。亦即，首先在絕緣基板（絕緣層）8進行電路圖 案用的開孔，形成電路圖案用孔1 3 (第3圖a)。絕緣基板8 係以上述絕緣基板7爲例。開孔以與上述通孔4之形成相同 的方法進行亦可。 然後，以導體物質14塡充電路圖案用孔13(第3圖b)。 導體物質1 4以上述導體物質3爲例。塡充以與上述通孔4之 塡充相同的方法進行亦可。 繼而，平坦化所塡充的導體物質14之表面，形成電路 圖案（導體配線層）5(第3圖c)。藉由平坦化，可降低信號 的雜訊，使接著、阻抗整合、氣泡的除去性等變爲良好。 平坦化係以與上述導體物質3的表面之平坦化相同的方法 進行亦可。 然後，電鍍上述已平坦化的電路圖案表面，形成電鍍 層15(第3圖d)。鍍著金屬以及電鍍法係以電鍍層1〇、1 1爲 例。從氣泡的除去性等的觀點來看以鎳-金鍍、錫鍍較佳 〇 但是’電鑛層1 5的鑛者金屬如第4圖所不，在積層電 路圖案形成基材1 6與通孔形成基材1 2之際，可生成與電鍍 層1 5相對向接觸之導體物質3的表面電鍍層亦即電鍍層1 1 之鍍者金屬與合金。因而，電鍍層1 5之鍍著金屬與電鍍層 1 1之鍍著金屬必須以可生成合金之方式組合。這種電鍍組 合例如以金鍍與錫鍍、銲劑電鍍與錫鍍等爲例。 此外，在第3圖中，電路圖案形成基材1 6雖僅例示電 鍍單面之情況，但亦可進行兩面電鍍。僅電鍍單面可藉由 1291847 (7) 電解電鍍進行。或是其他方法，首先藉由無電解電鍍兩面 電鍍之後’以電鍍溶解劑（鹽酸、硝酸等）除去單面的電鍍 層亦可。 兩面電鍍係藉由無電解電鍍暫時進行。或是其他方法 ’首先僅電解電鍍一單面之後，電解或無電解電鍍進行另 一方的單面。此時，一方的單面電鍍與另一方的單面電鍍 亦可使用相同或不同的電鍍液。 如上所述’必須個別製作需要片數之通孔形成基材以 及電路圖案形成基材。例如，在第1圖的多層電路基板的 製造中，與電路圖案形成基材1 6相同，更製作由絕緣層9 、導體配線層6、以及電鍍層1 7構成的電路圖案形成基材 1 8 〇 繼而’父互重豐通孔形成基材]2以及電路圖案形成基 材1 6以及1 8作爲層積體。以從層積體的兩面挾住該層積體 之方式進行熱壓（第4圖）。熱壓係例如1 5 0至4 0 0 °C，以1 5 0 至3 5 0 °C較佳，特別藉由真空熱壓機等以1 5 0至3 0 0 °C進行 30至300分鐘。 藉由上述的熱壓，使電鍍層1 1與1 5接觸、熱擴散，形 成合金1。藉此，以合金1使通孔4之導體物質3與導體配線 層（電路圖案）5接合（第1圖）。同樣地，使電鍍層丨〇與I 7接 觸、熱擴散，形成合金2。藉此，以合金2使通孔4之導體 物質3與導體配線層（電路圖案）6接合（第1圖）。此外，電鍍 層〗〇、1 1、] 5、1 7若爲銲劑，則即使是低溫熱壓亦可進行 合金接合（亦即所謂的「銲接」）。 - 10- 1291847 (8) 再者，藉由上述的熱壓，絕緣層7、8、及9包含熱溶 融性（或熱反應性）樹脂時，由於此等樹脂亦接觸、熱溶融 (或熱反應），因此絕緣層7、8、及9亦爲一體連接。 以上的結果，本發明之多層電路基板由於確實使導體 配線層5與6之間的通孔連接，因此不僅電性連接信賴性高 ，層間剝離強度亦提升。 [實施例] 以下，使用添附圖面具體說明本發明。 實施例1 (通孔形成基材的製作） 如第5圖所示，在厚度1 0 0 //的不鏡鋼支持板].9上塗佈 下述感光型樹脂組成物]3，在8 0 °C下乾燥3 0分鐘，獲得厚 度50 //的塗膜（第5圖a)。使負掩模與乾燥塗膜20接觸，藉 由超高水銀燈以lOOOmj/cm2進行光照射。然後，使用有機 溶劑以2Kg/cm2的噴射壓對未曝光部進行1分鐘的顯影。 然後，在1 6 0 °C下進行1小時熱硬化，形成深度5 0 #的 通孔2 1 (第5圖b)。在通孔2 1進行約5 0 //的電性銅電鍍，以 銅22完全塡充通孔（第5圖c)。以支撐於支持板]9的狀態， 使用陶瓷磨光（Ceramic buff)，以負載電力1 .5安培硏磨銅 22的表面（第5圖d)。在硏磨後，使支持板19剝離（第5圖e) ’在以銅22埋設的通孔表面進行無電解錫鍍，在通孔表面 形成電鍍層23、24(電鍍厚度1 /〇 (第5圖f)。如此，製作 -11 - 1291847 Ο) 通孔形成基材亦即通孔薄片2 5。 1 )組成（重量部）：甲酚（C r e s ο 1)酚醛（N 〇 v 〇 1 a c)樹脂型 環氧樹脂100、苯酚（Phenol )酚醛（Νονοί ac)樹脂9 〇、鎏 鹽系光陽離子催化聚合開始劑3 0、2 -乙基-9，1 〇 -二甲基經 基乙氧基蒽3 0、硫酸鋇1 〇 〇、消泡劑1、溶劑丨0 〇。 (電路圖案形成基材的製作） 如第6圖所示，在厚度1 Q 〇 μ的不銹鋼支持板丨9上塗佈 上述感光型樹脂組成物，在8 0 °C下乾燥3 0分鐘，獲得厚度 5〇 //的塗膜（第6圖a)。使負掩模與乾燥塗膜26接觸，藉由 超高水銀燈以1 0 0 0 mj / c m2進行光照射。然後，使用有機溶 劑以2Kg/cm2的噴射壓對未曝光部進行1分鐘的顯影。 然後，在1 6 0 °C下進行1小時熱硬化，形成深度5 0 //的 電路圖案用孔2 7 (第6圖b )。在電路圖案用孔2 7進行電鍍厚 度約5 0 //的電性銅電鍍，以銅電鍍2 8完全塡充電路圖案用 孔2 7 (第6圖〇。以支撐於支持板1 9之狀態，使用陶瓷磨 光’以負載電力1 .5安培硏磨銅電鍍28的表面，形成電路 圖案29(第6圖d)。以支撐於支持板19之狀態，進行電解 錬-金鑛（接合金鑛），對電路圖案2 9的一方之表面進彳了接 合金鍍3 0 (電鍍厚度]〇 /〇(第6圖e)。然後，使支持板1 9 剝離（弟6圖f )，在電路圖案2 9的另一方表面進行無電解錫 鍍3 1(電鍍厚度1 v )(第6圖g)，製作電路圖案形成基材亦 即圖案薄片3 2。 - 12 - 1291847 (10) 同樣地，單面進行無電解金鑛34，另一方之單面由進 行接合金鑛3 5之電路圖案3 3與塗膜3 6所構成的圖案薄片3 7 (多層電路基板的製造） 如第7圖所示，接合金鍍層30與3 5以進入表面側的方 式利用圖案薄片32與3 7挾住通孔薄片25，使用真空壓力機 ，以200 °C進行120分鐘之加熱壓縮。如此，以合金38使電 路圖案29與通孔的塡充銅22接合，以合金39使通孔的塡充 銅22與電路圖条33接合’且製造兩表面具有接合金鑛層30 與3 5之構造的本發明之多層電路基板（兩面印刷配線板）（ 第8圖）。 實施例2 (通孔形成基材的製作） 如第9圖所示，在厚度1 0 0 //的不銹鋼支持板1 9上塗佈 下述感光型樹脂組成物2)，在160 °C下熱硬化60分鐘，獲 得厚度50 μ的塗膜40(第9圖a)。在硬化塗膜40使用碳酸氣 體雷射，形成深度5 0 μ的通孔4 1 (第9圖b)。在通孔4 1進行 電鍍厚約50 //的電性銅電鍍，通孔完全被銅42塡充（第9圖 c)。以支撐在支持板1 9的狀態，使用陶瓷磨光，以負載電 力1 ·5安培硏磨銅42的表面（第9圖d)。在硏磨後，使使支 持板1 9剝離（第9圖e)，在以銅42塡充之通孔表面進行無電 解錫鍍，在通孔表面形成電鍍4 3、4 4 (電鍍厚度]")(第9 -13 - 1291847 (11) 圖f)。如此，製作通孔形成基材亦即圖案薄片45。 2 )組成（重量部）：甲 ( C r e s ο 1)酿醒（N 〇 v ο 1 a c )樹脂型 環氧樹脂100、苯酚（Phenol )酚醛（Novolac)樹脂90、三 苯膦（TRIPHENYLPHOSPHINE ) 1、硫酸鋇 1 00、消泡齊丨j ] 、溶劑1 0 0。 (電路圖案形成基材的製作） 如第1 〇圖所示，在厚度1 0 0 //的不銹鋼支持板1 9上塗 佈上述感光型樹脂組成物，在1 6 0 °C下熱硬化6 0分鐘，獲 得厚度30//的塗膜（第10圖a)。在硬化塗膜46使用碳酸氣 體雷射，形成厚度30//的電路圖案用孔47 (第10圖b)。在 電路圖案用孔4 7進行電鍍厚度約5 0 //的電性銅電鍍，電路 圖案用孔47完全被銅電鍍48塡充（第10圖〇。以支撐於支 持板1 9之狀態，使用陶瓷磨光，以負載電力1 . 5安培硏磨 銅電鍍48的表面，形成電路圖案49(第10圖d)。然後，使 支持板19剝離（第10圖e)，在電路圖案49的表面進行無電 解鎳-金鍍，形成電鍍50、51(電鍍厚度1 // )(第10圖f)。 如此，製作電路圖案形成基材亦即圖案薄片5 7。 同樣地，由具有表面電鍍層54、55之電路圖案53與塗 膜5 6構成，且形成成爲多層電路基板的背面之電路的圖案 片52(第1 1圖）。 (多層電路基板的製造） 如第1 1圖所示，以圖案薄片52與5 7挾住通孔薄片45， -14 - 1291847 (12) 使用真空壓力機，在2 0 0 °C下進行]20分鐘之加熱壓縮。如 此，製造以合金58使電路圖案49與通孔的塡充銅42接合， 且以合金5 9使通孔的塡充銅4 2與電路圖案5 3接合之構造的 本發明之多層電路基板（兩面印刷配線板）（第12圖）。 實施例3 (通孔形成基材的製作） 在與實施1相同的不銹鋼支持板上黏貼熱硬化型p p E 薄膜，使用真空壓力機在2 0 0。(：下熱硬化2小時。然後，與 實施例1相同，形成通孔，在硏磨之後，使支持板剝離， 進行無電解錫-銀合金鍍（電鍍厚度1 Α )，製作通孔薄片。 (電路圖案形成基材的製作） 與實施例1完全相同，製作2片具有厚度3 0 //的電路圖 案之圖案薄片。 (多層電路基板的製造） 與實施例1相同，以兩片圖案薄片挾住通孔薄片，使 用真空充壓機下220 °C下進行120分鐘之加熱壓縮，製造本 發明之多層電路基板（兩面印刷配線板）。 [發明的功效] 本發明之多層電路基板係合金接合有通孔與導體配線 層。結果，電路圖案（導體配線層）間的通孔連接之品質信 -15 - 1291847 (13) 賴性優良，且不易引起層間剝離。 再者，本發明之多層電路基板由於不需形成穿孔，因 此可以CAD進行自動配線。結果，可縮短設計時間。 本發明之多層電路基板將絕緣材料設爲相同。結果， 容易取得阻抗總合，容易進行模擬。 本發明之多層電路基板由於可總合電鍍設爲電性銅電 鍍’因此可降低電性電阻。結果，容易取得阻抗總合，容 易進行模擬。 本發明之多層電路基板由於在絕緣層可使用薄膜，因 此可使絕緣層厚度更爲穩定。結果，容易取得阻抗總合， 谷易進彳了模擬。 本發明之多層電路基板由於一般電路圖案表面未粗化 °結果’容易取得阻抗總合，容易進行模擬。 根據本發明之多層電路基板的製造法，可以總括沖壓 形成多層化。結果，抑制不良率並以低成本製造多層電路 基板。 根據本發明之多層電路基板的製造法，由於開孔不使 用Μ刻’故電路圖案形狀穩定性優良。結果阻抗穩定性佳 ’可高頻對應。 根據本發明之多層電路基板的製造法，由於僅以總括 沖壓進行多層化，故可製作在兩表面具有接合金鍍之基板 〇 根據本發明之多層電路基板的製造法，可在同一製造 衣置進行通孔薄片的製作與圖案薄片的製作。結果，使製 -16- 1291847 (14) 造裝置的種類變少，可降低成本。 根據本發明之多層電路基板的製造法，可平坦化已完 成的多層電路基板之表面。結果，使銲料抗蝕劑（S R)之形 成或安裝變爲容易。 根據本發明之多層電路基板的製造法，可製造基板表 面僅設爲安裝平面（land)之多層電路基板。結果不需要銲 料抗蝕劑，可防止與步驟銷減、銲料抗蝕劑有關的不良狀 況發生等，更可降低成本。 根據本發明之多層電路基板的製造法，在製造通孔薄 片後，雷射加工需要的部份，並且開孔，亦可內藏電阻或 電容器等被動元件。 [圖式簡單說明】 第1圖係本發明之多層電路基板的剖面構造。 第2圖係通孔形成基材的製作步驟。 第3圖係電路圖案形成基材的製作步驟。 第4圖係以電路圖案形成基材挾住通孔形成基材進行 熱壓之際的樣態。 第5圖係實施例1的通孔形成基材的製作步驟。 第6圖係實施例1的電路圖案形成基材之製作步驟。 第7圖係實施例1以電路圖案形成基材挾住通孔形成基 材進行熱壓之際的樣態。 第8圖係實施例1之本發明的多層電路基板之剖面構造 -17 - 1291847 (15) 第9圖係實施例2之通孔形成基材的製作步驟。 第]0圖係實施例2之電路圖案形成基材的製作步驟。 第1 1圖係實施例2之以電路圖案形成基材挾住通孔形 成基材進行熱壓之際的樣態。 第1 2圖係實施例2之本發明的多層電路基板之剖面構 造。 【主要元件符號說明】 1，2，3 8，3 9，5 8，5 9 :合金 3，1 4,22,28,42,4 8 :導體物質 4,21，41 :通孔 5.6.2 9,3 3,49,5 3 :導體配線層（電路圖案） 7,859 :絕緣層 1 〇，1 1 5 1 5，1 7 :電鍍層 1 2,2 5,45 :通孔形成基材（通孔薄片） 1352 7,47:電路圖案用孔 16518,32,37,52,57:電路圖案形成基材（圖案薄片） 1 9 :不錄鋼支持板 20.2 6,36,40,46,56:塗膜 3G，35 :接合金鍍 23,24;43,44 :錫鍍 :金鍍 5〇,51，5 4,5 5 :鎳-金鍍 -18 -1291847 (1) Description of the Invention [Technical Field] The present invention relates to a multilayer circuit substrate and a method and method for manufacturing the same. [Prior Art] A multilayer circuit board has been exemplified as disclosed in Japanese Laid-Open Patent Publication No. 274 72-3. In order to improve the reliability of the @via connection between the conductor wiring layers, the circuit substrate is filled with a metal conductor by a plating method. According to this publication, such a circuit board is formed by disposing an insulating layer and a conductor, and forming a double layer of the line layer in a cycle, which is produced by repeating the deposition method. However, in the deposition method, in the intermediate cycle, when the insulating layer or the conductor wiring layer is defective, it is difficult to remove only the poor insulating layer or the poor conductor wiring layer, and the good insulating layer and the conductor wiring formed so far. The result of the layer has also become obsolete, causing the problem of so-called waste. The method for avoiding such a problem is the one-piece stamping manufacturing method described below ("one-body stamping method"). In the integrated press method, first, a substrate (a double-sided substrate) having a pattern formed on both sides of a substrate having a via hole filled with a conductor material; and a sheet having a through hole filled with a conductor material (through hole) Sheet). Then, the overlapping number of the two-sided substrate and the through-hole sheet is overlapped, and the outermost layer is used to form a copper foil for the circuit on both sides, and is stamped (hot pressed, etc.) in one go, and then, and then the outermost layer is formed by etching. The circuit manufactures a multilayer circuit substrate. In the integrated press method, by removing the defective substrate and the defective sheet in advance, since only the substrate and the sheet which have been inspected are used, there is no so-called defective insulating layer or defective in the middle of the above -4 - 1291847 (2). The conductor wiring layer can reduce the defect rate and manufacturing cost. The multilayer circuit board manufactured by the integral press method is exemplified in the publication of the Japanese Patent Publication No. 2000-75. This circuit board is manufactured by laminating a prepreg having a through hole filled with a conductor 重叠 on both surfaces of a double-sided circuit board. ^ -------- When the prepreg of the metal enamel-filled hole such as the substrate copper is hot-pressed, the connection between the metal layers such as the through-hole φ copper and the circuit pattern is insufficient, so that the connection is trusted. Sexuality creates problems. [Problems to be Solved by the Invention] In view of the above, an object of the present invention is to improve the quality reliability of a through-hole connection in which a conductor wiring layer (circuit pattern) can be manufactured at a low cost by suppressing a defective rate. And a multilayer circuit substrate which is difficult to cause interlayer peeling. [Solution to Solve the Problem] In order to solve the above problems, the inventors of the present invention have found that the through-hole sheets prepared by alternately plating the surface of the metal filled with the via holes are formed on the surface of the plating circuit pattern. After the specific number of sheets of the pattern sheet, the effect of hot pressing from both sides of the layered body can be achieved, and the invention can be achieved. That is, the present invention provides a multilayer circuit substrate in which a conductor wiring layer is alternately laminated and through a through hole penetrating through the insulating layer, and the electrical connection conductor 1291847 (3) is electrically connected to the via hole by a conductor material. Further, the conductor material to be charged is bonded to the conductor wiring layer by an alloy. Furthermore, the present invention provides a method for manufacturing a multilayer circuit substrate which is manufactured by laminating a required number of members as a laminate and heat-pressing from both surfaces of the laminate: via-forming base The material is formed by forming a through hole in an insulating substrate, filling a through hole with a conductor material, planarizing a surface of the charged conductor material, and plating the flattened surface; and forming a substrate by a circuit pattern By performing an opening for the circuit pattern on the insulating substrate, the surface of the charged conductor material is planarized in the conductor material 塡 charging path pattern hole to form a circuit pattern, and the metal plating circuit pattern capable of forming an alloy is formed by the above plating Made on the surface. [Embodiment] Hereinafter, the present invention will be described in detail using the attached drawings. The multilayer circuit substrate of the present invention is alternately laminated with a conductor wiring layer (circuit pattern) and an insulating layer. The number of layers is not limited and is appropriately selected according to expectations. For example, the first figure is a multilayer circuit board having a three-layer structure in which the conductor wiring layers 5 and 6 are sandwiched by the insulating layer 7. The through hole 4 penetrates through the insulating layer 7 and is filled with the conductor material 3. By filling the vias 4 with the conductor material 3, the quality reliability of the via connection between the conductor wiring layers 5 and 6 is improved. As shown in Fig. 1, for example, in the multilayer circuit substrate of the present invention having a three-layer structure, the conductor material 3 is bonded to the conductor wiring layer 5 by the alloy 1, and the conductor material 3 and the conductor are made by the alloy 2. The wiring layer 6 is bonded. By this, while the through holes between the conductor wiring layers 5 and 6 can be surely connected, 1291847 (4) improves the interlayer peel strength. The multilayer circuit substrate of the present invention is formed by laminating a plurality of via-forming substrate and circuit pattern forming substrate as a laminate, which is produced by hot pressing from both sides of the laminate. For example, the multilayer circuit substrate of the present invention shown in Fig. 1 is produced by the method shown below. As shown in Fig. 2, the through hole forming substrate 12 was formed in the following manner. That is, first, the through hole 4 is formed in the insulating substrate (insulating layer) 7 (Fig. 2a). Any one of a single substrate or a laminate may be used as the insulating substrate 7. The laminate can be composed of either a single substrate or a composite substrate. Specifically, the insulating substrate 7 is an insulating plastic film composed of a resin "phenolic resin, epoxy resin, polyamidoamine, BT resin, polyester, engineering plastics (pp 〇, pp S, etc.)" Or a sheet); such a resin is immersed in a reinforcing agent (glass cloth, paper, etc.); and such a laminate. From the viewpoints of the strength and heat resistance of the sheet, epoxy resin, polyamine, and engineering plastics are preferable. Formation of the through hole 4: for example, laser (C〇2 laser, Nd: YAG laser, YAG laser, excimer laser, etc.) processing method; exposure and development using photosensitive insulating material; plasma processing Method; mechanical (through hole machine, drilling, etc.) processing method; lithography processing method; dry uranium engraving processing method can also be carried out. From the viewpoint of productivity and the like, the method of exposure and development using a photosensitive insulating material is optimal. Then, the via hole 4 is filled with the conductor material 3 (Fig. 2b). A metal or a conductive composition is used as the conductor material 3. Metals are: pure metals such as gold, silver, copper, nickel, indium, tin, lead, zinc, or these alloys (tin-silver, solder-Ί-(5) 1291847, etc.). The conductor composition is a mixture of a powder of the above metal and a resin (epoxy resin, polyamine resin, etc.). The conductor material 3 is preferably copper in terms of conductivity, cost, and the like. The metal crucible is filled in the through hole 4 as the conductor material 3, and can be carried out by a wet plating method (electrolytic plating, electroless plating, or the like) or a dry plating method (evaporation, sputtering, sputtering, flux coating, or the like). From the viewpoint of cost, the wet plating method is the best. Then, the surface of the charged conductor material 3 is planarized (Fig. 2c). By flattening, signal noise can be reduced, and the subsequent removal of bubbles can be improved. The flattening is performed by mechanical honing such as polishing, brushing, vibration, etc., including honing materials (ceramics, etc.), honing paper, and the like. Then, the planarized surface is plated to form a plating layer of 0, 1 1 (Fig. 2 d). The plated metal is exemplified by the metal exemplified as the conductor material 3 described above. Specifically, plating is performed by alloy plating (silver-tin plating, flux plating, etc.), pure metal plating (tin plating, copper plating, etc.). From the viewpoint of connection reliability, nickel-gold ore and copper plating are the best. The surface plating is performed by a wet plating method, a dry plating method, or the like exemplified in the shoulder filling of the through hole 4. The wet plating method is preferred from the viewpoint of cost. The m plating thickness of the plating layer 10, 1 1 is, for example, 〇 1 to 2 0 // preferably. In addition, the plating layer 1 〇 can be plated or not plated the same as 1 1 . For example, electroless plating is performed, and the same plating can be performed on the plating layer 1 1 and 1 1 . Further, if plating is performed twice, different plating can be performed on the plating layers 10 and 11. Further, as shown in Fig. 3, the circuit pattern forming substrate 16 is formed as follows - 8 - 1291847 (6). In other words, first, an opening for a circuit pattern is formed on an insulating substrate (insulating layer) 8, and a hole 1 3 for circuit pattern is formed (Fig. 3a). The insulating substrate 8 is exemplified by the above-described insulating substrate 7. The opening may be performed in the same manner as the above-described formation of the through hole 4. Then, the conductive material pattern hole 13 is formed by the conductor material 14 (Fig. 3b). The conductor substance 14 is exemplified by the conductor material 3 described above. The charging may be performed in the same manner as the charging of the through holes 4 described above. Then, the surface of the conductor material 14 to be filled is planarized to form a circuit pattern (conductor wiring layer) 5 (Fig. 3c). By flattening, the noise of the signal can be reduced, and the subsequent integration, impedance integration, bubble removal, and the like can be improved. The flattening may be performed in the same manner as the planarization of the surface of the conductor material 3 described above. Then, the surface of the above-described planarized circuit pattern is plated to form a plating layer 15 (Fig. 3D). The plating metal and the plating method are exemplified by the plating layers 1 and 11. From the viewpoint of the removal property of the bubbles, etc., it is preferable to use nickel-gold plating or tin plating, but the mineralizer metal of the electric ore layer 15 is as shown in Fig. 4, and the substrate pattern 16 is formed in the laminated circuit pattern. When the hole forms the substrate 12, a surface plating layer of the conductor material 3 which is in contact with the plating layer 15, that is, a plated metal and an alloy of the plating layer 1 can be formed. Therefore, the plated metal of the plating layer 15 and the plated metal of the plating layer 1 must be combined in such a manner as to form an alloy. Such a plating combination is exemplified by gold plating and tin plating, flux plating, and tin plating. Further, in Fig. 3, the circuit pattern forming substrate 16 is exemplified by only one side of the electroplated plate, but may be plated on both sides. Only one side of the plating can be performed by electrolytic plating of 1291847 (7). Alternatively, it is also possible to first remove the plating layer of one side by electroplating with a solvent (hydrochloric acid, nitric acid, etc.) after electroless plating on both sides. The two-sided plating is temporarily performed by electroless plating. Or other methods' First, after electroplating a single side, electrolysis or electroless plating is performed on the other side. In this case, the same or different plating solutions may be used for one side plating and the other single side plating. As described above, it is necessary to separately form a through-hole forming substrate and a circuit pattern forming substrate which are required to have a number of sheets. For example, in the manufacture of the multilayer circuit substrate of Fig. 1, the circuit pattern forming substrate 18 composed of the insulating layer 9, the conductor wiring layer 6, and the plating layer 17 is formed in the same manner as the circuit pattern forming substrate 16. Then, the 'parent mutual weight through hole forming substrate 2' and the circuit pattern forming substrates 1 6 and 18 are used as a laminate. Hot pressing is performed so as to cover the laminate from both sides of the laminate (Fig. 4). The hot pressing system is, for example, 150 to 400 ° C, preferably 150 to 350 ° C, particularly 30 to 300 ° C at a temperature of 150 to 300 ° C by a vacuum hot press or the like. . The plating layer 11 is brought into contact with and thermally diffused by the above-described hot pressing to form the alloy 1. Thereby, the conductor material 3 of the through hole 4 is bonded to the conductor wiring layer (circuit pattern) 5 by the alloy 1 (Fig. 1). Similarly, the plating layer is brought into contact with I 7 and thermally diffused to form alloy 2. Thereby, the conductor material 3 of the via hole 4 is bonded to the conductor wiring layer (circuit pattern) 6 by the alloy 2 (Fig. 1). Further, if the plating layers 1, 1, 1 , 5, and 17 are fluxes, alloy bonding (so-called "welding") can be performed even at a low temperature hot pressing. - 10- 1291847 (8) Further, when the insulating layers 7, 8, and 9 contain a heat-fusible (or thermally reactive) resin by the above-described hot pressing, since the resins are also in contact with each other, heat is melted (or heat). The reaction), therefore, the insulating layers 7, 8, and 9 are also integrally connected. As a result of the above, since the multilayer circuit board of the present invention is surely connected to the through holes between the conductor wiring layers 5 and 6, the electrical connection reliability is high and the interlayer peeling strength is also improved. [Examples] Hereinafter, the present invention will be specifically described using the accompanying drawings. Example 1 (Production of Through Hole Forming Substrate) As shown in Fig. 5, the following photosensitive resin composition 3 was applied to a non-mirror steel support plate of a thickness of 1.00], at 8 After drying at 0 ° C for 30 minutes, a coating film having a thickness of 50 // was obtained (Fig. 5 a). The negative mask was brought into contact with the dried coating film 20, and light irradiation was performed at 1000 mj/cm2 by an ultrahigh mercury lamp. Then, the unexposed portion was developed for 1 minute using an organic solvent at a jet pressure of 2 kg/cm2. Then, it was thermally hardened at 1 60 ° C for 1 hour to form a through hole 2 1 having a depth of 50 # (Fig. 5b). Electrical copper plating of about 50 // is performed in the via hole 2 1 to completely fill the via hole with the copper 22 (Fig. 5 c). The surface of the copper 22 was honed with a ceramic buff in a state of being supported by the support plate 9 (Fig. 5 d) using a ceramic buff. After the honing, the support plate 19 is peeled off (Fig. 5 e) 'electroless tin plating is performed on the surface of the via hole buried in the copper 22, and plating layers 23 and 24 are formed on the surface of the via hole (plating thickness 1 / 〇 (first 5 Figure f). Thus, the -11 - 1291847 制作) through-hole forming substrate, that is, the through-hole sheet 25 is produced. 1) Composition (weight portion): cresol (C res ο 1) phenolic (N 〇v 〇 1 ac) resin type epoxy resin 100, phenol (Phenol) phenolic (Νονοί ac) resin 9 〇, strontium salt photocation Catalytic polymerization initiator 30, 2-ethyl-9,1 〇-dimethylperoxy ethoxy hydrazine 3 0, cesium sulfate 1 〇〇, defoaming agent 1, solvent 丨0 〇. (Production of circuit pattern forming substrate) As shown in Fig. 6, the photosensitive resin composition was applied onto a stainless steel support plate 9 having a thickness of 1 Q 〇μ, and dried at 80 ° C for 30 minutes to obtain A coating film having a thickness of 5 〇// (Fig. 6 a). The negative mask was brought into contact with the dried coating film 26, and light irradiation was performed at 1000 mj / c m2 by an ultrahigh mercury lamp. Then, the unexposed portion was developed for 1 minute using an organic solvent at a jet pressure of 2 kg/cm2. Then, it was thermally cured at 1 60 ° C for 1 hour to form a circuit pattern hole 2 7 having a depth of 50 // (Fig. 6b). Electrode copper plating having a plating thickness of about 50 // is performed in the circuit pattern hole 27, and the copper plating plate is used to form a hole for the charging circuit pattern 2 7 (Fig. 6) to support the state of the support plate 19. The surface of the copper plating 28 is honed by a ceramic polishing 'with a load of 1.5 amps to form a circuit pattern 29 (Fig. 6 d). The electrolytic bismuth-gold ore (joining gold) is carried out in a state of being supported by the support plate 19. Mine), the surface of one of the circuit patterns 29 is joined with gold plating 3 0 (plating thickness) 〇 / 〇 (Fig. 6 e). Then, the support plate 1 9 is peeled off (different 6 Fig. f), The other surface of the circuit pattern 298 is subjected to electroless tin plating 31 (plating thickness 1 v ) (Fig. 6 g), and a circuit pattern forming substrate, that is, a pattern sheet 3 2 is produced. - 12 - 1291847 (10) The electroless gold ore 34 is performed on one side, and the pattern sheet 3 7 (manufacture of the multilayer circuit substrate) composed of the circuit pattern 3 3 and the coating film 36 which are bonded to the gold ore 3 is formed on one side (Fig. 7) As shown, the gold plating layers 30 and 35 are joined to the through-hole sheet 25 by the pattern sheets 32 and 37 in such a manner as to enter the surface side, using a vacuum press to 20 Heating compression is performed for 120 minutes at 0 ° C. Thus, the circuit pattern 29 is bonded to the via copper 22 of the via hole by the alloy 38, and the copper 29 of the via hole is bonded to the circuit strip 33 by the alloy 39' and both surfaces are fabricated. A multilayer circuit board (double-sided printed wiring board) of the present invention having a structure in which gold ore layers 30 and 35 are joined (Fig. 8). Example 2 (Production of via-forming substrate) As shown in Fig. 9, The following photosensitive resin composition 2) was applied to the stainless steel support plate 19 having a thickness of 1.00, and thermally cured at 160 ° C for 60 minutes to obtain a coating film 40 having a thickness of 50 μ (Fig. 9 a). A through-hole 4 1 having a depth of 50 μ is formed on the hard coat film 40 using a carbon dioxide gas laser (Fig. 9b). Electro-copper plating is performed on the through-hole 4 1 to a thickness of about 50 //, and the through-hole is completely Copper 42 塡 (Fig. 9c). In the state of supporting the support plate 19, the surface of the copper 42 is rubbed with a ceramic polishing force at a load of 1 · 5 amps (Fig. 9 d). So that the support plate 19 is peeled off (Fig. 9 e), electroless tin plating is performed on the surface of the through hole filled with copper 42, and plating is formed on the surface of the through hole 4 3, 4 4 (plating thickness) & qu Ot;) (9-13 - 1291847 (11) Figure f). Thus, a through-hole forming substrate, that is, a pattern sheet 45 is formed. 2) Composition (weight portion): A (C res ο 1) waking up (N 〇v ο 1 ac ) resin type epoxy resin 100, phenol (Phenol) phenolic (Novolac) resin 90, triphenylphosphine (TRIPHENYLPHOSPHINE) 1, barium sulfate 100, defoaming j], solvent 100. (Production of Circuit Pattern Forming Substrate) As shown in Fig. 1, the photosensitive resin composition was applied onto a stainless steel support plate 19 having a thickness of 1.00, and thermally cured at 160 °C. At 0 minutes, a coating film having a thickness of 30// was obtained (Fig. 10a). A carbonaceous gas laser is used in the hard coat film 46 to form a circuit pattern hole 47 having a thickness of 30// (Fig. 10b). Electrical copper plating having a plating thickness of about 50 // is performed in the circuit pattern hole 47, and the circuit pattern hole 47 is completely filled with copper plating 48 (Fig. 10). It is supported by the support plate 19 and used. The ceramic is polished, and the surface of the copper plating 48 is honed by a load of 1.5 amps to form a circuit pattern 49 (Fig. 10d). Then, the support plate 19 is peeled off (Fig. 10e), on the surface of the circuit pattern 49. Electroless nickel-gold plating is performed to form electroplating 50, 51 (plating thickness 1 //) (Fig. 10 f). Thus, a circuit pattern forming substrate, that is, a pattern sheet 57 is formed. Similarly, a surface plating layer is provided. The circuit pattern 53 of 54 and 55 is formed of a coating film 56, and a pattern sheet 52 (FIG. 1) which is a circuit on the back surface of the multilayer circuit board is formed. (Manufacturing of a multilayer circuit board) As shown in FIG. The through-hole sheet 45 is held by the pattern sheets 52 and 57, and -14 - 1291847 (12) is heated and compressed at 200 ° C for 20 minutes using a vacuum press. Thus, the circuit pattern is made with the alloy 58 49 is bonded to the via copper 42 of the via hole, and the copper 5 2 of the via hole is bonded to the circuit pattern 53 by the alloy 5 9 The multilayer circuit board of the present invention (two-sided printed wiring board) (Fig. 12). Example 3 (Production of through-hole forming substrate) A thermosetting type pp E film was adhered to the same stainless steel supporting plate as in the first embodiment. Using a vacuum press at 200 ° (:: heat hardening for 2 hours. Then, as in Example 1, a through hole was formed, and after the honing, the support plate was peeled off, and electroless tin-silver alloy plating (plating thickness) was performed. 1 Α ), a via sheet was produced. (Production of circuit pattern forming substrate) Two pattern sheets having a circuit pattern having a thickness of 3 // were produced in the same manner as in Example 1. (Manufacturing of Multilayer Circuit Board) and Implementation In the same manner as in Example 1, the through-hole sheet was sandwiched between two sheets of the pattern, and the multilayer circuit substrate (two-sided printed wiring board) of the present invention was produced by heating and compression at 220 ° C for 120 minutes using a vacuum filling machine. The multilayer circuit board of the present invention is characterized in that a through hole and a conductor wiring layer are bonded to each other. As a result, the quality of the through-hole connection between the circuit patterns (conductor wiring layers) is excellent, and it is not easy to be used. Further, since the multilayer circuit board of the present invention does not need to form perforations, it can be automatically wired by CAD. As a result, the design time can be shortened. The multilayer circuit board of the present invention has the same insulating material. As a result, it is easy to obtain. Since the impedance of the multilayer circuit board of the present invention can be electrically plated by electroplating, the electrical resistance can be reduced. As a result, the impedance is easily obtained and the simulation can be easily performed. Since the substrate can use a film in the insulating layer, the thickness of the insulating layer can be made more stable. As a result, it is easy to obtain the total impedance, and Gu Yijin has simulated. In the multilayer circuit board of the present invention, since the surface of the general circuit pattern is not roughened, the result is easy to obtain the total impedance, and the simulation is easy. According to the method of manufacturing a multilayer circuit substrate of the present invention, it is possible to collectively form a multilayer into a stamp. As a result, the defective ratio is suppressed and the multilayer circuit substrate is manufactured at low cost. According to the method of manufacturing a multilayer circuit substrate of the present invention, since the opening is not used, the shape of the circuit pattern is excellent in stability. As a result, the impedance stability is good. According to the manufacturing method of the multilayer circuit substrate of the present invention, since the multilayering is performed only by the collective stamping, the substrate having the gold plating on both surfaces can be produced. The manufacturing method of the multilayer circuit substrate according to the present invention can be made in the same manufacturing apparatus. Fabrication of through-hole sheets and production of pattern sheets. As a result, the number of devices manufactured by the -16-1291847 (14) is reduced, and the cost can be reduced. According to the method of manufacturing a multilayer circuit substrate of the present invention, the surface of the completed multilayer circuit substrate can be planarized. As a result, the formation or mounting of the solder resist (S R) becomes easy. According to the method of manufacturing a multilayer circuit substrate of the present invention, it is possible to manufacture a multilayer circuit substrate in which the surface of the substrate is only a mounting land. As a result, the solder resist is not required, and it is possible to prevent the occurrence of defects associated with the step reduction, the solder resist, and the like, and the cost can be reduced. According to the manufacturing method of the multilayer circuit substrate of the present invention, after the through-hole film is manufactured, the laser processing requires a portion, and the opening is also provided with a passive component such as a resistor or a capacitor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structure of a multilayer circuit substrate of the present invention. Fig. 2 is a manufacturing step of a through hole forming substrate. Fig. 3 is a manufacturing step of a circuit pattern forming substrate. Fig. 4 is a view showing a state in which a substrate pattern is formed by a circuit pattern and a through hole is formed to form a substrate for hot pressing. Fig. 5 is a manufacturing step of the through hole forming substrate of Example 1. Fig. 6 is a view showing the steps of fabricating the circuit pattern forming substrate of the first embodiment. Fig. 7 is a view showing a state in which a substrate pattern is formed by a circuit pattern forming a substrate and a through hole is formed to form a substrate for hot pressing. Fig. 8 is a sectional view showing the structure of the multilayer circuit substrate of the present invention in the first embodiment. -17 - 1291847 (15) Fig. 9 is a manufacturing step of the through hole forming substrate of the second embodiment. Fig. 0 is a manufacturing step of the circuit pattern forming substrate of the second embodiment. Fig. 1 is a view showing a state in which the circuit pattern forming substrate is caught in the through hole and the substrate is subjected to hot pressing in the second embodiment. Fig. 12 is a cross-sectional structure of the multilayer circuit substrate of the present invention in the second embodiment. [Main component symbol description] 1,2,3 8,3 9,5 8,5 9 : Alloy 3,1 4,22,28,42,4 8 : Conductor material 4,21,41 : Through hole 5.6.2 9,3 3,49,5 3 : Conductor wiring layer (circuit pattern) 7,859: insulating layer 1 〇, 1 1 5 1 5, 1 7 : plating layer 1 2, 2 5, 45 : through hole forming substrate (pass Hole sheet) 1352 7, 47: Holes for circuit pattern 16518, 32, 37, 52, 57: Circuit pattern forming substrate (pattern sheet) 1 9 : Unrecorded steel support plate 20.2 6, 36, 40, 46, 56: Coating film 3G, 35: Bonded gold plating 23, 24; 43, 44: Tin plating: Gold plating 5 〇, 51, 5 4, 5 5 : Nickel-gold plating -18 -