WO2022070317A1 - 炭化珪素半導体装置の製造方法、炭化珪素半導体装置および電力変換装置の製造方法 - Google Patents

炭化珪素半導体装置の製造方法、炭化珪素半導体装置および電力変換装置の製造方法 Download PDF

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WO2022070317A1
WO2022070317A1 PCT/JP2020/037178 JP2020037178W WO2022070317A1 WO 2022070317 A1 WO2022070317 A1 WO 2022070317A1 JP 2020037178 W JP2020037178 W JP 2020037178W WO 2022070317 A1 WO2022070317 A1 WO 2022070317A1
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Prior art keywords
trench
silicon carbide
carbide semiconductor
semiconductor device
forming
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English (en)
French (fr)
Japanese (ja)
Inventor
基 吉田
梨菜 田中
裕 福井
英之 八田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to CN202080105419.7A priority Critical patent/CN116195070B/zh
Priority to JP2022553311A priority patent/JP7370476B2/ja
Priority to US18/019,824 priority patent/US20230290874A1/en
Priority to PCT/JP2020/037178 priority patent/WO2022070317A1/ja
Priority to DE112020007652.0T priority patent/DE112020007652T5/de
Publication of WO2022070317A1 publication Critical patent/WO2022070317A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/146—VDMOS having built-in components the built-in components being Schottky barrier diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to a method for manufacturing a silicon carbide semiconductor device having a trench gate and a method for manufacturing a power conversion device using the silicon carbide semiconductor device.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor: isolated gate type field effect transistor
  • SBD Schottky barrier diode
  • the cost can be reduced compared to the case where the freewheeling diode is externally attached to the switching element.
  • SiC silicon carbide
  • the side wall of the trench is compared with the planar type MOSFET having the structure in which the gate electrode is formed on the surface of the semiconductor layer.
  • the channel width density can be improved and the on-resistance can be reduced by the amount that the channel can be formed.
  • a Schottky trench in which a Schottky electrode is embedded and a gate trench in which a gate electrode is embedded are formed by an etching method, and then a gate insulating film and a gate are formed in the gate trench.
  • a contact hole is formed in the interlayer insulating film, and at the same time, a Ni film is deposited with a part of the interlayer insulating film left on the side wall of the Schottky trench.
  • the silicide layer was formed by heat treatment (for example, Patent Document 1).
  • polycrystalline silicon to be a gate electrode is formed in the gate trench, or metal silicide is formed on the source region.
  • metal silicides such as Crystalline silicon
  • metal and its silicides may remain and be released as foreign matter when the interlayer insulating film is removed, causing contamination.
  • the polysilicon when forming a gate insulating film of silicon oxide and a gate electrode of polycrystalline silicon in the gate trench, the polysilicon is often processed by a dry etching method, but the shotky trench is also processed in the same manner as the gate trench.
  • silicon oxide and polysilicon are once formed in the silicon oxide and the polysilicon in the shotkey trench is removed by dry etching, a part of the polycrystalline silicon remains on the gate insulating film at the bottom of the shotkey trench.
  • silicide may also be formed at the bottom of the shotkey trench, and the silicide will be released in a later step, causing contamination. There was a case.
  • the present disclosure has been made to solve the above-mentioned problems, and it is possible to prevent the polycrystalline silicon material or the metal silicide material from remaining in an unplanned place, and there are few defects or reliability. It is an object of the present invention to provide a method for manufacturing a high silicon carbide semiconductor device.
  • the method for manufacturing a silicon carbide semiconductor device of the present disclosure includes a step of forming a drift layer on a silicon carbide semiconductor substrate, a step of forming a well region on the drift layer, and a step of forming a source region in an upper layer of the well region.
  • the step of removing the silicon oxide film in the shot key trench, and the step of removing the silicon oxide film in the shot key trench, the drift layer and the shot key in the shot key trench includes a step of forming a source electrode to be connected.
  • FIG. It is sectional drawing of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is a top view of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is section
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing explaining the manufacturing method in the case where the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 is not adopted. It is sectional drawing explaining the manufacturing method in the case where the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 is not adopted. It is sectional drawing explaining the manufacturing method in the case where the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 is not adopted.
  • FIG. 1 It is sectional drawing explaining the manufacturing method in the case where the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 is not adopted. It is sectional drawing of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is a top view of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. 2 It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. 2 It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. 2 is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 2.
  • FIG. It is a schematic diagram which shows the structure of the power conversion apparatus manufactured by the manufacturing method of the power conversion apparatus which concerns on Embodiment 3.
  • FIG. 1 is a cross-sectional view of a part of an active region of a trench-type silicon carbide MOSFET with a built-in Schottky barrier diode (SiC trench MOSFET with a built-in SBD), which is a silicon carbide semiconductor device manufactured by the manufacturing method according to the first embodiment.
  • FIG. 2 is a plan view of the SiC trench MOSFET with built-in SBD shown in FIG. 1, and is a plan view at a certain depth in which the trench is formed.
  • a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low resistance silicon carbide.
  • a well region 30 made of p-type silicon carbide is provided on the surface layer of the drift layer 20.
  • a source region 40 made of n-type silicon carbide is formed in the upper layer of the well region 30.
  • a contact region 35 made of low resistance p-type silicon carbide is formed on the surface layer portion of the well region 30 adjacent to the source region 40.
  • a region composed of silicon carbide (a region formed as the drift layer 20) is referred to as a silicon carbide layer regardless of the presence or absence of ion implantation.
  • a gate trench that penetrates the source region 40 and the well region 30 and reaches the drift layer 20 is formed. Further, a shot key trench that penetrates the well region 30 and reaches the drift layer 20 is formed at a position separated from the gate trench in which the source region 40 of the well region 30 is not formed.
  • a gate electrode 60 made of low-resistance polycrystalline silicon is formed via a gate insulating film 50.
  • a p-shaped first protected region 31 is formed in the drift layer 20 at the bottom of the gate trench.
  • a p-shaped second protected region 32 is formed in the drift layer 20 at the bottom of the shot key trench.
  • An interlayer insulating film 55 is formed on the gate electrode 60 and the gate insulating film 50 of the gate trench and in the vicinity of the opening of the shotkey trench. Further, an ohmic electrode 70 made of metal silicide is formed on the source region 40 and the contact region 35. A source electrode 80 is formed inside the Schottky trench, on the ohmic electrode 70, and on the interlayer insulating film 55, and the source electrode 80 inside the Schottky trench and the drift layer 20 are Schottky-bonded. .. A back surface ohmic electrode 71 and a drain electrode 85 are formed on the surface of the semiconductor substrate 10 opposite to the drift layer 20 on which the drift layer 20 is not formed. At the position where the source electrode 80 is in contact with the drift layer 20 in the shot key trench, the source electrode 80 is made of any of Ti, Mo, W, and Ni materials.
  • the gate trench in which the gate electrode 60 is formed and the shotkey trench in which the source electrode 80 is formed are formed linearly in a certain direction and are arranged alternately.
  • the distance between the gate trench and the shot key trench is constant.
  • the gate trench is formed with a p-shaped first connection region 33 from the gate trench toward the drift layer 20 in a direction orthogonal to the extending direction of the gate trench
  • the shot key trench is a shot key trench.
  • a p-shaped second connection region 34 is formed from the shot key trench toward the drift layer 20 in a direction orthogonal to the stretching direction of the above.
  • FIG. 3 is a cross-sectional view of an SBD built-in SiC trench MOSFET manufactured by the manufacturing method according to the first embodiment at a position where the first connection region 33 and the second connection region 34 are formed.
  • the first connection area 33 connects the first protection area 31 and the well area 30.
  • the second connection area 34 connects the second protected area 32 and the well area 30.
  • a plurality of the first connection region 33 and the second connection region 34 are formed at predetermined intervals along the extending direction of the gate trench and the shot key trench.
  • a chemical vapor deposition method is performed on a semiconductor substrate 10 made of n-type low-resistance silicon carbide having a (0001) plane having an off-angle plane orientation of the first main plane and having a polytype of 4H.
  • CVD method Chemical Vapor Deposition: CVD method
  • drift layer 20 made of n-type, 5 ⁇ m or more, and 50 ⁇ m or less thick silicon carbide with an impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 17 cm -3 or less. Epitaxially grows.
  • Al which is a p-type impurity
  • the depth of ion implantation of Al is set to about 0.5 ⁇ m or more and 3 ⁇ m or less, which does not exceed the thickness of the drift layer 20.
  • the impurity concentration of the ion-implanted Al is in the range of 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 19 cm -3 or less, which is higher than the impurity concentration of the drift layer 20.
  • the region in which Al ions are implanted becomes the well region 30 by this step, and the structure shown in FIG. 4 is obtained.
  • an injection mask is formed by a photoresist or the like so that a predetermined portion of the well region 30 on the surface of the drift layer 20 is opened, and N (nitrogen), which is an n-type impurity, is ion-implanted.
  • N nitrogen
  • the ion implantation depth of N is shallower than the thickness of the well region 30.
  • the impurity concentration of the ion-implanted N is in the range of 1 ⁇ 10 18 cm -3 or more and 1 ⁇ 10 21 cm -3 or less, and exceeds the p-type impurity concentration in the well region 30.
  • the region showing n type is the source region 40. Then remove the injection mask.
  • impurities in the range of 1 ⁇ 10 19 cm -3 or more and 1 ⁇ 10 21 cm -3 or less which are higher than the impurity concentration of the well region 30 in the predetermined region of the well region 30 adjacent to the source region 40.
  • the contact region 35 is formed by ion-implanting Al to a concentration.
  • a resist mask that opens a part of the region where the source region 40 is formed is formed, and a gate trench that penetrates the source region 40 and the well region 30 and reaches the drift layer 20 is formed by a dry etching method.
  • a resist mask that opens a part of the region where the source region 40 is not formed is formed, and a shot key trench that penetrates the well region 30 and reaches the drift layer 20 is formed by a dry etching method.
  • the formation of the gate trench and the shot key trench may be formed at the same depth in the same dry etching process.
  • FIG. 7 as a schematic cross-sectional view, p-type impurities are ion-implanted into the drift layer 20 at the bottom of the gate trench and the shot key trench, and the first protected region 31 and the second protected region 32 are respectively.
  • p-type impurities are ion-implanted into the drift layer 20 at the bottom of the gate trench and the shot key trench, and the first protected region 31 and the second protected region 32 are respectively.
  • To form. Remove the resist mask after ion implantation. Further, a resist mask having an opening at a portion forming the first connection region 33 and the second connection region 34 is formed, and the p-type impurity is implanted obliquely into the first connection region 33 and the second connection region 34. Form. Remove the resist mask after ion implantation.
  • the heat treatment apparatus performs annealing at a temperature of 1300 to 1900 ° C. for 30 seconds to 1 hour in an atmosphere of an inert gas such as argon (Ar) gas. This anne
  • the surface of the silicon carbide layer including the inside of the gate trench and the Schottky trench is thermally oxidized to form a silicon oxide film 51 having a thickness of 10 nm or more and 300 nm or less.
  • the silicon oxide film 51 is formed in contact with the inner walls of the gate trench and the Schottky trench.
  • the silicon oxide film 51 may be formed by a CVD method. By this step, the structure of the cross-sectional view shown in FIG. 8 is obtained.
  • a polycrystalline silicon film 61 having a thickness of 300 nm or more and a conductivity of 2000 nm or less on the silicon oxide film 51 by the reduced pressure CVD method the cross-sectional view shown in FIG. 9 is formed. To.
  • the polycrystalline silicon film 61 is left only inside the gate trench and the Schottky trench, and the structure of the cross-sectional view shown in FIG. 10 is obtained.
  • the polycrystalline silicon film 61 in the gate trench becomes the gate electrode 60.
  • an interlayer insulating film 55 made of silicon oxide having a thickness of 500 nm or more and 3000 nm or less is formed by a reduced pressure CVD method.
  • the interlayer insulating film 55 and the silicon oxide film 51 are patterned so as to open on the region where the source region 40 and the contact region 35 are formed and on the Schottky trench to form the cross-sectional structure shown in FIG. ..
  • the polysilicon film 61 in the shot key trench is removed by a wet etching method with an alkaline etching solution such as an alkaline developer.
  • an alkaline etching solution such as an alkaline developer.
  • an ohmic electrode 70 made of silicide is formed on the source region 40 and the contact region 35, as shown in the cross-sectional view in FIG.
  • a part (surface) of the silicon oxide film 51 and the interlayer insulating film 55 in the Schottky trench is removed by a wet etching method using hydrofluoric acid or the like.
  • the natural oxide film on the surface of the ohmic electrode 70 can also be removed.
  • the silicon oxide film 51 remaining in the gate trench becomes the gate insulating film 50.
  • a source electrode 80 for Schottky junction with the drift layer 20 is formed inside the Schottky trench and on the ohmic electrode 70 of the gate trench, and a back surface ohmic electrode 71 and a drain electrode 85 are formed on the back surface side. This makes it possible to manufacture an SBD-embedded SiC- MOSFET whose cross-sectional view is shown in FIG.
  • the Schottky trench is covered with a resist mask. It was necessary to form a contact hole as it was, and then to form another resist mask to remove the interlayer insulating film 55 in the Schottky trench.
  • the number of times the resist mask is formed can be reduced to manufacture the SBD-built-in SiC- MOSFET, and the manufacturing cost can be reduced.
  • the SiC- MOSFET with built-in SBD is manufactured by the manufacturing method of the present embodiment
  • the silicon oxide film 51 inside the Schottky trench is wet-etched
  • the silicon oxide film 51 and a part of the interlayer insulating film 55 (surface). ) Is wet-etched, so that a portion where the source electrode 80 and the source region 40 or the contact region 35 are in direct contact is formed on the gate trench side around the ohmic electrode 70, as shown in the cross-sectional view in FIG.
  • the method for manufacturing a silicon carbide semiconductor device According to the method for manufacturing a silicon carbide semiconductor device according to the present embodiment, it is possible to prevent the silicide and the gate insulating film from remaining in the Schottky trench, and it is possible to prevent the generation of foreign substances that cause contamination during the process. , Silicon carbide semiconductor devices with few defects can be manufactured.
  • FIG. 17 is a schematic cross-sectional view of a unit cell of an active region of a silicon carbide MOSFET having a built-in Schottky barrier diode (SiC- MOSFET with a built-in SBD), which is a silicon carbide semiconductor device manufactured by the manufacturing method according to the second embodiment.
  • FIG. 18 is a cross-sectional view at a position where the first connection region 33 and the second connection region 34 of the SBD built-in SiC- MOSFET) are formed.
  • the plan view of the depth at which the trench is formed is the same as that of FIG. 2 of the first embodiment.
  • the ohmic electrode 70 of the MOSFET of the gate trench is formed in the hole of the interlayer insulating film 55 at the upper part of the shotkey trench and the hole formed at a position separated from the hole in the sectional view.
  • the ohmic electrode 70 of the MOSFET of the gate trench and the source electrode 80 inside the shotkey trench are formed in the same hole of the interlayer insulating film 55, that is, adjacent to each other.
  • the interlayer insulating film 55 is not provided between the ohmic electrode 70 and the shot key trench. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.
  • the drift layer 20 is formed on the surface of the semiconductor substrate 10.
  • a well region 30 is provided on the surface layer portion of the drift layer 20, and a source region 40 and a contact region 35 are formed on the upper layer portion of the well region 30.
  • a gate trench that penetrates the source region 40 and the well region 30 and reaches the drift layer 20 is formed.
  • a shot key trench that penetrates the well region 30 and reaches the drift layer 20 is formed in a portion of the well region 30 where the source region 40 is not formed.
  • a gate insulating film 50 is formed inside the gate trench, and a gate electrode 60 is formed inside the gate insulating film 50.
  • a p-shaped first protected region 31 is formed in the drift layer 20 at the bottom of the gate trench.
  • a p-shaped second protected region 32 is formed in the drift layer 20 at the bottom of the shot key trench.
  • An interlayer insulating film 55 is formed on the gate electrode 60 and the gate insulating film 50 of the gate trench. Further, an ohmic electrode 70 is formed on the source region 40, the contact region 35, and the well region 30 near the Schottky trench. The interlayer insulating film 55 is not formed between the adjacent ohmic electrode 70 and the Schottky trench. A source electrode 80 is formed inside the Schottky trench, on the ohmic electrode 70, and on the interlayer insulating film 55, and the source electrode 80 inside the Schottky trench and the drift layer 20 are Schottky-bonded. ..
  • a back surface ohmic electrode 71 and a drain electrode 85 are formed on the surface of the semiconductor substrate 10 opposite to the drift layer 20 on which the drift layer 20 is not formed.
  • FIG. 18 which is a cross-sectional view of the position where the first protected area 31 and the second protected area are formed, in addition to the configuration of FIG. 17, the first protected area 31 is shot in the drift layer 20 of the side wall portion of the gate trench.
  • a second protective region 32 is formed in the drift layer 20 of the side wall portion of the key trench.
  • the method of manufacturing the SBD-embedded SiC- MOSFET which is the silicon carbide semiconductor device according to the second embodiment of the present disclosure, will be described with reference to the cross-sectional views of FIGS. 19 to 23 corresponding to the cross-sections shown in FIG. ..
  • the steps of FIGS. 4 to 11 of the first embodiment are the same as those of the first embodiment.
  • the interlayer insulating film 55 and the silicon oxide film 51 are etched except for the upper part of the gate electrode 60 and the silicon oxide film 51 of the gate trench. ..
  • Etching may be performed by plasma etching, or may be performed by combining plasma etching and wet etching.
  • the polycrystalline silicon film 61 in the shotkey trench is basically not etched, and a part of the upper side of the silicon oxide film made of the same material as the gate insulating film 50 in the shotkey trench is etched.
  • the silicon oxide film 51 remains in the lower part of the Schottky trench.
  • the polycrystalline silicon film 61 in the Schottky trench is selectively etched by the wet etching method.
  • a step of depositing and annealing the metal constituting the ohmic electrode 70 as shown in the cross-sectional view in FIG. 21, on the source region 40, on the contact region 35, and on the well region 30 near the Schottky trench.
  • an ohmic electrode 70 made of silicide is formed on the side surface of the well region 30 near the upper end of the Schottky trench.
  • the silicon oxide film 51 in the Schottky trench is wet-etched with hydrofluoric acid or the like.
  • a source electrode 80 for Schottky bonding with the drift layer 20 is formed on the interlayer insulating film 55, inside the Schottky trench, and on the ohmic electrode 70 of the gate trench, and the back surface ohmic electrode 71 and the drain electrode 85 are formed on the back surface side.
  • the ohmic electrode 70 may be formed from the outside to a part of the inside of the opening of the Schottky trench, and as shown in the cross section in FIG. 23, the ohmic electrode 70 is also formed on the upper part of the inside of the Schottky trench. Electrodes 70 may be formed. Further, when the silicon oxide film 51 inside the shot key trench is wet-etched, the silicon oxide film 51 and a part (surface) of the interlayer insulating film 55 are wet-etched. Therefore, a cross-sectional view thereof is shown in FIG. 22. As described above, a portion where the source electrode 80 and the source region 40 or the contact region 35 are in direct contact with each other is formed on the gate trench side around the ohmic electrode 70.
  • the method for manufacturing the SiC- MOSFET with built-in SBD which is a silicon carbide semiconductor device according to the present embodiment, can also prevent the silicide and the gate insulating film from remaining in the Schottky trench, and also cause contamination during the process. Since the generation of foreign matter can be prevented, a silicon carbide semiconductor device having few defects can be manufactured. Further, according to the silicon carbide semiconductor device of the present embodiment, since it is not necessary to form the interlayer insulating film 55 in the vicinity of the shotkey trench, it is not necessary to take a space for forming the interlayer insulating film 55, and it is not necessary to take a space between the trenches. The interval between the two can be made smaller, and a silicon carbide semiconductor device having a higher current density can be manufactured.
  • the method of forming the well region 30 and the source region 40 by the ion implantation method has been described, but the well region 30 and the source region 40 may be formed by another method. For example, it may be formed by an epitaxial method. Further, although the example in which the well region 30 is formed on the entire surface has been described, the well region 30 may be formed in a part of the upper layer portion of the drift layer 20. At that time, the shot key trench may be provided as it is on the drift layer 20 from the surface instead of being provided through the well region 30.
  • first and second embodiments an example in which the first protected area 31 and the second protected area 32 are provided in the lower part of the trench has been described, but the first protected area 31 and the second protected area 32 may be different. May not be present. At this time, neither the first connection area 33 nor the second connection area 34 may be provided.
  • the gate insulating film does not necessarily have to be an oxide film such as SiO 2 , and an insulating film other than the oxide film, or an insulating film other than the oxide film and the oxide film. It may be a combination of. Further, in the above embodiment, specific examples such as the crystal structure, the plane orientation of the main surface, the off-angle, and each injection condition have been described, but the applicable range is not limited to these numerical ranges.
  • the drain electrode 85 is formed on the back surface of the semiconductor substrate 10 and the SBD is built in the silicon carbide semiconductor device of the so-called vertical MOSFET has been described, but the drain electrode 85 is the drift layer 20. It can also be used for a so-called horizontal MOSFET having an SBD built-in, such as a RESURF (REDused SURface Field) type MOSFET formed on the surface.
  • the silicon carbide semiconductor device may be an insulated gate bipolar transistor (IGBT: Integrated Gate Bipolar Transistor) with an SBD built-in. It can also be applied to MOSFETs and IGBTs having a super junction structure with SBDs built-in.
  • Embodiment 3 the method for manufacturing a silicon carbide semiconductor device according to the above-described first and second embodiments is applied to the manufacturing of a power conversion device.
  • the present disclosure is not limited to the method for manufacturing a specific power conversion device, the case where the present disclosure is applied to the method for manufacturing a three-phase inverter will be described below as the third embodiment.
  • FIG. 24 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 24 includes a power supply 100, a power conversion device 200, and a load 300.
  • the power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200.
  • the power supply 100 can be configured with various things, for example, it can be configured with a DC system, a solar cell, a storage battery, or it can be configured with a rectifier circuit or an AC / DC converter connected to an AC system. May be good.
  • the power supply 100 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300.
  • the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal that drives each switching element of the main conversion circuit 201.
  • a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 is provided.
  • the drive circuit 202 off-controls each normally-off type switching element by making the voltage of the gate electrode and the voltage of the source electrode the same potential.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200.
  • the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices.
  • the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and by switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes.
  • a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to any one of the above-described embodiments 1 to 3 is applied to each switching element of the main conversion circuit 201.
  • the six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the drive circuit 202 generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element
  • the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
  • the control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) in which each switching element of the main conversion circuit 201 should be in the on state is calculated based on the electric power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off.
  • the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the silicon carbide semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device according to the first and second embodiments is applied as the switching element of the main conversion circuit 201, so that the loss is low. Moreover, it is possible to realize a power conversion device with improved reliability of high-speed switching.
  • the present disclosure is not limited to this, and can be applied to various power conversion devices.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is disclosed to a single-phase inverter. You may apply it.
  • the present disclosure can be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power source for a discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

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PCT/JP2020/037178 2020-09-30 2020-09-30 炭化珪素半導体装置の製造方法、炭化珪素半導体装置および電力変換装置の製造方法 Ceased WO2022070317A1 (ja)

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CN202080105419.7A CN116195070B (zh) 2020-09-30 2020-09-30 碳化硅半导体装置的制造方法、碳化硅半导体装置以及电力变换装置
JP2022553311A JP7370476B2 (ja) 2020-09-30 2020-09-30 炭化珪素半導体装置の製造方法、炭化珪素半導体装置および電力変換装置
US18/019,824 US20230290874A1 (en) 2020-09-30 2020-09-30 Method of manufacturing silicon carbide semiconductor device, silicon carbide semiconductor device, and power conversion apparatus
PCT/JP2020/037178 WO2022070317A1 (ja) 2020-09-30 2020-09-30 炭化珪素半導体装置の製造方法、炭化珪素半導体装置および電力変換装置の製造方法
DE112020007652.0T DE112020007652T5 (de) 2020-09-30 2020-09-30 Verfahren zur herstellung einer siliciumcarbid-halbleitereinheit, siliciumcarbidhalbleitereinheit und leistungswandlervorrichtung

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US20240290879A1 (en) * 2023-02-27 2024-08-29 Globalfoundries U.S. Inc. Field-effect transistors with deposited gate dielectric layers
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