WO2022061820A1 - 一种接收芯片及其制备方法、测距装置、可移动平台 - Google Patents

一种接收芯片及其制备方法、测距装置、可移动平台 Download PDF

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Publication number
WO2022061820A1
WO2022061820A1 PCT/CN2020/118149 CN2020118149W WO2022061820A1 WO 2022061820 A1 WO2022061820 A1 WO 2022061820A1 CN 2020118149 W CN2020118149 W CN 2020118149W WO 2022061820 A1 WO2022061820 A1 WO 2022061820A1
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Prior art keywords
wafer
layer
preparation
dielectric layer
bonding
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PCT/CN2020/118149
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English (en)
French (fr)
Inventor
郑国光
洪小平
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深圳市大疆创新科技有限公司
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Priority to CN202080014792.1A priority Critical patent/CN114599998A/zh
Priority to PCT/CN2020/118149 priority patent/WO2022061820A1/zh
Publication of WO2022061820A1 publication Critical patent/WO2022061820A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Definitions

  • the present application generally relates to the field of semiconductors, and more particularly, to a receiving chip and its manufacturing method, a distance measuring device, and a movable platform.
  • Lidar ranging device
  • the photosensitive sensor of the lidar can convert the obtained optical pulse signal into an electrical signal, and obtain the time information corresponding to the electrical signal based on the comparator, thereby obtaining the distance information between the lidar and the target.
  • Solid-state lidar is a good solution for receiver chips, but the core of solid-state lidar is the receiver chip of area array.
  • a 64-line radar requires 64 laser diodes (Laser diodes) and 64 avalanche photodiodes (APDs).
  • Laser diodes laser diodes
  • APDs avalanche photodiodes
  • the interconnection of circuits causes many coupling problems and low reliability problems.
  • a first aspect of the present application provides a method for preparing a receiving chip, the preparation method comprising:
  • the first surface of the first wafer is formed with a plurality of back-illuminated avalanche photodiodes
  • a second wafer is provided, and a plurality of signal processing units are formed on the first surface of the second wafer;
  • the first surface of the first wafer and the first surface of the second wafer are bonded, so that the back-illuminated avalanche photodiode and the signal processing unit corresponding to the top and bottom are electrically connected to each other.
  • a second aspect of the present application provides a receiving chip, the receiving chip comprising:
  • the bonded first wafer and the second wafer, the first wafer and the second wafer are obtained by cutting the bonded first wafer and the second wafer;
  • a plurality of back-illuminated avalanche photodiodes are formed on the first surface of the first wafer;
  • a plurality of signal processing units are formed on the first surface of the second wafer
  • the first surface of the first wafer and the first surface of the second wafer are bonded to each other, and the back-illuminated avalanche photodiodes corresponding to the upper and lower sides and the signal processing unit are electrically connected to each other.
  • a third aspect of the present application provides a distance measuring device, the distance measuring device comprising:
  • Light emitting circuit for emitting laser pulse signal
  • the aforementioned receiving chip is used to receive the optical pulse sequence reflected by the detected object, and output a time signal based on the received optical pulse sequence;
  • an arithmetic circuit for calculating the distance between the detected object and the distance measuring device according to the time signal.
  • a fourth aspect of the present application provides a movable platform comprising:
  • the distance measuring device is provided on the movable platform body.
  • the application provides a receiving chip and a preparation method thereof.
  • the chip adopts a bonding method to realize wafer-level integration of a back-illuminated avalanche photodiode and a signal processing unit to form a back-illuminated avalanche photodiode area array chip.
  • the chip described in this application can utilize the existing semiconductor manufacturing platform and technology to produce a large-scale, low-cost, and high-reliability back-illuminated avalanche photodiode area array chip, so as to meet the requirements of solid-state laser radar for receiving modules.
  • FIGS. 1A-1C show schematic cross-sectional views of each intermediate device in the first wafer processing process provided by the present application
  • FIGS. 2A-2D show schematic cross-sectional views of each intermediate device in the second wafer processing process provided by the present application
  • 3A-3J show schematic cross-sectional views of each intermediate device in the preparation process of the receiving chip provided by the present application
  • FIGS. 4A-4D show schematic cross-sectional views of each intermediate device in a microlens fabrication process provided in another embodiment of the present application.
  • FIG. 5 shows a schematic flowchart of the method for manufacturing a receiving chip provided by the present application.
  • a first aspect of the present application provides a method for preparing a receiving chip, as shown in FIG. 5 , the preparation method specifically includes the following steps:
  • Step S1 providing a first wafer, the first surface of the first wafer is formed with a plurality of back-illuminated avalanche photodiodes;
  • Step S2 providing a second wafer, a plurality of signal processing units are formed on the first surface of the second wafer;
  • Step S3 bonding the first surface of the first wafer and the first surface of the second wafer, so that the back-illuminated avalanche photodiode and the signal processing unit corresponding to the top and bottom are electrically connected to each other .
  • FIGS. 1A-1C show each intermediate device in the first wafer processing process provided by the present application.
  • 2A-2D show the schematic cross-sectional views of each intermediate device in the second wafer processing process provided by the present application;
  • Figures 3A-3J show the schematic cross-sectional views of each intermediate device in the preparation process of the receiving chip provided by the present application .
  • the material of the first wafer 101 can be Si, Ge, GaAs or InGaAs, which can be selected according to actual needs. It should be noted that the material of the first wafer 101 The materials are not limited to this example.
  • the first wafer 101 includes a first surface and a second surface disposed opposite to each other, wherein the first surface is a front surface, and the second surface is a back surface.
  • a plurality of backside illuminated avalanche photodiodes are formed on the first surface to form a linear or area array structure of avalanche photodiodes.
  • the plurality of back-illuminated avalanche photodiodes may be arranged in several rows or columns to form a linear array of back-illuminated avalanche photodiodes.
  • the plurality of backside illuminated avalanche photodiodes may also include an arrangement of several rows and several columns to form an area array of backside illuminated avalanche photodiodes.
  • the number of the back-illuminated avalanche photodiodes is not limited to a certain value range, and can be selected according to actual needs.
  • the arrays formed by the plurality of back-illuminated avalanche photodiodes can be arranged in other forms besides linear arrays and area arrays, and are not limited to linear arrays and area arrays, and can also be irregularly arranged. Arrangement, etc., can be set according to actual needs.
  • the semiconductor device is a back-illuminated device, that is, in the back-illuminated device, the photosensitive device APD is located in front of the circuit transistor, and light first enters the photosensitive device APD, thereby increasing the High sensitivity.
  • the method for forming the back-illuminated avalanche photodiode may include: performing an ion implantation process on the first surface of the first wafer 101 or an epitaxial layer on the first surface, so as to sequentially form the back-illuminated avalanche from bottom to top
  • Each functional area of a photodiode, each functional area of the back-illuminated avalanche photodiode includes a buffer layer, a diffusion barrier layer, an avalanche multiplication layer, an absorption layer and a contact layer.
  • an electric field control layer and a graded layer may be further formed between the avalanche multiplication layer and the absorption layer.
  • the back-illuminated avalanche photodiode sequentially includes a p-InP buffer layer, a p-AlInAs diffusion barrier layer, a low-doped n-InP avalanche multiplication layer, and an n-InP electric field control layer from bottom to top. , n-InGaAsP graded layer, nInGaAs light absorption layer, semi-insulating InP window layer and InGaAs contact layer.
  • each functional layer of the back-illuminated avalanche photodiode may be conventional doping concentrations and thicknesses, which will not be listed one by one here.
  • a plurality of first bonding pads 102 and a first dielectric layer 103 are further formed on the first surface of the first wafer 101 .
  • the first bonding pads 102 and the first dielectric layers 103 are alternately arranged, and the first dielectric layer 103 fills the gaps between the first bonding pads 102 .
  • the height of the first dielectric layer 103 is greater than the height of the first bonding pad 102 to prevent the temperature from rising during the bonding process, which may cause bonding due to the large thermal expansion coefficient of the first bonding pad 102 .
  • the together first wafer 101 and the second wafer are separated.
  • the material of the first bonding pad 102 is a metal material, and the metal material may be metal copper or aluminum. In an embodiment of the present application, the first bonding pad 102 is made of copper.
  • the first dielectric layer 103 can use oxide or nitride, for example, the first dielectric layer 103 can use silicon dioxide (SiO 2 ), fluorocarbon (CF), silicon nitride (SiN), One or more of silicon oxycarbide (SiOC), or silicon carbonitride (SiCN).
  • SiO 2 silicon dioxide
  • CF fluorocarbon
  • SiN silicon nitride
  • SiOC silicon oxycarbide
  • SiCN silicon carbonitride
  • the material of the second wafer 301 can be Si, Ge, GaAs or InGaAs, which can be selected according to actual needs. It should be noted that the second wafer 301 The materials are not limited to this example.
  • the material of the first wafer 101 and the material of the second wafer 301 are the same.
  • the material of the first wafer 101 and the material of the second wafer 301 are both silicon.
  • the second wafer 301 includes a first surface and a second surface disposed opposite to each other, wherein the first surface is a front surface, and the second surface is a back surface.
  • a plurality of signal processing units are formed on the first surface for processing signals transmitted by the back-illuminated avalanche photodiode.
  • the signal processing unit is integrated with a plurality of circuits.
  • the signal processing unit is integrated with a transimpedance amplifier circuit (TIA circuit), a multi-stage operational amplifier OPA, a comparator, and a time-to-digital converter Circuit (circuit that converts time into digital signal) or analog-to-digital conversion circuit (ADC circuit), and subsequent data processing circuit (DSP circuit).
  • TIA circuit is an analog front-end circuit that converts the APD photocurrent into a voltage.
  • the APD when the plurality of back-illuminated avalanche photodiodes convert optical signals into current signals, an external high-voltage power supply is required, and the APD can provide stable internal gain and improve the signal-to-noise ratio, and output current signals.
  • the TIA circuit is electrically connected to the back-illuminated avalanche photodiode, and the TIA circuit converts the current signal of the APD into a voltage signal and provides a conversion gain at the same time; the multi-stage operational amplifier OPA is connected to the The TIA circuit is electrically connected to amplify the signal output by the TIA circuit to meet the comparison amplitude requirement of the comparator.
  • the comparator is electrically connected to the multi-stage operational amplifier OPA, wherein a comparison threshold is set in the comparator to trigger the analog signal, convert the analog signal into a digital signal, and transmit the signal to the TDC circuit, and the TDC circuit is used to convert the analog signal into a digital signal.
  • the digital signal is converted to a time signal for distance calculation.
  • one TDC circuit may be shared, that is, the number of signal processing units may not correspond to the number of TDC circuits.
  • a storage system may be further provided in the signal processing unit to cache data, provide input and output buffer space for the interface, and provide space for internal calculation.
  • An interface can be further set in the signal processing unit to serve as a data input and output channel to output the measurement data.
  • a plurality of second bonding pads 302 and a second dielectric layer 303 spaced apart from each other are further formed on the first surface of the second wafer 301 .
  • the second bonding pads 302 and the second dielectric layers 303 are alternately arranged, and the second dielectric layer 303 fills the gaps between the second bonding pads 302 .
  • a number of interconnection structures are also formed in the second interlayers on the first surface of the second wafer 301 , and the interconnection structures include metal layers and through holes spaced up and down. Through the interconnection structures The second bonding pad 302 is electrically connected to the signal processing unit in the second wafer 301 .
  • connecting pads 304 are also formed in the edge region of the second wafer 301 for pulling out the signals of the structure obtained after the first wafer 101 and the second wafer 301 are bonded.
  • the connection pads 304 are electrically connected to the pins of the packaging module to draw out electrical signals.
  • the height of the second dielectric layer 303 is greater than the height of the second bonding pad 302 to prevent the temperature from rising during the bonding process, which may cause bonding due to the large thermal expansion coefficient of the second bonding pad 302 .
  • the together first wafer 101 and the second wafer 301 are separated.
  • the material of the second bonding pad 302 is a metal material, and the metal material may be metal copper or aluminum. In an embodiment of the present application, the second bonding pad 302 is made of copper.
  • the second dielectric layer 303 can use oxide or nitride, for example, the second dielectric layer 303 can use silicon dioxide (SiO 2 ), fluorocarbon (CF), silicon nitride (SiN), One or more of silicon oxycarbide (SiOC), or silicon carbonitride (SiCN).
  • SiO 2 silicon dioxide
  • CF fluorocarbon
  • SiN silicon nitride
  • SiOC silicon oxycarbide
  • SiCN silicon carbonitride
  • the first surface of the first wafer 101 and the first surface of the second wafer 301 are bonded to connect the back-illuminated avalanche photodiodes corresponding to the top and bottom with the
  • the signal processing unit is integrated into one.
  • the first surface of the first wafer 101 and the first surface of the second wafer 301 need to be bonded
  • the first surface of 301 is treated to increase the bond strength, specifically:
  • the first surface of the first wafer 101 and the first surface of the second wafer 301 are respectively subjected to plasma surface treatment to activate the first bonding pad 102, the second bonding pad 302, and the surface of the first dielectric layer 103 and the second dielectric layer 303, and then the first bonding pad 102, the second bonding pad 302, the first dielectric layer 103 and the second dielectric Unbonded atoms on the surface of layer 303 are more likely to form covalent bonds.
  • O 2 plasma is selected to irradiate the first bonding pad 102 , the second bonding pad 302 , and the first dielectric layer 103 respectively.
  • an oxygen-containing gas such as nitrogen dioxide, silicon dioxide, etc., can also be selected, which is not limited to any one.
  • the method further includes cleaning the surfaces of the first bonding pad 102 , the second bonding pad 302 , the first dielectric layer 103 and the second dielectric layer 303 respectively. step to change the charge characteristics of the surfaces of the first bonding pad 102 , the second bonding pad 302 , the first dielectric layer 103 and the second dielectric layer 303 .
  • the first bonding pad 102 , the second bonding pad 302 , the first dielectric layer 103 and the first bonding pad 102 are compared
  • the second dielectric layer 303 is subjected to O 2 plasma surface treatment and then cleaned with deionized water
  • the first bonding pad 102 , the second bonding pad 302 , the first dielectric layer 103 and the Negatively charged OH ⁇ is formed on the surface of the second dielectric layer 303 for bonding.
  • the first dielectric layer 103 and the second dielectric layer 303 are first aligned, and the first bonding pads 102 and the second bonding pads 302 are aligned at the same time.
  • the first dielectric layer 103 and the second dielectric layer 303 are temporarily bonded.
  • a high-temperature annealing process is performed, so that the first bonding pad 102 and the second bonding pad 302 are bonded at a high temperature together, so that the first bonding pad 102 and the second bonding pad 302 are electrically connected, as shown in FIG. 3A , to realize the electrical connection between the first wafer 101 and the second wafer 301 .
  • an annealing treatment is performed for about 2 hours in a temperature range of 300° C. to 400° C. to realize Cu-Cu bonding, so that the upper and lower back-illuminated avalanche photodiodes corresponding to the The signal processing units are electrically connected to each other.
  • the method further includes:
  • a thinning process is performed on the first wafer 101 to reduce the thickness of the first wafer 101 on the second surface, as shown in FIG. 3B , wherein the thinning process may include chemical mechanical masking One or a combination of film, planarization and polishing.
  • the thickness of the first wafer 101 may be several micrometers to several tens of micrometers, and the thickness may be selected according to actual needs, and is not limited to a certain numerical range.
  • the quantum efficiency of the APD is positively correlated with the thickness of the first wafer 101, then the thickness of the first wafer 101 can be selected according to the needs of the quantum efficiency.
  • the manufacturing method further includes the step of forming a plurality of high-voltage signal electrodes 305 spaced apart from each other on the second surface of the first wafer 101 .
  • the high-voltage signal electrodes 305 are used as high-voltage lead wires, and are disposed on the second surface of the first wafer 101 of the signal processing unit away from the second wafer 301 to prevent damage to various circuits in the signal processing unit. influence, and further improve the performance of the receiving chip.
  • the method for forming the high-voltage signal electrodes 305 includes: depositing an electrode material layer on the second surface of the first wafer 101 , and then etching the electrode material layer to form a plurality of the high-voltage signal electrodes 305 spaced apart from each other , as shown in Figure 3C.
  • the material of the high-voltage signal electrode 305 can be selected from a metal material, such as Al, but is not limited to Al, and can also be selected from materials such as gold and copper.
  • the method further includes: forming a passivation layer 306 on the second surface of the first wafer 101, as shown in FIG. 3D, to cover the photosensitive area 305 outside the high-voltage signal electrode to shield interference signals, The performance of the backside illuminated avalanche photodiode is improved.
  • the method further includes forming a plurality of microlenses 308 on the second surface of the first wafer 101 for incident light incident on the backside-illuminated avalanche photodiode The light is concentrated to improve the efficiency of incident light.
  • the formation method of the microlens 308 is related to the selected material.
  • the material of the microlens 308 is selected from a reflowable material
  • the microlens 308 can be formed by the following methods:
  • the lens material layer may be polyimide, but is not limited to the material
  • the lens material layer 307 is then patterned to retain the lens material layer 307 on the passivation layer 306 between the high voltage signal electrodes 305, as shown in FIG. 3E, wherein the patterning method includes First, a mask layer is formed on the lens material layer, and then the lens material layer 307 is etched using the mask layer as a mask;
  • a reflow process is performed to reflow the lens material layer 307 to form the microlenses 308 having spherical convex surfaces, as shown in FIG. 3F , wherein the microlenses are shaped like convex lenses.
  • the process flow of the microlens 308 is simpler, and can be completed only by the steps of photolithography and reflow.
  • microlenses 308 may also be formed by the following methods:
  • a lens material layer 307 is formed on the second surface of the first wafer 101 to cover the high voltage signal electrodes 305 .
  • a mask layer 312 is formed on the lens material layer 307, wherein the mask layer 312 can be photoresist or other reflowable materials, and is not limited to a certain one;
  • the mask layer 312 is patterned to retain the mask layer 312 on the passivation layer 306 between the high voltage signal electrodes 305 .
  • the photoresist can be exposed and developed to form a pattern of the photoresist at the target position;
  • a reflow process is performed to reflow the mask layer 312 to form a microlens pattern
  • the lens material layer 312 is etched using the microlens pattern as a mask to transfer the pattern to the lens material layer, thereby forming the microlens 308 .
  • the lens material layer is silicon oxide.
  • the refractive index of silicon dioxide is higher, and the converging effect of the prepared microlenses is better.
  • Cavities are formed in the edge region between the first wafer 101 and the second wafer 301 and above the connection pads, and the connection pads on the edge of the second wafer 301 are located in the below the cavity.
  • the method further includes: cutting the edge of the first wafer 101 to remove the first wafer The edge region of the wafer 101 to expose the connection pads 304 on the edge of the second wafer 301 for electrical connection in subsequent steps, as shown in FIG. 3G .
  • a protective layer is formed on the edge of the second wafer 301, as shown by the arrow in FIG. 2D, to cover the connection pads 304, In order to prevent the impurities dropped during the cutting process from scratching the second wafer 301 and causing damage to the second wafer 301 .
  • the protective layer may be a part of the second dielectric layer 303, for example, the height of the second dielectric layer 303 is higher than that of the connection pads 304 to cover the connection pads 304 and further serve as the The protective layer prevents impurities dropped during the cutting process from scratching the connection pads 304 .
  • the method further includes the step of removing the protective layer to expose the connection pads 304 .
  • the protective layer is removed by a method with a larger etching selectivity ratio than that of the second wafer 301 .
  • the method further includes encapsulating the bonded first wafer 101 and the second wafer 301 after removing the edge region of the first wafer 101, for example encapsulating the structure in a package module 309, as shown in FIG. 3H .
  • the package module 309 includes a base plate on the bottom and a side plate on the base plate to surround the receiving space.
  • the method further includes cutting the bonded first wafer 101 and the second wafer 301 after removing the edge region of the first wafer 101 to obtain a plurality of independent chip structures, and Each independent chip structure is fixed in the accommodating space of the package module to obtain the receiving chip.
  • each independent chip structure includes a plurality of back-illuminated avalanche photodiodes and signal processing units as described above, so as to realize their functions independently.
  • the substrate may be various types of substrates such as printed circuit board (PCB), ceramic substrate, etc., wherein the PCB is made of different components and a variety of complex process technologies, etc.
  • PCB printed circuit board
  • the substrate is made of different components and a variety of complex process technologies, etc.
  • the printed circuit board is mainly composed of pads, vias, mounting holes, wires, components, connectors, padding, electrical boundaries, and the like.
  • the common layer structures of printed circuit boards include three types: Single Layer PCB, Double Layer PCB, and Multi Layer PCB.
  • the specific structures are as follows:
  • Single-layer board that is, a circuit board with copper on one side and no copper on the other side. Usually components are placed on the side without copper, and the copper side is mainly used for wiring and soldering.
  • Double-layer board that is, a circuit board with copper on both sides, usually called one side is the top layer (Top Layer), and the other side is the bottom layer (Bottom Layer).
  • Top Layer a circuit board with copper on both sides
  • Bottom Layer the bottom layer
  • the top layer is used as the component placement surface
  • the bottom layer is used as the component welding surface.
  • Multilayer board that is, a circuit board containing multiple working layers. In addition to the top layer and the bottom layer, it also contains several intermediate layers. Usually, the intermediate layer can be used as a wire layer, a signal layer, a power layer, and a ground layer. The layers are insulated from each other, and the connection between layers is usually achieved through vias.
  • the printed circuit board includes many types of working layers, such as a signal layer, a protective layer, a silk screen layer, an inner layer, etc., which will not be repeated here.
  • the substrate described in this application can also be a ceramic substrate. or double-sided) on a special craft board.
  • the resulting ultra-thin composite substrate has excellent electrical insulation properties, high thermal conductivity, excellent solderability and high adhesion strength, and can be etched into various patterns like a PCB board, and has a large current carrying capacity. ability.
  • the substrate is also provided with a first pin and a second pin.
  • the high-voltage signal electrode 305 is electrically connected to the first pin of the packaging module; the connection pad is connected 304 is electrically connected to the second pin of the package module.
  • the surface of the receiving chip structure corresponding to the second wafer 301 is mounted on the substrate; and then a glue filling process is performed in the accommodating space to A sealant 310 is formed to cover and fix the chip structure, while exposing the high voltage signal electrodes 305 and the microlenses 308 corresponding to the surface of the first wafer 101 in the chip structure, as shown in FIG. 3I .
  • the accommodating space may be filled with waterproof glue, and before the glue is poured, a step of cleaning the surface of the receiving chip corresponding to the second wafer 305 may be further included.
  • a top plate 311 is formed on the side plate to form a closed accommodating space. As shown in FIG. 3J , at least a part of the top plate 311 is a light-transmitting area.
  • the top plate can be selected from commonly used light-transmitting materials, such as glass, which must have high transmittance to light.
  • the top plate 311 may be a plate-like structure that is fully transparent, or may be a metal flat plate with a glass window.
  • the present application provides a preparation method of a receiving chip, which adopts a bonding method to realize wafer-level integration of a back-illuminated avalanche photodiode and a signal processing unit, and forms a back-illuminated avalanche photodiode area array chip.
  • the high-level integration method can realize the area array interconnection of the illuminated avalanche photodiode and the signal processing unit, which has better precision and better yield, and can further improve the performance of the receiving chip.
  • wafer-level integration can reduce the gap between back-illuminated avalanche photodiodes and make them denser. When applied to point clouds, the obtained point cloud density is higher, which can help identify smaller objects.
  • the receiving chip described in this application can utilize the existing semiconductor manufacturing platform and technology to produce a back-illuminated avalanche photodiode area array chip in a large-scale, low-cost, and high-reliability manner, so as to meet the needs of solid-state laser radar for receiving modules.
  • a second aspect of the present application provides a receiving chip, as shown in FIG. 3J , the receiving chip includes:
  • the bonded first wafer and the second wafer, the first wafer and the second wafer are the first wafer 101 and the second wafer 301 bonded by dicing, wherein:
  • a plurality of back-illuminated avalanche photodiodes are formed on the first surface of the first wafer 101;
  • a plurality of signal processing units are formed on the first surface of the second wafer 301;
  • the first surface of the first wafer 101 and the first surface of the second wafer 301 are bonded to each other, and the back-illuminated avalanche photodiodes corresponding to the upper and lower sides and the signal processing unit are electrically connected to each other.
  • the material of the first wafer 101 may be Si, Ge, GaAs or InGaAs, which may be selected according to actual needs. It should be noted that the material of the first wafer 101 is not limited to this example.
  • the first wafer 101 includes a first surface and a second surface disposed opposite to each other, wherein the first surface is a front surface, and the second surface is a back surface.
  • a plurality of back-illuminated avalanche photodiodes are formed on the first surface to form a linear array or area array structure of avalanche photodiodes.
  • the plurality of back-illuminated avalanche photodiodes may be arranged in several rows or columns to form a linear array of back-illuminated avalanche photodiodes.
  • the plurality of backside illuminated avalanche photodiodes may also include an arrangement of several rows and several columns to form an area array of backside illuminated avalanche photodiodes.
  • the number of the back-illuminated avalanche photodiodes is not limited to a certain value range, and can be selected according to actual needs.
  • the avalanche photodiode is a back-illuminated device, that is, in the back-illuminated device, the back-illuminated avalanche photodiode is located in front of the circuit transistor, and light first enters the back-illuminated device Avalanche photodiode, thereby increasing the amount of light.
  • an electric field control layer and a graded layer may be further formed between the avalanche multiplication layer and the absorption layer.
  • the back-illuminated avalanche photodiode sequentially includes a p-InP buffer layer, a p-AlInAs diffusion barrier layer, a low-doped n-InP avalanche multiplication layer, and an n-InP electric field control layer from bottom to top. , n-InGaAsP graded layer, nInGaAs light absorption layer, semi-insulating InP window layer and InGaAs contact layer.
  • a plurality of first bonding pads 102 and a first dielectric layer 103 spaced apart from each other are further formed on the first surface of the first wafer 101 .
  • the first bonding pads 102 and the first dielectric layers 103 are alternately arranged, and the first dielectric layer 103 fills the gaps between the first bonding pads 102 .
  • the height of the first dielectric layer 103 is greater than the height of the first bonding pad 102 to prevent the temperature from rising during the bonding process, which may cause bonding due to the large thermal expansion coefficient of the first bonding pad 102 .
  • the first wafer and the second wafer that are together are separated.
  • the first dielectric layer 103 can use oxide or nitride, for example, the first dielectric layer 103 can use silicon dioxide (SiO 2 ), fluorocarbon (CF), silicon nitride (SiN), One or more of silicon oxycarbide (SiOC), or silicon carbonitride (SiCN).
  • SiO 2 silicon dioxide
  • CF fluorocarbon
  • SiN silicon nitride
  • SiOC silicon oxycarbide
  • SiCN silicon carbonitride
  • the material of the first bonding pad 102 is a metal material, and the metal material may be metal copper or aluminum. In an embodiment of the present application, the first bonding pad 102 is made of copper.
  • the material of the second wafer 301 may be Si, Ge, GaAs or InGaAs, which may be selected according to actual needs. It should be noted that the material of the second wafer 301 is not limited to this example.
  • the material of the first wafer 101 and the material of the second wafer 301 are the same.
  • the material of the first wafer 101 and the material of the second wafer 301 are both silicon.
  • the second wafer 301 includes a first surface and a second surface disposed opposite to each other, wherein the first surface is a front surface, and the second surface is a back surface.
  • a plurality of signal processing units are formed on the first surface for processing signals transmitted by the back-illuminated avalanche photodiode.
  • the signal processing unit is integrated with a plurality of circuits.
  • the signal processing unit is integrated with a transimpedance amplifier circuit (TIA circuit), a multi-stage operational amplifier OPA, a comparator, and a time-to-digital converter Circuit (circuit that converts time into digital signal) or analog-to-digital conversion circuit (ADC circuit), and subsequent data processing circuit (DSP circuit).
  • TIA circuit is an analog front-end circuit that converts the APD photocurrent into a voltage.
  • the APD when the plurality of back-illuminated avalanche photodiodes convert optical signals into current signals, an external high-voltage power supply is required, and the APD can provide stable internal gain and improve the signal-to-noise ratio, and output current signals.
  • the TIA circuit is electrically connected to the back-illuminated avalanche photodiode, and the TIA circuit converts the current signal of the APD into a voltage signal and provides a conversion gain at the same time; the multi-stage operational amplifier OPA is connected to the The TIA circuit is electrically connected to amplify the signal output by the TIA circuit to meet the comparison amplitude requirement of the comparator.
  • the comparator is electrically connected to the multi-stage operational amplifier OPA, wherein a comparison threshold is set in the comparator to trigger the analog signal, convert the analog signal into a digital signal, and transmit the signal to the TDC circuit, and the TDC circuit is used to convert the analog signal into a digital signal.
  • the digital signal is converted to a time signal for distance calculation.
  • one TDC circuit may be shared, that is, the number of signal processing units may not correspond to the number of TDC circuits.
  • a storage system may be further provided in the signal processing unit to cache data, provide input and output buffer space for the interface, and provide space for internal calculation.
  • An interface can be further set in the signal processing unit to serve as a data input and output channel to output the measurement data.
  • a plurality of second bonding pads 302 and a second dielectric layer 303 spaced apart from each other are further formed on the first surface of the second wafer 301 .
  • the second bonding pads 302 and the second dielectric layers 303 are alternately arranged, and the second dielectric layer 303 fills the gaps between the second bonding pads 302 .
  • the second dielectric layer 303 can use oxide or nitride, for example, the second dielectric layer 303 can use silicon dioxide (SiO 2 ), fluorocarbon (CF), silicon nitride (SiN), One or more of silicon oxycarbide (SiOC), or silicon carbonitride (SiCN).
  • SiO 2 silicon dioxide
  • CF fluorocarbon
  • SiN silicon nitride
  • SiOC silicon oxycarbide
  • SiCN silicon carbonitride
  • a number of interconnection structures are also formed in the second interlayers on the first surface of the second wafer 301 , and the interconnection structures include metal layers and through holes spaced up and down. Through the interconnection structures The second bonding pad 302 is electrically connected to the signal processing unit in the second wafer 301 .
  • connecting pads 304 are also formed in the edge region of the second wafer 301, so that after the bonded first wafer 101 and the second wafer 301 are cut, the edges of the corresponding second wafers
  • the connection pads 304 can be used to lead out the signals of the bonded structure.
  • the connection pads 304 are electrically connected to the pins of the packaging module to draw out electrical signals.
  • the height of the second dielectric layer 303 is greater than the height of the second bonding pad 302 to prevent the temperature from rising during the bonding process, which may cause bonding due to the large thermal expansion coefficient of the second bonding pad 302 .
  • the together first wafer 101 and the second wafer 301 are separated.
  • the material of the second bonding pad 302 is a metal material, and the metal material may be metal copper or aluminum. In an embodiment of the present application, the second bonding pad 302 is made of copper.
  • the first surface of the first wafer 101 and the first surface of the second wafer 301 are bonded to each other, and the back-illuminated avalanche photodiodes corresponding to the top and bottom are integrated with the signal processing unit.
  • the first dielectric layer 103 and the second dielectric layer 303 are bonded to each other; the first bonding pad 102 and the second bonding pad 302 are bonded to each other.
  • the first dielectric layer 103 and the second dielectric layer 303 are aligned, the first bonding pad 102 and the second bonding pad 302 are aligned at the same time, and then the first bonding pad 102 and the second bonding pad 302 are aligned at room temperature.
  • the first dielectric layer 103 and the second dielectric layer 303 are temporarily bonded.
  • the first bonding pad 102 and the second bonding pad 302 are bonded at high temperature, so that the first bonding pad 102 and the second bonding pad 302 are electrically connected to realize the first bonding Electrical connection of wafer 101 and second wafer 301 .
  • an annealing treatment is performed within a temperature range of 300° C. to 400° C. for about 2 hours to realize Cu-Cu bonding and realize the bonding between the first wafer and the second wafer.
  • the back-illuminated avalanche photodiode corresponding to the upper and lower sides and the signal processing unit are electrically connected to each other.
  • the thickness of the first wafer may be several micrometers to several tens of micrometers, wherein the quantum efficiency of the APD is positively correlated with the thickness of the first wafer, and can be selected according to the requirement of quantum efficiency.
  • a plurality of high-voltage signal electrodes 305 spaced apart from each other are formed on the second surface of the first wafer 101 .
  • the high-voltage signal electrode 305 is used as a high-voltage lead wire, and is disposed on the second surface of the first wafer 101 away from the signal processing unit of the second wafer 301, so as to prevent damage to the signal processing unit in the signal processing unit.
  • Each circuit has an influence, which further improves the performance of the receiving chip.
  • the material of the high-voltage signal electrode 305 can be selected from a metal material, such as Al, but is not limited to Al, and can also be selected from materials such as gold and copper.
  • a passivation layer 306 is formed on the second surface of the first wafer 101 to cover the photosensitive area 205 outside the high-voltage signal electrode to shield interference signals and improve the performance of the back-illuminated avalanche photodiode .
  • a plurality of microlenses 308 are also formed on the second surface of the first wafer 101 to condense the incident light incident on the back-illuminated avalanche photodiode to improve the efficiency of the incident light.
  • the material of the microlens 308 may be polyimide or silicon dioxide, but is not limited to the material, and the microlens has a shape similar to a convex lens.
  • a cavity is formed in the edge area between the first wafer 101 and the second wafer 301 and above the connection pads, and the connection pads 304 on the edge of the second wafer 301 are located at the below the cavity.
  • the edge of the first wafer 101 is cut to expose the connection pads on the edge of the second wafer for electrical connection in subsequent steps.
  • the receiving chip also includes a package module 309 including a base plate on the bottom and side plates on the base plate to surround and form a space for accommodating the first wafer and the second wafer.
  • each independent chip structure includes a plurality of back-illuminated avalanche photodiodes and signal processing units as described above, so as to realize their functions independently.
  • the substrate can be various types of substrates such as PCB substrates, ceramic substrates, etc., wherein the PCB is made of different components and a variety of complex process technologies, and the structure of the PCB circuit board has a single Layer, double layer, multi-layer structure, different hierarchical structures are made in different ways.
  • the printed circuit board is mainly composed of pads, vias, mounting holes, wires, components, connectors, padding, electrical boundaries, and the like.
  • the substrate described in this application can also be a ceramic substrate. or double-sided) on a special craft board.
  • the resulting ultra-thin composite substrate has excellent electrical insulation properties, high thermal conductivity, excellent solderability and high adhesion strength, and can be etched into various patterns like a PCB board, and has a large current carrying capacity. ability.
  • a first pin and a second pin are also arranged on the substrate, the high-voltage signal electrode 305 is electrically connected to the first pin of the package module; the connection pad 304 is connected to the package module The second pin is electrically connected.
  • the second wafer is mounted on the substrate and the accommodating space is filled with encapsulation glue to cover and fix the chip structure, while exposing the high-voltage signal electrodes 305 and the high-voltage signal electrodes 305 on the top of the first wafer.
  • the microlens 308 is described.
  • a top plate 311 is formed on the side plate to form a closed accommodating space, and at least part of the top plate 311 is a light-transmitting area.
  • the top plate 311 can be selected from commonly used light-transmitting materials, such as glass, and the glass must have high transmittance to light.
  • the top plate 311 may be a plate-like structure that is fully transparent, or may be a metal flat plate with a glass window.
  • the receiving chip (including the back-illuminated avalanche photodiode area array) described in this application does not scan the mechanical scanning lidar solution, but directly emits a large piece of laser covering the detection area in a short time, and then uses a highly sensitive It is a good solution for the receiver chip to complete the drawing of the image around the environment.
  • a third aspect of the present application also provides a ranging device.
  • the semiconductor device or receiver provided in each embodiment of the present application can be applied to the ranging device, and the ranging device can be an electronic device such as a laser radar or a laser ranging device.
  • the ranging device is used to sense external environmental information, for example, distance information, orientation information, reflection intensity information, speed information and the like of environmental objects.
  • the ranging device can detect the distance from the detected object to the ranging device by measuring the time of light propagation between the ranging device and the detected object, that is, Time-of-Flight (TOF).
  • TOF Time-of-Flight
  • the ranging device can also detect the distance from the detected object to the ranging device through other techniques, such as a ranging method based on phase shift measurement, or based on frequency shift
  • the ranging method for (frequency shift) measurement is not limited here.
  • the ranging device adopts the aforementioned receiving chip (including a back-illuminated avalanche photodiode area array), and the ranging device is a solid-state laser radar, which can be directly emitted in a short time and can cover the detection area.
  • the pulsed laser is then used to receive the echo signal with a highly sensitive area array receiver, and the detection and perception of the distance information of the surrounding environment are completed through a mode similar to a camera.
  • the ranging device may include a transmitting circuit, a receiving chip and an arithmetic circuit.
  • the receiving chip adopts a bonding method to realize the wafer-level integration of the back-illuminated avalanche photodiode and the signal processing unit, forming a back-illuminated avalanche photodiode area array chip.
  • the realization of the area array interconnection of the illuminated avalanche photodiode and the signal processing unit has better precision and better yield, and can further improve the performance of the receiving chip.
  • wafer-level integration can narrow the gap between back-illuminated avalanche photodiodes and make them denser. When applied to point clouds, the obtained point cloud density is higher, which can help identify smaller objects.
  • the ranging device using the receiving chip has higher precision and faster speed.
  • the transmit circuit may transmit a sequence of optical pulses (eg, a sequence of laser pulses).
  • the receiving chip can receive the optical pulse sequence reflected by the detected object, and output a time signal based on the received optical pulse sequence.
  • the arithmetic circuit can determine the distance between the distance measuring device and the detected object by the time signal.
  • the distance measuring device may further include a control circuit, which can control other circuits, for example, can control the working time of each circuit and/or set parameters for each circuit.
  • a control circuit which can control other circuits, for example, can control the working time of each circuit and/or set parameters for each circuit.
  • the distance and orientation detected by the ranging device can be used for remote sensing, obstacle avoidance, mapping, modeling, navigation, etc., such as realizing the perception of the surrounding environment, and performing two-dimensional or three-dimensional mapping of the external environment.
  • the distance measuring device of the embodiment of the present invention can be applied to the movable platform.
  • the present invention also provides a movable platform, wherein the aforementioned distance measuring device can be applied to the movable platform, and the distance measuring device can be installed on the movable platform body of the movable platform.
  • the movable platform includes at least one of an unmanned aerial vehicle, a car, a remote control car, a robot, and a camera.
  • the ranging device is applied to the unmanned aerial vehicle
  • the movable platform body is the fuselage of the unmanned aerial vehicle.
  • the movable platform body is the body of the automobile.
  • the vehicle may be an autonomous driving vehicle or a semi-autonomous driving vehicle, which is not limited herein.
  • the movable platform body is the body of the remote control car.
  • the movable platform body is the body of the robot.
  • the movable platform body is the body of the robot.
  • the ranging device is applied to the camera
  • the movable platform body is the body of the camera.
  • the movable platform may further include a power system for driving the movable platform body to move.
  • the power system may be an engine inside the vehicle, which will not be listed here.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or May be integrated into another device, or some features may be omitted, or not implemented.
  • Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all functions of some modules according to the embodiments of the present application.
  • DSP digital signal processor
  • the present application can also be implemented as a program of apparatus (eg, computer programs and computer program products) for performing part or all of the methods described herein.
  • Such a program implementing the present application may be stored on a computer-readable medium, or may be in the form of one or more signals. Such signals may be downloaded from Internet sites, or provided on carrier signals, or in any other form.

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Abstract

一种接收芯片及其制备方法、测距装置、可移动平台。所述制备方法包括：提供第一晶圆，所述第一晶圆的第一表面形成有多个背照式雪崩光电二极管；提供第二晶圆，所述第二晶圆的第一表面形成有多个信号处理单元；将所述第一晶圆的第一表面与所述第二晶圆的第一表面键合，以使上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。本申请所述芯片可以利用现有半导体制造平台和技术，大规模、低成本、高可靠性地生产出背照式雪崩光电二极管面阵芯片，以满足固态激光雷达的对接收模块的需求。

Description

一种接收芯片及其制备方法、测距装置、可移动平台
说明书
技术领域
本申请总地涉及半导体领域，更具体地涉及一种接收芯片及其制备方法、测距装置、可移动平台。
背景技术
激光雷达(测距装置)是以发射激光束探测目标的位置、速度等特征量的雷达系统。激光雷达的光敏传感器可以将获取到的光脉冲信号转变为电信号，基于比较器获取该电信号对应的时间信息，从而得到激光雷达与目标物之间的距离信息。
目前的激光雷达采用的都是机械旋转式激光雷达，机械旋转式激光雷达高昂的成本、不稳定的性能，让机械旋转式激光雷达难以跨越商业化量产的鸿沟。因此，固态激光雷达由于具有更小的尺寸、更低的成本，也因为其相较于机械转式激光雷更稳定的性能，更容易过车规，固态激光雷达(或称Flash雷达)一度被视为激光雷达的“终极未来”。
固态激光雷达是接收端芯片的良好方案，但固态激光雷达的核心，是面阵的接收端芯片。如64线雷达，需要64颗激光二极管(Laser diode)和64颗雪崩光电二极管(APD)，对于面阵的接收端芯片，大多是通过封装的手段，实现APD面阵的接收端芯片与信号处理电路的互联，造成耦合的问题较多，可靠性低的问题。
因此，需要对目前芯片进行改进，以克服上述问题。
发明内容
为了解决上述问题中的至少一个而提出了本申请。本申请第一方面提供了一种接收芯片的制备方法，所述制备方法包括：
提供第一晶圆，所述第一晶圆的第一表面形成有多个背照式雪崩光电 二极管；
提供第二晶圆，所述第二晶圆的第一表面形成有多个信号处理单元；
将所述第一晶圆的第一表面与所述第二晶圆的第一表面键合，以使上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
本申请的第二方面提供了一种接收芯片，所述接收芯片包括：
键合的第一晶片和第二晶片，所述第一晶片和所述第二晶片为通过切割键合后的第一晶圆和第二晶圆得到；其中：
所述第一晶圆的第一表面形成有多个背照式雪崩光电二极管；
所述第二晶圆的第一表面形成有多个信号处理单元；
所述第一晶圆的第一表面与所述第二晶圆的第一表面彼此相互接合，上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
本申请的第三方面提供了一种测距装置，所述测距装置包括：
光发射电路，用于出射激光脉冲信号；
前文所述的接收芯片，用于接收所述光发射电路出射的光脉冲序列经过被探测物反射的光脉冲序列，以及基于接收的光脉冲序列输出时间信号；
运算电路，用于根据所述时间信号计算所述被探测物与所述测距装置之间的距离。
本申请的第四方面提供了一种可移动平台，所述可移动平台包括:
可移动平台本体；
前文所述的测距装置，所述测距装置设于所述可移动平台本体上。
本申请提供了一种接收芯片及其制备方法，所述芯片采用键合的方式，实现背照式雪崩光电二极管和信号处理单元的晶圆级集成，形成了背照式雪崩光电二极管面阵芯片。本申请所述芯片可以利用现有半导体制造平台和技术，大规模、低成本、高可靠性地生产出背照式雪崩光电二极管面阵芯片，以满足固态激光雷达的对接收模块的需求。
附图说明
图1A-1C示出本申请提供的第一晶圆处理过程中各中间器件的剖面示意图；
图2A-2D示出本申请提供的第二晶圆处理过程中各中间器件的剖面 示意图；
图3A-3J示出本申请提供的接收芯片的制备过程中各中间器件的剖面示意图；
图4A-4D示出本申请另一实施例中提供的微透镜制备过程中各中间器件的剖面示意图；
图5示出本申请提供的接收芯片的制备方法的流程示意图。
具体实施方式
为了使得本申请的目的、技术方案和优点更为明显，下面将参照附图详细描述根据本申请的示例实施例。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是本申请的全部实施例，应理解，本申请不受这里描述的示例实施例的限制。基于本申请中描述的本申请实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本申请的保护范围之内。
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如 下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
为了解决前文所述的技术问题，本申请的第一方面提供了一种接收芯片的制备方法，如图5所示，所述制备方法具体包括以下步骤：
步骤S1：提供第一晶圆，所述第一晶圆的第一表面形成有多个背照式雪崩光电二极管；
步骤S2：提供第二晶圆，所述第二晶圆的第一表面形成有多个信号处理单元；
步骤S3：将所述第一晶圆的第一表面与所述第二晶圆的第一表面键合，以使上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
下面结合附图图1A-1C、图2A-2D以及图3A-3J对所述制备方法进行详细的说明，其中，图1A-1C示出本申请提供的第一晶圆处理过程中各中间器件的剖面示意图；图2A-2D示出本申请提供的第二晶圆处理过程中各中间器件的剖面示意图；图3A-3J示出本申请提供的接收芯片的制备过程中各中间器件的剖面示意图。
在所述步骤S1中，如图1A所示，所述第一晶圆101的材料可以为Si，Ge，GaAs或InGaAs，可以根据实际需要进行选择，需要说明的是所述第一晶圆101的材料并不局限于该示例。
其中，所述第一晶圆101包括相对设置的第一表面和第二表面，其中，所述第一表面为正面，所述第二表面为背面。
在所述第一表面上形成有多个背照式雪崩光电二极管(未示出)，以形成雪崩光电二极管的线阵或面阵结构。其中，所述多个背照式雪崩光电二极管可以包括若干行或若干列的排列，以形成背照式雪崩光电二极管的线阵。此外，所述多个背照式雪崩光电二极管还可以包括若干行和若干列的排列，以形成背照式雪崩光电二极管的面阵。所述背照式雪崩光电二极管的数目并不局限于某一数值范围，可以根据实际需要进行选择。
需要说明的是，所述多个背照式雪崩光电二极管形成的阵列除了线阵和面阵之外，还可以为其他形式的排列，并不局限于线阵和面阵，也可以是非规则方式的排列等，可以根据实际需要进行设置。
在本申请的一实施例中，所述半导体器件为背照式器件，即在所述背 照式器件中，所述感光器件APD位于电路晶体管前方的位置，光线首先进入感光器件APD，从而增大感光量。
所述背照式雪崩光电二极管的形成方法可以包括：在所述第一晶圆101的第一表面或第一表面的外延层上执行离子注入工艺，以由下往上依次形成背照式雪崩光电二极管的各功能区域，所述背照式雪崩光电二极管的各功能区域包括缓冲层、扩散阻挡层、雪崩倍增层、吸收层和接触层。
进一步，在所述雪崩倍增层和所述吸收层之间还可以进一步形成电场控制层和渐变层。
在本申请的一实施例中，背照式雪崩光电二极管由下往上依次包括p-InP缓冲层、p-AlInAs扩散阻挡层、低掺杂n-InP雪崩倍增层、n-InP电场控制层、n-InGaAsP渐变层、nInGaAs光吸收层、半绝缘InP窗口层和InGaAs接触层。
其中，所述背照式雪崩光电二极管的各功能层的掺杂浓度和厚度可以为常规的掺杂浓度和厚度，在此不再一一列举。
如图1A所示，在所述第一晶圆101的第一表面还形成有多个相互间隔的第一接合焊盘102和第一介质层103。其中所述第一接合焊盘102和所述第一介质层103交替设置，所述第一介质层103填充所述第一接合焊盘102之间的间隙。
其中，所述第一介质层103的高度大于所述第一接合焊盘102的高度，以避免在键合过程中温度升高，由于第一接合焊盘102的热膨胀系数大，而造成键合在一起的第一晶圆101和第二晶圆分开。
其中，所述第一接合焊盘102的材料为金属材料，所述金属材料可以为金属铜或铝，在本申请的一实施例中所述第一接合焊盘102采用铜。
其中，所述第一介质层103可以使用氧化物或者氮化物，例如所述第一介质层103可以使用例如二氧化硅(SiO 2)、碳氟化合物(CF)、氮化硅(SiN)、掺碳氧化硅(SiOC)、或碳氮化硅(SiCN)中的一种或多种。
在所述步骤S2中，如图2A所示，所述第二晶圆301的材料可以为Si，Ge，GaAs或InGaAs，可以根据实际需要进行选择，需要说明的是所述第二晶圆301的材料并不局限于该示例。
其中，所述第一晶圆101的材料和第二晶圆301的材料相同，例如在本申请的一实施例中，所述第一晶圆101的材料和第二晶圆301均为硅。
其中，所述第二晶圆301包括相对设置的第一表面和第二表面，其中，所述第一表面为正面，所述第二表面为背面。
在所述第一表面上形成有多个信号处理单元，以用来处理所述背照式雪崩光电二极管传输的信号。
所述信号处理单元集成有多个电路，在本申请的一实施例中，例如所述信号处理单元集成有跨阻放大器电路(TIA电路)、多级运算放大器OPA、比较器以及时间数字转换器电路(时间转化为数字信号的电路)或模数转换电路(ADC电路)，以及后续的数据处理电路(DSP电路)。其中，TIA电路为APD光电流转化为电压的模拟前段电路。
其中，所述多个背照式雪崩光电二极管在将光信号转换为电流信号时，需要外部高压供电，APD可以提供稳定的内部增益并提高信噪比，输出电流信号。
在所述信号处理单元中，所述TIA电路与所述背照式雪崩光电二极管电连接，所述TIA电路将APD的电流信号转换为电压信号，同时提供转换增益；多级运算放大器OPA与所述TIA电路电连接，用于对TIA电路输出的信号进行放大，以满足比较器的比较幅值需求。所述比较器与所述多级运算放大器OPA电连接，其中，比较器中设置比较阈值对模拟信号进行触发，将模拟信号转换为数字信号，并将信号传输至TDC电路，TDC电路用于将数字信号转换为时间信号，用于距离计算。其中，对于多个信号处理单元而言，可以共用一个TDC电路，也即，信号处理单元的数量与TDC电路的数量可以不对应。
在所述信号处理单元中还可以进一步设置存储系统，以缓存数据，为接口提供输入输出缓存空间，为内部计算提供空间。
在所述信号处理单元中还可以进一步设置接口，以作为数据输入输出通道，将测量数据输出。
其中，如图2A所示，在所述第二晶圆301的第一表面还形成有多个相互间隔的第二接合焊盘302和第二介质层303。其中所述第二接合焊盘302和第二介质层303交替设置，第二介质层303填充所述第二接合焊盘 302之间的间隙。
在所述第二晶圆301的第一表面的所述第二层间中还形成有若干互连结构，所述互连结构包括上下间隔设置的金属层和通孔，通过所述互连结构将所述第二接合焊盘302与所述第二晶圆301中的所述信号处理单元电连接。
进一步，在所述第二晶圆301的边缘区域还形成有连接焊盘304，以用于将第一晶圆101和第二晶圆301键合后得到的结构的信号引出。例如在进行封装时，将所述连接焊盘304与封装模块的引脚电连接，以引出电信号。
其中，所述第二介质层303的高度大于所述第二接合焊盘302的高度，以避免在键合过程中温度升高，由于第二接合焊盘302的热膨胀系数大，而造成键合在一起的第一晶圆101和第二晶圆301分开。
其中，所述第二接合焊盘302的材料为金属材料，所述金属材料可以为金属铜或铝，在本申请的一实施例中所述第二接合焊盘302采用铜。
其中，所述第二介质层303可以使用氧化物或者氮化物，例如所述第二介质层303可以使用例如二氧化硅(SiO 2)、碳氟化合物(CF)、氮化硅(SiN)、掺碳氧化硅(SiOC)、或碳氮化硅(SiCN)中的一种或多种。
在所述步骤S3中，将所述第一晶圆101的第一表面与所述第二晶圆301的第一表面键合，以将上下对应的所述背照式雪崩光电二极管与所述信号处理单元集成为一体。
具体地，在将第一晶圆101的第一表面与所述第二晶圆301的第一表面键合之前，需要对所述第一晶圆101的第一表面与所述第二晶圆301的第一表面进行处理，以增加键合强度，具体地：
分别对第一晶圆101的第一表面与所述第二晶圆301的第一表面进行等离子体表面处理，以活化所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303的表面，进而使所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303的表面未成键的原子更加容易形成共价键。
在本申请的一实施例中，如图1B和图2B所示，选用O 2等离子体分 别对所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303的表面进行表面处理，除了O 2等离子体之外，还可以选用含氧的气体，例如二氧化氮，二氧化硅等，并不局限于某一种。
在所述等离子体表面处理之后，还包括分别对所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303的表面进行清洗步骤，以改变所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303表面的电荷特性。
例如在本申请的一实施例中，如图1C和图2C所示，在对所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303进行O 2等离子体表面处理之后，再用去离子水进行清洗之后，会在所述第一接合焊盘102、所述第二接合焊盘302、所述第一介质层103和所述第二介质层303表面形成带负电荷的OH -，以进行键合。
在键合时，首先将所述第一介质层103和所述第二介质层303对准，同时将第一接合焊盘102、所述第二接合焊盘302对准，然后在室温下先将所述第一介质层103和所述第二介质层303临时键合。
在将所述第一介质层103和所述第二介质层303临时键合之后，再执行高温退火处理，以使所述第一接合焊盘102、所述第二接合焊盘302进行高温键合，以使所述第一接合焊盘102、所述第二接合焊盘302形成电连接，如图3A所示，实现第一晶圆101和第二晶圆301的电气连接。
在本申请的一实施例中，在温度为300℃～400℃的范围内执行2小时左右退火处理，以实现Cu-Cu键合，使上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
在将所述第一晶圆101与所述第二晶圆301键合之后，所述方法还包括：
对所述第一晶圆101执行减薄工艺，以在所述第二表面减小所述第一晶圆101的厚度，如图3B所示，其中，所述减薄工艺可以包括化学机械掩膜、平坦化处理以及抛光中的一种或者组合。在减薄之后所述第一晶圆101的厚度可以为几微米到几十微米，其厚度可以根据实际需要进行选择，并不局限于某一数值范围。其中，APD的量子效率与所述第一晶圆101的厚度呈正相关，则第一晶圆101的厚度可以根据量子效率的需要进行选 择。
在所述减薄工艺之后，所述制备方法还包括在所述第一晶圆101的第二表面形成多个相互间隔的高压信号电极305的步骤。所述高压信号电极305作为高压引出线，设置于远离所述第二晶圆301的所述信号处理单元第一晶圆101的第二表面，以防止对所述信号处理单元中的各个电路造成影响，进一步提高所述接收芯片的性能。
其中，所述高压信号电极305的形成方法包括：在所述第一晶圆101的第二表面沉积电极材料层，然后蚀刻所述电极材料层，以形成若干相互间隔的所述高压信号电极305，如图3C所示。
其中，所述高压信号电极305的材料可以选用金属材料，例如Al，但并不局限于Al，还可以选用金，铜等材料。
所述方法进一步包括：在所述第一晶圆101的第二表面上形成钝化层306，如图3D所示，以覆盖所述高压信号电极之外305的光敏区，以屏蔽干扰信号，提高所述背照式雪崩光电二极管的性能。
在形成所述钝化层306之后，所述方法还进一步包括在所述第一晶圆101的第二表面上形成多个微透镜308，以对入射至所述背照式雪崩光电二极管的入射光进行汇聚，提高入射光效率。
其中，所述微透镜308的形成方法跟选用的材料有关，当所述微透镜308的材料选用可回流的材料时，可以选用以下方法形成所述微透镜308：
在所述第一晶圆101的第二表面上形成透镜材料层307，其中，所述透镜材料层可以为聚酰亚胺，但并不局限于所述材料；
然后图案化所述透镜材料层307，以保留所述高压信号电极305之间的所述钝化层306上的所述透镜材料层307，如图3E所示，其中，所述图案化方法包括首先在所述透镜材料层上形成掩膜层，然后以所述掩膜层为掩膜蚀刻所述透镜材料层307；
最后执行回流工艺，以使所述透镜材料层307回流形成具有球形凸起表面的所述微透镜308，如图3F所示，其中所述微透镜类似凸透镜的形状。
该实施例中，所述微透镜308的工艺流程更加简单，仅通过光刻和回流步骤即可完成。
在本申请的另一实施例中，所述微透镜308还可以通过下述方法形成：
如图4A所示，在所述第一晶圆101的第二表面上形成透镜材料层307，以覆盖所述高压信号电极305。
在所述透镜材料层307上形成掩膜层312，其中，所述掩膜层312可以为光刻胶或其他可回流的材料，并不局限于某一种；
如图4B所示，图案化所述掩膜层312，以保留所述高压信号电极305之间的所述钝化层306上的所述掩膜层312，在本申请的一实施例中，所述掩膜层312为光刻胶时，可以对所述光刻胶进行曝光，显影，以在目标位置形成所述光刻胶的图案；
如图4C所示，执行回流工艺，以使所述掩膜层312回流形成微透镜图案；
如图4D所示，在形成微透镜图案之后，以所述微透镜图案为掩膜蚀刻所述透镜材料层312，以将图案转移至所述透镜材料层，进而形成所述微透镜308。
在该实施例中，所述透镜材料层为氧化硅。其中，二氧化硅的折射率更高，制备得到的微透镜的汇聚效果更好。
在所述第一晶圆101和所述第二晶圆301之间的边缘区域、所述连接焊盘的上方形成有空腔，所述第二晶圆301的边缘的连接焊盘位于所述空腔的下方。
在所述第一晶圆101和所述第二晶圆301键合之后，在进行封装之前，所述方法还包括：对所述第一晶圆101的边缘进行切割，以去除所述第一晶圆101的边缘区域，以露出所述第二晶圆301边缘的所述连接焊盘304，以在后续的步骤中进行电连接，如图3G所示。
在该步骤中，去除所述第一晶圆101的边缘区域之前，在所述第二晶圆301的边缘形成保护层，如图2D中箭头部分所示，以覆盖所述连接焊盘304，以防止在切割过程中掉落的杂质划伤所述第二晶圆301，对所述第二晶圆301造成损害。
其中，所述保护层可以为所述第二介质层303的一部分，例如所述第二介质层303的高度高于所述连接焊盘304，以覆盖所述连接焊盘304，进而作为所述保护层防止切割过程中掉落的杂质划伤所述连接焊盘304。
其中，在去除所述第一晶圆101的边缘区域之后，所述方法还包括去 除所述保护层的步骤，以露出所述连接焊盘304。在该步骤中，选用与所述第二晶圆301蚀刻选择比大的方法去除所述保护层。
所述方法还包括对键合后的第一晶圆101和第二晶圆301，在去除第一晶圆101的边缘区域之后进行封装，例如将该结构封装于封装模块309中，如图3H所示，所述封装模块309包括位于底部的基板和位于基板上的侧板，以围绕形成所述容纳空间。
在进行封装之前，还包括对所述键合后的第一晶圆101和第二晶圆301，在去除第一晶圆101的边缘区域之后进行切割，以得到多个独立的芯片结构，并将各个独立的芯片结构固定于封装模块的容纳空间中，以得到接收芯片。其中，在每个独立的芯片结构中均包含前文所述的多个背照式雪崩光电二极管和信号处理单元，以独立的实现其功能。
其中，所述基板可以为印刷电路板PCB基板、陶瓷基板等各种类型的基板，其中，所述PCB由不同的元器件和多种复杂的工艺技术处理等制作而成，其中PCB线路板的结构有单层、双层、多层结构，不同的层次结构其制作方式是不同的。
可选地，印刷电路板主要由焊盘、过孔、安装孔、导线、元器件、接插件、填充、电气边界等组成。
进一步，印刷电路板常见的板层结构包括单层板(Single Layer PCB)、双层板(Double Layer PCB)和多层板(Multi Layer PCB)三种，其具体结构如下所述：
(1)单层板：即只有一面敷铜而另一面没有敷铜的电路板。通常元器件放置在没有敷铜的一面，敷铜的一面主要用于布线和焊接。
(2)双层板：即两个面都敷铜的电路板，通常称一面为顶层(Top Layer)，另一面为底层(Bottom Layer)。一般将顶层作为放置元器件面，底层作为元器件焊接面。
(3)多层板：即包含多个工作层面的电路板，除了顶层和底层外还包含若干个中间层，通常中间层可作为导线层、信号层、电源层、接地层等。层与层之间相互绝缘，层与层的连接通常通过过孔来实现。
其中，印刷电路板包括许多类型的工作层面，如信号层、防护层、丝印层、内部层等，在此不再赘述。
此外，在本申请中所述基板还可以选用陶瓷基板，陶瓷基板是指铜箔在高温下直接键合到氧化铝(Al 2O 3)或氮化铝(AlN)陶瓷基片表面(单面或双面)上的特殊工艺板。所制成的超薄复合基板具有优良电绝缘性能，高导热特性，优异的软钎焊性和高的附着强度，并可像PCB板一样能刻蚀出各种图形，具有很大的载流能力。
其中，在所述基板上还设置有第一引脚和第二引脚，在封装时，将所述高压信号电极305与所述封装模块的第一引脚电连接；将所述连接焊盘304与所述封装模块的第二引脚电连接。
具体地，如图3H所示，在封装过程中，将所述接收芯片结构中对应第二晶圆301的表面贴装于所述基板上；然后在所述容纳空间内执行灌胶工艺，以形成密封胶310，覆盖并固定所述芯片结构，同时露出所述芯片结构中对应第一晶圆101的表面的所述高压信号电极305和所述微透镜308，如图3I所示。
其中，可以选用防水胶填充所述容纳空间，在灌胶之前，还可以进一步包括对所述接收芯片中对应第二晶圆305的表面进行清洁的步骤。
其中，在所述侧板上形成顶板311，以形成密闭的容纳空间，如图3J所示，所述顶板311中至少有部分区域为透光区域。
其中，所述顶板可以选用常用的透光材料，例如玻璃，所述玻璃必须是对光具有的高通过性。
可选地，所述顶板311可以为全部透光的板状结构，还可以为带玻璃窗口的金属平板。
本申请提供了一种接收芯片的制备方法，采用键合的方式，实现背照式雪崩光电二极管和信号处理单元的晶圆级集成，形成了背照式雪崩光电二极管面阵芯片，通过晶圆级集成的方法，可以实现照式雪崩光电二极管和信号处理单元的面阵互连，其精度更好，良率更好，可进一步提高接收芯片的性能。此外，晶圆级集成能够缩小背照式雪崩光电二极管之间的间隙，更加密集，当应用于点云时，获取的点云密度较高，能够有利于识别更小的物体。
本申请所述接收芯片可以利用现有半导体制造平台和技术，大规模、低成本、高可靠性地生产出背照式雪崩光电二极管面阵芯片，以满足固态 激光雷达的对接收模块的需求。
本申请的第二方面提供了一种接收芯片，如图3J所示，所述接收芯片包括：
键合的第一晶片和第二晶片，所述第一晶片和所述第二晶片为通过切割接合后的第一晶圆101和第二晶圆301，其中：
所述第一晶圆101的第一表面形成有多个背照式雪崩光电二极管；
所述第二晶圆301的第一表面形成有多个信号处理单元；
其中，所述第一晶圆101的第一表面与所述第二晶圆301的第一表面彼此相互接合，上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
下面结合附图对所述接收芯片详细的说明。其中，所述第一晶圆101的材料可以为Si，Ge，GaAs或InGaAs，可以根据实际需要进行选择，需要说明的是所述第一晶圆101的材料并不局限于该示例。
其中，所述第一晶圆101包括相对设置的第一表面和第二表面，其中，所述第一表面为正面，所述第二表面为背面。
在所述第一表面上形成有多个背照式雪崩光电二极管，以形成雪崩光电二极管的线阵或面阵结构。其中，所述多个背照式雪崩光电二极管可以包括若干行或若干列的排列，以形成背照式雪崩光电二极管的线阵。此外，所述多个背照式雪崩光电二极管还可以包括若干行和若干列的排列，以形成背照式雪崩光电二极管的面阵。所述背照式雪崩光电二极管的数目并不局限于某一数值范围，可以根据实际需要进行选择。
在本申请的一实施例中，所述雪崩光电二极管为背照式器件，即在所述背照式器件中所述背照式雪崩光电二极管位于电路晶体管前方的位置，光线首先进入背照式雪崩光电二极管，从而增大感光量。
进一步，在所述雪崩倍增层和所述吸收层之间还可以进一步形成电场控制层和渐变层。
在本申请的一实施例中，背照式雪崩光电二极管由下往上依次包括p-InP缓冲层、p-AlInAs扩散阻挡层、低掺杂n-InP雪崩倍增层、n-InP电场控制层、n-InGaAsP渐变层、nInGaAs光吸收层、半绝缘InP窗口层和InGaAs接触层。
在所述第一晶圆101的第一表面还形成有多个相互间隔的第一接合焊盘102和第一介质层103。其中所述第一接合焊盘102和所述第一介质层103相互交替设置，所述第一介质层103填充所述第一接合焊盘102之间的间隙。
其中，所述第一介质层103的高度大于所述第一接合焊盘102的高度，以避免在键合过程中温度升高，由于第一接合焊盘102的热膨胀系数大，而造成键合在一起的第一晶圆和第二晶圆分开。
其中，所述第一介质层103可以使用氧化物或者氮化物，例如所述第一介质层103可以使用例如二氧化硅(SiO 2)、碳氟化合物(CF)、氮化硅(SiN)、掺碳氧化硅(SiOC)、或碳氮化硅(SiCN)中的一种或多种。
其中，所述第一接合焊盘102的材料为金属材料，所述金属材料可以为金属铜或铝，在本申请的一实施例中所述第一接合焊盘102采用铜。
所述第二晶圆301的材料可以为Si，Ge，GaAs或InGaAs，可以根据实际需要进行选择，需要说明的是所述第二晶圆301的材料并不局限于该示例。其中，所述第一晶圆101的材料和第二晶圆301的材料相同，例如在本申请的一实施例中，所述第一晶圆101的材料和第二晶圆301均为硅。
其中，所述第二晶圆301包括相对设置的第一表面和第二表面，其中，所述第一表面为正面，所述第二表面为背面。
在所述第一表面上形成有多个信号处理单元，以用来处理所述背照式雪崩光电二极管传输的信号。
所述信号处理单元集成有多个电路，在本申请的一实施例中，例如所述信号处理单元集成有跨阻放大器电路(TIA电路)、多级运算放大器OPA、比较器以及时间数字转换器电路(时间转化为数字信号的电路)或模数转换电路(ADC电路)，以及后续的数据处理电路(DSP电路)。其中，TIA电路为APD光电流转化为电压的模拟前段电路。
其中，所述多个背照式雪崩光电二极管在将光信号转换为电流信号时，需要外部高压供电，APD可以提供稳定的内部增益并提高信噪比，输出电流信号。
在所述信号处理单元中，所述TIA电路与所述背照式雪崩光电二极管电连接，所述TIA电路将APD的电流信号转换为电压信号，同时提供转 换增益；多级运算放大器OPA与所述TIA电路电连接，用于对TIA电路输出的信号进行放大，以满足比较器的比较幅值需求。所述比较器与所述多级运算放大器OPA电连接，其中，比较器中设置比较阈值对模拟信号进行触发，将模拟信号转换为数字信号，并将信号传输至TDC电路，TDC电路用于将数字信号转换为时间信号，用于距离计算。其中，对于多个信号处理单元而言，可以共用一个TDC电路，也即，信号处理单元的数量与TDC电路的数量可以不对应。
在所述信号处理单元中还可以进一步设置存储系统，以缓存数据，为接口提供输入输出缓存空间，为内部计算提供空间。
在所述信号处理单元中还可以进一步设置接口，以作为数据输入输出通道，将测量数据输出。
其中，在所述第二晶圆301的第一表面还形成有多个相互间隔的第二接合焊盘302和第二介质层303。其中所述第二接合焊盘302和第二介质层303相互交替设置，第二介质层303填充所述第二接合焊盘302之间的间隙。
其中，所述第二介质层303可以使用氧化物或者氮化物，例如所述第二介质层303可以使用例如二氧化硅(SiO 2)、碳氟化合物(CF)、氮化硅(SiN)、掺碳氧化硅(SiOC)、或碳氮化硅(SiCN)中的一种或多种。
在所述第二晶圆301的第一表面的所述第二层间中还形成有若干互连结构，所述互连结构包括上下间隔设置的金属层和通孔，通过所述互连结构将所述第二接合焊盘302与所述第二晶圆301中的所述信号处理单元电连接。
进一步，在所述第二晶圆301的边缘区域还形成有连接焊盘304，以使得在键合后的第一晶圆101和第二晶圆301切割后，对应的第二晶片的边缘的连接焊盘304可以用于将键合后的结构的信号引出。例如在进行封装时，将所述连接焊盘304与封装模块的引脚电连接，以引出电信号。
其中，所述第二介质层303的高度大于所述第二接合焊盘302的高度，以避免在键合过程中温度升高，由于第二接合焊盘302的热膨胀系数大，而造成键合在一起的第一晶圆101和第二晶圆301分开。
其中，所述第二接合焊盘302的材料为金属材料，所述金属材料可以 为金属铜或铝，在本申请的一实施例中所述第二接合焊盘302采用铜。
其中，所述第一晶圆101的第一表面与所述第二晶圆301的第一表面相互键合，上下对应的所述背照式雪崩光电二极管与所述信号处理单元集成为一体。
其中，所述第一介质层103与所述第二介质层303相互键合；所述第一接合焊盘102与所述第二接合焊盘302相互键合。
在键合时，将所述第一介质层103和所述第二介质层303对准，同时将第一接合焊盘102、所述第二接合焊盘302对准，然后在室温下先将所述第一介质层103和所述第二介质层303临时键合。
所述第一接合焊盘102、所述第二接合焊盘302之间为高温键合，以使所述第一接合焊盘102、所述第二接合焊盘302形成电连接，实现第一晶圆101和第二晶圆301的电气连接。
在本申请的一实施例中，在温度为300℃～400℃的范围内执行2小时左右退火处理，以实现Cu-Cu键合，实现所述第一晶圆和第二晶圆之间的电气连接，使上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
其中，所述第一晶圆的厚度可以为几微米到几十微米，其中，APD的量子效率与所述第一晶圆的厚度呈正相关，可以根据量子效率的需要进行选择。
在所述第一晶圆101的第二表面形成有多个相互间隔的高压信号电极305。所述高压信号电极305作为高压引出线，设置于远离所述第二晶圆301的所述信号处理单元的所述第一晶圆101的第二表面，以防止对所述信号处理单元中的各个电路造成影响，进一步提高所述接收芯片的性能。
其中，所述高压信号电极305的材料可以选用金属材料，例如Al，但并不局限于Al，还可以选用金，铜等材料。
在所述第一晶圆101的第二表面上形成有钝化层306，以覆盖所述高压信号电极之外205的光敏区，以屏蔽干扰信号，提高所述背照式雪崩光电二极管的性能。
在所述第一晶圆101的第二表面上还形成有多个微透镜308，以对入射至所述背照式雪崩光电二极管的入射光进行汇聚，提高入射光效率。
所述微透镜308的材料可以为聚酰亚胺或二氧化硅，但并不局限于所述材料，所述微透镜类似凸透镜的形状。
在所述第一晶圆101和所述第二晶圆301之间的边缘区域、所述连接焊盘的上方形成有空腔，所述第二晶圆301的边缘的连接焊盘304位于所述空腔的下方。
所述第一晶圆101的边缘进行了切割，以露出所述第二晶圆边缘的所述连接焊盘，以在后续的步骤中进行电连接。
所述接收芯片还包括封装模块309，所述封装模块309包括位于底部的基板和位于基板上的侧板，以围绕形成容纳第一晶片和第二晶片的空间。
在进行封装之前，还包括对所述键合后的第一晶圆101和第二晶圆301进行切割，以得到多个独立的芯片结构，也即键合后的第一晶片和第二晶片。其中，在每个独立的芯片结构中均包含前文所述的多个背照式雪崩光电二极管和信号处理单元，以独立的实现其功能。
其中，所述基板可以为PCB基板、陶瓷基板等各种类型的基板，其中，所述PCB由不同的元器件和多种复杂的工艺技术处理等制作而成，其中PCB线路板的结构有单层、双层、多层结构，不同的层次结构其制作方式是不同的。
可选地，印刷电路板主要由焊盘、过孔、安装孔、导线、元器件、接插件、填充、电气边界等组成。
此外，在本申请中所述基板还可以选用陶瓷基板，陶瓷基板是指铜箔在高温下直接键合到氧化铝(Al 2O 3)或氮化铝(AlN)陶瓷基片表面(单面或双面)上的特殊工艺板。所制成的超薄复合基板具有优良电绝缘性能，高导热特性，优异的软钎焊性和高的附着强度，并可像PCB板一样能刻蚀出各种图形，具有很大的载流能力。
其中，在所述基板上还设置有第一引脚和第二引脚，所述高压信号电极305与所述封装模块的第一引脚电连接；所述连接焊盘304与所述封装模块的第二引脚电连接。
所述第二晶片贴装于所述基板上并且在所述容纳空间内填充了封装胶，以覆盖并固定所述芯片结构，同时露出所述第一晶片顶部的所述高压信号电极305和所述微透镜308。
其中，在所述侧板上形成顶板311，以形成密闭的容纳空间，所述顶板311中至少有部分区域为透光区域。
其中，所述顶板311可以选用常用的透光材料，例如玻璃，所述玻璃必须是对光具有的高通过性。
可选地，所述顶板311可以为全部透光的板状结构，还可以为带玻璃窗口的金属平板。
本申请所述接收芯片(包含背照式雪崩光电二极管面阵)不像机械式扫描激光雷达的方案会去进行扫描，而是短时间直接发射出一大片覆盖探测区域的激光，再以高度灵敏的面阵接收器，来完成对环境周围图像的绘制，是接收端芯片的良好方案。
本申请第三方面还提供了一种测距装置，本申请各个实施例提供的半导体器件或接收器可以应用于测距装置，该测距装置可以是激光雷达、激光测距设备等电子设备。在一种实施方式中，测距装置用于感测外部环境信息，例如，环境目标的距离信息、方位信息、反射强度信息、速度信息等。一种实现方式中，测距装置可以通过测量测距装置和探测物之间光传播的时间，即光飞行时间(Time-of-Flight，TOF)，来探测探测物到测距装置的距离。或者，测距装置也可以通过其他技术来探测探测物到测距装置的距离，例如基于相位移动(phase shift)测量的测距方法，或者基于频率移动
(frequency shift)测量的测距方法，在此不做限制。
所述测距装置采用了前文所述的接收芯片(包含背照式雪崩光电二极管面阵)，所述测距装置为固态激光雷达，所述固态激光雷达可以短时间直接发射出可以覆盖探测区域的脉冲激光，再以高度灵敏的面阵接收器，进行回波信号的接收，通过类似相机拍照的模式，完成对周围环境距离信息的探测和感知。
为了便于理解，以下将测距装置对测距的工作流程进行举例描述。
测距装置可以包括发射电路、接收芯片和运算电路。其中，所述接收芯片采用键合的方式，实现背照式雪崩光电二极管和信号处理单元的晶圆级集成，形成了背照式雪崩光电二极管面阵芯片，通过晶圆级集成的方法，可以实现照式雪崩光电二极管和信号处理单元的面阵互连，其精度更好，良率更好，可进一步提高接收芯片的性能。此外，晶圆级集成能够缩小背 照式雪崩光电二极管之间的间隙，更加密集，当应用于点云时，获取的点云密度较高，能够有利于识别更小的物体。采用所述接收芯片的测距装置具有更高的精度和更快的速度。
发射电路可以发射光脉冲序列(例如激光脉冲序列)。所述接收芯片可以接收光发射电路出射的光脉冲序列经过被探测物反射的光脉冲序列，以及基于接收的光脉冲序列输出时间信号。运算电路可以时间信号确定测距装置与被探测物之间的距离。
可选地，该测距装置还可以包括控制电路，该控制电路可以实现对其他电路的控制，例如，可以控制各个电路的工作时间和/或对各个电路进行参数设置等。
测距装置探测到的距离和方位可以用于遥感、避障、测绘、建模、导航等，如实现对周围环境的感知，对外部环境进行二维或三维的测绘。在一种实施方式中，本发明实施方式的测距装置可应用于所述可移动平台。
基于此，本发明还提供了一种可移动平台，其中前文所述的测距装置可应用于所述可移动平台，测距装置可安装在可移动平台的可移动平台本体。
在某些实施方式中，可移动平台包括无人飞行器、汽车、遥控车、机器人、相机中的至少一种。当测距装置应用于无人飞行器时，可移动平台本体为无人飞行器的机身。当测距装置应用于汽车时，可移动平台本体为汽车的车身。该汽车可以是自动驾驶汽车或者半自动驾驶汽车，在此不做限制。当测距装置应用于遥控车时，可移动平台本体为遥控车的车身。当测距装置应用于机器人时，可移动平台本体为机器人的机身。当测距装置应用于相机时，可移动平台本体为相机的机身。
在一些实施例中，所述可移动平台还可以进一步包括动力系统，用于驱动所述可移动平台本体移动。例如，当所述可移动平台为车辆时，所述动力系统可以为车辆内部的发动机，在此不再一一列举。
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本申请的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本申请的范围和精神。所有 这些改变和修改意在被包括在所附权利要求所要求的本申请的范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本申请并帮助理解各个发明方面中的一个或多个，在对本申请的示例性实施例的描述中，本申请的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该本申请的方法解释成反映如下意图：即所要求保护的本申请要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如相应的权利要求书所反映的那样，其发明点在于可以用少于某个公开的单个实施例的所有特征的特征来解决相应的技术问题。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本申请的单独实施例。
本领域的技术人员可以理解，除了特征之间相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括 其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本申请的范围之内并且形成不同的实施例。例如，在权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
本申请的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本申请实施例的一些模块的一些或者全部功能。本申请还可以实现为用于执行这里所描述的方法的一部分或者全部的装置程序(例如，计算机程序和计算机程序产品)。这样的实现本申请的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
应该注意的是上述实施例对本申请进行说明而不是对本申请进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。本申请可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上所述，仅为本申请的具体实施方式或对具体实施方式的说明，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。本申请的保护范围应以权利要求的保护范围为准。

Claims (31)

  1. 一种接收芯片的制备方法，其特征在于，所述制备方法包括：
    提供第一晶圆，所述第一晶圆的第一表面形成有多个背照式雪崩光电二极管；
    提供第二晶圆，所述第二晶圆的第一表面形成有多个信号处理单元；
    将所述第一晶圆的第一表面与所述第二晶圆的第一表面键合，以使上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
  2. 根据权利要求1所述的制备方法，其特征在于，所述第一晶圆的第一表面还形成有多个相互间隔的第一接合焊盘和填充所述第一接合焊盘之间间隙的第一介质层；
    所述第二晶圆上还形成有多个相互间隔的第二接合焊盘和填充所述第二接合焊盘之间间隙的第二介质层；
    先将所述第一介质层与所述第二介质层键合；
    再将所述第一接合焊盘与所述第二接合焊盘键合。
  3. 根据权利要求2所述的制备方法，其特征在于，在将所述第一介质层与所述第二介质层键合之前，所述方法还包括：
    分别对所述第一晶圆和所述第二晶圆进行等离子体表面处理，以活化所述第一接合焊盘、所述第二接合焊盘、所述第一介质层和所述第二介质层的表面；
    执行清洗步骤，以改变所述第一接合焊盘、所述第二接合焊盘、所述第一介质层和所述第二介质层表面的电荷特性。
  4. 根据权利要求3所述的制备方法，其特征在于，所述等离子体表面处理为O 2等离子体表面处理。
  5. 根据权利要求1所述的制备方法，其特征在于，将所述第一晶圆的第一表面与所述第二晶圆的第一表面键合之后，所述方法还包括：
    对所述第一晶圆执行减薄工艺，以在所述第二表面减小所述第一晶圆的厚度。
  6. 根据权利要求5所述的制备方法，其特征在于，在所述减薄工艺之后，所述制备方法还包括：
    在所述第一晶圆的第二表面形成多个相互间隔的高压信号电极；
    形成多个微透镜；
    将所述第一晶圆和所述第二晶圆键合后的结构进行封装。
  7. 根据权利要求6所述的制备方法，其特征在于，所述制备方法包括：
    在所述第一晶圆的第二表面形成电极材料层；
    蚀刻所述电极材料层，以形成多个所述高压信号电极；
    在所述第一晶圆的第二表面上形成钝化层，以覆盖所述高压信号电极之外的光敏区。
  8. 根据权利要求7所述的制备方法，其特征在于，所述形成多个微透镜包括：
    在所述第一晶圆的第二表面上形成透镜材料层；
    图案化所述透镜材料层，以保留所述高压信号电极之间的所述钝化层上的所述透镜材料层；
    执行回流工艺，以使所述透镜材料层回流形成所述微透镜。
  9. 根据权利要求8所述的制备方法，其特征在于，所述透镜材料层包括聚酰亚胺。
  10. 根据权利要求7所述的制备方法，其特征在于，所述形成多个微透镜包括：
    在所述第一晶圆的第二表面上形成依次形成透镜材料层和掩膜层；
    图案化所述掩膜层，以保留所述高压信号电极之间的所述钝化层上的所述掩膜层；
    执行回流工艺，以使所述掩膜层回流形成微透镜图案；
    以所述微透镜图案为掩膜蚀刻所述透镜材料层，以形成所述微透镜。
  11. 根据权利要求10所述的制备方法，其特征在于，所述透镜材料层包括氧化硅；和/或所述掩膜层包括光刻胶层。
  12. 根据权利要求6所述的制备方法，其特征在于，所述第二晶圆的边缘还形成有连接焊盘，且在所述第一晶圆和所述第二晶圆键合后的结构中，在所述第一晶圆和所述第二晶圆之间的边缘区域、所述连接焊盘的上方形成有空腔；
    将第一晶圆和第二晶圆键合后的结构进行封装，包括：
    去除所述第一晶圆的边缘区域，以露出所述第二晶圆边缘的所述连接焊盘；
    将去除所述第一晶圆的边缘区域的所述结构切割后得到的芯片结构固定于封装模块的容纳空间内；
    将所述高压信号电极与所述封装模块的第一引脚电连接；
    将所述连接焊盘与所述封装模块的第二引脚电连接。
  13. 根据权利要求12所述的制备方法，其特征在于，去除所述第一晶圆的边缘区域之前，所述第二晶圆的边缘还形成有保护层，以覆盖所述连接焊盘；
    在去除所述第一晶圆的边缘区域之后，去除所述保护层。
  14. 根据权利要求12所述的制备方法，其特征在于，所述封装模块包括位于底部的基板和位于基板上的侧板，以围绕形成所述容纳空间，所述制备方法还包括：
    将所述芯片结构中对应所述第二晶圆的表面封装于所述基板上；
    在所述容纳空间内执行灌胶工艺，并露出所述芯片结构中对应所述第一晶圆的表面的所述高压信号电极和所述微透镜。
  15. 根据权利要求14所述的制备方法，其特征在于，在所述侧板上形成顶板，以形成密闭的容纳空间，所述顶板中至少有部分区域为透光区域。
  16. 根据权利要求1所述的制备方法，其特征在于，所述第一晶圆的材料和所述第二晶圆的材料相同。
  17. 根据权利要求2所述的制备方法，其特征在于，所述第一介质层的高度大于所述第一接合焊盘的高度；和/或
    所述第二介质层的高度大于所述第二接合焊盘的高度。
  18. 一种接收芯片，其特征在于，所述芯片包括：
    键合的第一晶片和第二晶片，所述第一晶片和所述第二晶片为通过切割键合后的第一晶圆和第二晶圆得到；其中：
    所述第一晶圆的第一表面形成有多个背照式雪崩光电二极管；
    所述第二晶圆的第一表面形成有多个信号处理单元；
    所述第一晶圆的第一表面与所述第二晶圆的第一表面彼此相互接合， 上下对应的所述背照式雪崩光电二极管与所述信号处理单元彼此电连接。
  19. 根据权利要求18所述的接收芯片，其特征在于，所述第一晶圆的第一表面还形成有多个相互间隔的第一接合焊盘和填充所述第一接合焊盘之间间隙的第一介质层；
    所述第二晶圆的表面还形成有多个相互间隔的第二接合焊盘和填充所述第二接合焊盘之间间隙的第二介质层；
    所述第一介质层与所述第二介质层相互键合；
    所述第一接合焊盘与所述第二接合焊盘相互键合。
  20. 根据权利要求18所述的接收芯片，其特征在于，所述第一晶圆的第二表面形成有多个高压信号电极；
    所述第一晶圆的第二表面形成有多个微透镜。
  21. 根据权利要求20所述的接收芯片，其特征在于，所述第二表面上还形成有钝化层，用于覆盖所述高压信号电极之外的光敏区。
  22. 根据权利要求20所述的接收芯片，其特征在于，所述微透镜的材料为聚酰亚胺。
  23. 根据权利要求20所述的接收芯片，其特征在于，相互键合的所述第一晶片与所述第二晶片封装于封装模块的容纳空间内；
    所述高压信号电极与所述封装模块的第一引脚电连接；
    所述第二晶片的边缘还形成有连接焊盘，所述连接焊盘与所述封装模块的第二引脚电连接。
  24. 根据权利要求23所述的接收芯片，其特征在于，所述封装模块包括位于底部的基板和位于基板上的侧板，所述基板和所述侧板围绕形成所述容纳空间，所述第二晶片封装于所述基板上。
  25. 根据权利要求24所述的接收芯片，其特征在于，所述容纳空间内还注塑有封装胶，所述封装胶露出所述第一晶片顶部的所述高压信号电极和微透镜。
  26. 根据权利要求24所述的接收芯片，其特征在于，所述封装模块包括还包括位于所述侧板上的顶板，所述顶板中至少有部分区域为透光区域。
  27. 根据权利要求18所述的接收芯片，其特征在于，所述第一晶圆 的材料和所述第二晶圆的材料相同。
  28. 根据权利要求19所述的接收芯片，其特征在于，所述第一介质层的高度大于所述第一接合焊盘的高度；和/或
    所述第二介质层的高度大于所述第二接合焊盘的高度。
  29. 一种测距装置，其特征在于，所述测距装置包括：
    光发射电路，用于出射激光脉冲序列；
    如权利要求18至28之一所述的接收芯片，用于接收所述光发射电路出射的光脉冲序列经过被探测物反射的光脉冲序列，以及基于接收的光脉冲序列输出时间信号；
    运算电路，用于根据所述时间信号计算所述被探测物与所述测距装置之间的距离。
  30. 一种可移动平台，其特征在于，所述可移动平台包括:
    可移动平台本体；
    权利要求29所述的测距装置，所述测距装置设于所述可移动平台本体上。
  31. 根据权利要求30所述的可移动平台，其特征在于，所述可移动平台包括无人机、自动驾驶汽车或机器人。
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