WO2023155099A1 - 背照式雪崩光电二极管阵列芯片、接收芯片、测距装置及可移动平台 - Google Patents

背照式雪崩光电二极管阵列芯片、接收芯片、测距装置及可移动平台 Download PDF

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WO2023155099A1
WO2023155099A1 PCT/CN2022/076658 CN2022076658W WO2023155099A1 WO 2023155099 A1 WO2023155099 A1 WO 2023155099A1 CN 2022076658 W CN2022076658 W CN 2022076658W WO 2023155099 A1 WO2023155099 A1 WO 2023155099A1
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Prior art keywords
substrate
chip
avalanche photodiode
layer
photodiode array
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PCT/CN2022/076658
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English (en)
French (fr)
Inventor
郑国光
王国才
潘子健
曹伟东
黄潇
洪小平
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2022/076658 priority Critical patent/WO2023155099A1/zh
Publication of WO2023155099A1 publication Critical patent/WO2023155099A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Definitions

  • the invention relates to the field of integrated circuits, in particular to a back-illuminated avalanche photodiode array chip, a receiving chip, a distance measuring device and a movable platform.
  • lidar As the core sensor of autonomous driving, laser radar is currently the mainstream use of mechanical rotating laser radar. This type of lidar generally has problems such as low reliability due to the introduction of multiple mechanical components, and low production efficiency caused by difficulty in focusing and alignment.
  • Solid-state laser radar Compared with the mechanical scanning laser radar, the solid-state laser radar with smaller size and lower cost has more stable performance, excellent reliability, and is easier to pass the vehicle regulations. Solid-state laser radar (or Flash radar) It was once regarded as the "ultimate future" of lidar.
  • APD Advanced Photon Diode
  • APD avalanche Photon Diode
  • APD small-scale APD line arrays or APD area arrays
  • the core receiving chips used in solid-state lidar need to have Thousands of receiving units need to use highly integrated, arrayed receiving chips and integrated analog signal processing circuits and digital circuit chips, that is, area array APD receiving chips. Therefore, it is necessary to design an area array
  • the APD receiving chip has become the main concern of the industry.
  • the first aspect of the embodiment of the present application provides a back-illuminated avalanche photodiode array chip, and the back-illuminated avalanche photodiode array chip includes:
  • a first substrate having a first surface and a second surface oppositely disposed
  • an epitaxial layer having a third surface and a fourth surface oppositely disposed, the third surface of the epitaxial layer being formed on the second surface of the first substrate;
  • the second substrate is arranged on the side of the avalanche photodiode array away from the epitaxial layer, and the second substrate is formed through the second substrate and electrically connected to the avalanche photodiode array.
  • An electrical connection structure, the plurality of electrical connection structures are used to electrically connect the avalanche photodiode array and the signal processing unit.
  • the second aspect of the embodiment of the present application provides a receiving chip.
  • the receiving chip includes: the back-illuminated avalanche photodiode array chip mentioned above, which is used to receive the light pulse sequence emitted by the light emitting circuit after being reflected by the object to be detected. an optical signal, and converting the returned optical signal into an electrical signal;
  • a signal processing unit electrically connected to the back-illuminated avalanche photodiode array chip, for acquiring the electrical signal and outputting a time signal based on the acquired electrical signal.
  • the third aspect of the embodiment of the present application provides a distance measuring device, and the distance measuring device includes:
  • the transmitting circuit is used for emitting the light pulse sequence
  • the back-illuminated avalanche photodiode array chip mentioned above is used to receive the return light signal reflected by the detected object after the light pulse sequence emitted by the light emitting circuit, and convert the return light signal into an electrical signal;
  • a signal processing unit electrically connected to the back-illuminated avalanche photodiode array chip, for acquiring the electrical signal and outputting a time signal based on the acquired electrical signal;
  • An arithmetic circuit used to calculate the distance between the object to be detected and the distance measuring device according to the time signal.
  • the fourth aspect of the embodiment of the present application provides a distance measuring device, and the distance measuring device includes:
  • An arithmetic circuit used to calculate the distance between the object to be detected and the distance measuring device according to the time signal.
  • the fifth aspect of the embodiment of the present application provides a mobile platform, the mobile platform includes:
  • At least one distance measuring device mentioned above is arranged on the movable platform body.
  • a second substrate is provided on the fourth surface of the epitaxial layer, and a plurality of electrical connection structures electrically connected to the avalanche photodiode array are formed in the second substrate,
  • the electrical connection between the avalanche photodiode array and the signal processing unit is realized through multiple electrical connection structures, so as to transmit the output signal of the avalanche photodiode array to the signal processing unit for processing.
  • the second substrate can provide sufficient support for the epitaxial layer, the first substrate can be thinner, the electrical connection structure is conducive to the output of the signal, the chip structure is simpler, and it is used to make a back-illuminated avalanche photodiode array chip
  • the process is simpler and easier to implement, and can be applied to ranging devices such as solid-state lidar, which is conducive to promoting large-scale commercialization and promotion of solid-state lidar as soon as possible to meet the requirements of vehicle regulations.
  • the back-illuminated avalanche photodiode array chip of the present application can realize pixel-level interconnection with the signal processing chip, thereby reducing the length of the wiring, and further reducing the crosstalk between pixels.
  • the receiving chip, distance measuring device and movable platform of the present application have the same advantages as the aforementioned back-illuminated avalanche photodiode array chip.
  • Figure 1 shows a schematic cross-sectional view of a back-illuminated avalanche photodiode array chip in an embodiment provided by the present application
  • Figure 2 shows a schematic cross-sectional view of a back-illuminated avalanche photodiode in another embodiment provided by the present application
  • Figure 3 shows a schematic cross-sectional view of a back-illuminated avalanche photodiode in an embodiment provided by the present application
  • FIG. 4 shows a schematic cross-sectional view of a receiving chip in an embodiment provided by the present application
  • 5A to 5O show schematic cross-sectional views of intermediate devices during the preparation process of a back-illuminated avalanche photodiode array chip in an embodiment of the present application;
  • FIG. 6 shows a schematic flow chart of a method for manufacturing a back-illuminated avalanche photodiode array chip provided by the present application
  • Fig. 7 shows a schematic block diagram of a ranging device in an embodiment provided by the present application.
  • Fig. 8 shows a schematic diagram of a ranging device in an embodiment provided by the present application.
  • the first aspect of the present application provides a back-illuminated avalanche photodiode array chip 300.
  • the back-illuminated avalanche photodiode array chip 300 includes:
  • the first substrate 301 has a first surface and a second surface opposite to each other;
  • the epitaxial layer 302 has a third surface and a fourth surface oppositely disposed, and the third surface of the epitaxial layer 302 is formed on the second surface of the first substrate;
  • the second substrate 310 is arranged on the side of the avalanche photodiode array away from the epitaxial layer 302, and the avalanche photodiode array is formed in the second substrate 310.
  • a plurality of electrical connection structures for electrical connection, the plurality of electrical connection structures are used to electrically connect the avalanche photodiode array and the signal processing unit.
  • the structure of the back-illuminated avalanche photodiode array chip 300 will be described in detail below with reference to FIGS. 1 , 2 and 3 . On the premise of no conflict, the technical features of the various embodiments of the present application can be combined with each other.
  • the back-illuminated avalanche photodiode array chip 300 of the present application includes a first substrate 301 having a first surface and a second surface oppositely disposed.
  • the first substrate 301 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon germanium on insulator
  • GeOI germanium on insulator
  • the first substrate 301 may be silicon.
  • the first substrate 301 may be a P-type substrate or an N-type substrate.
  • the first substrate 301 of the present application may be a P-type heavily doped substrate, that is, a P+ type substrate, which can also be used for the voltage application layer of APD. It is worth mentioning that the first substrate 301 shown in FIG. 1, FIG. 2 and FIG. Be specific.
  • the epitaxial layer 302 has a third surface and a fourth surface oppositely disposed, and the third surface of the epitaxial layer 302 is formed on the second surface of the first substrate 301 .
  • the epitaxial layer 302 may be a semiconductor material, and in an embodiment of the present application, the epitaxial layer 302 may be an epitaxial silicon wafer.
  • the thickness of the epitaxial layer 302 is not limited to a certain value range.
  • the epitaxial layer 302 may be a low-doped epitaxial layer, and its doping type may be N-type or P-type, and generally the epitaxial layer 302 may be P-type doped.
  • setting the epitaxial layer 302 as a low-doped epitaxial layer can reduce the consumption of photogenerated carriers generated in the APD, and then quickly reach the avalanche collection area of the APD, increasing the corresponding speed of the APD, Avoid the smearing problem of APD and avoid the delay of the device.
  • a back-illuminated avalanche photodiode array (not shown) is formed on the fourth surface of the epitaxial layer 302.
  • the back-illuminated avalanche photodiode array may include a plurality of avalanche photodiodes, and each avalanche photodiode may corresponds to a pixel unit.
  • the avalanche photodiode may be a back-illuminated device, that is, in the back-illuminated device, the photosensitive device APD is located in front of the circuit transistor, and the light first enters the photosensitive device APD, thereby increasing the light sensitivity.
  • the avalanche photodiode array is formed on the fourth surface of the epitaxial layer 302 , and the light enters from the third surface of the epitaxial layer 302 .
  • the back-illuminated avalanche photodiode may include an avalanche region (not shown) located in the epitaxial layer, the avalanche region may include a first doped layer and a second doped layer and the first doped layer The region between the impurity layer and the second doped layer, wherein: the first doped layer has the first doping type; the second doped layer is located above the first doped layer (that is, the second doped layer The second doped layer is closer to the fourth surface of the epitaxial layer than the first doped layer), has a second doping type, and the first doping type is different from the second doping type.
  • the first doping type and the second doping type are different, the first doping layer and the second doping layer and the first doping layer and the second doping layer The region in between constitutes the avalanche region of the avalanche photodiode.
  • the first doped layer may be formed by performing first ion implantation of the first doping type on the epitaxial layer 302, and in this application, the implantation depth and dose of the first doped layer are adjusted to adjust The electric field strength in the avalanche region realizes the optimization of device gain noise factor.
  • the first doping type is P-type
  • the doping ions implanted in the first ion implantation may include but not limited to boron (B) ions.
  • the first doped layer and the second doped layer and the region between the first doped layer and the second doped layer constitute an avalanche region of the avalanche photodiode.
  • the first doping type is different from the second doping type, for example, the first doping type is P-type, and the second doping type is N-type.
  • the second doped layer can be formed by performing second ion implantation of the second doping type on the epitaxial layer, wherein the dopant ions implanted in the second ion implantation include but not limited to P (phosphorus) ions or As ions wait.
  • the depth of the peak concentration of the second ion implantation is less than or equal to 200 nm. In an embodiment of the present application, the depth of the peak concentration of the second ion implantation is 100 nm.
  • an absorbing layer may be further included below the avalanche region (that is, between the first doped layer and the third surface of the epitaxial layer), which will not be repeated here.
  • a guard ring is further formed in the epitaxial layer 302, the second doped layer surrounded by the guard ring, and the guard ring and the second doped layer can be formed simultaneously by performing a second ion implantation on the epitaxial layer , the yield and performance of the device are further improved by forming the guard ring to prevent edge breakdown.
  • the step of forming the guard ring may be before the first ion implantation of the first doping type, or after the first ion implantation of the first doping type and after the second doping type Before the second ion implantation, it can be selected according to actual needs.
  • the guard ring is formed before the first ion implantation of the first doping type.
  • the depth of the guard ring may be greater than or equal to 2 ⁇ m.
  • an isolation ring (not shown) is formed on the edge region of the fourth surface of the epitaxial layer, and the back-illuminated avalanche photodiode array is separated from the peripheral area by the isolation ring on the periphery of the array, and the isolation ring Connect the ground electrode through the metal electrode to reduce the optical crosstalk and electrical crosstalk that may be caused by the peripheral area of the array.
  • the isolation ring may be formed by performing ion implantation of the second doping type, wherein the fourth ion implantation of the second doping type is N-type ion implantation.
  • a first passivation layer 311 is formed on the fourth surface of the epitaxial layer 302, and a plurality of first electrodes 313 spaced from each other are arranged in the first passivation layer 311, wherein each of the first electrodes 313 Electrically connect at least one of the avalanche photodiodes, for example, each first electrode 313 is correspondingly connected to an avalanche photodiode, optionally, the first electrode 313 may include a pad, such as a conductive metal pad, a metal pad Including but not limited to aluminum pads, etc. Exemplarily, the top surface of the first passivation layer 311 is higher than the top surface of the first electrode 313 such as a pad.
  • the thickness of the first passivation layer 311 may be any suitable thickness, which is not specifically limited here.
  • the material of the first passivation layer 311 may use any suitable insulating material, for example, the first passivation layer 311 may use an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • the second substrate 310 is disposed on the side of the avalanche photodiode array away from the epitaxial layer 302, that is, on the side of the fourth surface of the epitaxial layer 302, such as the second substrate 310 Including the first surface and the second surface opposite to the first surface, the first surface of the second substrate 310 is bonded to, for example bonded to, the first passivation layer 311 formed on the epitaxial layer.
  • the second substrate 310 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • the second substrate 310 is made of silicon.
  • the second substrate 310 is formed with a plurality of electrical connection structures penetrating through the second substrate 310 and electrically connected to the avalanche photodiode array, and the plurality of electrical connection structures are used to make the avalanche photodiode
  • the array and the signal processing unit are electrically connected.
  • each of the electrical connection structures is electrically connected to at least one of the first electrodes 313 , and the ends of the electrical connection structures electrically connected to the first electrodes are located in the first passivation layer 311 .
  • the electrical connection structure includes a conductive plug 314 and a second electrode 315 electrically connected to the conductive plug 314, wherein the conductive plug 314 penetrates through the second substrate 310, the The second electrode 315 is disposed on a side of the second substrate 310 away from the epitaxial layer 302 .
  • the conductive plug 314 may be obtained by etching the second substrate 310 to form a conductive via hole, and then filling the conductive via hole with a metal such as W, and the side wall of the conductive via hole may also be Set passivation layer.
  • a second passivation layer 312 is provided on the side (for example, the second surface of the second substrate 310) on which the second electrode 315 is formed on the second substrate 310, and the second electrode 315 is arranged on the In the second passivation layer 312 , for example, adjacent second electrodes 315 are separated by the second passivation layer 312 .
  • each second electrode 315 is electrically connected to at least one conductive plug 314, for example, each second electrode 315 is correspondingly connected to one conductive plug 314, optionally, the second electrode 315 may include a pad,
  • conductive metal pads include but not limited to aluminum pads and the like.
  • the top surface of the second passivation layer 312 is higher than the top surface of the second electrode 315 such as a pad.
  • the thickness of the second passivation layer 312 may be any suitable thickness, which is not specifically limited here.
  • the material of the second passivation layer 312 may use any suitable insulating material, for example, the second passivation layer 312 may use an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • the first electrode 313 and the second electrode 315 are made of aluminum (Al), and the conductive plug 314 is made of tungsten (W) or other suitable metal materials.
  • each of the electrical connection structures further includes a bump structure, the bump structure is disposed on the second electrode 315, and the bump structure is used for electrically connecting the second electrode and signal processing. unit.
  • the bump structure may be any suitable structure known to those skilled in the art.
  • the bump structure includes a conductive base 317 and a conductive bump 318, and the conductive base 317 is embedded in the second passivation layer 312 and electrically connected to the second electrode 315, the conductive bump 318 is disposed on the conductive base 317, and the conductive bump 318 is away from the conductive base 317
  • One end of the solder 319 is also provided with solder 319, and the solder 319 can be used as a solder tip, which can be presented as a solder ball by, for example, reflow soldering, etc.
  • the solder 319 can include at least one of metal materials such as tin and silver. kind.
  • the conductive bump 318 may be any suitable structure, for example, the conductive bump 318 may include copper pillars or other suitable conductive structures.
  • the conductive base 317 may also be referred to as an under bump metallurgy (UBM), which may be formed of titanium (Ti), titanium nitride (TiN), copper nickel (CuNi), aluminum (Al), etc., which The thickness may be in the range of about 0.1 ⁇ m to about 5 ⁇ m, which can be reasonably selected according to actual needs.
  • UBM under bump metallurgy
  • a buffer layer 316 is further disposed on the second passivation layer 312, an opening is disposed in the second passivation layer 312 and the buffer layer 316, and the conductive base 317 includes a The first conductive portion on the bottom and the sidewall and the second conductive portion extending to the buffer layer 316, the buffer layer 316 is used to buffer the stress at the junction of the first conductive portion and the second conductive portion.
  • the material of the buffer layer 316 may be any suitable material capable of buffering stress.
  • the buffer layer 316 may include organic polymer materials such as polyimide.
  • a first isolation structure 306 may also be provided in the first substrate 301, and the first isolation structure 306 includes a first isolation groove and is filled in the first isolation
  • the insulating material in the groove can be silicon nitride, silicon oxide or silicon oxynitride insulating material, and optionally, the insulating material can also have the same material as the anti-reflection layer 304, for example, both can be nitrided. silicon etc.
  • the first isolation structure 306 at least runs through the first substrate 301, part of the first isolation structure 306 may extend into the epitaxial layer 302, so as to divide the first substrate 301 into At least two areas, for example, may be divided into two areas, or divided into more than two areas.
  • the first isolation structure 306 is used to divide the first substrate 301 into multiple regions, and the applied operating voltage is controlled by region. For example, the operating voltages are respectively applied to the left and right regions shown in FIG. 3 , which avoids the problems of large operating voltage differences in the first substrate 301 caused by voltage drops and difficult gain control as the chip size increases.
  • a second isolation structure 307 is further provided between adjacent avalanche photodiodes of the epitaxial layer 302, and the second isolation structure 307 includes a second isolation groove and is filled in the
  • the insulating material in the second isolation groove may be an insulating material such as silicon nitride, silicon oxide or silicon oxynitride.
  • the second isolation structure 307 penetrates the epitaxial layer 302 .
  • the second isolation structure 307 includes several rows and several columns to enclose a structure similar to a matts shape, and the back-illuminated structure is formed in the spaces of the matts structure.
  • Avalanche photodiodes to effectively suppress electrical crosstalk between adjacent back-illuminated avalanche photodiodes.
  • a light trapping structure 320 can also be formed on the third surface of the epitaxial layer 302, and the light trapping structure 320 is used to increase the optical distance. By setting the light trapping structure 320, the optical distance can be increased. , thereby increasing the quantum efficiency.
  • the light trapping structure 320 includes a plurality of protrusion structures disposed on the epitaxial layer 302, such as inverted pyramid protrusions, pillar protrusions, etc., the The light trapping structure 320 is used to increase the optical distance, thereby improving the quantum efficiency.
  • the back-illuminated avalanche photodiode array chip 300 of the present application further includes an anti-reflection layer 304 covering the first surface of the first substrate 301, wherein the anti-reflection layer 304 can be Si3N4 or other suitable light-transmitting films capable of anti-reflection are selected to further increase light transmittance, reduce light reflection, and improve device performance.
  • the anti-reflection layer 304 can be Si3N4 or other suitable light-transmitting films capable of anti-reflection are selected to further increase light transmittance, reduce light reflection, and improve device performance.
  • a lens structure 305 is formed on the anti-reflection layer 304, and the light can be condensed by the lens structure 305 and then incident on the APD, so as to improve the fill factor of the APD array chip device, increase the light responsivity, and improve crosstalk.
  • the lens structure may be a microlens array composed of a plurality of microlenses.
  • there may be a one-to-one correspondence between the microlenses in the microlens array and the avalanche photodiodes.
  • a second substrate is provided on the fourth surface of the epitaxial layer, and multiple substrates electrically connected to the avalanche photodiode array are formed in the second substrate.
  • An electrical connection structure is used to realize the electrical connection between the avalanche photodiode array and the signal processing unit through a plurality of electrical connection structures, so as to transmit the output signal of the avalanche photodiode array to the signal processing unit for processing.
  • the second substrate can provide sufficient support for the epitaxial layer, the first substrate can be thinner, the electrical connection structure is conducive to the output of the signal, the chip structure is simpler, and it is used to make a back-illuminated avalanche photodiode array chip
  • the process is simpler and easier to implement, and can be applied to ranging devices such as solid-state lidar, which is conducive to promoting large-scale commercialization and promotion of solid-state lidar as soon as possible to meet the requirements of vehicle regulations.
  • the back-illuminated avalanche photodiode array chip of the present application can realize pixel-level interconnection with the signal processing chip, thereby reducing the length of the wiring, and further reducing the crosstalk between pixels.
  • the present application also provides a receiving chip (the receiving chip may be a part of the receiver or detector), wherein the receiving chip includes: the back-illuminated avalanche photodiode chip described above , for receiving the light pulse sequence reflected by the object to be detected, and converting the received light pulse sequence into an electrical signal; a signal processing unit, electrically connected to the back-illuminated avalanche photodiode chip, for obtaining the electrical signal and outputting a time signal based on the acquired electrical signal.
  • the receiving chip includes: the back-illuminated avalanche photodiode chip described above , for receiving the light pulse sequence reflected by the object to be detected, and converting the received light pulse sequence into an electrical signal; a signal processing unit, electrically connected to the back-illuminated avalanche photodiode chip, for obtaining the electrical signal and outputting a time signal based on the acquired electrical signal.
  • the signal processing unit includes a signal processing chip 400 for receiving and processing the electrical signal of the back-illuminated avalanche photodiode chip to output a time signal.
  • the signal processing chip 400 may include a first surface and a second surface opposite to the first surface, a passivation layer 410 may be formed on the first surface of the signal processing chip 400, and a fourth The electrodes 430 , wherein the number of the fourth electrodes 430 may depend on the number of electrical connection structures of the back-illuminated avalanche photodiode array chip 300 , which may be in one-to-one correspondence with the electrical connection structures of the back-illuminated avalanche photodiode array chip 300 .
  • Adjacent fourth electrodes 430 are separated by the passivation layer 410 .
  • the fourth electrode 430 may include a pad, such as a conductive metal pad, and the metal pad includes but not limited to an aluminum pad.
  • the top surface of the passivation layer 410 is higher than the top surface of the fourth electrode 430 such as a pad.
  • the thickness of the passivation layer 410 may be any suitable thickness, which is not specifically limited here.
  • the material of the passivation layer 410 may use any suitable insulating material, for example, the passivation layer 410 may use an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • a bump structure for electrically connecting with the electrical connection structure of the back-illuminated avalanche photodiode array chip 300, and the bump structure can be used for electrically connecting the back-illuminated avalanche photodiode array chip 300.
  • the bump structure of the electrical connection structure is used to realize the electrical connection between the back-illuminated avalanche photodiode array chip 300 and the signal processing unit.
  • the bump structure can be any suitable structure known to those skilled in the art.
  • the bump structure includes a conductive base 441 and a conductive bump 442, and the conductive base 441 is embedded in the passivation layer 410 and electrically connected to the second electrode 315, the conductive bump 442 is disposed on the conductive base 441, and the conductive bump 442 is away from one end of the conductive base 441 Solder is also provided, and the solder can be used as a solder tip, which can be presented as a solder ball by, for example, reflow soldering.
  • the solder can include at least one of metal materials such as tin and silver.
  • the conductive bump 442 may be any suitable structure, for example, the conductive bump 442 may include copper pillars or other suitable conductive structures.
  • the solder can be melted and bonded with the solder of the aforementioned electrical connection structure, so as to realize electrical connection.
  • the conductive base 441 may also be referred to as an under bump metallurgy (UBM), which may be formed of titanium (Ti), titanium nitride (TiN), copper nickel (CuNi), aluminum (Al), etc., which The thickness may be in the range of about 0.1 ⁇ m to about 5 ⁇ m, which can be reasonably selected according to actual needs.
  • UBM under bump metallurgy
  • a buffer layer 420 is further disposed on the passivation layer 410, an opening is disposed in the passivation layer 410 and the buffer layer 420, and the conductive base 441 includes a bottom and a side wall disposed on the opening.
  • the first conductive part on the upper part and the second conductive part extending to the buffer layer 420, and the buffer layer 420 is used for buffering the stress at the junction of the first conductive part and the second conductive part.
  • the material of the buffer layer 420 may be any suitable material capable of buffering stress.
  • the buffer layer 420 may include organic polymer materials such as polyimide.
  • the gap between the signal processing chip 400 and the back-illuminated avalanche photodiode array chip 300 is also filled with an underfill material 450 , such as resin, filling glue, etc., for supporting and connecting.
  • an underfill material 450 such as resin, filling glue, etc.
  • the signal processing chip 400 includes:
  • Trans-Impedance Amplifier used to convert the current signal into a voltage signal
  • a comparator for comparing the voltage signal with a preset voltage threshold
  • a Time-to-Digital Converter (TDC for short), configured to output a time signal according to the comparison result of the comparator.
  • the signal processing unit is integrated with multiple circuits.
  • the signal processing unit is integrated with a transimpedance amplifier circuit (TIA circuit), a multi-stage operational amplifier OPA, comparator, and time-to-digital converter circuit (circuit that converts time into digital signal) or analog-to-digital conversion circuit (ADC circuit), and subsequent data processing circuit (DSP circuit).
  • TIA circuit is an analog front-end circuit that converts APD photocurrent into voltage.
  • the APD when the plurality of back-illuminated avalanche photodiodes convert optical signals into electrical signals, an external high-voltage power supply is required, and the APD can provide stable internal gain and improve signal-to-noise ratio, and output electrical signals.
  • the TIA circuit is electrically connected to the back-illuminated avalanche photodiode, and the TIA circuit converts the current signal of the APD into a voltage signal while providing conversion gain; the multi-stage operational amplifier OPA is connected with the The TIA circuit is electrically connected to amplify the signal output by the TIA circuit to meet the comparison amplitude requirement of the comparator.
  • the comparator is electrically connected to the multi-stage operational amplifier OPA, wherein a comparison threshold is set in the comparator to trigger the analog signal, convert the analog signal into a digital signal, and transmit the digital signal to the TDC circuit, and the TDC circuit is used for Convert digital signal to time signal for distance calculation.
  • one TDC circuit may be shared, that is, the number of signal processing units may not correspond to the number of TDC circuits.
  • a storage system may be further provided in the signal processing unit to cache data, provide input and output buffer space for the interface, and provide space for internal calculation.
  • An interface may be further provided in the signal processing unit as a data input and output channel to output measurement data.
  • the first input terminal of the comparator is used to receive the electrical signal input from the cross-group amplifier, that is, the amplified electrical signal
  • the second input terminal of the comparator is used to receive the preset Threshold
  • the output terminal of the comparator is used to output the result of the comparison operation, wherein the result of the comparison operation includes time information corresponding to the electrical signal.
  • the preset threshold received by the second input terminal of the comparator may be an electrical signal whose strength is the preset threshold.
  • the result of the comparison operation may be a digital signal corresponding to the electrical signal after the amplification operation.
  • the time-to-digital converter is electrically connected to the output terminal of the comparator, and is used for extracting time information corresponding to the electrical signal according to a comparison operation result output by the comparator.
  • the receiving chip may further include a substrate 460, and the second surface of the signal processing chip 400 of the present application may also be disposed on the substrate, for example, pasted on the substrate by bonding or other suitable methods.
  • the substrate may also include a circuit board, which may have various circuit structures, and the signal processing chip 400 and the back-illuminated avalanche photodiode array chip 300 may be electrically connected to one or more circuit structures on the substrate.
  • the receiving chip further includes a cover 470 disposed on the surface of the substrate 460, an accommodation space is formed between the substrate 460 and the cover 470, wherein at least part of the cover 470 is provided with a light-transmitting area, the back-illuminated avalanche photodiode array chip 300 and the signal processing unit 400 are arranged in the accommodating space, and light enters the back-illuminated avalanche photodiode array chip 300 through the light-transmitting area.
  • the cover body includes a U-shaped or square cover body with a window, and a light-transmitting plate that covers the window to form the light-transmitting area, wherein the light-transmitting plate is parallel to the surface of the base; Or the cover body is a plate-like structure that is completely transparent. Further, the cover body provides protection and an airtight environment for the chips enclosed therein.
  • the projection of the U-shaped cover body with windows on the first surface of the substrate is a circle, or other suitable shapes, and the projection of the square cover body on the first surface of the substrate It is square, wherein the size of the square cover body matches the size of the substrate, which can effectively reduce the size of the package.
  • the light-transmitting plate can be selected from commonly-used light-transmitting materials, such as glass, and the glass should have high passability for light incident on the APD.
  • the cover body is a plate-like structure that is completely transparent.
  • the plate-shaped structure is made of commonly used light-transmitting materials, such as glass, and the glass must have high passability for light incident on the APD.
  • the overall structure of the substrate can be in the shape of a groove, and the groove can be a square groove or a circular groove, and the cover is arranged on the top of the groove of the substrate and joined with the top surface of the substrate to The groove is sealed to form an accommodation space between the base plate and the cover body.
  • the receiving chip of the present application has the aforementioned back-illuminated avalanche photodiode array chip, it has the same advantages as the aforementioned back-illuminated avalanche photodiode array chip.
  • the receiving chip described in this application adopts the back-illuminated avalanche photodiode chip described above, and the back-illuminated avalanche photodiode array chip 300 can realize the electrical connection with the signal processing chip 400 through its electrical connection structure, for example, realize the electrical connection with the signal processing chip 400.
  • the pixel-level interconnection of the signal processing chip reduces the length of the wiring, thereby reducing the crosstalk between pixels, and it is easy to realize independent control of the avalanche photodiodes in each APD array.
  • the embodiment of the present application also provides a method for manufacturing a back-illuminated avalanche photodiode array chip 300, as shown in FIG. 6, the method includes the following steps:
  • Step S610 providing a first substrate, the first substrate has a first surface and a second surface opposite to each other, an epitaxial layer is formed on the second surface of the first substrate, and the epitaxial layer has a third surface and a fourth surface opposite to each other surface, the third surface of the epitaxial layer is formed on the second surface of the first substrate, an avalanche photodiode array is formed in the fourth surface of the epitaxial layer, the avalanche photodiode array includes a plurality of avalanche photodiodes, and the fourth surface of the epitaxial layer A first passivation layer is formed on the surface, a plurality of first electrodes are formed in the first passivation layer, and each first electrode is correspondingly electrically connected to an avalanche photodiode;
  • Step S620 providing a second substrate, the second substrate includes a first surface and a second surface away from the first surface, a plurality of grooves are formed in the second substrate, and the plurality of grooves the opening of the groove is located on the first surface of the second substrate;
  • Step S630 connecting the first surface of the second substrate 310 to the first substrate 301, and corresponding the opening of each trench to one of the first electrodes 313;
  • Step S640 Thinning the second substrate 310 from the second surface of the second substrate 310 to expose the bottom of the trench in the second substrate;
  • Step S650 filling the trenches with conductive material to form a plurality of conductive plugs.
  • FIGS. 5A-5O show schematic cross-sectional views of intermediate devices during the preparation process of the back-illuminated avalanche photodiode array chip 300 provided by the present application.
  • a first substrate 301 is provided, the first substrate has a first surface and a second surface oppositely arranged, and an epitaxial layer 302 is formed on the second surface of the first substrate 301 , the epitaxial layer 302 has a third surface and a fourth surface opposite to each other, the third surface of the epitaxial layer 302 is formed on the second surface of the first substrate 301, and an avalanche photovoltaic layer is formed in the fourth surface of the epitaxial layer 302
  • the avalanche photodiode array includes a plurality of avalanche photodiodes, a first passivation layer 311 is formed on the fourth surface of the epitaxial layer 302, and a plurality of first electrodes 313 are formed in the first passivation layer 311 , each of the first electrodes 313 is correspondingly electrically connected to one of the avalanche photodiodes.
  • the first substrate 301 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon germanium on insulator
  • GeOI germanium on insulator
  • the first substrate 301 is made of silicon.
  • the epitaxial layer 302 may be made of a semiconductor material, and in an embodiment of the present application, an epitaxial silicon wafer is used.
  • the thickness of the epitaxial layer 302 is not limited to a certain value range.
  • the method for forming the epitaxial layer 302 may be chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).
  • the avalanche photodiode may be a back-illuminated device, that is, in the back-illuminated device, the photosensitive device APD is located in front of the circuit transistor, and light first enters the photosensitive device APD, thereby Increase light sensitivity.
  • the APD is formed on the surface of the epitaxial layer 302 away from the first substrate 301 .
  • the epitaxial layer 302 has a low doping type, and the doping type can be N-type or P-type, and generally the epitaxial layer 302 is P-type doped.
  • setting the epitaxial layer 302 as a low-doping type can reduce the consumption of photogenerated carriers generated in the APD, and then quickly reach the avalanche collection area of the APD, increasing the corresponding speed of the APD, Avoid the smearing problem of APD and avoid the delay of the device.
  • the back-illuminated avalanche photodiode includes:
  • an avalanche region located in the epitaxial layer, including a first doped layer and a second doped layer and a region between the first doped layer and the second doped layer, wherein:
  • the first doped layer has a first doping type
  • the second doped layer located above the first doped layer, has a second doping type, and the first doping type is different from the second doping type.
  • the first doping type and the second doping type are different, the first doping layer and the second doping layer and the first doping layer and the second doping layer The region in between constitutes the avalanche region of the avalanche photodiode.
  • the first ion implantation of the first doping type is performed on the epitaxial layer 302 to form the first doped layer.
  • the implantation depth and dose of the first doped layer are adjusted to adjust the The electric field strength realizes the optimization of the device gain noise factor.
  • the first ion implantation is P-type ion implantation, and in an embodiment of the present application, the P-type ions are boron (B) ions.
  • the first doped layer and the second doped layer and the region between the first doped layer and the second doped layer constitute an avalanche region of the avalanche photodiode.
  • the first doping type is different from the second doping type, wherein the first ion implantation is P-type, and the second ion implantation is N-type.
  • the second ion implantation is P (phosphorus) ions or As ions.
  • an absorbing layer may be further included under the avalanche region, which will not be repeated here.
  • the depth of the peak concentration of the second ion implantation is less than or equal to 200 nm, and in one embodiment of the present application, the depth of the peak concentration of the second ion implantation is 100 nm.
  • a guard ring is also formed in the epitaxial layer 302, and during the subsequent second ion implantation step, the second ion implantation is performed in the guard ring to form the
  • the second doped layer can further improve the yield and performance of the device by forming the guard ring to prevent edge breakdown.
  • the step of forming the guard ring may be before the first ion implantation of the first doping type, or after the first ion implantation of the first doping type and after the second doping type Before the second ion implantation, it can be selected according to actual needs.
  • the guard ring is formed before the first ion implantation of the first doping type.
  • the depth of the guard ring is greater than or equal to 2 ⁇ m.
  • An isolation ring is also formed on the edge area of the fourth surface of the epitaxial layer, and the back-illuminated avalanche photodiode array is separated from the peripheral area by the isolation ring on the periphery of the array, and the isolation ring is connected to the ground electrode through a metal electrode, reducing the array periphery.
  • Optical and electrical crosstalk that may be caused by the area.
  • the isolation ring is formed by performing fourth ion implantation of the second doping type, wherein the fourth ion implantation of the second doping type is N-type ion implantation.
  • the first passivation layer 311 is provided with a plurality of first electrodes 313 spaced apart from each other, wherein each of the first electrodes 313 is electrically connected to at least one of the avalanche photodiodes, and each The electrical connection structure is electrically connected to at least one of the first electrodes 313 , and an end portion of the electrical connection structure electrically connected to the first electrode is located in the first passivation layer 311 .
  • the method for forming the first electrode 313 includes:
  • the region and distribution of the first electrodes are defined by photolithography, and the rest of the first electrode material layer is removed by etching to form a plurality of first electrodes 313 spaced apart from each other.
  • the first electrode material layer includes but not limited to aluminum (Al).
  • first passivation layer 311 to cover the first electrode 313 and the fourth surface of the epitaxial layer 302;
  • a plurality of electrode openings are formed in the second passivation layer 312 , each of the electrode openings exposes a part of the surface of the first electrode 313 opposite to it, so as to lead out the first electrode 313 .
  • a second isolation structure 307 is also provided between adjacent avalanche photodiodes of the epitaxial layer 302 .
  • a step of forming a second isolation structure 307 may also be included:
  • An insulating material is filled in the second isolation groove. Electrical crosstalk between adjacent pixels can be prevented by the second isolation structure.
  • a second substrate 310 is provided, and the second substrate 310 includes a first surface and a second surface away from the first surface, as shown in FIG. 5C As shown, a plurality of grooves are formed in the second substrate 310 , and the openings of the plurality of grooves are located on the first surface of the second substrate 310 .
  • the second substrate 310 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • the second substrate 310 is made of silicon.
  • photolithography and etching processes are performed to form a plurality of trenches in the second substrate 310, for example, a mask is formed on the first surface of the second substrate 310 through a photolithography process. film layer, and then use the mask layer as a mask to etch the second substrate 310 through an etching process such as dry etching or wet etching to form a plurality of grooves, the depth of which can be Any depth between 50-100 microns can be reasonably set according to actual needs.
  • an isolation layer 3101 may be further formed on the bottoms, side walls, and the first surface of the second substrate 310 of the plurality of trenches for isolation etching form a surface leakage current.
  • the isolation layer 3101 can be formed by thermal oxidation or chemical deposition, for example, an isolation layer 3101 of silicon oxide can be formed by thermal oxidation, and the thickness of the isolation layer 3101 is approximately between 0.2 microns and 0.8 microns , such as 0.2 microns, 0.5 microns, 0.7 microns, etc.
  • the first surface of the second substrate 310 is connected to the first substrate 301, and the opening of each trench is connected to one of the
  • the first electrode 313 corresponds to, for example, corresponds to the electrode opening on the first electrode 313 .
  • the epitaxial layer 302 is bonded to the second substrate 310 using a wafer-level bonding packaging process, for example, the isolation layer and the first passivation layer of the second substrate 310 Bonding is performed to realize the bonding of the first substrate and the epitaxial layer 302 .
  • the second substrate 310 is thinned from the second surface of the second substrate 310 to expose the groove located on the second substrate. 310 inside the bottom.
  • the second substrate is thinned by a process such as back grinding (Back Grinding) to expose the trench.
  • the position of the groove corresponds to the position of the electrode opening on the first electrode 313 , so as to further expose the first electrode 313 through the groove.
  • the trenches are filled with conductive material to form a plurality of conductive plugs 314 .
  • the conductive material includes but not limited to tungsten (W).
  • the manufacturing method further includes the following steps:
  • a plurality of electrode openings are formed in the second passivation layer 312 , and each electrode opening exposes a part of the surface of a second electrode 315 opposite to it.
  • the method for forming the plurality of second electrodes 315 can refer to the step of forming the plurality of first electrodes 313 , which will not be repeated here.
  • the second electrode material layer includes but not limited to aluminum (Al).
  • the manufacturing method further includes the following step: thinning the first substrate 301 .
  • the back surface of the first substrate 301 (that is, the first surface of the first substrate 301 ) is thinned by using back grinding (Back Grinding) and other processes.
  • the thickness of the thinned first substrate 301 can be reasonably set according to actual needs.
  • the manufacturing method further includes:
  • a lens structure 305 is formed on the antireflection layer 304 .
  • the method for forming the plurality of third electrodes 303 may refer to the step of forming the plurality of first electrodes 313 , which will not be repeated here.
  • An anti-reflection layer 304 is formed between the adjacent third electrodes 303 on the back side of the first substrate 301, wherein the anti-reflection layer 304 is made of Si 3 N 4 to further increase light transmittance, Reduce the reflection of light, thereby improving the performance of the device.
  • the method for forming the antireflection layer 304 includes:
  • the anti-reflection material whose height exceeds the height of the third electrode 303 is removed to expose the third electrode 303 .
  • the formation of the anti-reflection material layer can be selected from chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method and the like.
  • the method for removing the anti-reflection material whose height exceeds the height of the third electrode 303 may be a chemical mechanical polishing or etching process.
  • a first isolation structure 306 may also be formed in the first substrate 301, as shown in FIG. 3, the step of forming the first isolation structure 306 includes:
  • the anti-reflection layer 304 is formed to cover the back surface of the first substrate 301 and fill the isolation groove, and the isolation groove and the anti-reflection layer filled in the isolation groove form a first isolation structure 306, so The first isolation structure 306 at least penetrates the first substrate 301, part of the first isolation structure 306 may extend into the epitaxial layer 302, and the first isolation structure 306 divides the first substrate 301 for at least two regions.
  • the first isolation structure 306 is used to divide the first substrate 301 into multiple regions, and the applied operating voltage is controlled by region. For example, the operating voltages are respectively applied to the left and right regions shown in FIG. 2 , which avoids the problems of large operating voltage differences in the first substrate 301 caused by voltage drops and difficult gain control as the chip size increases.
  • step of forming the first isolation structure 306 with the step of forming the anti-reflection layer 304 can reduce the process flow, however, it should be noted that the step of forming the first isolation structure 306 can also Layer 304 is performed individually before or after.
  • the preparation method further includes: forming a filter (not shown) on the third electrode 303 and the anti-reflection layer 304 .
  • the integration of the APD array chip is increased by growing the optical filter directly above the back-illuminated avalanche photodiode array.
  • the filter material layer is defined by photolithography, and then the filter material layer is etched to form a filter above the back-illuminated avalanche photodiode array.
  • the method further includes: forming a plurality of lens structures 305 on the optical filter, as shown in FIG. One-to-one correspondence, by preparing the lens structure 305 above the optical filter, the filling factor of the APD array chip device is improved, the light responsivity is increased, and the crosstalk is improved.
  • a step of forming a light trapping structure is also included before forming the lens structure 305 .
  • the light trapping structure is formed on the third surface of the epitaxial layer, specifically including a plurality of raised structures disposed on the epitaxial layer, such as inverted pyramids Type protrusions, column type protrusions, etc., the light trapping structure is used to increase the optical distance, thereby improving the quantum efficiency.
  • the light trapping structure may be formed by performing wet etching or dry etching on the thinned first substrate 301 and the third surface of the epitaxial layer, and each avalanche photodiode may correspond to a group of light trapping structures.
  • the manufacturing method further includes:
  • the buffer layer 316 has a first opening corresponding to each of the electrode openings
  • a conductive base 317 is formed on the bottom of the electrode opening, on the sidewall of the electrode opening and on the sidewall of the first opening, wherein part of the conductive base 317 also extends to the buffer layer outside the first opening 316, wherein adjacent conductive substrates 317 are spaced from each other;
  • Conductive bumps 318 are formed on the conductive substrate 317 . Further, solder 319 is further provided on the end of the conductive bump 318 away from the conductive base 317 .
  • the method of forming the buffer layer 316 can be chemical vapor deposition (CVD) or other suitable methods, and the formed buffer layer covers the second passivation layer 312 and the part of the second electrode 315 exposed by the electrode opening.
  • CVD chemical vapor deposition
  • the step of forming a first opening corresponding to each of the electrode openings in the buffer layer 316 includes: forming a photoresist layer on the buffer layer 316; patterning the photoresist layer according to the arrangement of the electrode openings; resist layer; using the patterned photoresist layer as a mask, etch the buffer layer 316 to form first openings corresponding to the electrode openings in the buffer layer; ashing to remove the photoresist layer.
  • the method for forming the conductive base 317 on the bottom of the electrode opening, on the sidewall of the electrode opening and on the sidewall of the first opening includes the following steps: chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or atomic layer deposition (ALD) method to form a conductive material layer, the conductive material layer covers the surface of the buffer layer 316 and the bottom of the electrode opening, the side walls of the electrode opening and the The sidewall of the first opening; using methods such as chemical mechanical grinding or etching to remove part or all of the conductive material covering the surface of the buffer layer 316, at least located at the bottom of the electrode opening, on the sidewall of the electrode opening and all The remaining conductive material on the sidewalls of the first opening forms a conductive base 317 .
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the conductive bump 318 may be copper (Cu). Further, the end of the conductive bump 318 away from the conductive base 317 may also be provided with a solder 319, and the solder 319 may be tin-silver alloy (SnAg).
  • a distance measuring device is also provided.
  • the structure of a distance measuring device in the embodiment of the present application will be described in detail below with reference to FIG. 7 and FIG. 8 .
  • the distance measuring device This includes radar ranging devices such as lidar.
  • the distance measuring device may be an electronic device such as a laser radar or a laser distance measuring device.
  • the ranging device is used to sense external environment information, for example, distance information, orientation information, reflection intensity information, speed information, etc. of environmental objects.
  • the distance measuring device can detect the distance from the detection object to the distance measurement device by measuring the time of light propagation between the distance measurement device and the detection object, that is, the time-of-flight (TOF).
  • TOF time-of-flight
  • the distance measuring device can also detect the distance from the detection object to the distance measuring device by other technologies, such as a distance measuring method based on phase shift (phase shift) measurement, or a distance measuring method based on frequency shift (frequency shift) measurement, in This is not limited.
  • the distance measuring device adopts the back-illuminated avalanche photodiode array chip mentioned above, and the distance measuring device can be implemented as a solid-state laser radar, which can directly emit pulsed laser that can cover the detection area in a short time , and then use the highly sensitive area array APD chip to receive the echo signal, and complete the detection and perception of the distance information of the surrounding environment through a mode similar to that of a camera.
  • solid-state lidar Compared with mechanical scanning lidar, solid-state lidar has smaller size, lower cost, more stable performance, excellent reliability, and is easier to pass the vehicle regulations.
  • the ranging device 100 includes a transmitting circuit 110, a scanning module (not shown), a control module (not shown) and a detection module, and the detection module includes the aforementioned receiving chip, which may include a back-illuminated avalanche photodiode
  • the array chip 120 and the signal processing unit 130 may also include an arithmetic circuit 140 , and the back-illuminated avalanche photodiode array chip 120 may be realized by the aforementioned back-illuminated avalanche photodiode array chip 300 .
  • the transmitting circuit is used to transmit the light pulse sequence to detect the target scene; the scanning module 202 is used to sequentially change the propagation path of the light pulse sequence emitted by the transmitting circuit to different directions to form a scanning field of view; the detection module is used to receive The light pulse sequence reflected back by the object, and the distance and/or orientation of the object relative to the distance measuring device are determined according to the reflected light pulse sequence, so as to generate the point cloud points.
  • the transmitting circuit 110 may include a transmitter for emitting a sequence of light pulses (eg, a sequence of laser pulses).
  • the back-illuminated avalanche photodiode array chip 120 can receive the light pulse sequence reflected by the detected object, that is, obtain the pulse waveform of the echo signal through it, and perform photoelectric conversion on the light pulse sequence to obtain an electrical signal.
  • the arithmetic circuit 140 can determine the distance between the ranging device 100 and the detected object, that is, the depth, based on the output result of the signal processing unit 130 .
  • the ranging device 100 may also include a control module (not shown), which can control other circuits or modules, for example, can control the working time of each circuit or module and/or control each circuit Or the module performs parameter setting, etc., and the control module can also perform some calculation processing, etc., and can also perform channel coding, channel decoding, etc., and the control module can include a controller.
  • a control module (not shown), which can control other circuits or modules, for example, can control the working time of each circuit or module and/or control each circuit Or the module performs parameter setting, etc., and the control module can also perform some calculation processing, etc., and can also perform channel coding, channel decoding, etc., and the control module can include a controller.
  • the distance measuring device shown in FIG. 7 includes a transmitting circuit 110, a back-illuminated avalanche photodiode array chip 120, a signal processing unit 130 and an arithmetic circuit 140, it may also include, for example, a sampling circuit wait.
  • the distance measuring device 100 may also include a scanning module (not shown), configured to change the propagation direction of at least one optical pulse sequence (such as a laser pulse sequence) emitted by the transmitting circuit, to output Scan the field of view.
  • a scanning module configured to change the propagation direction of at least one optical pulse sequence (such as a laser pulse sequence) emitted by the transmitting circuit, to output Scan the field of view.
  • the scanning area of the scanning module within the field of view of the distance measuring device increases with the accumulation of time.
  • the module including the transmitting circuit 110, the back-illuminated avalanche photodiode array chip 120, the signal processing unit 130 and the arithmetic circuit 140 may be included, or the module including the back-illuminated avalanche photodiode array chip 120, the signal processing unit 130, and the arithmetic circuit
  • the modules of 140 and the control module 150 are called a ranging module, and the ranging module may be independent of other modules, for example, a scanning module.
  • a coaxial optical path may be used in the distance measuring device, that is, the light beam emitted by the distance measuring device and the reflected light beam share at least part of the light path in the distance measuring device.
  • the distance measuring device may also adopt an off-axis optical path, that is, the light beam emitted by the distance measuring device and the reflected light beam are respectively transmitted along different optical paths in the distance measuring device.
  • FIG. 8 shows a schematic diagram of an embodiment in which the distance measuring device of the present application adopts a coaxial optical path.
  • the ranging device 200 includes a ranging module 210, and the ranging module 210 includes a transmitter 203 (which may include the above-mentioned transmitting circuit), a collimating element 204, a receiver 205 and an optical path changing element 206, and the receiver 205 may include the above-mentioned back
  • the illuminated avalanche photodiode array chip 120, the signal processing unit 130, the computing circuit, and the ranging module 210 are used to emit light beams, receive the returned light, and convert the returned light into electrical signals.
  • the transmitter 203 can be used to transmit the light pulse sequence. In one embodiment, the transmitter 203 may emit a sequence of laser pulses.
  • the laser beam emitted by the transmitter 203 is a narrow-bandwidth beam whose wavelength is outside the range of visible light.
  • the collimating element 204 is arranged on the outgoing light path of the emitter, and is used for collimating the light beam emitted from the emitter 203, and collimating the light beam emitted by the emitter 203 into a parallel light that is emitted to the scanning module.
  • the collimating element is also used to converge at least a portion of the return light reflected by the detection object.
  • the collimating element 204 may be a collimating lens or other elements capable of collimating light beams.
  • the transmitting optical path and the receiving optical path in the distance measuring device are combined before the collimating element 204 through the optical path changing element 206, so that the transmitting optical path and the receiving optical path can share the same collimating element, so that the optical path more compact.
  • the transmitter 203 and the receiver 205 respectively use their own collimating elements, and the optical path changing element 206 is arranged on the optical path after the collimating element.
  • the optical path changing element can use a small-area reflector to The emitting light path and the receiving light path are merged.
  • the optical path changing element may also use a reflector with a through hole, wherein the through hole is used to transmit the outgoing light of the transmitter 203 , and the reflector is used to reflect the return light to the receiver 205 . This can reduce the shadowing of the return light by the support of the small reflector in the case of using a small reflector.
  • the optical path changing element deviates from the optical axis of the collimating element 204 .
  • the optical path changing element may also be located on the optical axis of the collimating element 204 .
  • the ranging device 200 also includes a scanning module 202 .
  • the scanning module 202 is placed on the outgoing optical path of the distance measuring module 210.
  • the scanning module 202 is used to change the transmission direction of the collimated light beam 219 emitted by the collimating element 204 and project it to the external environment, and project the return light to the collimating element 204 .
  • the returning light is converged to the receiver 205 through the collimation element 204 .
  • the scanning module 202 may include at least one optical element for changing the propagation path of the beam, wherein the optical element may change the propagation path of the beam by reflecting, refracting, diffracting, etc.
  • the optical element includes at least one light refraction element with a non-parallel exit surface and an incident surface.
  • the scanning module 202 includes a lens, a mirror, a prism, a vibrating mirror, a grating, a liquid crystal, an optical phased array (Optical Phased Array), or any combination of the above optical elements.
  • At least part of the optical elements are movable, for example, driven by a driving module to move the at least part of the optical elements, and the moving optical elements can reflect, refract or diffract light beams to different directions at different times.
  • multiple optical elements of scanning module 202 may rotate or vibrate about a common axis 209, with each rotating or vibrating optical element serving to continuously change the direction of propagation of the incident light beam.
  • the multiple optical elements of scanning module 202 may rotate at different rotational speeds, or vibrate at different speeds.
  • at least some of the optical elements of scanning module 202 may rotate at substantially the same rotational speed.
  • the multiple optical elements of the scanning module may also rotate about different axes.
  • the multiple optical elements of the scanning module may also rotate in the same direction or in different directions; or vibrate in the same direction or in different directions, which is not limited here.
  • the scanning module 202 includes a first optical element 214 and a driver 216 connected to the first optical element 214, the driver 216 is used to drive the first optical element 214 to rotate around the rotation axis 209, so that the first optical element 214 changes The direction of the collimated light beam 219 .
  • the first optical element 214 projects the collimated light beam 219 in different directions.
  • the angle between the direction of the collimated light beam 219 changed by the first optical element and the rotation axis 209 changes as the first optical element 214 rotates.
  • first optical element 214 includes a pair of opposing non-parallel surfaces through which collimated light beam 219 passes.
  • the first optical element 214 comprises a prism having a thickness varying along at least one radial direction.
  • the first optical element 214 includes a wedge prism that refracts the collimated light beam 219 .
  • the scanning module 202 further includes a second optical element 215 , the second optical element 215 rotates around the rotation axis 209 , and the rotation speed of the second optical element 215 is different from that of the first optical element 214 .
  • the second optical element 215 is used to change the direction of the light beam projected by the first optical element 214 .
  • the second optical element 215 is connected with another driver 217, and the driver 217 drives the second optical element 215 to rotate.
  • the first optical element 214 and the second optical element 215 can be driven by the same or different drivers, so that the rotation speed and/or the direction of rotation of the first optical element 214 and the second optical element 215 are different, thereby projecting a collimated light beam 219 to the external space In different directions, a larger spatial range can be scanned.
  • the controller 218 controls the drivers 216 and 217 to drive the first optical element 214 and the second optical element 215 respectively.
  • the rotational speeds of the first optical element 214 and the second optical element 215 can be determined according to the area and pattern expected to be scanned in practical applications.
  • Drivers 216 and 217 may include motors or other drivers.
  • the rotation directions of the first optical element 214 and the second optical element 215 are the same, or the rotation directions of the first optical element and the second optical element are different.
  • the second optical element 215 includes a pair of opposing non-parallel surfaces through which the light beam passes.
  • the second optical element 215 comprises a prism whose thickness varies along at least one radial direction.
  • the second optical element 215 comprises a wedge prism.
  • the scanning module 202 further includes a third optical element (not shown in the figure) and a driver for driving the movement of the third optical element.
  • the third optical element includes a pair of opposite non-parallel surfaces through which the light beam passes.
  • the third optical element comprises a prism whose thickness varies along at least one radial direction.
  • the third optical element comprises a wedge prism. At least two of the first, second and third optical elements rotate at different rotational speeds and/or deflections.
  • the scanning module includes 2 or 3 photorefractive elements sequentially arranged on the outgoing optical path of the optical pulse sequence.
  • at least two of the photorefractive elements in the scanning module rotate during the scanning process, so as to change the direction of the light pulse sequence.
  • the scanning path of the scanning module is different at least partly at different times.
  • the rotation of each optical element in the scanning module 202 can project light to different directions, such as the direction of the projected light 211 and the direction 213. space to scan.
  • the light 211 projected by the scanning module 202 hits the detection object 201 , a part of the light is reflected by the detection object 201 to the distance measuring device 200 in a direction opposite to the projected light 211 .
  • the return light 212 reflected by the detection object 201 enters the collimation element 204 after passing through the scanning module 202 .
  • the receiver 205 and the emitter 203 are placed on the same side of the collimation element 204, and the receiver 205 is used to convert at least part of the return light passing through the collimation element 204 into an electrical signal.
  • each optical element is coated with an anti-reflection film.
  • the thickness of the antireflection film is equal to or close to the wavelength of the light beam emitted by the emitter 203, which can increase the intensity of the transmitted light beam.
  • a filter layer is coated on the surface of a component located on the beam propagation path in the ranging device, or an optical filter is arranged on the beam propagation path, for at least transmitting the wavelength band of the beam emitted by the transmitter, Reflect other bands to reduce noise from ambient light to the receiver.
  • the transmitter 203 may include a laser diode, and the laser diode emits nanosecond-level laser pulses.
  • the laser pulse receiving time can be determined, for example, the laser pulse receiving time can be determined by detecting the rising edge time and/or falling edge time of the electrical signal pulse.
  • the distance measuring device 200 can calculate the TOF by using the pulse receiving time information and the pulse sending time information, so as to determine the distance from the detection object 201 to the distance measuring device 200 .
  • the distance and orientation detected by the ranging device 200 can be used for remote sensing, obstacle avoidance, surveying and mapping, modeling, navigation and so on.
  • the distance measuring device of the present application may not have a scanning module, so as to realize a solid-state laser radar.
  • the distance measuring device of the present application adopts the aforementioned back-illuminated avalanche photodiode array chip, so it has all the advantages of the back-illuminated avalanche photodiode array chip, which will not be repeated here.
  • the present application also provides a movable platform, wherein the distance measuring device mentioned above can be applied to the movable platform, and the distance measuring device can be installed on the movable platform body of the movable platform.
  • the mobile platform includes at least one of an unmanned aerial vehicle, an automobile, a remote control vehicle, a robot, and a camera.
  • the ranging device is applied to the unmanned aerial vehicle
  • the movable platform body is the fuselage of the unmanned aerial vehicle.
  • the movable platform body is the body of the car.
  • the car may be an automatic driving car or a semi-automatic driving car, which is not limited here.
  • the movable platform body is the body of the remote control car.
  • the movable platform body is a robot.
  • the movable platform body is the body of the camera.
  • the movable platform may further include a power system for driving the movable platform body to move.
  • the power system may be an engine inside the vehicle, which will not be listed one by one here.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another device, or some features may be omitted, or not implemented.
  • the various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all functions of some modules according to the embodiments of the present application.
  • DSP digital signal processor
  • the present application can also be implemented as an apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein.
  • Such a program implementing the present application may be stored on a computer-readable medium, or may be in the form of one or more signals.
  • Such a signal may be downloaded from an Internet site, or provided on a carrier signal, or provided in any other form.

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Abstract

一种背照式雪崩光电二极管阵列芯片、接收芯片、测距装置及可移动平台，背照式雪崩光电二极管阵列芯片包括：第一衬底，具有相对设置的第一表面和第二表面；外延层，具有相对设置的第三表面和第四表面，外延层的第三表面形成在第一衬底的第二表面上；雪崩光电二极管阵列，形成于外延层的第四表面；第二衬底，设置在雪崩光电二极管阵列背离外延层的一侧，第二衬底内形成有贯穿第二衬底并与雪崩光电二极管阵列电连接的多个电连接结构，多个电连接结构用于使雪崩光电二极管阵列和信号处理单元电连接。

Description

背照式雪崩光电二极管阵列芯片、接收芯片、测距装置及可移动平台
说明书
技术领域
本发明涉及集成电路领域，具体而言涉及一种背照式雪崩光电二极管阵列芯片、接收芯片、测距装置及可移动平台。
背景技术
激光雷达作为自动驾驶的核心传感器，目前主流采用的都是机械旋转式激光雷达。该类型的激光雷达一般具有由于引入多个机械部件造成的可靠性低，对焦对准困难造成的生产效率低等问题。
而有着更小的尺寸、更低成本的固态激光雷达，相较于机械扫描式激光雷达，拥有更稳定的性能，优异的可靠性，更容易过车规，固态激光雷达(或称Flash雷达)一度被视为激光雷达的“终极未来”。
目前激光雷达中用到的接收芯片，大多是单线雪崩光电二极管(Avalanche Photon Diode，APD)，或者小规模的APD线阵列或APD面阵列，而固态激光雷达中用到的核心接收芯片，需要有上千个接收单元，需要用到高集成度、阵列化的接收芯片和与之集成的模拟信号处理电路和数字电路芯片，即面阵化的APD接收芯片，因此，对设计一种面阵化的APD接收芯片已成为业界主要关注的问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
本申请实施例第一方面提供一种背照式雪崩光电二极管阵列芯片，所述背照式雪崩光电二极管阵列芯片包括：
第一衬底，具有相对设置的第一表面和第二表面；
外延层，具有相对设置的第三表面和第四表面，所述外延层的第三表面形成在所述第一衬底的第二表面上；
雪崩光电二极管阵列，形成于所述外延层的第四表面；
第二衬底，设置在所述雪崩光电二极管阵列背离所述外延层的一侧，所述第二衬底内形成有贯穿所述第二衬底并与所述雪崩光电二极管阵列电连接的多个电连接结构，所述多个电连接结构用于使所述雪崩光电二极管阵列和信号处理单元电连接。
本申请实施例第二方面提供一种接收芯片，所述接收芯片包括：前文所述的背照式雪崩光电二极管阵列芯片，用于接收光发射电路出射的光脉冲序列经过被探测物反射的回光信号，并将所述回光信号转换为电信号；
信号处理单元，和所述背照式雪崩光电二极管阵列芯片电连接，用于获取所述电信号 并基于获取到的所述电信号输出时间信号。
本申请实施例第三方面提供一种测距装置，所述测距装置包括：
发射电路，用于出射光脉冲序列；
前文所述的背照式雪崩光电二极管阵列芯片，用于接收所述光发射电路出射的光脉冲序列经过被探测物反射的回光信号，并将所述回光信号转换为电信号；
信号处理单元，和所述背照式雪崩光电二极管阵列芯片电连接，用于获取所述电信号并基于获取到的所述电信号输出时间信号；
运算电路，用于根据所述时间信号计算所述被探测物与所述测距装置之间的距离。
本申请实施例第四方面提供一种测距装置，所述测距装置包括：
前文所述的接收芯片；
运算电路，用于根据所述时间信号计算所述被探测物与所述测距装置之间的距离。
本申请实施例第五方面提供一种可移动平台，所述可移动平台包括：
可移动平台本体；
至少一个前文所述的测距装置，设置于所述可移动平台本体。
本申请的背照式雪崩光电二极管阵列芯片，通过在外延层的第四表面设置第二衬底，并在第二衬底内形成与所述雪崩光电二极管阵列电连接的多个电连接结构，通过多个电连接结构实现所述雪崩光电二极管阵列和信号处理单元的电连接，以将雪崩光电二极管阵列的输出信号传输至信号处理单元进行处理。通过以上设计，第二衬底能够对外延层提供足够支撑，第一衬底可以更薄，电连接结构有利于信号的输出，芯片结构更加简单，且用于制作背照式雪崩光电二极管阵列芯片的工艺实现更加简单易行，并且可以适用于固态激光雷达等测距装置，有利于推动固态激光雷达尽快大规模商用，推广，满足车规的要求。
另外，本申请的背照式雪崩光电二极管阵列芯片可以实现和信号处理芯片的像素级互联，从而减小走线长度，进而减小像素间的串扰。
本申请的接收芯片、测距装置和可移动平台由于具有前述的背照式雪崩光电二极管阵列芯片，因此具有和其相同的优点。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
在附图中：
图1示出本申请提供的一实施例中背照式雪崩光电二极管阵列芯片的剖面示意图；
图2示出本申请提供的另一实施例中背照式雪崩光电二极管的剖面示意图；
图3示出本申请提供的有一实施例中背照式雪崩光电二极管的剖面示意图；
图4示出了本申请提供的一个实施例中的接收芯片的剖面示意图；
图5A至图5O示出本申请提供一实施例中背照式雪崩光电二极管阵列芯片制备过程中各中间器件的剖面示意图；
图6示出本申请提供的背照式雪崩光电二极管阵列芯片的制造方法的流程示意图；
图7示出本申请提供的一实施例中的测距装置的示意性框图；
图8示出本申请提供的一实施例中的测距装置的示意图。
具体实施方式
为了使得本申请的目的、技术方案和优点更为明显，下面将参照附图详细描述根据本申请的示例实施例。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是本申请的全部实施例，应理解，本申请不受这里描述的示例实施例的限制。基于本申请中描述的本申请实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本申请的保护范围之内。
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构，以便阐释本申请提出的技术方案。本申请的可选实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本申请的第一方面提供了一种背照式雪崩光电二极管阵列芯片300，如图1所示，所述背照式雪崩光电二极管阵列芯片300包括：
第一衬底301，具有相对设置的第一表面和第二表面；
外延层302，具有相对设置的第三表面和第四表面，所述外延层302的第三表面形成在所述第一衬底的第二表面上；
雪崩光电二极管阵列，形成于所述外延层302的第四表面；
第二衬底310，设置在所述雪崩光电二极管阵列背离所述外延层302的一侧，所述第二衬底310内形成有贯穿所述第二衬底310并与所述雪崩光电二极管阵列电连接的多个电连接结构，所述多个电连接结构用于使所述雪崩光电二极管阵列和信号处理单元电连接。
下面结合附图1、图2和图3对背照式雪崩光电二极管阵列芯片300的结构进行详细的说明，在不冲突的前提下，本申请的各个实施例的技术特征可以相互结合。
作为示例，本申请的背照式雪崩光电二极管阵列芯片300包括第一衬底301，所述第一衬底301具有相对设置的第一表面和第二表面。
其中，所述第一衬底301可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本申请的一实施例中，所述第一衬底301可以选用硅。
可选地，第一衬底301可以是P型衬底或者N型衬底，例如，在一个实施例中，本申请的第一衬底301可以是P型重掺杂衬底，也即P+型衬底，从而还可以用于APD的电压施加层。值得一提的是，在图1、图2和图3中所示的第一衬底301是经过减薄后的衬底，其减薄后的厚度可以根据实际需要合理设定，在此不做具体限定。
其中，所述外延层302具有相对设置的第三表面和第四表面，所述外延层302的第三表面形成在所述第一衬底301的第二表面上。可选地，所述外延层302可以选用半导体材料，在本申请的一实施例中，外延层302可以选用外延硅片。所述外延层302的厚度并不局限于某一数值范围。
可选地，所述外延层302可以为低掺杂的外延层，其掺杂类型可以为N型或P型，通常所述外延层302可以为P型掺杂。
在本申请中将所述外延层302设置为低掺杂的外延层可以减小APD中产生光生载流子的消耗，进而快速到达所述APD的雪崩收集区，提高所述APD的相应速度，避免APD的拖尾问题，避免器件的延迟。
在所述外延层302的第四表面形成有背照式雪崩光电二极管阵列(未示出)，可选地，背照式雪崩光电二极管阵列可以包括多个雪崩光电二极管，每个雪崩光电二极管可以对应作为一个像素单元。在本申请的一实施例中，雪崩光电二极管可以为背照式器件，即在所述背照式器件中所述感光器件APD位于电路晶体管前方的位置，光线首先进入感光器件APD，从而增大感光量。在本申请中雪崩光电二极管阵列形成于所述外延层302的第四表面，光线从外延层302的第三表面射入。
在一个示例中，背照式雪崩光电二极管可以包括雪崩区(未示出)，其位于所述外延层中，雪崩区可以包括第一掺杂层和第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域，其中：第一掺杂层，具有第一掺杂类型；第二掺杂层，位于所述第一掺杂层的上方(也即第二掺杂层比第一掺杂层更靠近外延层的第四表面)，具有第二掺杂类型，所述第一掺杂类型和所述第二掺杂类型不同。
其中，所述第一掺杂类型和所述第二掺杂类型不同，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
具体地，第一掺杂层可以是通过对所述外延层302进行第一掺杂类型的第一离子注入而形成的，在本申请中通过调节第一掺杂层的注入深度和剂量来调节雪崩区的电场强度，实现器件增益噪声因子的优化。在本申请的一实施例中，所述第一掺杂类型为P型，则第一离子注入所注入的掺杂离子可以包括但不限于硼(B)离子。
其中，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
具体地，所述第一掺杂类型和所述第二掺杂类型不同，例如，所述第一掺杂类型为P型，所述第二掺杂类型为N型，在本申请的一实施例中，第二掺杂层可以通过对外延层进行第二掺杂类型的第二离子注入而形成，其中第二离子注入所注入的掺杂离子包括但不限于P(磷)离子或As离子等。可选地，所述第二离子注入的峰值浓度的深度小于或等于200nm，在本申请的一实施例中，所述第二离子注入的峰值浓度的深度为100nm。
可选地，在所述雪崩区的下方(也即第一掺杂层和外延层的第三表面之间)还可以 进一步包括吸收层等，在此不再赘述。
在一个示例中，在所述外延层302中还形成有保护环，保护环包围的所述第二掺杂层，保护环和第二掺杂层可以通过对外延层执行第二离子注入同时形成，通过形成所述保护环以防止边缘击穿，进一步提高器件的良率和性能。
其中，所述保护环的形成步骤可以在所述第一掺杂类型的第一离子注入之前，还可以在所述第一掺杂类型的第一离子注入之后以及在所述第二掺杂类型的第二离子注入之前，可以根据实际需要进行选择。在本申请的一实施例中，在所述第一掺杂类型的第一离子注入之前形成所述保护环。
可选地，所述保护环的深度可以大于或等于2μm。
在一个示例中，在所述外延层的第四表面的边缘区域还形成有隔离环(未示出)，阵列外围通过隔离环将背照式雪崩光电二极管阵列与外围区域分离开，且隔离环通过金属电极连接接地电极，减少阵列外围区域可能引起的光串扰和电串扰。在一个示例中，可以通过执行第二掺杂类型的离子注入的方法形成隔离环，其中，所述第二掺杂类型的第四离子注入为N型离子注入。
在所述外延层302的第四表面形成有第一钝化层311，所述第一钝化层311内设置有彼此间隔的多个第一电极313，其中，每个所述第一电极313电连接至少一个所述雪崩光电二极管，例如，每个第一电极313对应连接一个雪崩光电二极管，可选地，第一电极313可以包括焊盘，例如具有导电性的金属焊盘，金属焊盘包括但不限于铝焊盘等。示例性地，所述第一钝化层311的顶面高于第一电极313例如焊盘的顶面。第一钝化层311的厚度可以是任意适合的厚度，在此不做具体限定。
第一钝化层311的材料可以使用任何适合的绝缘材料，例如第一钝化层311使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层。
在本申请的一实施例中，第二衬底310设置在所述雪崩光电二极管阵列背离所述外延层302的一侧，即外延层的302的第四表面一侧，例如第二衬底310包括第一表面和与第一表面相对的第二表面，则第二衬底310的第一表面和形成在外延层上的第一钝化层311相接合，例如相键合。
其中，所述第二衬底310可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本申请的一实施例中，所述第二衬底310选用硅。
所述第二衬底310内形成有贯穿所述第二衬底310并与所述雪崩光电二极管阵列电连接的多个电连接结构，所述多个电连接结构用于使所述雪崩光电二极管阵列和信号处理单元电连接。可选地，每个所述电连接结构电连接至少一个所述第一电极313，所述电连接结构与所述第一电极电连接的端部位于所述第一钝化层311内。
在一个示例中，所述电连接结构包括导电插塞314和与所述导电插塞314电连接的第二电极315，其中，所述导电插塞314贯穿所述第二衬底310，所述第二电极315设置于所述第二衬底310背离所述外延层302的一侧。
其中，导电插塞314可以是通过对第二衬底310刻蚀形成导电通孔，再利用金属例如W等填充该导电通孔而获得的，并且，在该导电通孔的侧壁上还可以设置钝化层。
在所述第二衬底310形成有所述第二电极315的一侧(例如第二衬底310的第二表面) 设置有第二钝化层312，所述第二电极315设置于所述第二钝化层312内，例如相邻第二电极315通过第二钝化层312相隔离。可选地，每个所述第二电极315电连接至少一个导电插塞314，例如，每个第二电极315对应连接一个导电插塞314，可选地，第二电极315可以包括焊盘，例如具有导电性的金属焊盘，金属焊盘包括但不限于铝焊盘等。示例性地，所述第二钝化层312的顶面高于第二电极315例如焊盘的顶面。第二钝化层312的厚度可以是任意适合的厚度，在此不做具体限定。
第二钝化层312的材料可以使用任何适合的绝缘材料，例如第二钝化层312使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层。在本申请的一实施例中，所述第一电极313和所述第二电极315选用铝(Al)，所述导电插塞314选用钨(W)或者其他适合的金属材料。
在一个示例中，每个所述电连接结构还包括凸块结构，所述凸块结构设置于所述第二电极315上，所述凸块结构用于电连接所述第二电极和信号处理单元。
凸块结构可以是本领域技术人员熟知的任意适合的结构，在本申请的一实施例中，如图1所示，所述凸块结构包括导电基底317和导电凸块318，所述导电基底317嵌入在所述第二钝化层312中并与所述第二电极315电连接，所述导电凸块318设置于所述导电基底317上，所述导电凸块318背离所述导电基底317的一端还设置有焊料319，该焊料319可以作为焊锡端(solder tip)，其可以通过例如回流焊等呈现为焊锡球，可选地，焊料319可以包括锡、银等金属材料中的至少一种。可选地，导电凸块318可以是任意适合的结构，例如导电凸块318可以包括铜柱或者其他适合的导电结构。
可选地，导电基底317也可以称为凸块下底部金属层(UBM)，其可以由钛(Ti)、氮化钛(TiN)、铜镍(CuNi)、铝(Al)等形成，其厚度可能介于约0.1μm至约5μm的范围内，具体可以根据实际需要合理选择。
在一个示例中，第二钝化层312上还设置有缓冲层316，所述第二钝化层312和所述缓冲层316内设置有开口，所述导电基底317包括设置于所述开口的底部和侧壁上的第一导电部分和延伸至缓冲层316上的第二导电部分，所述缓冲层316用于缓冲所述第一导电部分和所述第二导电部分连接处的应力。缓冲层316的材料可以是任意适合的能够起到应力缓冲作用的材料，例如缓冲层316可以包括聚酰亚胺等有机聚合物材料。
在一个实施例中，如图3所示，在所述第一衬底301中还可以设置第一隔离结构306，所述第一隔离结构306包括第一隔离槽和填充于所述第一隔离槽内的绝缘材料，例如绝缘材料可以采用氮化硅，氧化硅或者氮氧化硅等绝缘材料，可选地，该绝缘材料还可以和减反射层304具有相同的材料，例如可以均为氮化硅等。可选地，所述第一隔离结构306至少贯穿所述第一衬底301，部分所述第一隔离结构306可以延伸至所述外延层302内，以将所述第一衬底301划分为至少两个区域，例如，可以划分为两个区域，或者，划分为多于两个的区域。
由于APD工作期间将光信号转换为电信号，需要外部高压(HV)供电，在本申请中利用第一隔离结构306将第一衬底301划分为多个区域，对施加的工作电压进行分区控制，例如在图3所示的左右区域中分别施加工作电压，避免了随着芯片尺寸的增加，压降导致第一衬底301内的工作电压差别大、增益控制难的问题。
可选地，如图2所示，在所述外延层302的相邻雪崩光电二极管之间还设置有第二隔离结构307，所述第二隔离结构307包括第二隔离槽和填充于所述第二隔离槽内的绝缘材 料，例如绝缘材料可以采用氮化硅，氧化硅或者氮氧化硅等绝缘材料。可选地，所述第二隔离结构307贯穿所述外延层302。
在本申请的一实施例中，所述第二隔离结构307包括若干行和若干列，以围成类似田字格形状的结构，在所述田字格结构的空格中形成所述背照式雪崩光电二极管，以有效抑制相邻所述背照式雪崩光电二极管之间的电串扰。
在一个示例中，如图2所示，在所述外延层302的第三表面还可以形成有光捕获结构320，光捕获结构320用于增加光程，通过设置光捕获结构320可以增加光程，进而提高量子效率。
在本申请的一实施例中，如图2所示，光捕获结构320包括设置在所述外延层302上的多个凸起结构，例如倒金字塔型凸起、柱型凸起等，所述光捕获结构320用于增加光程，进而提高量子效率。
在一个示例中，本申请的背照式雪崩光电二极管阵列芯片300还包括减反射层304，减反射层304覆盖所述第一衬底301的第一表面，其中，所述减反射层304可以选用Si3N4或者其他适合的能够起到减反作用的透光膜层，以进一步增加光线的透光率，减小光线的反射，进而提高器件的性能。
在一个示例中，在所述减反射层304上形成有透镜结构305，光可以经过透镜结构305会聚后入射到APD，从而提高APD阵列芯片器件填充因子，增加光响应率，改善串扰。在本申请的一实施例中，所述透镜结构可以是由多个微透镜组成的微透镜阵列。可选地，微透镜阵列中的微透镜和雪崩光电二极管可以是一一对应。
综上所述，本申请的背照式雪崩光电二极管阵列芯片，通过在外延层的第四表面设置第二衬底，并在第二衬底内形成与所述雪崩光电二极管阵列电连接的多个电连接结构，通过多个电连接结构实现所述雪崩光电二极管阵列和信号处理单元的电连接，以将雪崩光电二极管阵列的输出信号传输至信号处理单元进行处理。通过以上设计，第二衬底能够对外延层提供足够支撑，第一衬底可以更薄，电连接结构有利于信号的输出，芯片结构更加简单，且用于制作背照式雪崩光电二极管阵列芯片的工艺实现更加简单易行，并且可以适用于固态激光雷达等测距装置，有利于推动固态激光雷达尽快大规模商用，推广，满足车规的要求。
另外，本申请的背照式雪崩光电二极管阵列芯片可以实现和信号处理芯片的像素级互联，从而减小走线长度，进而减小像素间的串扰。
进一步，如图4所示，本申请还提供了一种接收芯片(接收芯片可以是接收器或探测器的一部分)，其中，所述接收芯片包括：前文所述的背照式雪崩光电二极管芯片，用于接收经过被探测物反射的光脉冲序列，并将接收的光脉冲序列转换为电信号；信号处理单元，和所述背照式雪崩光电二极管芯片电连接，用于获取所述电信号并基于获取到的所述电信号输出时间信号。
例如，如图4所示，信号处理单元包括信号处理芯片400，用于接收所述背照式雪崩光电二极管芯片的电信号并进行处理，以输出时间信号。信号处理芯片400可以包括第一表面和与第一表面相对的第二表面，在信号处理芯片400的第一表面可以形成有钝化层410，在钝化层410内设置有间隔设置的第四电极430，其中，第四电极430的数量可以取决于背照式雪崩光电二极管阵列芯片300的电连接结构的数量，其可以和背照式雪崩光电二极管阵列芯片300的电连接结构一一对应。
相邻第四电极430通过钝化层410相隔离。可选地，第四电极430可以包括焊盘，例如具有导电性的金属焊盘，金属焊盘包括但不限于铝焊盘等。示例性地，所述钝化层410的顶面高于第四电极430例如焊盘的顶面。钝化层410的厚度可以是任意适合的厚度，在此不做具体限定。钝化层410的材料可以使用任何适合的绝缘材料，例如钝化层410使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层。在第四电极430上还形成有用于和背照式雪崩光电二极管阵列芯片300的电连接结构电连接的凸块结构，该凸块结构可以用于电连接背照式雪崩光电二极管阵列芯片300的电连接结构的凸块结构，以实现背照式雪崩光电二极管阵列芯片300和信号处理单元的电连接。
凸块结构可以是本领域技术人员熟知的任意适合的结构，在本申请的一实施例中，如图4所示，所述凸块结构包括导电基底441和导电凸块442，所述导电基底441嵌入在所述钝化层410中并与所述第二电极315电连接，所述导电凸块442设置于所述导电基底441上，所述导电凸块442背离所述导电基底441的一端还设置有焊料，该焊料可以作为焊锡端(solder tip)，其可以通过例如回流焊等呈现为焊锡球，可选地，焊料可以包括锡、银等金属材料中的至少一种。可选地，导电凸块442可以是任意适合的结构，例如导电凸块442可以包括铜柱或者其他适合的导电结构。该焊料可以和前述的电连接结构的焊料经过熔融后相接合，从而实现电连接。
可选地，导电基底441也可以称为凸块下底部金属层(UBM)，其可以由钛(Ti)、氮化钛(TiN)、铜镍(CuNi)、铝(Al)等形成，其厚度可能介于约0.1μm至约5μm的范围内，具体可以根据实际需要合理选择。
在一个示例中，钝化层410上还设置有缓冲层420，所述钝化层410和所述缓冲层420内设置有开口，所述导电基底441包括设置于所述开口的底部和侧壁上的第一导电部分和延伸至缓冲层420上的第二导电部分，所述缓冲层420用于缓冲所述第一导电部分和所述第二导电部分连接处的应力。缓冲层420的材料可以是任意适合的能够起到应力缓冲作用的材料，例如缓冲层420可以包括聚酰亚胺等有机聚合物材料。
在一个示例中，在信号处理芯片400和背照式雪崩光电二极管阵列芯片300之间的空隙中还填充有底部填充材料450，例如树脂、填充胶等，以起到支撑和连接作用。
其中，信号处理芯片400包括：
跨组放大器(Trans-Impedance Amplifier，简称TIA)，用于将所述电流信号转换为电压信号；
比较器，用于比较所述电压信号与预设电压阈值；
时间数字转换器(Time-to-Digital Converter，简称TDC)，用于根据所述比较器的比较结果，输出时间信号。
在本申请的一实施例中，所述信号处理单元集成有多个电路，在本申请的一实施例中，例如所述信号处理单元集成有跨阻放大器电路(TIA电路)、多级运算放大器OPA、比较器以及时间数字转换器电路(时间转化为数字信号的电路)或模数转换电路(ADC电路)，以及后续的数据处理电路(DSP电路)。其中，TIA电路为APD光电流转化为电压的模拟前段电路。
其中，所述多个背照式雪崩光电二极管在将光信号转换为电信号时，需要外部高压供电，APD可以提供稳定的内部增益并提高信噪比，输出电信号。
在所述信号处理单元中，所述TIA电路与所述背照式雪崩光电二极管电连接，所述 TIA电路将APD的电流信号转换为电压信号，同时提供转换增益；多级运算放大器OPA与所述TIA电路电连接，用于对TIA电路输出的信号进行放大，以满足比较器的比较幅值需求。所述比较器与所述多级运算放大器OPA电连接，其中，比较器中设置比较阈值对模拟信号进行触发，将模拟信号转换为数字信号，并将数字信号传输至TDC电路，TDC电路用于将数字信号转换为时间信号，用于距离计算。其中，对于多个信号处理单元而言，可以共用一个TDC电路，也即，信号处理单元的数量与TDC电路的数量可以不对应。
在所述信号处理单元中还可以进一步设置存储系统，以缓存数据，为接口提供输入输出缓存空间，为内部计算提供空间。
在所述信号处理单元中还可以进一步设置接口，以作为数据输入输出通道，将测量数据输出。
在本申请的一具体实施例中，比较器的第一输入端用于接收从跨组放大器输入的电信号，也即放大运算后的电信号，比较器的第二输入端用于接收预设阈值，比较器的输出端用于输出比较运算的结果，其中，比较运算的结果中包含与电信号对应的时间信息。可以理解，比较器的第二输入端接收的预设阈值可以是强度为预设阈值的电信号。比较运算的结果可以是放大运算后的电信号对应的数字信号。
可选地，所述时间数字转换器与比较器的输出端电连接，用于根据比较器输出的比较运算的结果，提取与电信号对应的时间信息。
在一个示例中，接收芯片还可以包括基板460，本申请的信号处理芯片400的第二表面还可以设置于基板上，例如通过粘接或者其他适合的方式粘贴于基板上。其中，基板还可以包括电路板，包括上可以具有各种电路结构，信号处理芯片400和背照式雪崩光电二极管阵列芯片300可以和基板上的一个或多个电路结构电连接。
在一个示例中，接收芯片还包括罩体470，设置在所述基板460的表面上，基板460和罩体470之间形成容纳空间，其中，在所述罩体470上至少部分地设置透光区域，背照式雪崩光电二极管阵列芯片300和信号处理单元400设置在所述容纳空间内，从光透过透光区域入射至背照式雪崩光电二极管阵列芯片300。
进一步地，罩体包括具有窗口的U形或方形罩体本体，以及封罩所述窗口的透光板以形成所述透光区域，其中，所述透光板与所述基体的表面平行；或所述罩体为全部透光的板状结构。进一步地，所述罩体为其内部封罩的芯片提供保护和气密环境。
示例性地，所述具有窗口的U型罩体本体在所述基板的第一表面上的投影为圆形，或者其他适合的形状，方形罩体本体在所述基板的第一表面上的投影为方形，其中，方形罩体本体与基板的尺寸相匹配，可以有效降低封装尺寸。
其中，所述透光板可以选用常用的透光材料，例如玻璃，所述玻璃应该对入射至APD的光具有高的通过性。
在另一个示例中，所述罩体为全部透光的板状结构。所述板状结构选用常用的透光材料，例如玻璃，所述玻璃必须是对对入射至APD的光具有的高通过性。其中，所述基板整体结构可以呈凹槽形状，所述凹槽可以是方形凹槽或者圆形凹槽，所述罩体设置在所述基板的凹槽顶部，与基板的顶面接合，以封罩所述凹槽，在所述基板和所述罩体之间形成容纳空间。
本申请的接收芯片由于具有前述的背照式雪崩光电二极管阵列芯片，因此具有和前述背照式雪崩光电二极管阵列芯片相同的优点。
本申请所述接收芯片采用了前文所述的背照式雪崩光电二极管芯片，所述背照式雪崩光电二极管阵列芯片300可以通过其电连接结构实现与信号处理芯片400的电连接，例如实现与信号处理芯片的像素级互联，从而减小走线长度，进而减小像素间的串扰，且容易实现对各个APD阵列中的雪崩光电二极管的独立控制。
本申请实施例还提供一种背照式雪崩光电二极管阵列芯片300的制造方法，如图6所示，所述方法包括以下步骤：
步骤S610：提供第一衬底，第一衬底具有相对设置的第一表面和第二表面，第一衬底的第二表面形成有外延层，外延层具有相对设置的第三表面和第四表面，外延层的第三表面形成在第一衬底的第二表面上，外延层的第四表面内形成有雪崩光电二极管阵列，雪崩光电二极管阵列包括多个雪崩光电二极管，外延层的第四表面上形成有第一钝化层，第一钝化层内形成有多个第一电极，每个第一电极对应电连接一个雪崩光电二极管；
步骤S620：提供第二衬底，所述第二衬底包括第一表面和与第一表面相背离的第二表面，所述第二衬底内形成有多个沟槽，所述多个沟槽的开口位于所述第二衬底的第一表面；
步骤S630：将所述第二衬底310的第一表面和所述第一衬底301相连接，并且将每个所述沟槽的开口和一个所述第一电极313相对应；
步骤S640：自所述第二衬底310的所述第二表面减薄所述第二衬底310，以露出所述沟槽位于所述第二衬底内的底部；
步骤S650：在所述沟槽内填充导电材料，以形成多个导电插塞。
下面结合附图5A-图5O对所述制备方法进行详细的说明，其中，图5A-图5O示出本申请提供的背照式雪崩光电二极管阵列芯片300制备过程中各中间器件的剖面示意图。
在所述步骤S610中，如图5A所示，提供第一衬底301，第一衬底具有相对设置的第一表面和第二表面，第一衬底301的第二表面形成有外延层302，外延层302具有相对设置的第三表面和第四表面，外延层302的第三表面形成在第一衬底301的第二表面上，所述外延层302的第四表面内形成有雪崩光电二极管阵列，所述雪崩光电二极管阵列包括多个雪崩光电二极管，外延层302的第四表面上形成有第一钝化层311，所述第一钝化层311内形成有多个第一电极313，每个所述第一电极313对应电连接一个所述雪崩光电二极管。
其中，所述第一衬底301可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本申请的一实施例中，所述第一衬底301选用硅。
所述外延层302可以选用半导体材料，在本申请的一实施例中，选用外延硅片。所述外延层302的厚度并不局限于某一数值范围。所述外延层302的形成方法可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等。
在本申请的一实施例中，所述雪崩光电二极管可以为背照式器件，即在所述背照式器件中所述感光器件APD位于电路晶体管前方的位置，光线首先进入感光器件APD，从而增大感光量。在本申请中所述APD形成于所述外延层302背离所述第一衬底301的表面。
可选地，所述外延层302具有低掺杂类型，掺杂类型可以为N型或P型，通常所述 外延层302为P型掺杂。
在本申请中将所述外延层302设置为低掺杂类型可以减小所述APD中产生光生载流子的消耗，进而快速到达所述APD的雪崩收集区，提高所述APD的相应速度，避免APD的拖尾问题，避免器件的延迟。
所述背照式雪崩光电二极管包括：
雪崩区，位于所述外延层中，包括第一掺杂层和第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域，其中：
所述第一掺杂层，具有第一掺杂类型；
所述第二掺杂层，位于所述第一掺杂层的上方，具有第二掺杂类型，所述第一掺杂类型和所述第二掺杂类型不同。
其中，所述第一掺杂类型和所述第二掺杂类型不同，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
具体地，对所述外延层302进行第一掺杂类型的第一离子注入，以形成第一掺杂层，在本申请中通过调节第一掺杂层的注入深度和剂量来调节雪崩区的电场强度，实现器件增益噪声因子的优化。
其中，所述第一离子注入为P型离子注入，在本申请的一实施例中，所述P型离子为硼(B)离子。
其中，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
具体地，所述第一掺杂类型和所述第二掺杂类型不同，其中，所述第一离子注入为P型，所述第二离子注入为N型，在本申请的一实施例中，所述第二离子注入为P(磷)离子或As离子。
可选地，在所述雪崩区的下方还可以进一步包括吸收层等，在此不再赘述。
其中，所述第二离子注入的峰值浓度的深度小于或等于200nm，在本申请的一是实施例中，所述第二离子注入的峰值浓度的深度为100nm。
在所述外延层302中还形成有保护环，并在后续的所述第二离子注入步骤时，在所述保护环内执行所述第二离子注入并形成被所述保护环包围的所述第二掺杂层，通过形成所述保护环以防止边缘击穿，进一步提高器件的良率和性能。
其中，所述保护环的形成步骤可以在所述第一掺杂类型的第一离子注入之前，还可以在所述第一掺杂类型的第一离子注入之后以及在所述第二掺杂类型的第二离子注入之前，可以根据实际需要进行选择。
在本申请的一实施例中，在所述第一掺杂类型的第一离子注入之前形成所述保护环。
其中，所述保护环的深度为大于或等于2μm。
在所述外延层的第四表面的边缘区域还形成有隔离环，阵列外围通过隔离环将背照式雪崩光电二极管阵列与外围区域分离开，且隔离环通过金属电极连接接地电极，减少阵列外围区域可能引起的光串扰和电串扰。
通过执行第二掺杂类型的第四离子注入的方法形成所述隔离环，其中，所述第二掺杂类型的第四离子注入为N型离子注入。
进一步，继续如图5A所示，第一钝化层311内设置有彼此间隔的多个第一电极313， 其中，每个所述第一电极313电连接至少一个所述雪崩光电二极管，每个所述电连接结构电连接至少一个所述第一电极313，所述电连接结构与所述第一电极电连接的端部位于所述第一钝化层311内。
所述第一电极313的形成方法包括：
在所述外延层302背离所述第一衬底301的表面形成第一电极材料层；
通过光刻定义第一电极区域及分布，将其余第一电极材料层通过刻蚀方式清除干净，以形成相互间隔的多个第一电极313。
在本申请的一实施例中，所述第一电极材料层包括但不限于铝(Al)。
在形成相互间隔的多个第一电极313之后，还包括以下步骤：
形成第一钝化层311，以覆盖所述第一电极313和所述外延层302的第四表面；
在所述第二钝化层312中形成多个电极开口，每个所述电极开口露出与其相对的一个所述第一电极313的部分表面，以便于将第一电极313引出。
可选地，在所述外延层302的相邻所述雪崩光电二极管之间还设置有第二隔离结构307。
在形成所述第一电极313及所述第一钝化层311之前还可以包括形成第二隔离结构307的步骤：
采用深反应离子刻蚀形成贯穿所述外延层302的第二隔离槽；
在所述第二隔离槽中填充绝缘材料。通过第二隔离结构可以方式相邻像素之间的电串扰。
在所述步骤S620中，如图5B-5D所示，提供第二衬底310，所述第二衬底310包括第一表面和与所述第一表面相背离的第二表面，如图5C所示，所述第二衬底310内形成有多个沟槽，所述多个沟槽的开口位于第二衬底310的第一表面。
其中，所述第二衬底310可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本申请的一实施例中，所述第二衬底310选用硅。
在本申请的一实施例中，执行光刻以及刻蚀工艺以在所述第二衬底310内形成多个沟槽，例如通过光刻工艺在第二衬底310的第一表面上形成掩膜层，再以该掩膜层为掩膜，通过例如干法刻蚀或者湿法刻蚀等刻蚀工艺刻蚀第二衬底310，形成多个沟槽，该多个沟槽的深度可以在50-100微米之间的任意深度，具体可以根据实际需要合理设定。
在本申请的一实施例中，如图5D所示，还可以进一步在所述多个沟槽的底部、侧壁以及第二衬底310的第一表面形成隔离层3101，用于隔离刻蚀形成表面漏电流。可选地，可以通过热氧化或者化学沉积等方法形成该隔离层3101，例如可以通过热氧化的方法形成例如氧化硅的隔离层3101，该隔离层3101的厚度大约在0.2微米-0.8微米之间，例如0.2微米、0.5微米、0.7微米等。
在所述步骤S630中，如图5E所示，将所述第二衬底310的第一表面和所述第一衬底301相连接，并且将每个所述沟槽的开口和一个所述第一电极313相对应，例如和第一电极313上的电极开口相对应。
在本申请的一实施例中，采用晶圆级键合封装工艺将所述外延层302与所述第二衬底310键合，例如将第二衬底310的隔离层和第一钝化层进行键合，以实现第一衬底和外 延层302的键合。
在所述步骤S640中，如图5F所示，自所述第二衬底310的所述第二表面减薄所述第二衬底310，以露出所述沟槽位于所述第二衬底310内的底部。
在本申请的一实施例中，采用背面研磨(Back Grinding)等工艺减薄所述第二衬底，以露出所述沟槽。所述沟槽的位置与上述第一电极313上的电极开口的位置相对应，以进一步通过所述沟槽露出所述第一电极313。
在所述步骤S650中，如图5G所示，在所述沟槽内填充导电材料，以形成多个导电插塞314。
在本申请的一实施例中，所述导电材料包括但不限于钨(W)。
进一步，在形成所述导电插塞314之后，如图5H所示，所述制造方法还包括以下步骤：
在所述第二衬底310的第二表面上形成分别与所述导电插塞314电连接的多个第二电极315；
形成第二钝化层312，以覆盖所述第二电极315和所述第二衬底310的第二表面；
在所述第二钝化层312中形成多个电极开口，每个所述电极开口露出与其相对的一个所述第二电极315的部分表面。
其中，形成所述多个第二电极315的方法可以参照形成多个第一电极313的步骤，在此不再赘述。
在本申请的一实施例中，所述第二电极材料层包括但不限于铝(Al)。
接下来，如图5I所示，所述制造方法还包括以下步骤：减薄第一衬底301。
在本申请的一实施例中，采用背面研磨(Back Grinding)等工艺减薄所述第一衬底301的背面(也即第一衬底301的第一表面)。减薄后的第一衬底301的厚度可以根据实际需要合理设定。
接下来，如图5J-5L所示，所述制造方法还包括：
在所述第一衬底301的背面(也即第一表面)形成彼此间隔的多个第三电极303；
在所述第一衬底301的背面相邻的所述第三电极303之间形成减反射层304；
在所述减反射层304上形成透镜结构305。
其中，形成所述多个第三电极303的方法可以参照形成多个第一电极313的步骤，在此不再赘述。
在所述第一衬底301的背面相邻的所述第三电极303之间形成减反射层304，其中，所述减反射层304选用Si 3N 4，以进一步增加光线的透光率，减小光线的反射，进而提高器件的性能。
形成所述减反射层304的方法包括：
在所述第一衬底301的背面上形成覆盖所述第一衬底301背面以及多个第三电极303的减反射材料层；
去除高度超出所述第三电极303高度的减反射材料，以露出所述第三电极303。
其中，形成所述减反射材料层可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法等。
其中，去除高度超出所述第三电极303高度的减反射材料的方法可以选用化学机械研磨或刻蚀工艺。
可选地，在形成所述减反射层304的同时还可以在所述第一衬底301中形成第一隔离结构306，如图3所示，形成所述第一隔离结构306的步骤包括：
自所述第一衬底301的背面刻蚀所述第一衬底形成贯穿所述第一衬底301的隔离槽；
形成所述减反射层304，以覆盖所述第一衬底301的背面并填充所述隔离槽，所述隔离槽和填充在所述隔离槽内的减反射层形成第一隔离结构306，所述第一隔离结构306至少贯穿所述第一衬底301，部分所述第一隔离结构306可以延伸至所述外延层302内，所述第一隔离结构306将所述第一衬底301划分为至少两个区域。
由于APD工作期间将光信号转换为电信号，需要外部高压(HV)供电，在本申请中利用第一隔离结构306将第一衬底301划分为多个区域，施加的工作电压进行分区控制，例如在图2所示的左右区域中分别施加工作电压，避免了随着芯片尺寸的增加，压降导致第一衬底301内的工作电压差别大、增益控制难的问题。
将形成第一隔离结构306的步骤与形成所述减反射层304的步骤合并可以减少工艺流程，然而，需要说明的是，形成所述第一隔离结构306的步骤也可以在形成所述减反射层304之前或之后单独进行。
可选地，所述制备方法还包括：在所述第三电极303和所述减反射层304上形成滤光片(未示出)。通过在背照式雪崩光电二极管阵列上方直接生长滤光片，增加APD阵列芯片的集成度。
在本申请的一实施例中，通过光刻的方式定义滤光片材料层，然后蚀刻所述滤光片材料层，以在所述背照式雪崩光电二极管阵列上方形成滤光片。
在形成所述滤光片之后，所述方法进一步包括：在所述滤光片上形成多个透镜结构305，如图5L所示，每个透镜结构305与上述背照式雪崩光电二极管上下一一对应，通过在滤光片上方制备透镜结构305，提高APD阵列芯片器件填充因子，增加光响应率，改善串扰。
可选地，如图2所示，在形成透镜结构305之前还包括形成光捕获结构的步骤。
在本申请的一实施例中，如图2所示，所述光捕获结构形成在所述外延层的第三表面，具体包括设置在所述外延层上的多个凸起结构，例如倒金字塔型凸起、柱型凸起等，所述光捕获结构用于增加光程，从而提高量子效率。
可以通过对减薄后的第一衬底301和外延层的第三表面进行湿法刻蚀或者干法刻蚀而形成光捕获结构，可以是每个雪崩光电二极管对应一组光捕获结构。
接下来，如图5M-图5O所示，所述制造方法还包括：
在所述第二钝化层312上形成缓冲层316，所述缓冲层316中具有和每个所述电极开口分别对应的第一开口；
在所述电极开口的底部、所述电极开口的侧壁上以及所述第一开口的侧壁上形成导电基底317，其中部分所述导电基底317还延伸到所述第一开口外侧的缓冲层316，其中，相邻所述导电基底317之间彼此间隔；
在所述导电基底317上形成导电凸块318。进一步，所述导电凸块318背离所述导电基底317的一端还设置有焊料319。
其中，形成所述缓冲层316的方法可以选用化学气相沉积(CVD)或其他合适的方法，形成的缓冲层覆盖第二钝化层312和电极开口露出的部分第二电极315。
其中，在缓冲层316中形成和每个所述电极开口分别对应的第一开口的步骤包括： 在所述缓冲层316上形成光刻胶层；根据所述电极开口的布置图案化所述光刻胶层；以所述图案化的光刻胶层为掩膜，蚀刻所述缓冲层316，以在所述缓冲层中形成与所述电极开口分别对应的第一开口；灰化去除所述光刻胶层。
其中，在所述电极开口的底部、所述电极开口的侧壁上以及所述第一开口的侧壁上形成导电基底317的方法包括以下步骤：采用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等方法形成导电材料层，所述导电材料层覆盖所述缓冲层316表面以及所述电极开口的底部、所述电极开口的侧壁上以及所述第一开口的侧壁；采用化学机械研磨或刻蚀等方法去除覆盖所述缓冲层316表面的部分或全部导电材料，至少位于所述电极开口的底部、所述电极开口的侧壁上以及所述第一开口的侧壁上的剩余的导电材料形成导电基底317。
在本申请的一实施例中，导电凸块318可以选用铜(Cu)。进一步，导电凸块318背离所述导电基底317的一端还可以设置有焊料319，所述焊料319可以选用锡银合金(SnAg)。
在本申请的另一实施例中，还提供一种测距装置，下面将参考图7和图8对本申请实施例中的一种测距装置的结构做详细的示例性地描述，测距装置包括雷达测距装置，例如激光雷达。
本申请各个实施例提供的方案可以应用于测距装置，该测距装置可以是激光雷达、激光测距设备等电子设备。在一种实施方式中，测距装置用于感测外部环境信息，例如，环境目标的距离信息、方位信息、反射强度信息、速度信息等。一种实现方式中，测距装置可以通过测量测距装置和探测物之间光传播的时间，即光飞行时间(Time-of-Flight，TOF)，来探测探测物到测距装置的距离。或者，测距装置也可以通过其他技术来探测探测物到测距装置的距离，例如基于相位移动(phase shift)测量的测距方法，或者基于频率移动(frequency shift)测量的测距方法，在此不做限制。
所述测距装置采用了前文所述的背照式雪崩光电二极管阵列芯片，所述测距装置可以实现为固态激光雷达，所述固态激光雷达可以短时间直接发射出可以覆盖探测区域的脉冲激光，再以高度灵敏的面阵APD芯片，进行回波信号的接收，通过类似相机拍照的模式，完成对周围环境距离信息的探测和感知。相较于机械扫描式激光雷达，固态激光雷达有着更小的尺寸、更低的成本的、更稳定的性能、优异的可靠性，更容易过车规。
为了便于理解，以下将结合图7所示的测距装置100对测距的工作流程进行举例描述。
作为示例，测距装置100包括发射电路110、扫描模块(未示出)、控制模块(未示出)和探测模块，探测模块包括前述的接收芯片，该接收芯片可以包括背照式雪崩光电二极管阵列芯片120和信号处理单元130，或者还可以包括运算电路140，背照式雪崩光电二极管阵列芯片120可以由前述的背照式雪崩光电二极管阵列芯片300实现。发射电路用于发射光脉冲序列，以探测目标场景；扫描模块202用于将所述发射电路发射的光脉冲序列的传播路径依次改变至不同方向出射，形成一个扫描视场；探测模块用于接收经物体反射回的光脉冲序列，以及根据所述反射回的光脉冲序列确定所述物体相对所述测距装置的距离和/或方位，以生成所述点云点。
发射电路110可以包括发射器用于出射光脉冲序列(例如激光脉冲序列)。背照式雪崩光电二极管阵列芯片120可以接收经过被探测物反射的光脉冲序列，也即通过其获得回波信号的脉冲波形，并对该光脉冲序列进行光电转换，以得到电信号。运算电路140可以 基于信号处理单元130的输出结果，以确定测距装置100与被探测物之间的距离，也即深度。
可选地，该测距装置100还可以包括控制模块(未示出)，该控制模块可以实现对其他电路或模块的控制，例如，可以控制各个电路或模块的工作时间和/或对各个电路或模块进行参数设置等，控制模块还可以进行一些运算处理等，还可以进行信道编码、信道解码等，控制模块可以包括控制器。
应理解，虽然图7示出的测距装置中包括一个发射电路110、背照式雪崩光电二极管阵列芯片120和信号处理单元130和一个运算电路140，除此之外其还可以包括例如采样电路等。
一些实现方式中，如图1所示，测距装置100还可以包括扫描模块(未示出)，用于将发射电路出射的至少一路光脉冲序列(例如激光脉冲序列)改变传播方向出射，以对视场进行扫描。示例性地，所述扫描模块在测距装置的视场内的扫描区域随着时间的累积而增加。
其中，可以将包括发射电路110、背照式雪崩光电二极管阵列芯片120和信号处理单元130和运算电路140的模块，或者，包括背照式雪崩光电二极管阵列芯片120和信号处理单元130、运算电路140和控制模块150的模块称为测距模块，该测距模块可以独立于其他模块，例如，扫描模块。
测距装置中可以采用同轴光路，也即测距装置出射的光束和经反射回来的光束在测距装置内共用至少部分光路。例如，发射电路出射的至少一路激光脉冲序列经扫描模块改变传播方向出射后，经探测物反射回来的激光脉冲序列经过扫描模块后入射至接收电路。或者，测距装置也可以采用异轴光路，也即测距装置出射的光束和经反射回来的光束在测距装置内分别沿不同的光路传输。图8示出了本申请的测距装置采用同轴光路的一种实施例的示意图。
测距装置200包括测距模块210，测距模块210包括发射器203(可以包括上述的发射电路)、准直元件204、接收器205和光路改变元件206，接收器205其可以包括上述的背照式雪崩光电二极管阵列芯片120和信号处理单元130和运算电路，测距模块210用于发射光束，且接收回光，将回光转换为电信号。其中，发射器203可以用于发射光脉冲序列。在一个实施例中，发射器203可以发射激光脉冲序列。可选的，发射器203发射出的激光束为波长在可见光范围之外的窄带宽光束。准直元件204设置于发射器的出射光路上，用于准直从发射器203发出的光束，将发射器203发出的光束准直为平行光出射至扫描模块。准直元件还用于会聚经探测物反射的回光的至少一部分。该准直元件204可以是准直透镜或者是其他能够准直光束的元件。
在图8所示实施例中，通过光路改变元件206来将测距装置内的发射光路和接收光路在准直元件204之前合并，使得发射光路和接收光路可以共用同一个准直元件，使得光路更加紧凑。在其他的一些实现方式中，也可以是发射器203和接收器205分别使用各自的准直元件，将光路改变元件206设置在准直元件之后的光路上。
在图8所示实施例中，由于发射器203出射的光束的光束孔径较小，测距装置所接收到的回光的光束孔径较大，所以光路改变元件可以采用小面积的反射镜来将发射光路和接收光路合并。在其他的一些实现方式中，光路改变元件也可以采用带通孔的反射镜，其中该通孔用于透射发射器203的出射光，反射镜用于将回光反射至接收器205。这样可以 减小采用小反射镜的情况中小反射镜的支架会对回光的遮挡。
在图8所示实施例中，光路改变元件偏离了准直元件204的光轴。在其他的一些实现方式中，光路改变元件也可以位于准直元件204的光轴上。
测距装置200还包括扫描模块202。扫描模块202放置于测距模块210的出射光路上，扫描模块202用于改变经准直元件204出射的准直光束219的传输方向并投射至外界环境，并将回光投射至准直元件204。回光经准直元件204汇聚到接收器205上。
在一个实施例中，扫描模块202可以包括至少一个光学元件，用于改变光束的传播路径，其中，该光学元件可以通过对光束进行反射、折射、衍射等等方式来改变光束传播路径，例如所述光学元件包括至少一个具有非平行的出射面和入射面的光折射元件。例如，扫描模块202包括透镜、反射镜、棱镜、振镜、光栅、液晶、光学相控阵(Optical Phased Array)或上述光学元件的任意组合。一个示例中，至少部分光学元件是运动的，例如通过驱动模块来驱动该至少部分光学元件进行运动，该运动的光学元件可以在不同时刻将光束反射、折射或衍射至不同的方向。在一些实施例中，扫描模块202的多个光学元件可以绕共同的轴209旋转或振动，每个旋转或振动的光学元件用于不断改变入射光束的传播方向。在一个实施例中，扫描模块202的多个光学元件可以以不同的转速旋转，或以不同的速度振动。在另一个实施例中，扫描模块202的至少部分光学元件可以以基本相同的转速旋转。在一些实施例中，扫描模块的多个光学元件也可以是绕不同的轴旋转。在一些实施例中，扫描模块的多个光学元件也可以是以相同的方向旋转，或以不同的方向旋转；或者沿相同的方向振动，或者沿不同的方向振动，在此不作限制。
在一个实施例中，扫描模块202包括第一光学元件214和与第一光学元件214连接的驱动器216，驱动器216用于驱动第一光学元件214绕转动轴209转动，使第一光学元件214改变准直光束219的方向。第一光学元件214将准直光束219投射至不同的方向。在一个实施例中，准直光束219经第一光学元件改变后的方向与转动轴209的夹角随着第一光学元件214的转动而变化。在一个实施例中，第一光学元件214包括相对的非平行的一对表面，准直光束219穿过该对表面。在一个实施例中，第一光学元件214包括厚度沿至少一个径向变化的棱镜。在一个实施例中，第一光学元件214包括楔角棱镜，对准直光束219进行折射。
在一个实施例中，扫描模块202还包括第二光学元件215，第二光学元件215绕转动轴209转动，第二光学元件215的转动速度与第一光学元件214的转动速度不同。第二光学元件215用于改变第一光学元件214投射的光束的方向。在一个实施例中，第二光学元件215与另一驱动器217连接，驱动器217驱动第二光学元件215转动。第一光学元件214和第二光学元件215可以由相同或不同的驱动器驱动，使第一光学元件214和第二光学元件215的转速和/或转向不同，从而将准直光束219投射至外界空间不同的方向，可以扫描较大的空间范围。在一个实施例中，控制器218控制驱动器216和217，分别驱动第一光学元件214和第二光学元件215。第一光学元件214和第二光学元件215的转速可以根据实际应用中预期扫描的区域和样式确定。驱动器216和217可以包括电机或其他驱动器。可选地，所述第一光学元件214和所述第二光学元件215的旋转方向(本文也称转向)相同，或者，所述第一光学元件和所述第二光学元件的旋转方向不同。
在一个实施例中，第二光学元件215包括相对的非平行的一对表面，光束穿过该对表面。在一个实施例中，第二光学元件215包括厚度沿至少一个径向变化的棱镜。在一个实 施例中，第二光学元件215包括楔角棱镜。
一个实施例中，扫描模块202还包括第三光学元件(图未示)和用于驱动第三光学元件运动的驱动器。可选地，该第三光学元件包括相对的非平行的一对表面，光束穿过该对表面。在一个实施例中，第三光学元件包括厚度沿至少一个径向变化的棱镜。在一个实施例中，第三光学元件包括楔角棱镜。第一、第二和第三光学元件中的至少两个光学元件以不同的转速和/或转向转动。
在一个实施例中，所述扫描模块包括在所述光脉冲序列的出射光路上依次排布的2个或3个所述光折射元件。可选地，所述扫描模块中的至少2个所述光折射元件在扫描过程中旋转，以改变所述光脉冲序列的方向。
所述扫描模块在至少部分不同时刻的扫描路径不同，扫描模块202中的各光学元件旋转可以将光投射至不同的方向，例如投射的光211的方向和方向213，如此对测距装置200周围的空间进行扫描。当扫描模块202投射出的光211打到探测物201时，一部分光被探测物201沿与投射的光211相反的方向反射至测距装置200。探测物201反射的回光212经过扫描模块202后入射至准直元件204。
接收器205与发射器203放置于准直元件204的同一侧，接收器205用于将穿过准直元件204的至少部分回光转换为电信号。
一个实施例中，各光学元件上镀有增透膜。可选的，增透膜的厚度与发射器203发射出的光束的波长相等或接近，能够增加透射光束的强度。
一个实施例中，测距装置中位于光束传播路径上的一个元件表面上镀有滤光层，或者在光束传播路径上设置有滤光器，用于至少透射发射器所出射的光束所在波段，反射其他波段，以减少环境光给接收器带来的噪音。
在一些实施例中，发射器203可以包括激光二极管，通过激光二极管发射纳秒级别的激光脉冲。进一步地，可以确定激光脉冲接收时间，例如，通过探测电信号脉冲的上升沿时间和/或下降沿时间确定激光脉冲接收时间。如此，测距装置200可以利用脉冲接收时间信息和脉冲发出时间信息计算TOF，从而确定探测物201到测距装置200的距离。测距装置200探测到的距离和方位可以用于遥感、避障、测绘、建模、导航等。
值得一提的是，在本申请的测距装置中可以不具有扫描模块，从而实现固态激光雷达。
本申请的测距装置采用了前文所述背照式雪崩光电二极管阵列芯片，因此具有背照式雪崩光电二极管阵列芯片的所有优点，在此不再赘述。
基于此，本申请还提供了一种可移动平台，其中前文所述的测距装置可应用于所述可移动平台，测距装置可安装在可移动平台的可移动平台本体。
在某些实施方式中，可移动平台包括无人飞行器、汽车、遥控车、机器人、相机中的至少一种。当测距装置应用于无人飞行器时，可移动平台本体为无人飞行器的机身。当测距装置应用于汽车时，可移动平台本体为汽车的车身。该汽车可以是自动驾驶汽车或者半自动驾驶汽车，在此不做限制。当测距装置应用于遥控车时，可移动平台本体为遥控车的车身。当测距装置应用于机器人时，可移动平台本体为机器人。当测距装置应用于相机时，可移动平台本体为相机的机身。
其中，所述可移动平台还可以进一步包括动力系统，用于驱动所述可移动平台本体移动。例如当所述可移动平台为车辆时，所述动力系统可以为车辆内部的发动机，在此不 再一一列举。
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本申请的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本申请的范围和精神。所有这些改变和修改意在被包括在所附权利要求所要求的本申请的范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本申请并帮助理解各个发明方面中的一个或多个，在对本申请的示例性实施例的描述中，本申请的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该本申请的方法解释成反映如下意图：即所要求保护的本申请要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如相应的权利要求书所反映的那样，其发明点在于可以用少于某个公开的单个实施例的所有特征的特征来解决相应的技术问题。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本申请的单独实施例。
本领域的技术人员可以理解，除了特征之间相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本申请的范围之内并且形成不同的实施例。例如，在权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
本申请的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本申请实施例的一些模块的一些或者全部功能。本申请还可以实现为用于执行这里所描述的方法的一部分或者全部的装置程序(例如，计算机程序和计算机程序产品)。这样的实现本申请的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
应该注意的是上述实施例对本申请进行说明而不是对本申请进行限制，并且本领域 技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。本申请可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上所述，仅为本申请的具体实施方式或对具体实施方式的说明，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。本申请的保护范围应以权利要求的保护范围为准。

Claims (32)

  1. 一种背照式雪崩光电二极管阵列芯片，其特征在于，包括：
    第一衬底，具有相对设置的第一表面和第二表面；
    外延层，具有相对设置的第三表面和第四表面，所述外延层的第三表面形成在所述第一衬底的第二表面上；
    雪崩光电二极管阵列，形成于所述外延层的第四表面；
    第二衬底，设置在所述雪崩光电二极管阵列背离所述外延层的一侧，所述第二衬底内形成有贯穿所述第二衬底并与所述雪崩光电二极管阵列电连接的多个电连接结构，所述多个电连接结构用于使所述雪崩光电二极管阵列和信号处理单元电连接。
  2. 如权利要求1所述的芯片，其特征在于，所述外延层的第四表面和所述第二衬底之间还设置有多个第一电极，其中，每个所述第一电极电连接至少一个所述雪崩光电二极管，每个所述电连接结构电连接至少一个所述第一电极。
  3. 如权利要求2所述的芯片，其特征在于，所述外延层的第四表面形成有第一钝化层，所述多个第一电极彼此间隔设置于所述第一钝化层内。
  4. 如权利要求2所述的芯片，其特征在于，所述电连接结构与所述第一电极电连接的端部位于所述第一钝化层内。
  5. 如权利要求2所述的芯片，其特征在于，所述电连接结构包括导电插塞和与所述导电插塞电连接的第二电极，其中，所述导电插塞贯穿所述第二衬底，所述第二电极设置于所述第二衬底背离所述外延层的一侧。
  6. 如权利要求5所述的芯片，其特征在于，每个所述电连接结构还包括凸块结构，所述凸块结构设置于所述第二电极上，所述凸块结构用于电连接所述第二电极和所述信号处理单元。
  7. 如权利要求6所述的芯片，其特征在于，所述凸块结构包括导电基底和导电凸块，所述导电基底设置于所述第二电极上并和所述第二电极电连接，所述导电凸块设置于所述导电基底上。
  8. 如权利要求7所述的芯片，其特征在于，所述导电凸块背离所述导电基底的一端还设置有焊料。
  9. 如权利要求6所述的芯片，其特征在于，所述第二衬底形成有所述第二电极的一侧设置有第二钝化层，所述第二电极设置于所述第二钝化层内。
  10. 如权利要求9所述的芯片，其特征在于，所述导电基底部分嵌入在所述第二钝化层中并与所述第二电极电连接。
  11. 如权利要求9所述的芯片，其特征在于，所述第二钝化层上还设置有缓冲层，所述第二钝化层和所述缓冲层内设置有开口，所述导电基底包括设置于所述开口的底部和侧壁上的第一导电部分和延伸至缓冲层上的第二导电部分，所述缓冲层用于缓冲所述第一导电部分和所述第二导电部分连接处的应力。
  12. 如权利要求1至11任一项所述的芯片，其特征在于，还包括第一隔离结构，所述第一隔离结构将所述第一衬底划分为至少两个区域。
  13. 如权利要求12所述的芯片，其特征在于，所述第一隔离结构至少贯穿所述第一衬底并延伸至所述外延层内。
  14. 如权利要求12或13所述的芯片，其特征在于，所述第一隔离结构包括第一隔离 槽和填充于所述第一隔离槽内的绝缘材料。
  15. 如权利要求1至14任一项所述的芯片，其特征在于，所述芯片还包括减反射层，所述减反射层覆盖所述第一衬底的第一表面。
  16. 如权利要求1至15任一项所述的芯片，其特征在于，相邻所述雪崩光电二极管之间还设置有第二隔离结构。
  17. 如权利要求16所述的芯片，其特征在于，所述第二隔离结构贯穿所述外延层。
  18. 如权利要求16所述的芯片，其特征在于，所述第二隔离结构包括第二隔离槽和填充于所述第二隔离槽内的绝缘材料。
  19. 如权利要求1至18任一项所述的芯片，其特征在于，还包括光捕获结构，所述光捕获结构形成在所述外延层的第三表面，所述光捕获结构用于增加光程。
  20. 如权利要求19所述的芯片，其特征在于，所述光捕获结构包括设置在所述外延层上的多个凸起结构。
  21. 如权利要求20所述的芯片，其特征在于，所述多个凸起结构包括倒金字塔型凸起、柱型凸起。
  22. 如权利要求1至21任一项所述的芯片，其特征在于，所述第一衬底的第一表面形成有减反射层，所述减反射层上形成有透镜结构。
  23. 如权利要求22所述的芯片，其特征在于，所述透镜结构包括由多个微透镜组成的微透镜阵列。
  24. 一种接收芯片，其特征在于，所述接收芯片包括：
    如权利要求1至23之一所述的背照式雪崩光电二极管阵列芯片，用于接收光发射电路出射的光脉冲序列经过被探测物反射的回光信号，并将所述回光信号转换为电信号；
    信号处理单元，和所述背照式雪崩光电二极管阵列芯片电连接，用于获取所述电信号并基于获取到的所述电信号输出时间信号。
  25. 如权利要求24所述的接收芯片，其特征在于，所述信号处理单元包括信号处理芯片，用于接收所述背照式雪崩光电二极管阵列芯片的电信号并进行处理，以输出时间信号。
  26. 如权利要求25所述的接收芯片，其特征在于，所述信号处理芯片与所述背照式雪崩光电二极管阵列芯片之间设置填充层，所述信号处理芯片与所述背照式雪崩光电二极管阵列芯片在所述填充层内进行电连接。
  27. 如权利要求26所述的接收芯片，其特征在于，所述信号处理芯片包括第一表面和与第一表面相对设置的第二表面，所述第一表面上设置有第四电极，所述第四电极与所述背照式雪崩光电二极管阵列芯片的电连接结构一一对应设置。
  28. 如权利要求27所述的接收芯片，其特征在于，所述第四电极上设置有用于和所述背照式雪崩光电二极管阵列芯片的电连接结构电连接的凸块结构，所述凸块结构深入所述填充层和所述背照式雪崩光电二极管阵列芯片的电连接结构实现电连接。
  29. 一种测距装置，其特征在于，所述测距装置包括：
    发射电路，用于出射光脉冲序列；
    如权利要求1至23之一所述的背照式雪崩光电二极管阵列芯片，用于接收所述光发射电路出射的光脉冲序列经过被探测物反射的回光信号，并将所述回光信号转换为电信号；
    信号处理单元，和所述背照式雪崩光电二极管阵列芯片电连接，用于获取所述电信号 并基于获取到的所述电信号输出时间信号；
    运算电路，用于根据所述时间信号计算所述被探测物与所述测距装置之间的距离。
  30. 一种测距装置，其特征在于，所述测距装置包括：
    发射电路，用于出射光脉冲序列；
    如权利要求24至28之一所述的接收芯片，用于接收所述发射电路出射的光脉冲序列经过被探测物反射的回光信号并输出时间信号；
    运算电路，用于根据所述时间信号计算所述被探测物与所述测距装置之间的距离。
  31. 一种可移动平台，其特征在于，所述可移动平台包括：
    可移动平台本体；
    至少一个如权利要求29或30所述的测距装置，设置于所述可移动平台本体。
  32. 如权利要求31所述的可移动平台，其特征在于，所述可移动平台包括：飞行器、车辆、船、手持设备或机器人。
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