WO2022100443A1 - 光学感测封装体 - Google Patents

光学感测封装体 Download PDF

Info

Publication number
WO2022100443A1
WO2022100443A1 PCT/CN2021/126997 CN2021126997W WO2022100443A1 WO 2022100443 A1 WO2022100443 A1 WO 2022100443A1 CN 2021126997 W CN2021126997 W CN 2021126997W WO 2022100443 A1 WO2022100443 A1 WO 2022100443A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
window
chip
optical sensing
layer
Prior art date
Application number
PCT/CN2021/126997
Other languages
English (en)
French (fr)
Inventor
周正三
范成至
Original Assignee
神盾股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 神盾股份有限公司 filed Critical 神盾股份有限公司
Publication of WO2022100443A1 publication Critical patent/WO2022100443A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Definitions

  • the present invention relates to an optical sensing package, and more particularly, to an optical sensing package that uses a chip packaging layer to surround the side of the photosensitive chip and defines a first window to allow the photosensitive chip to receive sensing light.
  • TOF Time Of Flight
  • 3D three-dimensional imaging or proximity detection
  • camera focusing Today's smart phones, tablet computers or other handheld devices are equipped with optical modules, such as Time Of Flight (TOF) sensors, to achieve functions such as gesture detection, three-dimensional (3D) imaging or proximity detection, or camera focusing.
  • TOF Time Of Flight
  • the TOF sensor emits near-infrared light into the scene, and uses the time-of-flight information of the light to measure the distance of objects in the scene.
  • the advantages of the TOF sensor are that the calculation amount of depth information is small, the anti-interference is strong, and the measurement range is long, so it has gradually been favored.
  • the core components of the TOF sensor include: light source, especially infrared vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser, VCSEL); light sensor, especially Single Photon Avalanche Diode (SPAD) ; and Time to Digital Converter (TDC).
  • SPAD is a photodetector avalanche diode with single-photon detection capability, which can generate current as long as there is a weak light signal.
  • the VCSEL in the TOF sensor transmits a pulse wave to the scene, the SPAD receives the pulse wave reflected from the object to be measured, the TDC records the time interval between the transmitted pulse wave and the received pulse wave, and uses the time of flight to calculate the depth information of the object to be measured .
  • FIG. 1 shows a schematic diagram of a conventional TOF optical sensing module 300 .
  • the TOF optical sensing module 300 includes a cap 310 , a light-emitting unit 320 , a sensor chip 330 and a substrate 350 .
  • the substrate 350 is, for example, a printed circuit board.
  • the light emitting unit 320 and the sensor chip 330 are disposed on the substrate 350 through an adhesive material.
  • the light emitting unit 320 and the sensor chip 330 are electrically connected to the substrate 350 .
  • At least one sensing pixel 341 and/or at least one reference pixel 331 are formed on the sensor chip 330 .
  • the cap 310 has an emission window 314 and a reception window 312 and is disposed above the substrate 350 to accommodate the light emitting unit 320 and the sensor chip 330 on the substrate 350 in a chamber 315 of the cap 310 .
  • the light emitting unit 320 emits the measuring light L1 to reach the object (not shown) through the emission window 314 , and the sensing pixel 341 receives the sensing light L3 reflected by the object through the receiving window 312 .
  • the reference light L2 is generated and travels toward the reference pixel 331 . By calculating the time difference between the sensing pixel 341 and the reference pixel 331 receiving the light, it can be converted into distance information.
  • the sensing pixels 341, the reference pixels 331 and the light emitting units 320 are disposed above the substrate 350 by a conventional pick and place method.
  • the sensing pixels 341 , the reference pixels 331 and the light emitting units 320 are electrically connected to the substrate 350 by bonding wires 351 , and then the electrical connection points are pulled out from one side of the substrate 350 to the circuit board.
  • the bonding wire 351 is fixed by using the encapsulant 352 .
  • the cap 310 is assembled on the substrate 350 .
  • the sensing pixels 341 , the reference pixels 331 and the light emitting units 320 are arranged in a pick-and-place manner, it is easy to generate placement errors (eg, several tens of micrometers) during production. Furthermore, when assembling the cap 310 , the alignment of the receiving window 312 with the corresponding sensing pixel 341 and/or the emitting window 314 and the corresponding light emitting unit 320 also has production problems in assembly accuracy. More importantly, due to the pick-and-place arrangement and the wire-bonding electrical connection, the geometric size and thickness of the conventional package are not easily reduced. For example, in the above-mentioned conventional package, the sensor chip 330 and the light-emitting unit 320 occupy the entire package.
  • the area ratio of electronic products is about 30% to 35%, that is to say, if we want to keep up with the requirements of the trend of thin and small electronic products, the related electronic components are required to have the characteristics of thin, thin and short packages and modules.
  • the gap between the sensing pixel 341 and the light-emitting unit 320 is narrowed in order to reduce the volume of the optical sensing module 300, the wire bonding process is bound to be severely challenged.
  • the separate manufacturing process of one element is another issue in terms of cost.
  • an object of the present invention is to provide an optical sensing package, which utilizes the chip-scale packaging technology and helps to reduce the volume of the optical sensing package.
  • the present invention provides an optical sensing package, which at least includes: a photosensitive chip; and a chip packaging layer, which surrounds multiple sides of the photosensitive chip, partially covers a front surface of the photosensitive chip, and has a first window, so that the front side of the photosensitive chip receives the sensing light through the first window.
  • the chip encapsulation layer may include: a molding compound layer surrounding the plurality of side surfaces of the photosensitive chip; a plurality of conductors penetrating the molding compound layer; On the photosensitive chip, there are a plurality of first wires and an insulating material covering the plurality of first wires, wherein a plurality of electrical contacts on the front surface of the photosensitive chip pass through the plurality of first wires and the plurality of first wires respectively.
  • the conductors are electrically connected to a plurality of contacts on a back surface of the chip packaging layer, wherein the window defining layer has a first window.
  • the above-mentioned optical sensing package may further include a light-emitting chip, which is disposed on one side of the photosensitive chip, and is surrounded and fixed by the molding compound layer.
  • the window defining layer is also located on the light emitting chip and has a plurality of second wires, the light emitting chip is electrically connected to the photosensitive chip, wherein the window defining layer also has a second window to expose a part of the light emitting chip to emit measurement light.
  • the photosensitive chip can be packaged by the molding compound of the packaging process and the light-receiving window of the photosensitive chip can be defined, the light-receiving window of the photosensitive chip can be defined by the window definition layer, and the light-receiving window of the photosensitive chip can be defined by using the window definition layer.
  • FIG. 1 shows a schematic diagram of a conventional optical sensing module.
  • FIGS. 2A and 2B are schematic structural diagrams of partial steps of a manufacturing method of an example of an optical sensing package according to a preferred embodiment of the present invention.
  • 2C and 2D are schematic structural diagrams of partial steps of a manufacturing method of another example of an optical sensing package according to a preferred embodiment of the present invention.
  • FIG. 3 shows a schematic diagram of an optical sensing package according to a preferred embodiment of the present invention.
  • 4 to 8 are schematic views showing several variations of the optical sensing package of FIG. 3 .
  • the present invention mainly adopts the wafer-level packaging technology to manufacture an optical sensing package, wherein the plane size of the package is close to the plane size of the photosensitive chip, which can improve the size and thickness shortcomings of the aforesaid known packaging technology, and in the manufacture It is also different from the arrangement and wire bonding of individual chips in the known technology.
  • the wafer-level batch manufacturing process can be used to reduce costs in mass production, and through integrated optical manufacturing, the arrangement of light-emitting chips and photosensitive chips can be greatly improved.
  • the precision (even to the micron level precision) completely solves the problems encountered by the aforesaid known technologies, and the detailed description is as follows.
  • FIG. 2A to 2B are schematic structural diagrams of partial steps of an example of a manufacturing method of an optical sensing package according to a preferred embodiment of the present invention.
  • a plurality of photosensitive chips 20 are firstly arranged on a handling wafer 10 at intervals, so that a gap G is formed between adjacent photosensitive chips 20 .
  • a peeling layer (not shown in the figure) can also be provided between the photosensitive chip 20 and the processing wafer 10.
  • this figure does not Not specified.
  • the gap G is filled with molding compound to form a molding compound layer 40 .
  • the molding compound layer 40 may be formed by thermocompression molding, but the present invention is of course not limited to this.
  • the molding compound can also overflow above the photosensitive chip 20, and then the molding compound on the photosensitive chip 20 can be left, or the molding compound on the surface of the photosensitive chip 20 can be removed by grinding, for example.
  • a window defining layer 60 is formed over the photosensitive chip 20 and the molding compound layer 40 , which has a first window 64 (also called a sensing window) that transmits light.
  • the molding compound of the molding compound layer 40 is an opaque material and is located in the gap G, and the window defining layer 60 partially covers the photosensitive chip 20, and can be filled with a light-transmitting material (such as an organic or inorganic dielectric material).
  • a transparent layer is formed in the first window 64 as a light transmission medium.
  • an optical lens 66 with a focusing function can also be formed on the material surface of the first window 64, such as a curved mirror, a diffraction optical element (Diffraction Optical Element, DOE) , filter elements or other optical elements, etc.
  • the window definition layer 60 may be made of another material (which may be an opaque molding compound, other opaque organic materials, other opaque inorganic materials, or other opaque inorganic materials).
  • the window defining layer 60 may be formed of the molding compound, that is, the molding compound layer 40 provides the first window 64.
  • a conductor 50 penetrating the molding compound layer 40 in the gap G may be further included, for example, through molding via (TMV).
  • Conductor 50 is located between handle wafer 10 and window definition layer 60 .
  • a first redistribution (not shown) may be disposed on the surface of the handle wafer 10
  • a second redistribution (not shown) may be disposed in the window definition layer 60 .
  • the purpose of rearranging the electrical connections is achieved by constructing a new wire connection, such as a fan-out wire connection, through the first rewiring, the second rewiring, and the conductor 50 .
  • the handle wafer 10 may be peeled off using a physical or chemical process (eg, using a laser to irradiate the above-mentioned peeling layer), as shown in FIG. 2B , and dicing along the dicing line CL to generate a plurality of optical sensing packages body.
  • a conductive path can be provided by the conductor 50 from the electrical connection point (not shown) near the front side of the photosensitive chip 20 to the electrical connection point (not shown) near the back side of the photosensitive chip 20, so it can be installed by surface mounting technology ( Surface Mount Technology, SMT) disposes the optical sensing package on a motherboard (not shown). Therefore, part or all of the components of the optical sensing package can be placed on the processing wafer 10 by using the wafer-level chip-scale packaging process, so as to reduce the packaging area or volume.
  • SMT Surface Mount Technology
  • FIG. 2C and 2D are schematic structural diagrams of partial steps of a manufacturing method of another example of an optical sensing package according to a preferred embodiment of the present invention.
  • the manufacturing method is similar to that of FIG. 2A or FIG. 2B , and the light-emitting chip 70 can be further arranged beside the photosensitive chip 20 and in the gap G by the precise alignment effect of the wafer-level manufacturing technology.
  • the molding compound layer 40 is filled in the gap G to fix the photosensitive chip 20 and the light-emitting chip 70 , so as to realize a light, thin, short, and small-sized integrated optical device.
  • the conductor 50 , the window definition layer 60 and the RDL are used to complete the electrical connection of the light-emitting chip 70 to solve the problems of difficult wiring and overflow of glue, and the molding compound layer 40 is used to configure a light-transmitting device in a manner similar to the first window 64 .
  • the second window 65 also called the emission window
  • the transparent layer filled in the second window 65 are used as a light transmission medium.
  • an optical lens 67 similar to the optical lens 66 can also be disposed above the second window 65 and the transparent layer, so as to control the emission angle and light-emitting characteristics of the light-emitting chip 70 .
  • the optical sensing package may further include a light-emitting driving module (not shown) for controlling the operation of the light-emitting chip 70 .
  • a light-emitting driving module (not shown) for controlling the operation of the light-emitting chip 70 .
  • the light-emitting driving module can be integrated with the photosensitive chip 20 , or can be separated from the photosensitive chip 20 and the light-emitting chip 70 and electrically connected together by wires, so there is no particular limitation here.
  • FIG. 3 shows a schematic diagram of an optical sensing package according to a preferred embodiment of the present invention.
  • 2A to FIG. 2D have the same reference numerals, and the components have the same functions, and are not repeated here.
  • the optical sensing package 100 at least includes a photosensitive chip 20 and a chip packaging layer 30 .
  • the function of the optical sensing package 100 is not particularly limited to the measurement of the time-of-flight of light, and may be a function of single light receiving, or a function of transmitting and receiving.
  • the chip encapsulation layer 30 surrounds a plurality of side surfaces 22 of the photosensitive chip 20 , partially covers a front surface 24 of the photosensitive chip 20 , and has a first window 64 , so that the front surface 24 of the photosensitive chip 20 is partially exposed to the chip packaging layer 30 and passes through the first window 64 Sensing light L3 from a target (not shown) is received.
  • the chip encapsulation layer 30 provides partial fixation to the outer surface of the photosensitive chip 20 , forms a first window 64 matching the photosensitive function of the photosensitive chip 20 , and provides certain protection to the photosensitive chip 20 .
  • a transparent layer may be formed in the first window 64 to serve as a light transmission medium, and at the same time, the surface of the photosensitive chip 20 may be protected.
  • the above-mentioned optical lens 66, DOE, filter element or other optical element, etc. can also be formed on the surface of the transparent layer of the first window 64, and similar arrangements are arranged above the second window 65 and the transparent layer.
  • Optical lens 67 of optical lens 66 Since the wafer-level packaging technology is used, no wire bonding process is required, and the area ratio A1/A2 of the area A1 of the photosensitive chip 20 and the area A2 of the entire optical sensing package 100 can be less than 1 and greater than or equal to 0.5, 0.6 , 0.7 or 0.8 and so on.
  • the chip encapsulation layer 30 includes a molding compound layer 40, a conductor 50 and a window definition layer 60 (with an RDL inside), and the molding compound layer 40 surrounds the side surface 22 of the photosensitive chip 20 to fix the photosensitive chip 20 and provide a connection with the photosensitive chip. 20 flush planes.
  • the molding compound layer 40 due to the fixation of the molding compound layer 40 , it is not necessary for the package substrate to support the photosensitive chip 20 upward, so that the overall thickness of the optical sensing package 100 can be reduced and thinning can be achieved.
  • Conductors 50 run through molding compound layer 40 to provide vertical electrical connections.
  • the window definition layer 60 is located on the molding compound layer 40 and the photosensitive chip 20, and has a plurality of first wires 61 and an insulating material 63 covering the plurality of first wires 61.
  • the first wires 61 provide horizontal and vertical directions. electrical connection.
  • the plurality of electrical contacts 23 on the front surface 24 of the photosensitive chip 20 are respectively electrically connected to the contacts 52 on the back of the optical sensing package 100 through the plurality of first wires 61 and the plurality of conductors 50 (represented schematically by arrows). ).
  • the contact includes a solder pad or a solder ball, which may be a Ball Grid Array (BGA) or a Land Grid Array (LGA).
  • an additional RDL may also be disposed on the backside of the optical sensing package 100 to redistribute the solder pads or solder balls of the package.
  • RDL may also be disposed on the backside of the optical sensing package 100 to redistribute the solder pads or solder balls of the package.
  • using RDL to cooperate with TMV does not require a wire bonding process, and the package area or volume can be reduced.
  • the metal material in the RDL can also isolate light, in addition to using the RDL insulating material to configure the first window 64, it also The first window 64 can be configured by using the metal material of the RDL to control the light-receiving range of the photosensitive chip 20 .
  • the side surfaces of the light-emitting chip 70 are also surrounded and fixed by the molding compound layer 40 .
  • the light-emitting chip 70 and the photosensitive chip 20 can be arranged on the processing wafer 10 (see FIG. 2C ) by the precise alignment effect of the wafer-level manufacturing technology, and then the molding compound layer 40 is used to fix the light-emitting The chip 70 and the photosensitive chip 20 .
  • a window defining layer 60 is formed on the photosensitive chip 20 , the light emitting chip 70 and the molding compound layer 40 .
  • the window definition layer 60 may have a plurality of second wires 62 to provide electrical connection paths for the light-emitting chip 70 to the outside world.
  • the insulating material 63 of the window definition layer 60 is disposed between the second wire 62 and the first wire 61 and covers the second wire 62 and the first wire 61 . Therefore, in this example, the window definition layer 60 also includes the redistribution layer and the first wire 61 and the second wire 62 disposed therein, so the light can be exposed to light through the conductor 50 , the first wire 61 and the second wire 62
  • the chip 20 and the light-emitting chip 70 are electrically connected to the outside world. In FIG. 3, the light-emitting chip 70 is electrically connected to the photosensitive chip 20 through the plurality of second wires 62.
  • the advantage of this configuration is that the size of the light-emitting chip 70 is usually much smaller than the size of the photosensitive chip 20, so let the light-emitting chip 70 It is more convenient to manage the electrical connection points on the photosensitive chip 20 uniformly.
  • the second window 65 of the window definition layer 60 exposes a part of the light-emitting chip 70 to emit the measurement light L1, and the light-emitting range of the light-emitting chip 70 can be controlled, so that the measurement light L1 hits the object to be measured within the light-emitting range to generate sensing light L3.
  • the photosensitive chip 20 has: a photosensitive structure, such as a photodiode, an avalanche diode (Avalanche Photo Diode, APD), etc.; a collimation structure (not shown) located above the photosensitive structure, wherein the collimation structure may include micro Optical elements such as lenses, filter layers, and light apertures; and sensing circuits for processing electrical signals from photosensitive structures.
  • the photosensitive chip 20 can be fabricated by, for example, a complementary metal-oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) process, for example, a front side illumination (FSI) or a back side illumination (BSI) process, or or other semiconductor processes, the present invention is not limited to this.
  • CMOS complementary metal-oxide semiconductor
  • FSI front side illumination
  • BSI back side illumination
  • the material of the photosensitive chip 20 may include semiconductor materials, such as silicon, germanium, gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium alloy, phosphorus arsenide Gallium alloy, arsenic aluminum indium alloy, arsenic aluminum gallium alloy, arsenic indium gallium alloy, phosphorus indium gallium alloy, phosphorus indium arsenic gallium alloy, or a combination of the above materials.
  • One or more electrical components may also be included on the pixel substrate.
  • Integrated circuits may be analog or digital circuits, which may be implemented as active elements, passive elements, conductive and dielectric layers, etc. formed within a chip and electrically connected according to the electrical design and function of the chip.
  • the light-emitting chip 70 may have a VCSEL or a Light-Emitting Diode (LED), such as an infrared LED.
  • FIG. 4 to 8 are schematic views showing several variations of the optical sensing package of FIG. 3 .
  • the optical sensing package 100 further includes a retaining wall 80 , which can be disposed on the window definition layer by wafer-level molding or assembly.
  • the retaining wall body 80 has a first middle window 84 and a second middle window 85 .
  • the first middle window 84 and the second middle window 85 communicate with the first window 64 and the second window 65 respectively, and serve as the light confinement structure of the sensing light L3 and the measuring light L1, further limiting the angle of light emission and light receiving, and also avoid The stray light enters the photosensitive chip 20 .
  • the material of the retaining wall body 80 may be the same as or different from the material of the molding compound layer 40 .
  • the optical sensing package 100 further includes a first optical element 91 located above the first middle window 84 .
  • the optical sensing package 100 further includes a second optical element 92 located above the second middle window 85
  • the first optical element 91 may be an optical lens component required by the photosensitive chip 20
  • the optical element 92 can be an optical lens assembly required by the light-emitting chip 70.
  • the above-mentioned optical lens assembly includes but is not limited to a light-transmitting element or an optical device with special optical functions, such as a filter element for a specific wavelength, etc. Condensing lens or DOE, etc., or a combination of multiple optical functions.
  • the first optical element 91 covering the first middle window 84 or the second optical element 92 covering the second middle window 85 can be disposed on the blocking wall body 80 by assembling, as a light processing structure for the sensing light L3 and the measuring light L1 .
  • the first optical element 91 or the second optical element 92 provides a cap-like structure, which protects the photosensitive chip 20 or the light-emitting chip 70 as a whole, and provides the required optical processing function, thereby realizing an assembled optical device .
  • the photosensitive chip 20 may also have a reference pixel.
  • the second optical element 92 reflects a part of the measurement light L1 to generate the reference light, the reference pixel receives the reference light, and the optical sensing package 100 and the target object are determined according to the time difference between the light-receiving time of the reference pixel and the light-receiving time of the sensing pixel the distance.
  • the optical sensing package 100 further includes a cap 90 , which is disposed on the window defining layer 60 by an assembly method, and is partially located in the first window 64 and the second window 60 .
  • On the window 65 there are light confinement structures and light guide structures for the sensing light L3 and the measuring light L1.
  • the cap 90 includes a body 93 as a light confinement structure, and a first optical element 91 and a second optical element 92 as a light guide structure and connected to the body 93 .
  • the first optical element 91 and the second optical element 92 seal the first upper window 94 and the second upper window 96 of the main body 93 .
  • an encapsulation protective cover can be formed as the body 93 by means of injection molding, the optical lens assembly is completed or assembled in the encapsulated protective cover to form the cap 90, and then the cap 90 is pasted along the arrow direction with adhesive Assembled to the window definition layer 60 .
  • the above-mentioned assembly process may be performed in a chip-level or wafer-level manner.
  • this example is similar to FIG. 3 except that the light emitting chip 70 is disposed on the window defining layer 60 , and the light emitting chip 70 is electrically connected to the photosensitive chip 20 through the RDL (not shown) in the window defining layer 60 .
  • the area where the light-emitting chip 70 and the photosensitive chip 20 are projected on the horizontal plane do not overlap, in another example, the area where the light-emitting chip 70 and the photosensitive chip 20 are projected on the horizontal plane may partially overlap. , thereby reducing the lateral size of the optical sensing package 100 .
  • FIG. 8 this example is similar to FIG. 7 , with the difference that a cap 90 similar to FIG. 6 is provided, and the cap 90 is disposed on the window definition layer 60 , which has the advantages of integration of FIGS. 7 and 6 .
  • the procedure of disposing the photosensitive chip and the light-emitting chip on the processing wafer is a pick-and-place process that is not a wafer-level process
  • the rest of the invention can adopt a wafer-level manufacturing method, especially above the photosensitive chip and the light-emitting chip.
  • Manufacturing corresponding optical elements such as the aforementioned curved mirror, DOE, filter element, or other optical components, etc., can also avoid the relative error problem during assembly, and can also solve the assembly and cost problems of individual optical elements.
  • the area or volume of the package can be effectively reduced, whether by manufacturing an integrated optical element or by using an independent optical element in an assembled manner.
  • the molding compound can be used to fix the photosensitive chip, and the rewiring layer can also be used to complete the electrical connection output and input of the photosensitive chip and the light-emitting chip. Since no wire bonding process is required, the wire overflow of the photosensitive chip can be solved. glue problem.
  • BGA or LGA packaging can be implemented to reduce the volume of the optical sensing package to meet the requirements of light, thin and short electronic devices. It is also possible to use the blocking wall body and the cap to cooperate with the optical element to provide a covered optical sensing package to realize the effect of light-receiving, light-receiving or time-of-flight sensing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

一种光学感测封装体，至少包含：一感光芯片；及一芯片封装层，包围感光芯片的多个侧面，局部覆盖感光芯片的一正面，并且具有一第一窗口，使感光芯片的正面通过第一窗口接收感测光。

Description

光学感测封装体 技术领域
本发明是有关于一种光学感测封装体，且特别是有关于一种利用芯片封装层包围感光芯片的侧面并定义出第一窗口来让感光芯片接收感测光的光学感测封装体。
背景技术
现今的智能电话、平板计算机或其他手持装置搭配有光学模块，例如飞行时间(Time Of Flight，TOF)感测器，来达成手势检测、三维(3D)成像或近接检测或者相机对焦等功能。操作时，TOF感测器向场景中发射近红外光，利用光的飞行时间信息，测量场景中物体的距离。TOF感测器的优点是深度信息计算量小，抗干扰性强，测量范围远，因此已经渐渐受到青睐。
TOF感测器的核心组件包含：光源，特别是红外线垂直共振腔面射雷射(Vertical Cavity Surface Emitting Laser,VCSEL)；光感测器，特别是单光子雪崩二极管(Single Photon Avalanche Diode,SPAD)；和时间至数字转换器(Time to Digital Converter,TDC)。SPAD是一种具有单光子探测能力的光电探测雪崩二极管，只要有微弱的光信号就能产生电流。TOF感测器中的VCSEL向场景发射脉冲波，SPAD接收从待测物体反射回来的脉冲波，TDC记录发射脉冲波和接收脉冲波之间的时间间隔，利用飞行时间计算待测物体的深度信息。
图1显示一种传统的TOF光学感测模块300的示意图。如图1所示，TOF光学感测模块300包含一帽盖(cap)310、一发光单元320、一感测器芯片330及一基板350。基板350譬如是印刷电路板。基板350上通过粘胶材料设置发光单元320及感测器芯片330。发光单元320及感测器芯片330电连接至基板350。感测器芯片330上形成有至少一感测像素341及/或至少一参考像素331。帽盖310具有一发射窗314及一接收窗312，并且设置于基板350的上方，以将基板350上的发光单元320及感测器芯片330容置于帽盖310的一腔室315中。发光单元320发出测量光L1通过发射窗314到达物体(未显示)，感测像素341通过接收窗312接收物体反射的感测光L3。测量光L1被帽盖310反射后产生参考光L2朝参考像素331行进。借由计算感测像素341与参考像素331收到光线的时间差，可以换算成距离信息。
在上述的光学感测模块300中，感测像素341、参考像素331及发光单元320是通过传统的取放(pick and place)方式设置于基板350上方。接着，通过打线351而将感测像素341、参考像素331及发光单元320电连接至基板350，再从基板350的一侧拉出电连接点到电路板。然后，使用封装胶352来固定打线351。接着，将帽盖310组装至基板350上。因为用取放方式设置感测像素341、参考像素331及发光单元320，故很容易在生产时产生放置时的误差(例如几十微米)。再者，在组装帽盖310时，接收窗312与对应的感测像素341及/或发射窗314与对应的发光单元320的对准也都有组装精准度上的生产问题。更重要的是，由于采用取放的布置方式以及打线的电连接方式，使得传统封装的几何尺寸跟厚度不容易缩小，例如上述传统封装中，感测器芯片330及发光单元320占整体封装的面积比约为30％至35％，也就是说如果要跟上电子产品轻薄短小趋势的要求的话，则要求相关电子零组件也要有封装及模块的轻薄短小特征。另一方面，当为了缩小光学感测模块300的体积而缩小感测像素341与发光单元320之间的间隙时，打线连接的工艺势必受到严格的挑战，且这种传统的封装，都是一个一个元件独立制造处理，在成本上也是另一问题。
发明内容
因此，本发明的一个目的是提供一种光学感测封装体，利用芯片级封装的技术，并有助于缩小光学感测封装体的体积。
为达上述目的，本发明提供一种光学感测封装体，至少包含：一感光芯片；及一芯片封装层，包围感光芯片的多个侧面，局部覆盖感光芯片的一正面，并且具有一第一窗口，使感光芯片的正面通过第一窗口接收感测光。
于上述光学感测封装体中，芯片封装层可以包含：一模塑料层，包围感光芯片的所述多个侧面；多个导体，贯穿模塑料层；以及一窗口定义层，位于模塑料层与感光芯片上，并具有多条第一导线及包覆所述多条第一导线的一绝缘材料，其中感光芯片的正面上的多个电气接点分别通过所述多条第一导线及所述多个导体而电连接至芯片封装层的一背面的多个接点，其中窗口定义层具有第一窗口。上述光学感测封装体可以还包含一发光芯片，设置于感光芯片的一侧，并被模塑料层包围固定。窗口定义层还位于发光芯片上，并且还具有多条第二导线，发光芯片电连接至感光芯片，其中窗口定义层还具有一第二窗口以露出发光芯片的一部分来发射测量光。
借由上述的实施例，可以利用封装工艺的模塑料来封装感光芯片并定义出感光芯片的收光窗口，利用窗口定义层来定义出感光芯片的收光窗口，利用导体配合重新布线的方式来完成感光芯片与发光芯片的电连接输出及输入，实现电连接点的阵列的封装，缩小光学感测封装体的体积，还可利用重新布线层重新定义控制的发光范围及收光范围。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下。
附图说明
图1显示一种传统的光学感测模块的示意图。
图2A与图2B显示依据本发明较佳实施例的光学感测封装体的一个例子的制造方法的局部步骤的结构示意图。
图2C与图2D显示依据本发明较佳实施例的光学感测封装体的另一例子的制造方法的局部步骤的结构示意图。
图3显示依据本发明较佳实施例的光学感测封装体的示意图。
图4至图8显示图3的光学感测封装体的数个变化例的示意图。
附图标号：
A1:面积
A2:面积
CL:切割线
G:间隙
L1:测量光
L2:参考光
L3:感测光
10:处理晶圆
20:感光芯片
22:侧面
23:电气接点
24:正面
30:芯片封装层
40:模塑料层
50:导体
52:接点
60:窗口定义层
61:第一导线
62:第二导线
63:绝缘材料
64:第一窗口
65:第二窗口
66:光学镜头
67:光学镜头
70:发光芯片
80:挡墙体
84:第一中窗口
85:第二中窗口
90:帽盖
91:第一光学元件
92:第二光学元件
93:本体
94:第一上窗口
96:第二上窗口
100:光学感测封装体
300:TOF光学感测模块
310:帽盖
312:接收窗
314:发射窗
315:腔室
320:发光单元
330:感测器芯片
331:参考像素
341:感测像素
350:基板
351:打线
352:封装胶
具体实施方式
本发明主要是采用晶圆级封装技术来制造一种光学感测封装体，其中封装体的平面尺寸接近于感光芯片的平面尺寸，可以改进前述公知封装技术的尺寸及厚度缺点，而且在制造上也不同于公知技术的个别芯片的布置及打线连接，而是可以利用晶圆级的批量制造工艺，来大量生产降低成本，并且通过整合性的光学制造，大幅改进发光芯片与感光芯片排列的精准度(甚至到微米级精度)，完全解决前述公知技术所碰到的问题，详细说明如下。
图2A至图2B显示依据本发明较佳实施例的光学感测封装体的制造方法的一个例子的局部步骤的结构示意图。如图2A所示，制造时，首先将多个感光芯片20间隔排列设置于一处理晶圆(handling wafer)10上，使得相邻的感光芯片20之间形成有间隙G。当然，为了让处理晶圆10可以被剥离再利用，也可以设置一剥离层(图中未示)于感光芯片20与处理晶圆10之间，由于本领域技术人员应了解，在此图并未明示。接着，在间隙G中填入模塑料以形成一模塑料(molding compound)层40。于一例中，模塑料层40可以利用热压成型来形成，但本发明当然不限定于此。于另一例中，也可以让模塑料满溢于感光芯片20上方，然后可以选择留下感光芯片20上方的模塑料，或者利用例如研磨方式将感光芯片20表面的模塑料去除。然后，在感光芯片20及模塑料层40上方形成一窗口定义层60，其具有透光的第一窗口64(亦称感测窗口)。于本例中，模塑料层40的模塑料为不透光材料，位于间隙G中，而窗口定义层60局部覆盖感光芯片20，且可以将透光材料(例如有机或无机介电材料)填入第一窗口64中形成透明层当作光传递介质，当然也可以在第一窗口64的材料表面形成具有聚焦功能的光学镜头66，例如曲面镜、绕射光学元件(Diffraction Optical Element，DOE)、滤光元件或其他光学元件等等。在模塑料仅充填于间隙G中的情况下，窗口定义层60可以是由另一材料(可以是不透光的模塑料、其他不透光有机材料、其他不透光无机材料、或其他不透光有机与无机材料两者的组合)形成，或是由感光芯片20上方的重新布线层(Redistribution Layer,RDL)所形成，其中RDL包含形成导线的金属材料及包覆导线的绝缘材料。在模塑料从间隙G满溢于感光芯片20上方的情况下，窗口定义层60可以是由所述模塑料所形成，也就是模塑料层 40提供第一窗口64。在又另一例中，可以更进一步包含贯穿间隙G中的模塑料层40的导体50，例如，导电填孔(Through Molding Via,TMV)。导体50位于处理晶圆10与窗口定义层60之间。处理晶圆10的表面上可设置有第一重新布线(图中未示)，且窗口定义层60上中可设置有第二重新布线(图中未示)。借由第一重新布线、第二重新布线及导体50，来建构一种新的导线连接，例如扇出(fan-out)导线连接，来达成重新布置电连接的目的。
封装完成后，可以采用物理或化学工艺(例如采用雷射照射上述剥离层)来剥离处理晶圆10，如图2B所示，并且沿着切割线CL进行切割，以产生多个光学感测封装体。借由导体50可以提供一条导电路径，从靠近感光芯片20的正面的电连接点(未显示)导引到靠近感光芯片20的背面的电连接点(未显示)，所以可以通过表面安装技术(Surface Mount Technology,SMT)将光学感测封装体设置于一主机板(未显示)上。因此，可以利用晶圆级芯片尺寸封装的工艺将光学感测封装体的部分或全部元件置放于处理晶圆10之上，以达到缩小封装面积或体积的目的。
图2C与图2D显示依据本发明较佳实施例的光学感测封装体的另一例子的制造方法的局部步骤的结构示意图。如图2C与图2D所示，其制造方式与图2A或图2B相似，可以借由晶圆级制造技术的精准对位效果，更进一步将发光芯片70配置在感光芯片20旁及间隙G中，而模塑料层40填入间隙G中以固定住感光芯片20及发光芯片70，实现轻薄短小尺寸的整合式光学器件。另外，利用导体50、窗口定义层60及RDL，来完成发光芯片70的电连接，解决打线不易及溢胶的问题，并且利用模塑料层40以类似第一窗口64的方式配置一个透光的第二窗口65(亦称发射窗口)及填入第二窗口65的透明层当作光传递介质。当然，亦可在第二窗口65及透明层的上方设置类似光学镜头66的光学镜头67，以控制发光芯片70的发射角度及发光特性。于另一实施例中，光学感测封装体还可以包含一发光驱动模块(未显示)，用于控制发光芯片70的操作。可以理解的，发光驱动模块可以与感光芯片20整合成一体，也可以与感光芯片20及发光芯片70分开，借由导线而电连接在一起，故于此不作特别限制。
图3显示依据本发明较佳实施例的光学感测封装体的示意图。与图2A至图2D具有相同元件符号知元件具有相同功能，在此不再赘述。如图3所示，光学感测封装体100至少包括感光芯片20及一芯片封装层30。光学感测封装体100的功能并不特别受限于光的飞行时间的测量，也可以是单一光接收的功能，也可以是发射加上接收的功能。芯片封装层30包围感光芯片20的多个侧面22，局部覆盖感光芯片20的一正面24，并且 具有第一窗口64，使感光芯片20的正面24局部露出芯片封装层30并通过第一窗口64接收来自目标物(未显示)的感测光L3。芯片封装层30对感光芯片20的外表面提供局部固定，而形成配合感光芯片20的感光功能的第一窗口64，并且对感光芯片20提供一定的保护。可选地，在第一窗口64中可形成透明层当作光传递介质，同时可保护感光芯片20的表面。在另一实施例中当然也可以在第一窗口64的透明层的表面形成上述光学镜头66、DOE、滤光元件或其他光学元件等等，以及在第二窗口65及透明层的上方设置类似光学镜头66的光学镜头67。由于使用晶圆级封装技术，故不需要打线工艺，可以让感光芯片20的面积A1与整个光学感测封装体100的面积A2的一面积比A1/A2小于1且大于或等于0.5，0.6，0.7或0.8等等。
芯片封装层30包含模塑料层40、导体50以及窗口定义层60(其内部具有RDL)，模塑料层40包围感光芯片20的侧面22，以将感光芯片20固定住，并提供一个与感光芯片20齐平的平面。于本例中，由于模塑料层40的固定，故可以不需要封装基板向上支撑感光芯片20，因此可降低光学感测封装体100整体厚度，实现薄型化。导体50贯穿模塑料层40，以提供垂直方向的电连接。窗口定义层60位于模塑料层40与感光芯片20上，并具有多条第一导线61及包覆所述多条第一导线61的绝缘材料63，第一导线61提供水平方向及垂直方向的电连接。感光芯片20的正面24上的多个电气接点23分别通过所述多条第一导线61及所述多个导体50而电连接至光学感测封装体100的背面的接点52(以箭头示意表示)。接点的实施方式有很多，于此不特别限制。于一例中，接点包含一焊垫或一焊球，可以采用球栅网格阵列封装(Ball Grid Array,BGA)或平面网格阵列封装(Land Grid Array,LGA)。于另一例中，也可以在光学感测封装体100的背面配置有额外的RDL(图中未示)来将封装的焊垫或焊球做重新分布。借此，利用RDL配合TMV，不需要打线工艺，可以缩小封装面积或体积，同时，因为RDL中的金属材料也能隔绝光线，所以除了利用RDL的绝缘材料来配置第一窗口64以外，也可以利用RDL的金属材料来配置第一窗口64来控制感光芯片20的收光范围。
发光芯片70的侧面亦被模塑料层40包围固定。实际制作时，可以借由晶圆级制造技术的精准对位效果，将发光芯片70与感光芯片20设置于处理晶圆10(可参见图2C)上，然后再用模塑料层40来固定发光芯片70与感光芯片20。接着，在感光芯片20、发光芯片70与模塑料层40上形成窗口定义层60。窗口定义层60可具有多条第二导线62，提供给发光芯片70对外界的电连接路径。窗口定义层60的绝缘材料63设置于第二导线62与第一导线61之间并且包覆第二导线62与第一导线61。因此，于本例中，窗 口定义层60也包含了重新布线层及设置于其内的第一导线61及第二导线62，故可以通过导体50、第一导线61及第二导线62将感光芯片20和发光芯片70与外界做电性连接。在图3中，让发光芯片70通过所述多条第二导线62而电连接至感光芯片20，这样配置的好处在于发光芯片70的尺寸通常远小于感光芯片20的尺寸，所以让发光芯片70的电连接点统一在感光芯片20上作管理是比较方便的作法。窗口定义层60的第二窗口65露出发光芯片70的一部分来发射测量光L1，可控制发光芯片70的发光范围，使得测量光L1打到发光范围内的待测的目标物后产生感测光L3。
于一实施例中，感光芯片20具有：光敏结构，例如光电二极管、雪崩二极管(Avalanche Photo Diode,APD)等等；位于光敏结构上方的准直结构(未显示)，其中准直结构可以包含微透镜、滤光层、光孔等光学元件；以及感测电路，用于处理来自于光敏结构的电信号。感光芯片20的制造可以是使用例如互补式金属氧化物半导体(Complementary Metal-Oxide Semiconductor,CMOS)工艺，例如采用前面照度(Front Side Illumination,FSI)或背面照度(Back Side Illumination,BSI)工艺，抑或者其他的半导体工艺，本发明并不以此为限。感光芯片20的材料可以包含半导体材料，半导体材料例如硅、锗、氮化镓、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、硅锗合金、磷砷镓合金、砷铝铟合金、砷铝镓合金、砷铟镓合金、磷铟镓合金、磷砷铟镓合金或上述材料的组合。像素基板上可以还包括一个或多个电气元件(如集成电路)。集成电路可以是类比或数字电路，类比或数字电路可以被实现为在芯片内形成并且根据芯片的电气设计与功能而达成电连接的主动元件、被动元件、导电层和介电层等等。此外，发光芯片70可具有VCSEL或发光二极管(Light-Emitting Diode,LED)，例如红外线LED。
图4至图8显示图3的光学感测封装体的数个变化例的示意图。如图4所示，本例类似于图3，差异点在于光学感测封装体100还包含一挡墙体80，可以利用晶圆级成型(Wafer-Level Molding)或组装方式设置于窗口定义层60上，挡墙体80具有一第一中窗口84及一第二中窗口85。第一中窗口84与第二中窗口85分别与第一窗口64和第二窗口65相通，并作为感测光L3及测量光L1的光限制结构，进一步限制发光与收光的角度，也避免杂散光进入感光芯片20。挡墙体80的材料可以与模塑料层40的材料相同或不同。
如图5所示，本例类似于图4，差异点在于光学感测封装体100还包含位于第一中窗口84上方的一第一光学元件91。于另一实施例中，光学感测封装体100还包含位于第二中窗口85上方的一第二光学元件92，第一光学元件91可以是感光芯片20所需的 光学镜头组件，而第二光学元件92可以是发光芯片70所需的光学镜头组件，上述光学镜头组件包含但不限于透光元件或者具有特殊光学功能的光学器件，例如特定波长的滤光元件等等，或者具有例如散光或聚光功能的镜头或DOE等等，抑或多个光学功能的结合。覆盖第一中窗口84的第一光学元件91或覆盖第二中窗口85的第二光学元件92可利用组装方式设置于挡墙体80上，作为感测光L3及测量光L1的光处理结构。借此，第一光学元件91或第二光学元件92提供类似帽盖的结构，将感光芯片20或发光芯片70整体保护起来，并提供所需的光学处理的功能，实现一种组装式光学器件。
可以理解的，感光芯片20还可具有一参考像素。第二光学元件92反射测量光L1的一部分而产生参考光，参考像素接收参考光，依据参考像素的收光时间与感测像素的收光时间的时间差来判断光学感测封装体100与目标物的距离。
如图6所示，本例类似于图3，差异点在于光学感测封装体100还包含一帽盖90，利用组装方式设置于窗口定义层60上，并局部位于第一窗口64及第二窗口65上，作为感测光L3及测量光L1的光限制结构及光导引结构。帽盖90包含作为光限制结构的一本体93，以及作为光导引结构并且连接至本体93的第一光学元件91与第二光学元件92。第一光学元件91与第二光学元件92封住本体93的第一上窗口94及第二上窗口96。借此，可以利用射出成型的方式形成一封装保护盖作为本体93，先将光学镜头组件完成或组装于封装保护盖中而形成帽盖90，再沿着箭头方向利用粘胶将帽盖90粘贴组装到窗口定义层60上。上述的组装工艺可以是芯片级或晶圆级方式进行。
如图7所示，本例类似于图3，差异点在于发光芯片70设置于窗口定义层60上，发光芯片70通过窗口定义层60中RDL(未显示)电连接至感光芯片20。虽然图7所示的结构中，发光芯片70与感光芯片20投影在水平面的区域不重叠，但是于另一例子中，也可将让发光芯片70与感光芯片20投影在水平面的区域有局部重叠，借此可缩小光学感测封装体100的横向尺寸。
如图8所示，本例类似于图7，差异点在于提供类似图6的帽盖90，将帽盖90设置于窗口定义层60上，具有图7与图6的整合优点。
本发明除了将感光芯片及发光芯片设置于处理晶圆上的程序为非晶圆级工艺的取放工艺以外，其余可采用晶圆级的制造方式，特别在感光芯片与发光芯片上方，可以同时制造对应的光学元件，如前述的曲面镜、DOE、滤光元件、或其他光学组件等等，还可以免除组装时相对误差问题，也可以解决个别光学元件的组装及成本问题。
借由上述的实施例的光学感测封装体，不管是借由集成化的光学元件的制造，或者借由组装方式的独立光学元件，都可以有效缩小封装体的面积或体积。此外，可以利用模塑料达成感光芯片的固定，再者也可利用重新布线层来完成感光芯片与发光芯片的电连接输出及输入，因不需打线工艺，故可解决感光芯片的打线溢胶的问题。此外，可以实现BGA或LGA的封装，缩小光学感测封装体的体积，以满足轻薄短小的电子装置的需求。亦可利用挡墙体与帽盖配合光学元件来提供一个包覆式的光学感测封装体，实现收光、收发光或飞行时间感测的效果。
在较佳实施例的详细说明中所提出的具体实施例仅用以方便说明本发明的技术内容，而非将本发明狭义地限制于上述实施例，在不超出本发明的精神及申请专利范围的情况下，所做的种种变化实施，皆属于本发明的范围。

Claims (21)

  1. 一种光学感测封装体(100)，其特征在于，至少包含：
    一感光芯片(20)；及
    一芯片封装层(30)，包围所述感光芯片(20)的多个侧面(22)，局部覆盖所述感光芯片(20)的一正面(24)，并且具有一第一窗口(64)，使所述感光芯片(20)的所述正面(24)通过所述第一窗口(64)接收感测光(L3)。
  2. 根据权利要求1所述的光学感测封装体(100)，其特征在于，所述感光芯片(20)与所述光学感测封装体(100)的一面积比小于1，并大于或等于0.5。
  3. 根据权利要求1所述的光学感测封装体(100)，其特征在于，所述芯片封装层(30)包含：
    一模塑料层(40)，包围所述感光芯片(20)的所述多个侧面(22)。
  4. 根据权利要求1所述的光学感测封装体(100)，其特征在于，还包含一透明层，设置于所述第一窗口(64)中，其中所述透明层可透光。
  5. 根据权利要求4所述的光学感测封装体(100)，其特征在于，还包含一光学镜头(66)，设置于所述透明层上。
  6. 根据权利要求1所述的光学感测封装体(100)，其特征在于，还包含一挡墙体(80)，设置于所述芯片封装层(30)上，并具有一第一中窗口(84)，作为所述感测光(L3)的光限制结构。
  7. 根据权利要求6所述的光学感测封装体(100)，其特征在于，还包含一第一光学元件(91)，设置于所述挡墙体(80)上，并分别覆盖所述第一中窗口(84)，作为所述感测光(L3)的光处理结构。
  8. 根据权利要求1所述的光学感测封装体(100)，其特征在于，还包含一帽盖(90)，设置于所述芯片封装层(30)上，并局部位于所述第一窗口(64)上方，作为所述感测光(L3)的光限制结构及光导引结构。
  9. 根据权利要求1所述的光学感测封装体(100)，其特征在于，还包含一发光芯片(70)，设置于所述感光芯片(20)的一侧，并被所述芯片封装层(30)包围固定。
  10. 根据权利要求1所述的光学感测封装体(100)，其特征在于，所述芯片封装层(30)包含：
    一模塑料层(40)，包围所述感光芯片(20)的所述多个侧面(22)；
    多个导体(50)，贯穿所述模塑料层(40)；以及
    一窗口定义层(60)，位于所述模塑料层(40)与所述感光芯片(20)上，并具有多条第一导线(61)及包覆所述多条第一导线(61)的一绝缘材料(63)。
  11. 根据权利要求10所述的光学感测封装体(100)，其特征在于，所述感光芯片(20)的所述正面(24)上的多个电气接点(23)分别通过所述多条第一导线(61)及所述多个导体(50)而电连接至所述芯片封装层(30)的一背面的多个接点(52)，其中所述窗口定义层(60)具有所述第一窗口(64)。
  12. 根据权利要求10所述的光学感测封装体(100)，其特征在于，还包含：
    一发光芯片(70)，设置于所述感光芯片(20)的一侧，并被所述模塑料层(40)包围固定，其中所述窗口定义层(60)还位于所述发光芯片(70)上，并且还具有多条第二导线(62)，所述发光芯片(70)电连接至所述感光芯片(20)，其中所述窗口定义层(60)还具有一第二窗口(65)以露出所述发光芯片(70)的一部分来发射测量光(L1)。
  13. 根据权利要求12所述的光学感测封装体(100)，其特征在于，还包含一透明层，设置于所述第一窗口(64)与所述第二窗口(65)中，其中所述透明层可透光，所述模塑料层(40)不可透光。
  14. 根据权利要求12所述的光学感测封装体(100)，其特征在于，还包含一挡墙体(80)，设置于所述窗口定义层(60)上，并具有一第一中窗口(84)及一第二中窗口(85)，作为所述感测光(L3)及所述测量光(L1)的光限制结构。
  15. 根据权利要求14所述的光学感测封装体(100)，其特征在于，还包含一第一光学元件(91)与一第二光学元件(92)，设置于所述挡墙体(80)上，并分别覆盖所述第一中窗口(84)及所述第二中窗口(85)，作为所述感测光(L3)及所述测量光(L1)的光处理结构。
  16. 根据权利要求14所述的光学感测封装体(100)，其特征在于，还包含一帽盖(90)，设置于所述窗口定义层(60)上，并局部位于所述第一窗口(64)及所述第二窗口(65)上方，作为所述感测光(L3)及所述测量光(L1)的光限制结构及光导引结构。
  17. 根据权利要求1所述的光学感测封装体(100)，其特征在于，还包含：
    一发光芯片(70)，用于发射测量光(L1)，并且设置于所述芯片封装层(30)上。
  18. 根据权利要求17所述的光学感测封装体(100)，其特征在于，还包含一帽盖(90)，设置于所述芯片封装层(30)上，并覆盖所述第一窗口(64)，作为所述感测光(L3)及所述测量光(L1)的光限制结构及光导引结构。
  19. 根据权利要求18所述的光学感测封装体(100)，其特征在于，所述帽盖(90)包含：
    一本体(93)，作为所述光限制结构；以及
    一第一光学元件(91)，连接至所述本体(93)，并作为所述光导引结构。
  20. 根据权利要求19所述的光学感测封装体(100)，其特征在于，所述帽盖(90)还包含一第二光学元件(92)，连接至所述本体(93)，并作为所述光导引结构。
  21. 根据权利要求1所述的光学感测封装体(100)，其特征在于，所述感光芯片(20)与所述光学感测封装体(100)的一面积比小于1，并大于或等于0.8。
PCT/CN2021/126997 2020-11-10 2021-10-28 光学感测封装体 WO2022100443A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063112061P 2020-11-10 2020-11-10
US63/112,061 2020-11-10

Publications (1)

Publication Number Publication Date
WO2022100443A1 true WO2022100443A1 (zh) 2022-05-19

Family

ID=79743188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/126997 WO2022100443A1 (zh) 2020-11-10 2021-10-28 光学感测封装体

Country Status (3)

Country Link
CN (2) CN113990856A (zh)
TW (2) TW202220224A (zh)
WO (1) WO2022100443A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI822302B (zh) * 2022-09-05 2023-11-11 財團法人工業技術研究院 光學雷達及其光訊號拾取方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101945214A (zh) * 2009-07-01 2011-01-12 三星泰科威株式会社 摄像模块
CN205752171U (zh) * 2016-05-17 2016-11-30 歌尔股份有限公司 一种光学传感器封装结构
CN109698208A (zh) * 2017-10-20 2019-04-30 新加坡有限公司 图像传感器的封装方法、图像传感器封装结构和镜头模组
CN109872986A (zh) * 2017-12-04 2019-06-11 新加坡有限公司 光学传感器的封装结构及光学传感器的封装方法
US20200020815A1 (en) * 2017-01-03 2020-01-16 Stmicroelectronics (Grenoble 2) Sas Method for manufacturing a cover for an electronic package and electronic package comprising a cover

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101945214A (zh) * 2009-07-01 2011-01-12 三星泰科威株式会社 摄像模块
CN205752171U (zh) * 2016-05-17 2016-11-30 歌尔股份有限公司 一种光学传感器封装结构
US20200020815A1 (en) * 2017-01-03 2020-01-16 Stmicroelectronics (Grenoble 2) Sas Method for manufacturing a cover for an electronic package and electronic package comprising a cover
CN109698208A (zh) * 2017-10-20 2019-04-30 新加坡有限公司 图像传感器的封装方法、图像传感器封装结构和镜头模组
CN109872986A (zh) * 2017-12-04 2019-06-11 新加坡有限公司 光学传感器的封装结构及光学传感器的封装方法

Also Published As

Publication number Publication date
CN215955279U (zh) 2022-03-04
CN113990856A (zh) 2022-01-28
TW202220224A (zh) 2022-05-16
TWM625090U (zh) 2022-04-01

Similar Documents

Publication Publication Date Title
US10749067B2 (en) Optical sensor package including a cavity formed in an image sensor die
US9684074B2 (en) Optical sensor arrangement and method of producing an optical sensor arrangement
US9443835B2 (en) Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by the methods
US9496247B2 (en) Integrated camera module and method of making same
CN111052406B (zh) 制造多个飞行时间传感器器件的方法
CN106057964B (zh) 具有串音屏障的晶圆级光电子器件封装及其制造方法
US9543282B2 (en) Optical sensor package
CN210123731U (zh) 电子模块
WO2022100443A1 (zh) 光学感测封装体
US9018645B2 (en) Optoelectronics assembly and method of making optoelectronics assembly
CN114429949A (zh) 小型化光传感器封装及其制作方法
WO2022061820A1 (zh) 一种接收芯片及其制备方法、测距装置、可移动平台
CN215953857U (zh) Tof光学感测模块
CN216285703U (zh) 堆叠式光学感测封装体
KR20230122573A (ko) 센서 및 이를 이용한 ToF 카메라
US20230132008A1 (en) Optical Sensor, Optical Distance Sensing Modlule and Fabricating Method Thereof
CN115685146A (zh) 直接飞行时间感测模组
KR20240048974A (ko) 반도체 패키징을 이용한 광소자 패키지
CN117936636A (zh) 光感应芯片及其制备方法、激光雷达及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21890970

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21890970

Country of ref document: EP

Kind code of ref document: A1