WO2022165837A1 - 背照式雪崩光电二极管芯片及制备方法、接收芯片、测距装置、可移动平台 - Google Patents

背照式雪崩光电二极管芯片及制备方法、接收芯片、测距装置、可移动平台 Download PDF

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WO2022165837A1
WO2022165837A1 PCT/CN2021/076010 CN2021076010W WO2022165837A1 WO 2022165837 A1 WO2022165837 A1 WO 2022165837A1 CN 2021076010 W CN2021076010 W CN 2021076010W WO 2022165837 A1 WO2022165837 A1 WO 2022165837A1
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Prior art keywords
layer
preparation
avalanche photodiode
substrate
illuminated avalanche
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PCT/CN2021/076010
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English (en)
French (fr)
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王国才
郑国光
黄潇
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2021/076010 priority Critical patent/WO2022165837A1/zh
Publication of WO2022165837A1 publication Critical patent/WO2022165837A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Definitions

  • the present application generally relates to the field of integrated circuits, and more particularly, to a back-illuminated avalanche photodiode chip and its manufacturing method, a receiving chip, a ranging device, and a movable platform.
  • lidar As the core sensor of autonomous driving, lidar is currently the mainstream use of mechanical rotating lidar. This type of lidar generally has problems such as low reliability caused by the introduction of multiple mechanical components, and low production efficiency caused by difficulty in focusing and alignment.
  • Solid-state lidar Compared with mechanical scanning lidar, solid-state lidar with smaller size and lower cost has more stable performance, excellent reliability, and is easier to pass vehicle regulations. Solid-state lidar (or Flash radar) It was once regarded as the "ultimate future" of lidar.
  • the core of solid-state lidar is the receiver chip of the area array.
  • the receiving end chip of the area array how to solve the unified power supply of the chip array and the quantum efficiency loss that may be introduced by the unified power supply process has become a problem that needs to be solved at present.
  • a first aspect of the embodiments of the present application provides a backside-illuminated avalanche photodiode chip, where the backside-illuminated avalanche photodiode chip includes:
  • an epitaxial layer having a third surface and a fourth surface disposed oppositely, the third surface of the epitaxial layer is formed on the first surface of the substrate;
  • a back-illuminated avalanche photodiode array formed on the fourth surface of the epitaxial layer
  • An opening array runs through the substrate, and the openings in the opening array are in one-to-one correspondence with the back-illuminated avalanche photodiodes in the back-illuminated avalanche photodiode array.
  • a second aspect of the embodiments of the present application provides a method for preparing a backside-illuminated avalanche photodiode chip, the preparation method comprising:
  • the substrate including first and second oppositely disposed surfaces
  • the epitaxial layer comprising a third surface and a fourth surface arranged oppositely, and the third surface of the epitaxial layer is located on the substrate;
  • An array of openings is formed on the substrate to penetrate through the substrate, wherein the openings in the array of openings correspond one by one with the back-illuminated avalanche photodiodes in the back-illuminated avalanche photodiode array.
  • a third aspect of the embodiments of the present application provides a receiving chip, where the receiving chip includes:
  • the aforementioned avalanche photodiode chip is used to receive the optical pulse sequence reflected by the detected object, and convert the received optical pulse sequence into a current signal;
  • a cross-group amplifier for converting the current signal into a voltage signal
  • a comparator for comparing the voltage signal with a preset voltage threshold
  • a time-to-digital converter configured to output a digital signal corresponding to the flight time of the optical pulse sequence according to the comparison result of the comparator.
  • a fourth aspect of the embodiments of the present application provides a ranging device, where the ranging device includes:
  • Light emitting circuit for emitting light pulse sequence
  • the aforementioned receiving chip is used to receive the optical pulse sequence reflected by the detected object, and output a digital signal based on the received optical pulse sequence;
  • an arithmetic circuit for calculating the distance between the detected object and the distance measuring device according to the digital signal.
  • a fifth aspect of the embodiments of the present application provides a movable platform, where the movable platform includes:
  • the distance measuring device is provided on the movable platform body;
  • a power system is used to drive the movable platform body to move.
  • the present application provides a back-illuminated avalanche photodiode chip, a substrate of the back-illuminated avalanche photodiode chip is formed with an array of openings penetrating the substrate, and in the light incident direction, the back-illuminated avalanche photodiode
  • the photosensitive region of the substrate is completely etched, while preserving the substrate between adjacent BSI photodiodes.
  • the above arrangement can avoid the influence on the photoresponsivity of the back-illuminated avalanche photodiode caused by the existence of a substrate with a certain thickness in the photosensitive region.
  • part of the substrate remaining between adjacent back-illuminated avalanche photodiodes is connected to the substrate of the entire array or chip, which can ensure uniform and stable power supply of the entire array of chips.
  • FIG. 1A-1G show schematic cross-sectional views of intermediate devices in the process of manufacturing a back-illuminated avalanche photodiode chip according to an embodiment of the present application
  • FIG. 2 shows a schematic cross-sectional view of a back-illuminated avalanche photodiode chip in another embodiment provided by the present application
  • FIG. 3 shows a schematic flowchart of the method for manufacturing a receiving chip provided by the present application.
  • a first aspect of the present application provides a back-illuminated avalanche photodiode chip, as shown in FIG. 1G and FIG. 2 , the back-illuminated avalanche photodiode chip includes:
  • a substrate 101 having a first surface and a second surface arranged oppositely;
  • the epitaxial layer 102 has a third surface and a fourth surface arranged opposite to each other, and the third surface of the epitaxial layer is formed on the first surface of the substrate;
  • the opening array 109 runs through the substrate, and the openings in the opening array correspond to the back-illuminated avalanche photodiodes in the back-illuminated avalanche photodiode array one by one.
  • the substrate 101 includes a first surface and a second surface arranged oppositely.
  • the substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S-SiGeOI), Silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI) etc.
  • the substrate 101 is made of silicon.
  • the epitaxial layer 102 can be selected from semiconductor materials, and in an embodiment of the present application, an epitaxial silicon wafer is selected.
  • the thickness of the epitaxial layer 102 is not limited to a certain value range.
  • the epitaxial layer 102 is formed on the first surface of the substrate, the epitaxial layer 102 includes a third surface and a fourth surface disposed opposite to each other, and the third surface of the epitaxial layer is located on the substrate .
  • the fourth surface is the front surface
  • the third surface is the back surface.
  • the avalanche photodiode may be a back-illuminated device, that is, in the back-illuminated device, the photosensitive device APD is located in front of the circuit transistor, and light first enters the photosensitive device APD, thereby Increase the sensitivity.
  • the APD is formed on the fourth surface of the epitaxial layer 102 , that is, the front surface of the epitaxial layer 102 . .
  • the epitaxial layer 102 has a low doping type, and the doping type may be N-type or P-type. Generally, the epitaxial layer 102 is P-type doped.
  • setting the epitaxial layer 102 to a low-doped type can reduce the consumption of photogenerated carriers in the APD, thereby quickly reaching the avalanche collection area of the APD, and improving the corresponding speed of the APD, Avoid the tailing problem of APD and avoid the delay of the device.
  • Isolation structures are formed on the fourth surface of the epitaxial layer 102 to form the back-illuminated avalanche photodiode in the region between the isolation structures.
  • the isolation structure may be an isolation groove 103, as shown in FIG. 1A, wherein the isolation groove includes several rows and several columns to enclose a structure similar to a square lattice , the back-illuminated avalanche photodiodes are formed in the spaces of the square-shaped lattice structure, so as to effectively suppress the electrical crosstalk between the adjacent back-illuminated avalanche photodiodes.
  • an isolation layer may be further formed on the surface of the isolation groove 103, for example, a fifth ion implantation of the second doping type is performed to form an isolation layer on the surface of the isolation groove, for Isolation etching creates surface leakage currents.
  • B ion implantation may be performed on the surface of the isolation groove 103 to form a B isolation layer on the surface of the isolation groove.
  • an isolation material layer is formed in the isolation groove 103 to completely fill the isolation groove, and the effect of the isolation etching to form the surface leakage current is further improved by the isolation material layer.
  • the etching depth of the isolation groove 103 is between 3-5um.
  • the isolation groove 103 defines a deep trench isolation region on the epitaxial layer 102 by a photolithography process, and after the photolithography is completed, deep trench etching is performed by dry etching or wet etching.
  • the isolation structure may use the doped isolation layer 112 shown in FIG. 2 in addition to the filled or unfilled isolation grooves 103 .
  • a sixth ion implantation of the second doping type is performed on the fourth surface of the epitaxial layer to form a doped isolation layer as the isolation structure.
  • the doped isolation layer 112 is P-type, and is not limited to a certain type of ions.
  • the implantation depth of the doped isolation layer 112 needs to be greater than 3um, so as to play the role of isolating and etching to form surface leakage current.
  • a back-illuminated avalanche photodiode array is formed on the fourth surface of the epitaxial layer 102 .
  • the backside illuminated avalanche photodiode includes:
  • an avalanche region located in the epitaxial layer, comprising a first doped layer and a second doped layer and a region between the first doped layer and the second doped layer, wherein:
  • the first doping layer has a first doping type
  • the second doping layer located above the first doping layer, has a second doping type, and the first doping type is different from the second doping type.
  • the first doping type and the second doping type are different, the first doping layer and the second doping layer and the first doping layer and the second doping layer The area in between constitutes the avalanche region of the avalanche photodiode 104 .
  • a first ion implantation of a first doping type is performed on the epitaxial layer 102 to form a first doping layer.
  • the implantation depth and dose of the first doping layer are adjusted to adjust the avalanche region.
  • the electric field strength can be used to optimize the gain and noise factor of the device.
  • the first ion implantation is P-type ion implantation.
  • the P-type ions are B ions.
  • the first doped layer and the second doped layer and the region between the first doped layer and the second doped layer constitute the avalanche region of the avalanche photodiode.
  • the first doping type is different from the second doping type, wherein the first ion implantation is P-type, and the second ion implantation is N-type, in an embodiment of the present application , the second ion implantation is P (phosphorus) ion or As ion.
  • an absorbing layer and the like may be further included below the avalanche region, which will not be repeated here.
  • the depth of the peak concentration of the second ion implantation is less than or equal to 200 nm, and in one embodiment of the present application, the depth of the peak concentration of the second ion implantation is 100 nm.
  • a guard ring is also formed in the epitaxial layer 102, and in the subsequent second ion implantation step, the second ion implantation is performed in the guard ring to form the guard ring surrounded by the guard ring.
  • the second doping layer further improves the yield and performance of the device by forming the guard ring to prevent edge breakdown.
  • the step of forming the guard ring may be before the first ion implantation of the first doping type, or after the first ion implantation of the first doping type and after the second doping type Before the second ion implantation, it can be selected according to actual needs.
  • the guard ring is formed before the first ion implantation of the first doping type.
  • the depth of the guard ring is greater than or equal to 2 ⁇ m.
  • An isolation ring 105 is also formed on the edge region of the fourth surface of the epitaxial layer, the back-illuminated avalanche photodiode array is separated from the peripheral region by the isolation ring 105, and the isolation ring 105 is connected to the ground electrode through the metal electrode, Reduces optical and electrical crosstalk that can be caused by the peripheral areas of the array.
  • the isolation ring 105 is formed by performing a fourth ion implantation of the second doping type, wherein the fourth ion implantation of the second doping type is N-type ion implantation.
  • the back-illuminated avalanche photodiode chip further includes: a first electrode 108 formed on the second surface of the substrate outside the opening;
  • the second electrode 106' is formed on the back-illuminated avalanche photodiode.
  • a plurality of first electrodes 108 are formed on the second surface of the substrate 101, as shown in FIG. 1G, for extracting the electrical signals of the back-illuminated avalanche photodiode.
  • Both the second electrode 106' and the ground electrode 106 are formed on the fourth surface of the epitaxial layer 102, and the second electrode 106' is located on the backside-illuminated avalanche photodiode for connecting the backside
  • the electrical signal of the illuminated avalanche photodiode is drawn out, and the ground electrode 106 is located on the isolation ring, and is used to ground the back-illuminated avalanche photodiode array to reduce optical and electrical crosstalk that may be caused by the peripheral area of the array.
  • the preparation process further includes the step of performing a thinning process on the second surface of the substrate to thin the substrate, for example, thinning the substrate to 30 ⁇ 50 ⁇ m.
  • the substrate in the light incident direction, the substrate is completely etched in the photosensitive region of the backside illuminated avalanche photodiodes, while the substrate between adjacent backside illuminated avalanche photodiodes is preserved.
  • the above arrangement can avoid the influence on the photoresponsivity of the back-illuminated avalanche photodiode caused by the existence of a substrate with a certain thickness in the photosensitive region.
  • part of the substrate remaining between adjacent back-illuminated avalanche photodiodes is connected to the substrate of the entire array or chip, which can ensure uniform and stable power supply of the entire array of chips.
  • the back-illuminated avalanche photodiode array described in this application reduces crosstalk and reduces the process difficulty after the substrate is thinned by opening the backside. Array performance is inconsistent due to power supply differences.
  • An anti-reflection layer is formed on the surface of the opening and the first electrode, wherein, Si 3 N 4 is selected for the anti-reflection layer to further increase the transmittance of light, reduce the reflection of light, and further improve the device performance.
  • a filling material layer may be formed in the opening to fill the opening and cover the antireflection layer, and the absorption rate of the filling material layer to light is lower than the absorption rate of the substrate to the light.
  • a filter 110 is formed on the first electrode and the filling material layer, as shown in FIG. 1G .
  • the integration level of the APD array chip is increased.
  • a plurality of microlenses 111 are formed on the filter. As shown in FIG. 1G , each microlens 111 corresponds to the back-illuminated avalanche photodiode one by one. By preparing the microlenses above the filter 110 111. Improve the fill factor of the APD array chip device, increase the light responsivity, and improve the crosstalk.
  • An array of openings penetrating the substrate is formed in the substrate of the back-illuminated avalanche photodiode chip of the present application.
  • the substrate In the light incident direction, the substrate is completely etched in the photosensitive region of the back-illuminated avalanche photodiode, while retaining Substrate between adjacent back-illuminated avalanche photodiodes.
  • the above arrangement can avoid the influence on the photoresponsivity of the back-illuminated avalanche photodiode caused by the existence of a substrate with a certain thickness in the photosensitive region.
  • part of the substrate remaining between adjacent back-illuminated avalanche photodiodes is connected to the substrate of the entire array or chip, which can ensure uniform and stable power supply of the entire array of chips.
  • a second aspect of the present application provides a method for preparing a backside-illuminated avalanche photodiode chip, as shown in FIG. 3 , the preparation method specifically includes the following steps:
  • Step S1 providing a substrate, the substrate includes a first surface and a second surface arranged oppositely;
  • Step S2 forming an epitaxial layer on the first surface of the substrate, the epitaxial layer includes a third surface and a fourth surface arranged oppositely, and the third surface of the epitaxial layer is located on the substrate;
  • Step S3 forming a back-illuminated avalanche photodiode array on the fourth surface of the epitaxial layer;
  • Step S4 forming an array of openings on the substrate to penetrate the substrate, wherein the openings in the opening array are one on top of the back-illuminated avalanche photodiodes in the back-illuminated avalanche photodiode array correspond.
  • FIGS. 1A-1G show schematic cross-sectional views of intermediate devices during the preparation of the back-illuminated avalanche photodiode chip provided by the present application.
  • a substrate 101 is provided, and the substrate includes a first surface and a second surface that are oppositely arranged.
  • the substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S-SiGeOI), Silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI) etc.
  • the substrate 101 is made of silicon.
  • the epitaxial layer 102 can be made of a semiconductor material, and in an embodiment of the present application, an epitaxial silicon wafer is selected.
  • the thickness of the epitaxial layer 102 is not limited to a certain value range.
  • the epitaxial layer 102 is formed on the first surface of the substrate, the epitaxial layer 102 includes a third surface and a fourth surface disposed opposite to each other, and the third surface of the epitaxial layer is located on the substrate .
  • the fourth surface is the front surface
  • the third surface is the back surface.
  • the avalanche photodiode may be a back-illuminated device, that is, in the back-illuminated device, the photosensitive device APD is located in front of the circuit transistor, and light first enters the photosensitive device APD, thereby Increase the sensitivity.
  • the APD is formed on the fourth surface of the epitaxial layer 102 , that is, the front surface of the epitaxial layer 102 . .
  • the epitaxial layer 102 has a low doping type, and the doping type may be N-type or P-type. Generally, the epitaxial layer 102 is P-type doped.
  • setting the epitaxial layer 102 to a low-doped type can reduce the consumption of photogenerated carriers in the APD, thereby quickly reaching the avalanche collection area of the APD, and improving the corresponding speed of the APD, Avoid the tailing problem of APD and avoid the delay of the device.
  • the method further includes forming isolation structures on the fourth surface of the epitaxial layer 102 to form the backside-illuminated avalanche photodiodes in regions between the isolation structures.
  • the isolation structure may be an isolation groove 103, as shown in FIG. 1A, wherein the isolation groove includes several rows and several columns to enclose a structure similar to a square lattice , the back-illuminated avalanche photodiodes are formed in the spaces of the square-shaped lattice structure, so as to effectively suppress the electrical crosstalk between the adjacent back-illuminated avalanche photodiodes.
  • a fifth ion implantation of the second doping type may be further performed on the surface of the isolation groove 103 to form an isolation layer on the surface of the isolation groove for isolation and etching to form surface leakage. current.
  • B ion implantation may be performed on the surface of the isolation groove 103 to form a B isolation layer on the surface of the isolation groove.
  • an isolation material layer may be further formed in the isolation groove 103 to completely fill the isolation groove, and the effect of the isolation etching to form the surface leakage current is further improved through the isolation material layer.
  • the etching depth of the isolation groove 103 is between 3-5um.
  • the isolation groove 103 defines a deep trench isolation region on the epitaxial layer 102 by a photolithography process, and after the photolithography is completed, deep trench etching is performed by dry etching or wet etching.
  • the isolation structure may use the doped isolation layer 112 shown in FIG. 2 in addition to the filled or unfilled isolation grooves 103 .
  • a sixth ion implantation of the second doping type is performed on the fourth surface of the epitaxial layer to form a doped isolation layer as the isolation structure.
  • the doped isolation layer 112 is P-type, and is not limited to a certain type of ions.
  • the implantation depth of the doped isolation layer 112 needs to be greater than 3um, so as to play the role of isolating and etching to form surface leakage current.
  • the method for forming a back-illuminated avalanche photodiode array on the fourth surface of the epitaxial layer 102 includes:
  • the first doping type and the second doping type are different, the first doping layer and the second doping layer and the first doping layer and the second doping layer The area in between constitutes the avalanche region of the avalanche photodiode 104 .
  • a first ion implantation of a first doping type is performed on the epitaxial layer 102 to form a first doping layer, as shown in FIG. 1C , in this application, by adjusting the implantation depth of the first doping layer and The dose can be used to adjust the electric field strength in the avalanche region to achieve the optimization of the device gain and noise factor.
  • the method before performing the first ion implantation, the method further includes the step of forming a protective layer on the surface of the epitaxial layer.
  • the protective layer can be selected from conventional oxides, such as silicon oxide, to reduce the damage to the surface lattice during the ion implantation process.
  • the thickness of the protective layer is about 10 nm, and the thickness of the protective layer is not limited to a certain value range.
  • the first ion implantation is P-type ion implantation.
  • the P-type ions are B ions.
  • the energy of the first ion implantation is 1200keV ⁇ 1600keV.
  • a second ion implantation of a second doping type is performed on the epitaxial layer 102 to form a second doping layer, and the second doping layer is located above the first doping layer.
  • the first doped layer and the second doped layer and the region between the first doped layer and the second doped layer constitute the avalanche region of the avalanche photodiode.
  • the first doping type is different from the second doping type, wherein the first ion implantation is P-type, and the second ion implantation is N-type, in an embodiment of the present application , the second ion implantation is P (phosphorus) ion or As ion.
  • an absorbing layer and the like may be further included below the avalanche region, which will not be repeated here.
  • the depth of the peak concentration of the second ion implantation is less than or equal to 200 nm, and in one embodiment of the present application, the depth of the peak concentration of the second ion implantation is 100 nm.
  • the preparation method further includes: performing a rapid annealing step, the temperature of the rapid annealing is 900 degrees Celsius to 1150 degrees Celsius, and the time is 10s to 60s, for activating the implanted ions and eliminating ion implantation defects .
  • the method further includes:
  • a guard ring is formed in the epitaxial layer 102, and in the subsequent second ion implantation step, the second ion implantation is performed in the guard ring and the second ion implantation surrounded by the guard ring is formed
  • the doped layer by forming the guard ring to prevent edge breakdown, further improves the yield and performance of the device.
  • the step of forming the guard ring may be before the first ion implantation of the first doping type, or after the first ion implantation of the first doping type and after the second doping type Before the second ion implantation, it can be selected according to actual needs.
  • the guard ring is formed before the first ion implantation of the first doping type.
  • the method for forming the guard ring includes:
  • a photoresist layer is formed on the epitaxial layer as the mask layer, and then the photoresist layer is exposed to light, developed, and then exposed to form the guard ring. area.
  • a third ion implantation of the second doping type is performed using the mask layer as a mask to form the guard ring in the exposed region.
  • the second doping type is N-type
  • the third ion implantation is P (phosphorus) ion or As ion.
  • the third ion implantation is P (phosphorus) ions. Compared with As ions, P (phosphorus) ions have smaller ions and deeper implantation depths, and have better protection effects.
  • low temperature annealing is performed, wherein the annealing temperature is 800-1000 degrees Celsius for 1-30 minutes to diffuse the implanted phosphorus ions in the guard ring region to activate the ions and eliminate defects.
  • the depth of the guard ring is greater than or equal to 2 ⁇ m.
  • the mask layer is removed.
  • the method for forming the guard ring may also include the following steps:
  • the epitaxial layer is etched to form a trench; wherein the depth of the trench is greater than or equal to 2 ⁇ m.
  • the trench is then filled to form the guard ring to perform the second ion implantation within the guard ring and to form the second doped layer surrounded by the guard ring.
  • the avalanche layer of the back-illuminated avalanche photodiode described in the present application can be formed through the above steps, and the electric field strength of the avalanche region can be effectively adjusted by adjusting the implantation depth and dose of the first doped layer, so as to realize the optimization of the device gain and noise factor.
  • the method further includes performing a fourth ion implantation of the second doping type in the edge region of the fourth surface of the epitaxial layer to form an isolation ring 105 through which the back-illuminated avalanche photodiode array is connected to the periphery of the array. Separated from the peripheral area, and the isolation ring 105 is connected to the ground electrode through the metal electrode, the optical crosstalk and electrical crosstalk that may be caused by the peripheral area of the array are reduced.
  • the fourth ion implantation of the second doping type is N-type ion implantation.
  • the step S3 further includes a step of forming a second electrode 106' and a ground electrode 106, both of which are formed on the fourth surface of the epitaxial layer 102, and the
  • the second electrode 106' is located on the backside-illuminated avalanche photodiode, and is used for extracting the electrical signal of the backside-illuminated avalanche photodiode.
  • the ground electrode 106 is located on the isolation ring, and is used for connecting the backside-illuminated avalanche photodiode. Illuminated avalanche photodiode arrays are grounded to reduce optical and electrical crosstalk that can arise from areas surrounding the array.
  • the method for forming the second electrode 106' and the ground electrode 106 includes depositing a metal electrode on the fourth surface, defining a metal electrode area by photolithography, removing the metal electrode in the remaining area by etching, and leaving the metal electrode in the remaining area.
  • the preparation method before forming the opening array on the substrate, the preparation method further includes:
  • the wafer on which the second electrode 106' and the ground electrode 106 are formed is inverted and fixed on another carrier wafer 107, wherein the carrier wafer 107 can be selected from conventional materials, such as silicon wafers, as shown in FIG. 1D described.
  • a thinning process may be further performed on the second surface of the substrate to thin the substrate, for example, the substrate is thinned to 30 ⁇ 50um.
  • a plurality of first electrodes 108 are formed on the second surface of the substrate 101, as shown in FIG. 1E, for extracting the electrical signals of the back-illuminated avalanche photodiode.
  • the method for forming the first electrode 108 includes:
  • the first electrode region and distribution are defined by photolithography, and the remaining first electrode material layers are removed by etching to form a plurality of first electrodes spaced apart from each other.
  • the substrate is etched using the first electrode 108 as a mask, and the etching depth is the remaining substrate thickness after thinning, that is, the interface between the substrate and the epitaxial layer is etched to form
  • the opening array 109 as shown in FIG. 1F, wherein the opening array runs through the substrate, and the openings in the opening array are connected to the back-illuminated avalanche photodiode in the back-illuminated avalanche photodiode array.
  • the diodes correspond one by one.
  • the substrate in the light incident direction, the substrate is completely etched in the photosensitive region of the backside illuminated avalanche photodiodes, while the substrate between adjacent backside illuminated avalanche photodiodes is preserved.
  • the influence on the photoresponsivity of the back-illuminated avalanche photodiode caused by the existence of a substrate with a certain thickness in the photosensitive region can be avoided.
  • part of the substrate remaining between adjacent back-illuminated avalanche photodiodes is connected to the substrate of the entire array or chip, which can ensure uniform and stable power supply of the entire array of chips.
  • the back-illuminated avalanche photodiode array described in this application reduces crosstalk and reduces the process difficulty after the substrate is thinned by opening the backside. Array performance is inconsistent due to power supply differences.
  • the preparation method further includes:
  • An anti-reflection layer is formed on the surface of the opening and the first electrode, wherein Si 3 N 4 is selected for the anti-reflection layer to further increase the transmittance of light, reduce the reflection of light, and further improve the device's performance. performance.
  • a filling material layer may be formed in the opening to fill the opening and cover the antireflection layer, and the absorption rate of the filling material layer to light is lower than the absorption rate of the substrate to the light.
  • silicon oxide may be deposited in the opening to further suppress optical crosstalk, and the thickness of the silicon oxide is slightly larger than the thickness of the etched substrate, even if the silicon oxide fills the entire etched groove. After the deposition is completed, the silicon oxide and the antireflection layer on the surface of the first electrode 108 are removed by chemical mechanical polishing.
  • the preparation method further includes: forming a filter 110 on the first electrode and the filling material layer, as shown in FIG. 1G .
  • a filter 110 By growing the filter 110 directly above the back-illuminated avalanche photodiode array, the integration level of the APD array chip is increased.
  • a filter material layer is defined by photolithography, and then the filter material layer is etched to form a filter 110 over the back-illuminated avalanche photodiode array.
  • the method further includes: forming a plurality of microlenses 111 on the optical filter, as shown in FIG. 1G , each microlens 111 is associated with the back-illuminated avalanche photodiode
  • the filling factor of the APD array chip device is increased, the light responsivity is increased, and the crosstalk is improved.
  • the support wafer is removed, and the photosensitive array chip is interconnected with an application-specific integrated circuit (ASIC, Application Specific Integrated Circuit) chip to form a receiving array chip.
  • ASIC Application Specific Integrated Circuit
  • a third aspect of the present application also provides a receiving chip, wherein the receiving chip includes:
  • the aforementioned back-illuminated avalanche photodiode chip is used to receive the light pulse sequence reflected by the detected object, and convert the received light pulse sequence into a current signal;
  • the signal processing chip is used for receiving the current signal of the back-illuminated avalanche photodiode chip and processing it to output the time signal.
  • the receiving chip of the present application adopts the back-illuminated avalanche photodiode chip described above, and the back-illuminated avalanche photodiode chip is formed in the substrate with an array of openings penetrating the substrate. , the substrate is completely etched in the photosensitive region of the back-illuminated avalanche photodiodes, while the substrates between adjacent back-illuminated avalanche photodiodes are preserved.
  • the influence on the photoresponsivity of the back-illuminated avalanche photodiode caused by the existence of a substrate with a certain thickness in the photosensitive region can be avoided.
  • part of the substrate remaining between adjacent back-illuminated avalanche photodiodes is connected to the substrate of the entire array or chip, which can ensure uniform and stable power supply of the entire array of chips.
  • the signal processing chip includes:
  • a cross-group amplifier for converting the current signal into a voltage signal
  • a comparator for comparing the voltage signal with a preset voltage threshold
  • the time-to-digital converter is used for outputting a time signal according to the comparison result of the comparator.
  • the signal processing unit integrates multiple circuits.
  • the signal processing unit integrates a transimpedance amplifier circuit (TIA circuit), a multi-stage operational amplifier OPAs, comparators, and time-to-digital converter circuits (circuits that convert time into digital signals) or analog-to-digital conversion circuits (ADC circuits), and subsequent data processing circuits (DSP circuits).
  • TIA circuit is an analog front-end circuit that converts the APD photocurrent into a voltage.
  • the APD when the plurality of back-illuminated avalanche photodiodes convert optical signals into current signals, an external high-voltage power supply is required, and the APD can provide stable internal gain and improve the signal-to-noise ratio, and output current signals.
  • the TIA circuit is electrically connected to the back-illuminated avalanche photodiode, and the TIA circuit converts the current signal of the APD into a voltage signal and provides a conversion gain at the same time;
  • the multi-stage operational amplifier OPA is connected to the The TIA circuit is electrically connected to amplify the signal output by the TIA circuit to meet the comparison amplitude requirement of the comparator.
  • the comparator is electrically connected to the multi-stage operational amplifier OPA, wherein a comparison threshold is set in the comparator to trigger the analog signal, the analog signal is converted into a digital signal, and the digital signal is transmitted to the TDC circuit,
  • TDC circuits are used to convert digital signals into time signals for distance calculation. Wherein, for multiple signal processing units, one TDC circuit may be shared, that is, the number of signal processing units may not correspond to the number of TDC circuits.
  • a storage system may be further provided in the signal processing unit to cache data, provide input and output buffer space for the interface, and provide space for internal calculation.
  • An interface can be further set in the signal processing unit to serve as a data input and output channel to output the measurement data.
  • the first input terminal of the comparator is used to receive the electrical signal input from the amplifiers across the group, that is, the electrical signal after the amplification operation
  • the second input terminal of the comparator is used to receive the preset Threshold
  • the output end of the comparator is used to output the result of the comparison operation, wherein the result of the comparison operation includes time information corresponding to the electrical signal.
  • the preset threshold value received by the second input end of the comparator may be an electrical signal whose intensity is the preset threshold value.
  • the result of the comparison operation may be a digital signal corresponding to the electric signal after the amplification operation.
  • the time-to-digital converter (Time-to-Digital Converter, TDC) is electrically connected to the output end of the comparator, and is used for extracting time information corresponding to the electrical signal according to the result of the comparison operation output by the comparator.
  • TDC Time-to-Digital Converter
  • a fourth aspect of the present application also provides a ranging device.
  • the back-illuminated avalanche photodiode chip or the receiving chip provided by the various embodiments of the present invention can be applied to the ranging device, and the ranging device can be a lidar, a laser Electronic equipment such as distance equipment.
  • the ranging device is used to sense external environmental information, for example, distance information, orientation information, reflection intensity information, speed information and the like of environmental objects.
  • the ranging device can detect the distance from the detected object to the ranging device by measuring the time of light propagation between the ranging device and the detected object, that is, Time-of-Flight (TOF).
  • TOF Time-of-Flight
  • the ranging device can also detect the distance from the detected object to the ranging device through other technologies, such as a ranging method based on phase shift measurement, or a ranging method based on frequency shift measurement. This does not limit.
  • the ranging device adopts the back-illuminated avalanche photodiode chip described above, and the ranging device is a solid-state laser radar, which can directly emit a pulsed laser that can cover the detection area in a short time, and then use the solid-state laser radar.
  • the highly sensitive area array APD chip receives the echo signal, and completes the detection and perception of the surrounding environment distance information through a camera-like mode.
  • solid-state lidar Compared with mechanical scanning lidar, solid-state lidar has smaller size, lower cost, more stable performance, excellent reliability, and it is easier to pass vehicle regulations.
  • the ranging device may include a transmitting circuit, a receiving chip and an arithmetic circuit.
  • the transmit circuit may transmit a sequence of optical pulses (eg, a sequence of laser pulses).
  • the receiving chip can receive the optical pulse sequence reflected by the detected object, and output a time signal based on the received optical pulse sequence.
  • the arithmetic circuit may determine the distance between the distance measuring device and the detected object based on the time signal.
  • the distance measuring device may further include a control circuit, which can control other circuits, for example, can control the working time of each circuit and/or set parameters for each circuit.
  • a control circuit which can control other circuits, for example, can control the working time of each circuit and/or set parameters for each circuit.
  • the distance and orientation detected by the ranging device can be used for remote sensing, obstacle avoidance, mapping, modeling, navigation, etc., for example, to realize the perception of the surrounding environment, and to perform two-dimensional or three-dimensional mapping of the external environment.
  • the distance measuring device of the embodiment of the present application can be applied to the movable platform.
  • the distance measuring device adopts the aforementioned back-illuminated avalanche photodiode chip, so it has all the advantages of the back-illuminated avalanche photodiode chip, which will not be repeated here.
  • a fifth aspect of the present application further provides a movable platform, wherein the distance measuring device described above can be applied to the movable platform, and the distance measuring device can be installed on the movable platform body of the movable platform.
  • the movable platform includes at least one of an unmanned aerial vehicle, a car, a remote control car, a robot, and a camera.
  • the ranging device is applied to the unmanned aerial vehicle
  • the movable platform body is the fuselage of the unmanned aerial vehicle.
  • the movable platform body is the body of the automobile.
  • the vehicle may be an autonomous driving vehicle or a semi-autonomous driving vehicle, which is not limited herein.
  • the movable platform body is the body of the remote control car.
  • the movable platform body is the robot.
  • the movable platform body is the body of the camera.
  • the movable platform may further include a power system for driving the movable platform body to move.
  • the power system may be an engine inside the vehicle, which will not be listed here.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or May be integrated into another device, or some features may be omitted, or not implemented.
  • Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all functions of some modules according to the embodiments of the present application.
  • DSP digital signal processor
  • the present application can also be implemented as a program of apparatus (eg, computer programs and computer program products) for performing part or all of the methods described herein.
  • Such a program implementing the present application may be stored on a computer-readable medium, or may be in the form of one or more signals. Such signals may be downloaded from Internet sites, or provided on carrier signals, or in any other form.

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Abstract

一种背照式雪崩光电二极管芯片及制备方法、接收芯片、测距装置、可移动平台。所述背照式雪崩光电二极管芯片包括：衬底，具有相对设置的第一表面和第二表面；外延层，具有相对设置的第三表面和第四表面，所述外延层的第三表面形成于所述衬底的第一表面上；背照式雪崩光电二极管阵列，形成于外延层的第四表面；开口阵列，贯穿衬底，并且开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。在光入射方向，在背照式雪崩光电二极管的感光区域将衬底完全刻蚀，同时保留相邻背照式雪崩光电二极管之间的衬底。通过所述设置可以避免由于感光区域存在一定厚度的衬底对背照式雪崩光电二极管光响应率造成的影响。

Description

背照式雪崩光电二极管芯片及制备方法、接收芯片、测距装置、可移动平台 技术领域
本申请总地涉及集成电路领域，更具体地涉及一种背照式雪崩光电二极管芯片及制备方法、接收芯片、测距装置、可移动平台。
背景技术
激光雷达作为自动驾驶的核心传感器，目前主流采用的都是机械旋转式激光雷达。该类型的激光雷达一般具有由于引入多个机械部件造成的可靠性低，对焦对准困难造成的生产效率低等问题。
而有着更小的尺寸、更低成本的固态激光雷达，相较于机械扫描式激光雷达，拥有更稳定的性能，优异的可靠性，更容易过车规，固态激光雷达(或称Flash雷达)一度被视为激光雷达的“终极未来”。
固态激光雷达的核心是面阵的接收端芯片。对于面阵的接收端芯片，如何解决芯片阵列统一供电及统一供电过程可能引入的量子效率损耗成为目前需要解决的问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
本申请实施例第一方面提供一种背照式雪崩光电二极管芯片，所述背照式雪崩光电二极管芯片包括：
衬底，具有相对设置的第一表面和第二表面；
外延层，具有相对设置的第三表面和第四表面，所述外延层的第三表面形成于所述衬底的第一表面上；
背照式雪崩光电二极管阵列，形成于所述外延层的第四表面；
开口阵列，贯穿所述衬底，并且所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
本申请实施例第二方面提供一种背照式雪崩光电二极管芯片的制备方法，所述制备方法包括：
提供衬底，所述衬底包括相对设置的第一表面和第二表面；
在所述衬底的第一表面上形成外延层，所述外延层包括相对设置的第三表面和第四表面，所述外延层的第三表面位于所述衬底上；
在所述外延层的第四表面形成背照式雪崩光电二极管阵列；
在所述衬底上形成开口阵列，以贯穿所述衬底，其中，所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
本申请实施例第三方面提供一种接收芯片，所述接收芯片包括：
前文所述的雪崩光电二极管芯片，用于接收经过被探测物反射的光脉冲序列，并将接收的光脉冲序列转换为电流信号；
跨组放大器，用于将所述电流信号转换为电压信号；
比较器，用于比较所述电压信号与预设电压阈值；
时间数字转换器，用于根据所述比较器的比较结果，输出所述光脉冲序列的飞行时间对应的数字信号。
本申请实施例第四方面提供一种测距装置，所述测距装置包括：
光发射电路，用于出射光脉冲序列；
前文所述的接收芯片，用于接收所述光发射电路出射的光脉冲序列经过被探测物反射的光脉冲序列，以及基于接收的光脉冲序列输出数字信号；
运算电路，用于根据所述数字信号计算所述被探测物与所述测距装置之间的距离。
本申请实施例第五方面提供一种可移动平台，所述可移动平台包括：
可移动平台本体；
前文所述的测距装置，所述测距装置设于所述可移动平台本体上；
动力系统，用于驱动所述可移动平台本体移动。
本申请提供了一种背照式雪崩光电二极管芯片，所述背照式雪崩光电二极管芯片的衬底中形成有贯穿所述衬底的开口阵列，在光入射方向，在背照式雪崩光电二极管的感光区域将衬底完全刻蚀，同时保留相邻背照式 雪崩光电二极管之间的衬底。通过所述设置可以避免由于感光区域存在一定厚度的衬底对背照式雪崩光电二极管光响应率造成的影响。同时，相邻背照式雪崩光电二极管之间留存的部分衬底与整个阵列或者芯片的衬底连接在一起，可以保证整个整列芯片的统一稳定供电。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
在附图中：
图1A-1G示出本申请提供一实施例中背照式雪崩光电二极管芯片制备过程中各中间器件的剖面示意图；
图2示出本申请提供的另一实施例中背照式雪崩光电二极管芯片的剖面示意图；
图3示出本申请提供的接收芯片的制备方法的流程示意图。
具体实施方式
为了使得本申请的目的、技术方案和优点更为明显，下面将参照附图详细描述根据本申请的示例实施例。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是本申请的全部实施例，应理解，本申请不受这里描述的示例实施例的限制。基于本申请中描述的本申请实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本申请的保护范围之内。
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构，以便阐释本申请提出的技术方案。本申请的可选实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本申请的第一方面提供了一种背照式雪崩光电二极管芯片，如图1G和图2所示，所述背照式雪崩光电二极管芯片包括：
衬底101，具有相对设置的第一表面和第二表面；
外延层102，具有相对设置的第三表面和第四表面，所述外延层的第三表面形成于所述衬底的第一表面上；
背照式雪崩光电二极管阵列104，形成于所述外延层的第四表面；
开口阵列109，贯穿所述衬底，并且所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
下面结合附图1G和图2对背照式雪崩光电二极管芯片的结构进行详细的说明。
其中，所述衬底101包括相对设置的第一表面和第二表面.
其中，所述衬底101可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本申请的一实施例中，所述衬底101选用硅。
所述外延层102可以选用半导体材料，在本申请的一实施例中，选用外延硅片。所述外延层102的厚度并不局限于某一数值范围。
其中，所述外延层102形成于所述衬底的第一表面上，所述外延层102包括相对设置的第三表面和第四表面，所述外延层的第三表面位于所述衬底上。其中，所述第四表面为正面，所述第三表面为背面。
在本申请的一实施例中，所述雪崩光电二极管可以为背照式器件，即 在所述背照式器件中所述感光器件APD位于电路晶体管前方的位置，光线首先进入感光器件APD，从而增大感光量。在本申请中所述APD形成于所述外延层102的第四表面即外延层102的正面，光线从所述外延层102的背面摄入，即从所述外延层102的第三表面射入。
可选地，所述外延层102具有低掺杂类型，掺杂类型可以为N型或P型，通常所述外延层102为P型掺杂。
在本申请中将所述外延层102设置为低掺杂类型可以减小所述APD中产生光生载流子的消耗，进而快速到达所述APD的雪崩收集区，提高所述APD的相应速度，避免APD的拖尾问题，避免器件的延迟。
在所述外延层102的第四表面形成有隔离结构，以在所述隔离结构之间的区域内形成所述背照式雪崩光电二极管。
在本申请的一实施例中，所述隔离结构可以为隔离凹槽103，如图1A所示，其中，所述隔离凹槽包括若干行和若干列，以围成类似田字格形状的结构，在所述田字格结构的空格中形成所述背照式雪崩光电二极管，以有效抑制相邻所述背照式雪崩光电二极管之间的电串扰。
在一示例中，还可以进一步在所述隔离凹槽103的表面形成有隔离层，例如执行第二掺杂类型的第五离子注入，以在所述隔离凹槽的表面形成隔离层，用于隔离刻蚀形成表面漏电流。
例如可以在所述隔离凹槽103的表面执行B离子注入，以在所述隔离凹槽的表面形成B的隔离层。
在另一示例中，在所述隔离凹槽103中形成有隔离材料层，以完全填充所述隔离凹槽，通过所述隔离材料层进一步提高隔离刻蚀形成表面漏电流的效果。
其中，所述隔离凹槽103的刻蚀深度在3～5um之间。
可选地，所述隔离凹槽103通过光刻工艺在所述外延层102上定义深槽隔离区域，光刻完成后通过干法蚀刻或者湿法蚀刻进行深槽刻蚀。
进一步，所述隔离结构除了采用填充或未被填充的所述隔离凹槽103之外还可以采用如图2所示的掺杂隔离层112。例如在所述外延层的第四表面执行第二掺杂类型的第六离子注入，以形成掺杂隔离层，作为所述隔离结构。
其中，所述掺杂隔离层112为P型，并不局限于某一种离子。
可选地，所述掺杂隔离层112的注入深度需要达到大于3um，以起到隔离刻蚀形成表面漏电流的作用。
在所述外延层102的第四表面形成有背照式雪崩光电二极管阵列。
所述背照式雪崩光电二极管包括：
雪崩区，位于所述外延层中，包括第一掺杂层和第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域，其中：
所述第一掺杂层，具有第一掺杂类型；
所述第二掺杂层，位于所述第一掺杂层的上方，具有第二掺杂类型，所述第一掺杂类型和所述第二掺杂类型不同。
其中，所述第一掺杂类型和所述第二掺杂类型不同，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管104的雪崩区。
具体地，对所述外延层102进行第一掺杂类型的第一离子注入，以形成第一掺杂层，在本申请中通过调节第一掺杂层的注入深度和剂量来调节雪崩区的电场强度，实现器件增益噪声因子的优化。
其中，所述第一离子注入为P型离子注入，在本申请的一实施例中，所述P型离子为B离子。
其中，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
具体地，所述第一掺杂类型和所述第二掺杂类型不同，其中，所述第一离子注入为P型，所述第二离子注入为N型，在本申请的一实施例中，所述第二离子注入为P(磷)离子或As离子。
可选地，在所述雪崩区的下方还可以进一步包括吸收层等，在此不再赘述。
其中，所述第二离子注入的峰值浓度的深度小于或等于200nm，在本申请的一是实施例中，所述第二离子注入的峰值浓度的深度为100nm。
在所述外延层102中还形成有保护环，并在后续的所述第二离子注入步骤时，在所述保护环内执行所述第二离子注入并形成被所述保护环包围的所述第二掺杂层，通过形成所述保护环以防止边缘击穿，进一步提高器件的良率和性能。
其中，所述保护环的形成步骤可以在所述第一掺杂类型的第一离子注 入之前，还可以在所述第一掺杂类型的第一离子注入之后以及在所述第二掺杂类型的第二离子注入之前，可以根据实际需要进行选择。
在本申请的一实施例中，在所述第一掺杂类型的第一离子注入之前形成所述保护环。
其中，所述保护环的深度为大于或等于2μm。
在所述外延层的第四表面的边缘区域还形成有隔离环105，阵列外围通过隔离环105将背照式雪崩光电二极管阵列与外围区域分离开，且隔离环105通过金属电极连接接地电极，减少阵列外围区域可能引起的光串扰和电串扰。
通过执行第二掺杂类型的第四离子注入的方法形成所述隔离环105，其中，所述第二掺杂类型的第四离子注入为N型离子注入。
所述背照式雪崩光电二极管芯片还包括：第一电极108，形成于所述衬底的所述第二表面上的所述开口之外的区域；
第二电极106'，形成于所述背照式雪崩光电二极管上。
在衬底101的第二表面形成有多个第一电极108，如图1G所示，以用于将所述背照式雪崩光电二极管的电信号引出。
所述第二电极106'和接地电极106均形成于所述外延层102的第四表面上，并且所述第二电极106'位于所述背照式雪崩光电二极管上，用于将所述背照式雪崩光电二极管的电信号引出，所述接地电极106位于所述隔离环上，用于将所述背照式雪崩光电二极管阵列接地，减少阵列外围区域可能引起的光串扰和电串扰。
制备过程还包括对所述衬底的第二表面执行减薄工艺的步骤，以减薄所述衬底，例如将所述衬底减薄至30～50um。
在本申请中在光入射方向，在背照式雪崩光电二极管的感光区域将衬底完全刻蚀，同时保留相邻背照式雪崩光电二极管之间的衬底。通过所述设置可以避免由于感光区域存在一定厚度的衬底对背照式雪崩光电二极管光响应率造成的影响。同时，相邻背照式雪崩光电二极管之间留存的部分衬底与整个阵列或者芯片的衬底连接在一起，可以保证整个整列芯片的统一稳定供电。
在本申请中所述背照式雪崩光电二极管阵列通过背面开窗的方式减少串扰及降低衬底减薄后的工艺难度，同时通过留存衬底作为互连线，使 得整个阵列芯片供电均匀，减少供电差异造成的阵列性能不一致。
在所述开口的表面和所述第一电极上形成有减反层，其中，所述减反层选用Si 3N 4，以进一步增加光线的透光率，减小光线的反射，进而提高器件的性能。
进一步，还可以在所述开口中形成填充材料层，以填充所述开口并覆盖所述减反层，所述填充材料层对光线的吸收率小于所述衬底对所述光线的吸收率。
在所述第一电极和所述填充材料层上形成有滤光片110，如图1G所示。通过在背照式雪崩光电二极管阵列上方直接生长滤光片110，增加APD阵列芯片的集成度。
在所述滤光片上形成有多个微透镜111，如图1G所示，每个微透镜111与所述背照式雪崩光电二极管上下一一对应，通过在滤光片110上方制备微透镜111，提高APD阵列芯片器件填充因子，增加光响应率，改善串扰。
本申请所述背照式雪崩光电二极管芯片的衬底中形成有贯穿所述衬底的开口阵列，在光入射方向，在背照式雪崩光电二极管的感光区域将衬底完全刻蚀，同时保留相邻背照式雪崩光电二极管之间的衬底。通过所述设置可以避免由于感光区域存在一定厚度的衬底对背照式雪崩光电二极管光响应率造成的影响。同时，相邻背照式雪崩光电二极管之间留存的部分衬底与整个阵列或者芯片的衬底连接在一起，可以保证整个整列芯片的统一稳定供电。
本申请的第二方面提供了一种背照式雪崩光电二极管芯片的制备方法，如图3所示，所述制备方法具体包括以下步骤：
步骤S1：提供衬底，所述衬底包括相对设置的第一表面和第二表面；
步骤S2：在所述衬底的第一表面上形成外延层，所述外延层包括相对设置的第三表面和第四表面，所述外延层的第三表面位于所述衬底上；
步骤S3：在所述外延层的第四表面形成背照式雪崩光电二极管阵列；
步骤S4：在所述衬底上形成开口阵列，以贯穿所述衬底，其中，所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
下面结合附图1A-1G对所述制备方法进行详细的说明，其中，图1A-1G 示出本申请提供的背照式雪崩光电二极管芯片制备过程中各中间器件的剖面示意图。
在所述步骤S1中，如图1A所示，提供衬底101，所述衬底包括相对设置的第一表面和第二表面.
其中，所述衬底101可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在本申请的一实施例中，所述衬底101选用硅。
在所述步骤S2中，所述外延层102可以选用半导体材料，在本申请的一实施例中，选用外延硅片。所述外延层102的厚度并不局限于某一数值范围。
其中，所述外延层102形成于所述衬底的第一表面上，所述外延层102包括相对设置的第三表面和第四表面，所述外延层的第三表面位于所述衬底上。其中，所述第四表面为正面，所述第三表面为背面。
在本申请的一实施例中，所述雪崩光电二极管可以为背照式器件，即在所述背照式器件中所述感光器件APD位于电路晶体管前方的位置，光线首先进入感光器件APD，从而增大感光量。在本申请中所述APD形成于所述外延层102的第四表面即外延层102的正面，光线从所述外延层102的背面摄入，即从所述外延层102的第三表面射入。
可选地，所述外延层102具有低掺杂类型，掺杂类型可以为N型或P型，通常所述外延层102为P型掺杂。
在本申请中将所述外延层102设置为低掺杂类型可以减小所述APD中产生光生载流子的消耗，进而快速到达所述APD的雪崩收集区，提高所述APD的相应速度，避免APD的拖尾问题，避免器件的延迟。
所述方法进一步包括：在所述外延层102的第四表面形成隔离结构，以在所述隔离结构之间的区域内形成所述背照式雪崩光电二极管。
在本申请的一实施例中，所述隔离结构可以为隔离凹槽103，如图1A所示，其中，所述隔离凹槽包括若干行和若干列，以围成类似田字格形状的结构，在所述田字格结构的空格中形成所述背照式雪崩光电二极管，以有效抑制相邻所述背照式雪崩光电二极管之间的电串扰。
在一示例中，还可以进一步在所述隔离凹槽103的表面执行第二掺杂类型的第五离子注入，以在所述隔离凹槽的表面形成隔离层，用于隔离刻蚀形成表面漏电流。
例如可以在所述隔离凹槽103的表面执行B离子注入，以在所述隔离凹槽的表面形成B的隔离层。
在另一示例中，还可以进一步在所述隔离凹槽103中形成隔离材料层，以完全填充所述隔离凹槽，通过所述隔离材料层进一步提高隔离刻蚀形成表面漏电流的效果。
其中，所述隔离凹槽103的刻蚀深度在3～5um之间。
可选地，所述隔离凹槽103通过光刻工艺在所述外延层102上定义深槽隔离区域，光刻完成后通过干法蚀刻或者湿法蚀刻进行深槽刻蚀。
进一步，所述隔离结构除了采用填充或未被填充的所述隔离凹槽103之外还可以采用如图2所示的掺杂隔离层112。例如在所述外延层的第四表面执行第二掺杂类型的第六离子注入，以形成掺杂隔离层，作为所述隔离结构。
其中，所述掺杂隔离层112为P型，并不局限于某一种离子。
可选地，所述掺杂隔离层112的注入深度需要达到大于3um，以起到隔离刻蚀形成表面漏电流的作用。
在所述步骤S3中，在所述外延层102的第四表面形成背照式雪崩光电二极管阵列的方法包括：
对所述外延层102的第四表面进行第一掺杂类型的第一离子注入，以形成第一掺杂层；
对所述外延层的第四表面进行第二掺杂类型的第二离子注入，以形成第二掺杂层，所述第二掺杂层位于所述第一掺杂层的上方；
其中，所述第一掺杂类型和所述第二掺杂类型不同，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管104的雪崩区。
具体地，对所述外延层102进行第一掺杂类型的第一离子注入，以形成第一掺杂层，如图1C所示，在本申请中通过调节第一掺杂层的注入深度和剂量来调节雪崩区的电场强度，实现器件增益噪声因子的优化。
具体地，在执行所述第一离子注入之前，所述方法还进一步包括在所述外延层的表面形成保护层的步骤。
其中，所述保护层可以选用常规的氧化物，例如可以选用氧化硅，以减少离子注入过程中对表面晶格损伤。
在一实施例中，所述保护层的厚度为大约10nm，所述保护层的厚度并不局限于某一数值范围。
其中，所述第一离子注入为P型离子注入，在本申请的一实施例中，所述P型离子为B离子。
具体地，所述第一离子注入的能量为1200keV～1600keV。
接着，对所述外延层102进行第二掺杂类型的第二离子注入，以形成第二掺杂层，所述第二掺杂层位于所述第一掺杂层的上方。
其中，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
具体地，所述第一掺杂类型和所述第二掺杂类型不同，其中，所述第一离子注入为P型，所述第二离子注入为N型，在本申请的一实施例中，所述第二离子注入为P(磷)离子或As离子。
可选地，在所述雪崩区的下方还可以进一步包括吸收层等，在此不再赘述。
其中，所述第二离子注入的峰值浓度的深度小于或等于200nm，在本申请的一是实施例中，所述第二离子注入的峰值浓度的深度为100nm。
在所述第二离子注入之后，所述制备方法还包括：执行快速退火步骤，所述快速退火的温度为900摄氏度～1150摄氏度，时间为10s～60s，用于活化注入离子，消除离子注入缺陷。
在进行所述第二掺杂类型的第二离子注入之前，所述方法还进一步包括：
在所述外延层102中形成保护环，并在后续的所述第二离子注入步骤时，在所述保护环内执行所述第二离子注入并形成被所述保护环包围的所述第二掺杂层，通过形成所述保护环以防止边缘击穿，进一步提高器件的良率和性能。
其中，所述保护环的形成步骤可以在所述第一掺杂类型的第一离子注入之前，还可以在所述第一掺杂类型的第一离子注入之后以及在所述第二 掺杂类型的第二离子注入之前，可以根据实际需要进行选择。
在本申请的一实施例中，在所述第一掺杂类型的第一离子注入之前形成所述保护环。
具体地，形成所述保护环的方法包括：
在所述外延层上形成图案化的掩膜层，以露出拟形成所述保护环的区域；
在本申请的一实施例中，在所述外延层上形成光刻胶层，作为所述掩膜层，然后对所述光刻胶层进行曝光，显影，进而露出拟形成所述保护环的区域。
以所述掩膜层为掩膜执行第二掺杂类型的第三离子注入，以在露出的区域内形成所述保护环。
其中，所述第二掺杂类型为N型，所述第三离子注入为P(磷)离子或As离子。在本申请的一实施例中，所述第三离子注入为P(磷)离子，P(磷)离子与As离子相比，离子较小，注入深度较深，具有更好的保护效果。
在进行离子注入之后，接着进行低温退火，其中退火温度为800-1000摄氏度退火1～30min，使所述保护环区域注入的磷离子扩散，以活化离子并消除缺陷。
其中，所述保护环的深度为大于或等于2μm。
在形成所述保护环之后，去除所述掩膜层。
在本申请的另一实施例中，形成所述保护环的方法还可以为以下步骤：
在所述第二离子注入之前，蚀刻所述外延层，以形成沟槽；其中，所述沟槽的深度为大于或等于2μm。
然后填充所述沟槽，形成所述保护环，以在所述保护环内执行所述第二离子注入并形成被所述保护环包围的所述第二掺杂层。
本申请中所述背照式雪崩光电二极管的雪崩层可以通过上述步骤形成，通过调节所述第一掺杂层的注入深度和剂量有效调节雪崩区的电场强度，实现器件增益噪声因子的优化。
所述方法还进一步包括在所述外延层的第四表面的边缘区域执行第二掺杂类型的第四离子注入，以形成隔离环105，阵列外围通过隔离环105将背照式雪崩光电二极管阵列与外围区域分离开，且隔离环105通过金属 电极连接接地电极，减少阵列外围区域可能引起的光串扰和电串扰。
其中，所述第二掺杂类型的第四离子注入为N型离子注入。
在所述步骤S3中还进一步包括形成第二电极106'和接地电极106的步骤，所述第二电极106'和接地电极106均形成于所述外延层102的第四表面上，并且所述第二电极106'位于所述背照式雪崩光电二极管上，用于将所述背照式雪崩光电二极管的电信号引出，所述接地电极106位于所述隔离环上，用于将所述背照式雪崩光电二极管阵列接地，减少阵列外围区域可能引起的光串扰和电串扰。
其中，形成所述第二电极106'和接地电极106的方法包括在第四表面上沉积金属电极，并通过光刻定义金属电极区域，将其余区域金属电极通过刻蚀方式清除干净，保留所述隔离环上的所述接地电极106和背照式雪崩光电二极管上的第二电极106'。
在所述步骤S4中，在所述衬底上形成开口阵列之前，所述制备方法还包括：
将形成所述第二电极106'和接地电极106的晶圆倒置，固定在另一个承载晶圆107上，其中所述承载晶圆107可以选用常规的材料，例如硅晶圆，如图1D所述。
可选地，在形成所述承载晶圆107之后，还可以进一步对所述衬底的第二表面执行减薄工艺，以减薄所述衬底，例如将所述衬底减薄至30～50um。
在衬底减薄之后，在衬底101的第二表面形成多个第一电极108，如图1E所示，以用于将所述背照式雪崩光电二极管的电信号引出。
所述第一电极108的形成方法包括：
在所述衬底的第二表面上形成第一电极材料层；
通过光刻定义第一电极区域及分布，将其余第一电极材料层通过刻蚀方式清除干净，以形成相互间隔的多个第一电极。
在所述步骤S4中，以所述第一电极108为掩膜蚀刻所述衬底，刻蚀深度为减薄之后剩余衬底厚度，即刻蚀到衬底与外延层的交界面处，以形成所述开口阵列109，如图1F所示，其中，所述开口阵列，贯穿所述衬底，并且所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
在本申请中在光入射方向，在背照式雪崩光电二极管的感光区域将衬底完全刻蚀，同时保留相邻背照式雪崩光电二极管之间的衬底。通过所述设置可以避免由于感光区域存在一定厚度的衬底对背照式雪崩光电二极管光响应率造成的影响。同时，相邻背照式雪崩光电二极管之间留存的部分衬底与整个阵列或者芯片的衬底连接在一起，可以保证整个整列芯片的统一稳定供电。
在本申请中所述背照式雪崩光电二极管阵列通过背面开窗的方式减少串扰及降低衬底减薄后的工艺难度，同时通过留存衬底作为互连线，使得整个阵列芯片供电均匀，减少供电差异造成的阵列性能不一致。
可选地，形成所述开口阵列之后，所述制备方法还包括：
在所述开口的表面和所述第一电极上形成减反层，其中，所述减反层选用Si 3N 4，以进一步增加光线的透光率，减小光线的反射，进而提高器件的性能。
进一步，还可以在所述开口中形成填充材料层，以填充所述开口并覆盖所述减反层，所述填充材料层对光线的吸收率小于所述衬底对所述光线的吸收率。
在本申请的一示例中，可以在所述开口中沉积氧化硅，以进一步抑制光串扰，所述氧化硅厚度稍大于刻蚀衬底的厚度，即使氧化硅充满整个刻蚀槽。沉积完成后，通过化学机械研磨的方式，将所述第一电极108表面的氧化硅和所述减反层去除。
在形成所述开口阵列之后，所述制备方法还包括：在所述第一电极和所述填充材料层上形成滤光片110，如图1G所示。通过在背照式雪崩光电二极管阵列上方直接生长滤光片110，增加APD阵列芯片的集成度。
在本申请的一实施例中，通过光刻的方式定义滤光片材料层，然后蚀刻所述滤光片材料层，以在所述背照式雪崩光电二极管阵列上方形成滤光片110。
在形成所述滤光片110之后，所述方法进一步包括：在所述滤光片上形成多个微透镜111，如图1G所示，每个微透镜111与所述背照式雪崩光电二极管上下一一对应，通过在滤光片110上方制备微透镜111，提高APD阵列芯片器件填充因子，增加光响应率，改善串扰。
最后，去除所述支撑晶圆，将感光阵列芯片与专门应用的集成电路 (ASIC，Application Specific Integrated Circuit)芯片互联，形成接收阵列芯片。
本申请的第三方面还提供了一种接收芯片，其中，所述接收芯片包括：
前文所述的背照式雪崩光电二极管芯片，用于接收经过被探测物反射的光脉冲序列，并将接收的光脉冲序列转换为电流信号；
信号处理芯片，用于接收所述背照式雪崩光电二极管芯片的电流信号并进行处理，以输出时间信号。
本申请所述接收芯片采用了前文所述的背照式雪崩光电二极管芯片，所述背照式雪崩光电二极管芯片在所述衬底中形成有贯穿所述衬底的开口阵列，在光入射方向，在背照式雪崩光电二极管的感光区域将衬底完全刻蚀，同时保留相邻背照式雪崩光电二极管之间的衬底。通过所述设置可以避免由于感光区域存在一定厚度的衬底对背照式雪崩光电二极管光响应率造成的影响。同时，相邻背照式雪崩光电二极管之间留存的部分衬底与整个阵列或者芯片的衬底连接在一起，可以保证整个整列芯片的统一稳定供电。
其中，所述信号处理芯片包括：
跨组放大器，用于将所述电流信号转换为电压信号；
比较器，用于比较所述电压信号与预设电压阈值；
时间数字转换器，用于根据所述比较器的比较结果，输出时间信号。
在本申请的一实施例中，所述信号处理单元集成有多个电路，在本申请的一实施例中，例如所述信号处理单元集成有跨阻放大器电路(TIA电路)、多级运算放大器OPA、比较器以及时间数字转换器电路(时间转化为数字信号的电路)或模数转换电路(ADC电路)，以及后续的数据处理电路(DSP电路)。其中，TIA电路为APD光电流转化为电压的模拟前段电路。
其中，所述多个背照式雪崩光电二极管在将光信号转换为电流信号时，需要外部高压供电，APD可以提供稳定的内部增益并提高信噪比，输出电流信号。
在所述信号处理单元中，所述TIA电路与所述背照式雪崩光电二极管电连接，所述TIA电路将APD的电流信号转换为电压信号，同时提供转换增益；多级运算放大器OPA与所述TIA电路电连接，用于对TIA电路输出的信号进行放大，以满足比较器的比较幅值需求。所述比较器与所述 多级运算放大器OPA电连接，其中，比较器中设置比较阈值对模拟信号进行触发，将模拟信号转换为数字信号，并将数字信号传输至TDC电路，
TDC电路用于将数字信号转换为时间信号，用于距离计算。其中，对于多个信号处理单元而言，可以共用一个TDC电路，也即，信号处理单元的数量与TDC电路的数量可以不对应。
在所述信号处理单元中还可以进一步设置存储系统，以缓存数据，为接口提供输入输出缓存空间，为内部计算提供空间。
在所述信号处理单元中还可以进一步设置接口，以作为数据输入输出通道，将测量数据输出。
在本申请的一具体实施例中，比较器的第一输入端用于接收从跨组放大器输入的电信号，也即放大运算后的电信号，比较器的第二输入端用于接收预设阈值，比较器的输出端用于输出比较运算的结果，其中，比较运算的结果中包含与电信号对应的时间信息。可以理解，比较器的第二输入端接收的预设阈值可以是强度为预设阈值的电信号。比较运算的结果可以是放大运算后的电信号对应的数字信号。
可选地，所述时间数字转换器(Time-to-Digital Converter，TDC)与比较器的输出端电连接，用于根据比较器输出的比较运算的结果，提取与电信号对应的时间信息。
本申请的第四方面还提供了一种测距装置，本发明各个实施例提供的背照式雪崩光电二极管芯片或接收芯片可以应用于测距装置，该测距装置可以是激光雷达、激光测距设备等电子设备。在一种实施方式中，测距装置用于感测外部环境信息，例如，环境目标的距离信息、方位信息、反射强度信息、速度信息等。一种实现方式中，测距装置可以通过测量测距装置和探测物之间光传播的时间，即光飞行时间(Time-of-Flight，TOF)，来探测探测物到测距装置的距离。或者，测距装置也可以通过其他技术来探测探测物到测距装置的距离，例如基于相位移动(phase shift)测量的测距方法，或者基于频率移动(frequency shift)测量的测距方法，在此不做限制。
所述测距装置采用了前文所述的背照式雪崩光电二极管芯片，所述测距装置为固态激光雷达，所述固态激光雷达可以短时间直接发射出可以覆 盖探测区域的脉冲激光，再以高度灵敏的面阵APD芯片，进行回波信号的接收，通过类似相机拍照的模式，完成对周围环境距离信息的探测和感知。相较于机械扫描式激光雷达，固态激光雷达有着更小的尺寸、更低的成本的、更稳定的性能、优异的可靠性，更容易过车规。
为了便于理解，以下将测距装置对测距的工作流程进行举例描述。
测距装置可以包括发射电路、接收芯片和运算电路。
发射电路可以发射光脉冲序列(例如激光脉冲序列)。所述接收芯片可以接收光发射电路出射的光脉冲序列经过被探测物反射的光脉冲序列，以及基于接收的光脉冲序列输出时间信号。运算电路可以基于时间信号确定测距装置与被探测物之间的距离。
可选地，该测距装置还可以包括控制电路，该控制电路可以实现对其他电路的控制，例如，可以控制各个电路的工作时间和/或对各个电路进行参数设置等。
测距装置探测到的距离和方位可以用于遥感、避障、测绘、建模、导航等，例如，实现对周围环境的感知，对外部环境进行二维或三维的测绘。在一种实施方式中，本申请实施方式的测距装置可应用于所述可移动平台。
所述测距装置采用了前文所述背照式雪崩光电二极管芯片，因此具有背照式雪崩光电二极管芯片的所有优点，在此不再赘述。
基于此，本申请第五方面还提供了一种可移动平台，其中前文所述的测距装置可应用于所述可移动平台，测距装置可安装在可移动平台的可移动平台本体。
在某些实施方式中，可移动平台包括无人飞行器、汽车、遥控车、机器人、相机中的至少一种。当测距装置应用于无人飞行器时，可移动平台本体为无人飞行器的机身。当测距装置应用于汽车时，可移动平台本体为汽车的车身。该汽车可以是自动驾驶汽车或者半自动驾驶汽车，在此不做限制。当测距装置应用于遥控车时，可移动平台本体为遥控车的车身。当测距装置应用于机器人时，可移动平台本体为机器人。当测距装置应用于相机时，可移动平台本体为相机的机身。
其中，所述可移动平台还可以进一步包括动力系统，用于驱动所述可移动平台本体移动。例如当所述可移动平台为车辆时，所述动力系统可以 为车辆内部的发动机，在此不再一一列举。
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本申请的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本申请的范围和精神。所有这些改变和修改意在被包括在所附权利要求所要求的本申请的范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本申请并帮助理解各个发明方面中的一个或多个，在对本申请的示例性实施例的描述中，本申请的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该本申请的方法解释成反映如下意图：即所要求保护的本申请要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如相应的权利要求书所反映的那样，其发明点在于可以用少于某个公开的单个实施例的所有特征的特征来解决相应的技术问题。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本申请的单独实施例。
本领域的技术人员可以理解，除了特征之间相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非 另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本申请的范围之内并且形成不同的实施例。例如，在权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
本申请的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本申请实施例的一些模块的一些或者全部功能。本申请还可以实现为用于执行这里所描述的方法的一部分或者全部的装置程序(例如，计算机程序和计算机程序产品)。这样的实现本申请的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
应该注意的是上述实施例对本申请进行说明而不是对本申请进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。本申请可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上所述，仅为本申请的具体实施方式或对具体实施方式的说明，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。本申请的保护范围应以权利要求的保护范围为准。

Claims (36)

  1. 一种背照式雪崩光电二极管芯片，其特征在于，所述背照式雪崩光电二极管芯片包括：
    衬底，具有相对设置的第一表面和第二表面；
    外延层，具有相对设置的第三表面和第四表面，所述外延层的第三表面形成于所述衬底的第一表面上；
    背照式雪崩光电二极管阵列，形成于所述外延层的第四表面；
    开口阵列，贯穿所述衬底，并且所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
  2. 根据权利要求1所述的背照式雪崩光电二极管芯片，其特征在于，在所述开口中还形成有填充材料层，所述填充材料层对光线的吸收率小于所述衬底对所述光线的吸收率。
  3. 根据权利要求2所述的背照式雪崩光电二极管芯片，其特征在于，在所述开口的表面和所述填充材料层之间还形成有减反层。
  4. 根据权利要求1所述的背照式雪崩光电二极管芯片，其特征在于，在相邻的所述背照式雪崩光电二极管之间设置有隔离结构。
  5. 根据权利要求4所述的背照式雪崩光电二极管芯片，其特征在于，所述隔离结构包括隔离凹槽。
  6. 根据权利要求5所述的背照式雪崩光电二极管芯片，其特征在于，在所述隔离凹槽的表面上形成有隔离层。
  7. 根据权利要求6所述的背照式雪崩光电二极管芯片，其特征在于，在所述隔离凹槽中的所述隔离层上还填充有隔离材料层。
  8. 根据权利要求4所述的背照式雪崩光电二极管芯片，其特征在于，所述隔离结构包括离子注入形成的掺杂隔离层。
  9. 根据权利要求1所述的背照式雪崩光电二极管芯片，其特征在于，在所述外延层的边缘处还形成有隔离环，所述隔离环与接地电极电连接。
  10. 根据权利要求1所述的背照式雪崩光电二极管芯片，其特征在于，还包括：
    第一电极，形成于所述衬底的所述第二表面上的所述开口之外的区域；
    第二电极，形成于所述背照式雪崩光电二极管上。
  11. 根据权利要求1所述的背照式雪崩光电二极管芯片，其特征在于，在所述衬底的第二表面上还形成有滤光片层。
  12. 根据权利要求11所述的背照式雪崩光电二极管芯片，其特征在于，在所述滤光片层上还形成有微透镜阵列，所述微透镜阵列中的微透镜位于所述开口上方，与所述背照式雪崩光电二极管上下一一对应。
  13. 根据前述任一项所述的背照式雪崩光电二极管芯片，其特征在于，所述背照式雪崩光电二极管包括：
    雪崩区，位于所述外延层中，包括第一掺杂层和第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域，其中：
    所述第一掺杂层，具有第一掺杂类型；
    所述第二掺杂层，位于所述第一掺杂层的上方，具有第二掺杂类型，所述第一掺杂类型和所述第二掺杂类型不同。
  14. 根据权利要求13所述的背照式雪崩光电二极管芯片，其特征在于，所述背照式雪崩光电二极管包括：
    位于所述外延层中的保护环，所述保护环包围所述第二掺杂层。
  15. 一种背照式雪崩光电二极管芯片的制备方法，其特征在于，所述制备方法包括：
    提供衬底，所述衬底包括相对设置的第一表面和第二表面；
    在所述衬底的第一表面上形成外延层，所述外延层包括相对设置的第三表面和第四表面，所述外延层的第三表面位于所述衬底上；
    在所述外延层的第四表面形成背照式雪崩光电二极管阵列；
    在所述衬底上形成开口阵列，以贯穿所述衬底，其中，所述开口阵列中的开口与所述背照式雪崩光电二极管阵列中的背照式雪崩光电二极管上下一一对应。
  16. 根据权利要求15所述的制备方法，其特征在于，在所述外延层的第四表面形成背照式雪崩光电二极管阵列的方法包括：
    对所述外延层的第四表面进行第一掺杂类型的第一离子注入，以形成第一掺杂层；
    对所述外延层的第四表面进行第二掺杂类型的第二离子注入，以形成第二掺杂层，所述第二掺杂层位于所述第一掺杂层的上方；
    其中，所述第一掺杂类型和所述第二掺杂类型不同，所述第一掺杂层和所述第二掺杂层以及所述第一掺杂层和所述第二掺杂层之间的区域构成所述雪崩光电二极管的雪崩区。
  17. 根据权利要求16所述的制备方法，其特征在于，所述制备方法包括：
    在所述第二离子注入之前，在所述外延层中形成保护环，以在所述保护环内执行所述第二离子注入并形成被所述保护环包围的所述第二掺杂层。
  18. 根据权利要求17所述的制备方法，其特征在于，所述制备方法包括：
    在所述外延层上形成图案化的掩膜层，以露出拟形成所述保护环的区域；
    以所述掩膜层为掩膜执行第二掺杂类型的第三离子注入，以在露出的区域内形成所述保护环。
  19. 根据权利要求16所述的制备方法，其特征在于，所述制备方法包括：
    在所述外延层的第四表面的边缘区域执行第二掺杂类型的第四离子注入，以形成隔离环。
  20. 根据权利要求19所述的制备方法，其特征在于，所述制备方法包括：
    在所述外延层的第四表面上形成第二电极和接地电极，其中，所述第二电极位于所述背照式雪崩光电二极管上，所述接地电极位于所述隔离环上。
  21. 根据权利要求15所述的制备方法，其特征在于，所述制备方法还包括：
    在所述外延层的第四表面形成隔离结构，以在所述隔离结构之间的区域内形成所述背照式雪崩光电二极管。
  22. 根据权利要求21所述的制备方法，其特征在于，所述制备方法还包括：
    在所述外延层的第四表面形成隔离凹槽，所述隔离凹槽包括多行和多列；
    在所述隔离凹槽的表面执行第二掺杂类型的第五离子注入，以在所述 隔离凹槽的表面形成隔离层。
  23. 根据权利要求22所述的制备方法，其特征在于，所述制备方法还包括：
    在所述隔离凹槽中形成隔离材料层，以填充所述隔离凹槽。
  24. 根据权利要求21所述的制备方法，其特征在于，所述制备方法还包括：
    在所述外延层的第四表面执行第二掺杂类型的第六离子注入，以形成掺杂隔离层，作为所述隔离结构。
  25. 根据权利要求15所述的制备方法，其特征在于，在所述衬底上形成开口阵列之前，所述制备方法还包括：
    在所述外延层的第四表面上形成支撑晶圆；
    对所述衬底的第二表面执行减薄工艺。
  26. 根据权利要求25所述的制备方法，其特征在于，减薄后的衬底的厚度为30μm-50μm。
  27. 根据权利要求25所述的制备方法，其特征在于，所述制备方法还包括：
    在所述衬底的第二表面上形成第一电极材料层；
    图案化所述电极材料层，以形成相互间隔的多个第一电极。
  28. 根据权利要求27所述的制备方法，其特征在于，所述制备方法还包括：
    以所述第一电极为掩膜蚀刻所述衬底，以形成所述开口阵列。
  29. 根据权利要求25所述的制备方法，其特征在于，形成所述开口阵列之后，所述制备方法还包括：
    在所述开口的表面和所述第一电极上形成减反层；
    在所述开口中形成填充材料层，以填充所述开口并覆盖所述减反层，所述填充材料层对光线的吸收率小于所述衬底对所述光线的吸收率。
  30. 根据权利要求29所述的制备方法，其特征在于，所述制备方法还包括：
    执行平坦化步骤至所述第一电极，以去除所述第一电极上的所述减反层和所述填充材料层。
  31. 根据权利要求29所述的制备方法，其特征在于，形成所述开口 阵列之后，所述制备方法还包括：
    在所述第一电极和所述填充材料层上形成滤光片材料层；
    图案化所述滤光片材料层，以在所述背照式雪崩光电二极管阵列上方形成滤光片；
    在所述滤光片上形成多个微透镜，每个微透镜与所述背照式雪崩光电二极管上下一一对应。
  32. 根据权利要求31所述的制备方法，其特征在于，所述制备方法还包括去除所述支撑晶圆的步骤。
  33. 一种接收芯片，其特征在于，所述接收芯片包括：
    背照式雪崩光电二极管芯片，用于接收经过被探测物反射的光脉冲序列，并将接收的光脉冲序列转换为电流信号；
    信号处理芯片，用于接收所述背照式雪崩光电二极管芯片的电流信号并进行处理，以输出时间信号。
  34. 一种测距装置，其特征在于，所述测距装置包括：
    光发射电路，用于出射光脉冲序列；
    权利要求33所述的接收芯片，用于接收所述光发射电路出射的光脉冲序列经过被探测物反射的光脉冲序列，以及基于接收的光脉冲序列输出数字信号；
    运算电路，用于根据所述数字信号计算所述被探测物与所述测距装置之间的距离。
  35. 一种可移动平台，其特征在于，所述可移动平台包括：
    可移动平台本体；
    权利要求34所述的测距装置，所述测距装置设于所述可移动平台本体上；
    动力系统，用于驱动所述可移动平台本体移动。
  36. 根据权利要求35所述的可移动平台，其特征在于，所述可移动平台包括无人机、自动驾驶汽车或机器人。
PCT/CN2021/076010 2021-02-08 2021-02-08 背照式雪崩光电二极管芯片及制备方法、接收芯片、测距装置、可移动平台 WO2022165837A1 (zh)

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