WO2022057132A1 - CMOS结构及FinFET CMOS、FD CMOS、GAA CMOS的制备方法 - Google Patents

CMOS结构及FinFET CMOS、FD CMOS、GAA CMOS的制备方法 Download PDF

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WO2022057132A1
WO2022057132A1 PCT/CN2020/138548 CN2020138548W WO2022057132A1 WO 2022057132 A1 WO2022057132 A1 WO 2022057132A1 CN 2020138548 W CN2020138548 W CN 2020138548W WO 2022057132 A1 WO2022057132 A1 WO 2022057132A1
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gate electrode
cmos
channel region
layer
pmos
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PCT/CN2020/138548
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English (en)
French (fr)
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胡辉勇
王斌
王利明
舒斌
孟令尧
杨茂龙
史鑫龙
陈睿
宣荣喜
张鹤鸣
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西安电子科技大学
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Priority claimed from CN202010988350.9A external-priority patent/CN112349717B/zh
Priority claimed from CN202011435233.6A external-priority patent/CN112687689A/zh
Application filed by 西安电子科技大学 filed Critical 西安电子科技大学
Priority to JP2023541854A priority Critical patent/JP2023546734A/ja
Priority to KR1020237010116A priority patent/KR20230056744A/ko
Publication of WO2022057132A1 publication Critical patent/WO2022057132A1/zh
Priority to US18/122,783 priority patent/US20230223408A1/en

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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the invention belongs to the technical field of semiconductors, and in particular relates to a CMOS structure and a preparation method of FinFET CMOS, FD CMOS and GAA CMOS.
  • CMOS complementary metal oxide semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • FinFET CMOS FinFET CMOS
  • FD-SOI CMOS FD-SOI CMOS
  • GAA CMOS GAA CMOS
  • CMOS structure need to use semiconductor materials of different conductivity types respectively, and similarly, the gate electrodes of nMOS and pMOS also need to use conductive materials with different work functions respectively.
  • the present invention provides a CMOS structure and a preparation method of FinFET CMOS, FD CMOS and GAA CMOS.
  • the technical problem to be solved by the present invention is realized by the following technical solutions:
  • a CMOS structure includes nMOS and pMOS, the nMOS includes a first channel region and a first gate electrode arranged on a semiconductor substrate, the pMOS includes a second channel region arranged on the semiconductor substrate and the second gate electrode, where,
  • the first channel region and the second channel region are formed of the same conductive type semiconductor material
  • the first gate electrode and the second gate electrode are formed of conductive materials with the same work function.
  • the CMOS structure is a FinFET CMOS structure, wherein,
  • the first channel region is formed in a first fin
  • the second channel region is formed in a second fin
  • the first and second fins are made of the same conductivity type semiconductor material form
  • the first gate electrode is located on the first fin, and the second gate electrode is located on the second fin.
  • the CMOS structure is an FD CMOS structure, wherein,
  • the first channel region and the second channel region are formed in a top semiconductor layer of a semiconductor substrate including an insulating layer and a top semiconductor layer and the top semiconductor layer is on the insulating layer ;
  • the first gate electrode is located on the first channel region, and the second gate electrode is located on the second channel region.
  • the CMOS structure is a GAA CMOS structure, wherein,
  • the first channel region is formed in a first nanobody structure
  • the second channel region is formed in a second nanobody structure
  • the first nanobody structure and the second nanobody structure have the same electrical conductivity type of semiconductor material formed
  • the first gate electrode surrounds the first nanobody structure, and the second gate electrode surrounds the second nanobody structure.
  • the materials of the first channel region and the second channel region are n-type semiconductor materials with the same doping concentration, and the first source region and the first drain region of the nMOS are The electrode region is n-type doped, and the second source region and the second drain region of the pMOS are p-type doped.
  • the work functions of the first gate electrode and the second gate electrode range from 4.6 to 5.1 eV.
  • the materials of the first channel region and the second channel region are p-type semiconductor materials with the same doping concentration, and the first source region and the first drain of the nMOS are The electrode region is n-type doped, and the second source region and the second drain region of the pMOS are p-type doped.
  • the work functions of the first gate electrode and the second gate electrode range from 4.1 to 4.5 eV.
  • An embodiment of the present invention also provides a preparation method of a FinFET CMOS structure, the preparation method comprising:
  • a second source region and a second drain region are prepared for the second fin to form a pMOS.
  • An embodiment of the present invention also provides a preparation method of an FD CMOS structure, the preparation method comprising:
  • the semiconductor substrate includes an insulating layer and a top semiconductor layer, the top semiconductor layer is located on the insulating layer, and the top semiconductor layer is p-type doped or n-type doped;
  • a second source region and a second drain region are prepared for the top semiconductor layer to form a pMOS.
  • An embodiment of the present invention also provides a preparation method of a GAA CMOS structure, the preparation method comprising:
  • first material stack and the second material stack etching the first material stack and the second material stack to form a first nanobody structure and a second nanobody structure, wherein the first nanobody structure and the second nanobody structure have the same conductivity type;
  • a gate dielectric layer and a first gate electrode and a second gate electrode having the same work function are formed around the first nanobody structure and the second nanobody structure.
  • the nMOS and pMOS of the present invention are fabricated on semiconductor materials of the same conductivity type (preferably the same doping concentration), so that there is no need to separately prepare the n-type region or the p-type region.
  • the materials used for the gate electrodes of the nMOS and pMOS of the present invention are conductive materials with the same work function (preferably the same conductive material), there is no need to prepare the gate electrodes of the nMOS and the gate electrodes of the pMOS respectively, so the present invention
  • the process steps for preparing the CMOS are reduced, and the process process is shortened, so that the preparation cost and process difficulty can be reduced, thereby also improving the electrical characteristics and reliability of the CMOS and its integrated circuit.
  • FIG. 1 is a schematic diagram of the principle of a CMOS provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a FinFET CMOS provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a FinFET CMOS based on a bulk silicon substrate provided by an embodiment of the present invention
  • FIGS. 4a-4f are schematic diagrams of a preparation process of a FinFET CMOS structure based on a bulk silicon substrate provided by an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of another FinFET CMOS based on a bulk silicon substrate provided by an embodiment of the present invention.
  • FIGS. 6a-6f are schematic diagrams of a preparation process of another FinFET CMOS structure based on a bulk silicon substrate provided by an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a SOI substrate-based FinFET CMOS provided by an embodiment of the present invention.
  • FIGS. 8a-8e are schematic diagrams of a preparation process of a FinFET CMOS structure based on an SOI substrate provided by an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another SOI substrate-based FinFET CMOS provided by an embodiment of the present invention.
  • 10a to 10e are schematic diagrams of a preparation process of another SOI substrate-based FinFET CMOS structure provided by an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a FinFET CMOS based on a p-type semiconductor substrate provided by an embodiment of the present invention.
  • FIGS. 12a to 12g are schematic diagrams of a preparation process of a FinFET CMOS structure based on a p-type semiconductor substrate provided by an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a FinFET CMOS based on an n-type semiconductor substrate provided by an embodiment of the present invention.
  • FIGS. 14a to 14g are schematic diagrams of a preparation process of a FinFET CMOS structure based on an n-type semiconductor substrate provided by an embodiment of the present invention.
  • FIG. 15 is a schematic structural diagram of an FD CMOS provided by an embodiment of the present invention.
  • 16a-16f are schematic diagrams of a preparation process of an FD CMOS provided by an embodiment of the present invention.
  • FIG. 17 is a schematic diagram of a GAA CMOS structure provided by an embodiment of the present invention.
  • FIG. 18 is a schematic diagram of another GAA CMOS structure provided by an embodiment of the present invention.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • FD-SOI CMOS fully depleted silicon-on-insulator CMOS
  • GAA CMOS gate all around CMOS
  • CMOS is a structure in which the drain of the nMOS and the drain of the pMOS are connected together, and the gate of the nMOS and the gate of the pMOS are connected together.
  • Both nMOS and pMOS are composed of three regions called source region, drain region and gate region or called channel region, correspondingly there is one electrode in each of source region, drain region and gate region. , are called source (electrode) electrode, drain (electrode) electrode and gate (electrode) electrode, respectively.
  • the channel region of the nMOS is made of p-type semiconductor material, and the source and drain regions are made of n-type semiconductor material.
  • the channel region of pMOS is made of n-type semiconductor material, and the source and drain regions are made of p-type semiconductor material. Meanwhile, the gate electrodes of nMOS and pMOS are conductive materials with different work functions. The above shows that there are two concerns for CMOS, namely:
  • the channel region of nMOS and the channel region of pMOS need to use semiconductor materials of different conductivity types;
  • the gate electrode of nMOS and the gate electrode of pMOS need to use conductive materials with different work functions.
  • the substrate can be bulk Si or SOI.
  • nMOS and pMOS are three-dimensional bulk structures, and the three-dimensional bulk structures of nMOS and pMOS are fin (Fin) type, so they are called fins.
  • Fin fin
  • the rest of the characteristics are the same as those of conventional CMOS, and there are also two concerns:
  • nMOS fins and pMOS fins need to use semiconductor materials of different conductivity types
  • the gate electrode of nMOS and the gate electrode of pMOS need to use conductive materials with different work functions.
  • FD CMOS For FD CMOS, the substrate is SOI.
  • CMOS complementary metal-oxide-semiconductor
  • nMOS and pMOS are prepared on the top semiconductor thin layer material of SOI, and the channel regions of nMOS and pMOS are fully depleted when there is no bias voltage.
  • FD CMOS also has two concerns:
  • the channel region of nMOS and the channel region of pMOS need to use semiconductor materials of different conductivity types;
  • the gate electrode of nMOS and the gate electrode of pMOS need to use conductive materials with different work functions.
  • the substrate can be bulk Si or SOI.
  • GAA gate-all-around
  • gate-all-around means that the gate metal surrounds the channel region of MOS.
  • the channel region material of GAA can be nanowires or nanosheets. It is called gate-all-around nanowire CMOS, and the latter is called gate-all-around nanosheet CMOS.
  • the gate-all-around nanowire/sheet CMOS can be a single layer distributed in a horizontal plane or a three-dimensional multilayer. When multi-layered, it is referred to as stacked gate-all-around nanowire/sheet CMOS. At present, whether it is a single-layer gate-all-around nanowire/chip CMOS or a stacked gate-all-around nanowire/chip CMOS, the same as conventional CMOS, there are the following two problems:
  • the gate-all-around nMOS nanowire/sheet and the gate-all-around pMOS nanowire/sheet require semiconductor materials of different conductivity types;
  • the gate electrode of the gate-all-around nanowire/sheet nMOS and the gate electrode of the gate-all-around nanowire/sheet pMOS require conductive materials with different work functions.
  • this embodiment provides a CMOS structure, the CMOS structure includes nMOS and pMOS, the nMOS includes a first channel region and a first gate electrode disposed on a semiconductor substrate, and the pMOS includes a first gate electrode disposed on the semiconductor substrate The second channel region and the second gate electrode, wherein the first channel region and the second channel region are formed of the same conductive type semiconductor material; the first gate electrode and the second gate electrode are made of conductive materials with the same work function form.
  • the materials of the first channel region and the second channel region are n-type semiconductor materials with the same doping concentration, and the first source region and the first drain region of the nMOS are n-type doped , the second source region and the second drain region of the pMOS are p-type doped.
  • first channel region and the second channel region are both prepared by using the same n-type semiconductor material with the same doping concentration
  • first gate electrode and the second gate electrode are prepared by using the work function in the n-type semiconductor material.
  • the same conductive material near the top of the band, and the work functions of the first gate electrode and the second gate electrode are selected to completely deplete the n-type semiconductor material in the channel region, preferably the first gate electrode and the second gate electrode.
  • the range of the work function is 4.6-5.1 eV, and the specific value is determined by parameters such as the thickness and doping concentration of the n-type semiconductor material, which is not limited here.
  • the materials of the first channel region and the second channel region are p-type semiconductor materials with the same doping concentration
  • the first source region and the first drain region of the nMOS are n-type doping
  • the second source region and the second drain region of the pMOS are p-type doped.
  • both the first channel region and the second channel region are prepared by using the same p-type semiconductor material with the same doping concentration, then the first gate electrode and the second gate electrode use the work function to conduct the p-type semiconductor material.
  • the same conductive material near the bottom of the band, and the work functions of the first gate electrode and the second gate electrode are selected to completely deplete the p-type semiconductor material in the channel region, preferably the first gate electrode and the second gate electrode.
  • the range of the work function is 4.1-4.5 eV, and the specific value is determined by parameters such as the thickness of the p-type semiconductor material and the doping concentration, which is not limited here.
  • FIG. 1 is a schematic diagram of the principle of a CMOS provided by an embodiment of the present invention. It can be seen from the CMOS structure provided in this embodiment and FIG. 1 that when a positive voltage V D is applied to the power supply and the input terminal is not connected to a voltage, that is, when the input terminal is floating, both nMOS and pMOS are in an off state, and CMOS does not work.
  • V D positive voltage
  • the pMOS is turned on and the output terminal is high.
  • the pMOS gradually transitions to the cutoff
  • the nMOS gradually transitions to the passthrough.
  • a low level is output.
  • the channel regions of the nMOS and pMOS in this embodiment are made of semiconductor materials of the same conductivity type, and have the same or similar doping concentration, preferably the same doping concentration, that is, the first channel region of the nMOS and the second channel of the pMOS.
  • the channel region is prepared on the p-type semiconductor with a certain doping concentration, or on the n-type semiconductor with a certain doping concentration, so that it is not necessary to specially prepare the n-type region or the p-type region, so the CMOS structure of this embodiment is The process of preparing the n-type region or the p-type region can be omitted.
  • the process of making the n-type region or the p-type region is omitted on the surface, it can reduce multiple process steps, which is beneficial to shortening the process cycle and controlling Process errors, reducing chip process costs, and improving the performance and reliability of devices and circuits are extremely beneficial and beneficial, and this problem is just one of the core issues that the industry has attached great importance to and has long been concerned about.
  • the materials used for the gate electrodes of the nMOS and pMOS in this embodiment are conductive materials with the same work function, preferably the same conductive material, when the same conductive material is used as the gate electrode, it is not necessary to prepare the gate electrodes of the nMOS separately.
  • the electrode and the gate electrode of the pMOS can also reduce multiple process steps, shorten the process cycle, control the process error, and reduce the chip process cost.
  • the gate electrode area of CMOS is its sensitive area.
  • the gate electrode controls the performance of CMOS, and the process of gate electrode preparation will affect the performance of CMOS. Therefore, the gate electrode of nMOS and the gate electrode of pMOS use the same work function.
  • the conductive material only needs to be prepared once, which is beneficial to improve the performance and reliability of the CMOS circuit.
  • this embodiment simplifies the two key process technologies of CMOS through the above-mentioned methods, reduces the process steps of preparing CMOS, reduces the process and process difficulty, thus can reduce the manufacturing cost, thereby also improving CMOS and The yield, performance and reliability of its integrated circuits.
  • the CMOS structure provided in this embodiment can also increase the threshold voltage regulation dimension and improve the switching speed.
  • CMOS structure of this embodiment may be any one of the FinFET CMOS structure, the FD CMOS structure, and the GAA CMOS structure, or may be other CMOS structures with similar characteristics.
  • FIG. 2 is a schematic structural diagram of a FinFET CMOS provided by an embodiment of the present invention.
  • this embodiment provides a FinFET CMOS structure
  • the FinFET CMOS structure includes nMOS and pMOS
  • the nMOS includes a plurality of first fins 20 and first gate electrodes 30 provided on the semiconductor substrate 10
  • the pMOS includes a plurality of second fins 40 and a second gate electrode 50 provided on the semiconductor substrate 10, wherein the first fins 20 and the second fins 40 are formed of the same conductive type semiconductor material, that is, the first fin of the nMOS A channel region and a second channel region of pMOS are formed by the first fin portion 20 and the second fin portion 40 of the same conductivity type; the first gate electrode 30 and the second gate electrode 50 are located on the first fin portion 20 and the second on the two fins 40 .
  • first fin portion 20 and the second fin portion 40 should meet the requirements of complete depletion under the action of the gate electrode work function.
  • the work function of the first gate electrode 30 and the second gate electrode 50 is to completely deplete the channel region of the fin.
  • the work function of the first gate electrode 30 and the second gate electrode 50 ranges from 4.6 to 5.1 eV.
  • the work function of the first gate electrode 30 and the second gate electrode 50 ranges from 4.1 to 4.5 eV.
  • the specific value of the work function of the gate electrode is determined by parameters such as the thickness of the fin and the doping concentration, which is not limited here.
  • the semiconductor substrate 10 may be a bulk silicon substrate or an SOI substrate, so the first fin portion 20 and the second fin portion 40 may be directly formed by etching the surface layer silicon material of bulk silicon or SOI.
  • the material of the first fin portion 20 and the second fin portion 40 can also be Ge, SiGe, III-V group or SiC, etc., for example, these materials can be formed by epitaxial growth on the surface of the silicon material, and the first fin portion can be formed by etching 20 and the second fin 40.
  • the fins of the nMOS and pMOS in this embodiment are prepared on the same conductive type semiconductor material, and have the same or similar doping concentration, preferably the same doping concentration, so that multiple process steps can be reduced, which can shorten the process cycle. It is extremely beneficial and beneficial to control process errors, reduce chip process costs, and improve the performance and reliability of devices and circuits.
  • the materials used for the gate electrodes of the nMOS and pMOS in this embodiment are conductive materials with the same work function, preferably the same conductive material, the number of process steps can be reduced, the process cycle can be shortened, the process error can be controlled, and the Chip process cost.
  • the gate electrode of nMOS and the gate electrode of pMOS are made of the same conductive material with the same work function, and only need to be prepared once, which is beneficial to improve the performance and reliability of FinFET CMOS circuits.
  • this embodiment simplifies the two key process technologies of FinFET CMOS in the above-mentioned manner, reduces the process steps of preparing FinFET CMOS, reduces the process and process difficulty, thus can reduce the manufacturing cost, thereby also improving the Yield, performance, and reliability of FinFETs and their integrated circuits.
  • the FinFET CMOS structure provided in this embodiment can also increase the threshold voltage regulation dimension and improve the switching speed.
  • this embodiment also provides a preparation method of a FinFET CMOS structure, and the preparation method of the FinFET CMOS structure includes:
  • Step 3.1 select the semiconductor substrate 10
  • Step 3.2 forming the first fin portion 20 and the second fin portion 40 of the same conductivity type on the semiconductor substrate 10;
  • Step 3.3 forming a gate dielectric layer and a first gate electrode 30 and a second gate electrode 50 with the same work function on the top and sidewall surfaces of the first fin portion 20 and the second fin portion 40;
  • Step 3.4 preparing a first source region and a first drain region for the first fin portion 20 to form nMOS
  • Step 3.5 preparing a second source region and a second drain region for the second fin portion 40 to form a pMOS.
  • step 3.2 may specifically include: etching the semiconductor substrate 10 , and forming the first fin portion 20 and the second fin portion 40 of the same conductivity type on the semiconductor substrate 10 .
  • the semiconductor substrate 10 can be directly etched to form the first fin portion 20 and the second fin portion 40 on semiconductor materials of the same conductivity type with the same or similar doping concentration, for example, the semiconductor substrate 10 is bulk silicon substrate or SOI substrate,.
  • step 3.2 may further specifically include: forming a fin material layer on the semiconductor substrate 10 ; Two fins 40 .
  • a fin material layer for forming the first fins 20 and the second fins 40 is formed on the semiconductor substrate 10 , and then the fins are etched according to the structures of the first fins 20 and the second fins 40 Therefore, the first fin part 20 and the second fin part 40 can be formed on the semiconductor substrate 10 , and the fin material layer can be Si, Ge, SiGe, III-V group or SiC, etc., for example.
  • step 3.3 may specifically include: growing a dielectric material on the top and sidewall surfaces of the first fin portion 20 and the second fin portion 40 to form a gate dielectric layer; growing on the surface of the gate dielectric layer the same gate electrode material to form the first gate electrode 30 and the second gate electrode 50 having the same work function.
  • a gate dielectric layer needs to be formed on the top and sidewall surfaces of all the first fins 20 and the second fins 40 first, and then a gate dielectric layer can be formed on the gate dielectric layer.
  • a layer of conductive material for forming the first gate electrode 30 and the second gate electrode 50 is formed thereon, the first fin portion 20 corresponds to the first gate electrode 30, and the second fin portion 40 corresponds to the second gate electrode 50.
  • the sequence of steps in the preparation method of this embodiment is not the only sequence for realizing the FinFET CMOS structure provided in Embodiment 1, it is only for the convenience of explaining the preparation method of this embodiment.
  • the first source region, the first drain region, the second source region and the second drain region are prepared first, and then the gate dielectric layer, the first gate electrode and the second gate electrode are prepared.
  • the sequence of steps is limited.
  • the process technology involved in the present invention is compatible with the existing CMOS process technology, so this embodiment does not provide all the process processes, and some process processes can be changed in order.
  • FIG. 3 is a schematic structural diagram of a FinFET CMOS based on a bulk silicon substrate provided by an embodiment of the present invention.
  • This embodiment further provides a FinFET CMOS structure prepared on bulk silicon on the basis of Embodiment 2 and Embodiment 3, that is, the semiconductor substrate 10 of this embodiment is bulk silicon, and the nMOS of the FinFET CMOS structure is included in the Several first fins 20 provided on bulk silicon, pMOS comprises several second fins 40 provided on bulk silicon, the bulk silicon includes a Si substrate layer 101 and a Si epitaxial layer located on the Si substrate layer, the Si substrate layer 101 is a p-type material, the Si epitaxial layer is an n-type material, and the first fin portion 20 and the second fin portion 40 are made of the Si epitaxial layer located on the surface layer, so the material of the first fin portion 20 and the second fin portion 40 is It is an n-type semiconductor material with the same doping concentration; then a first insulating layer 60 is provided on the
  • the first gate electrode 30 and the second gate electrode 50 are made of conductive materials with the same work function.
  • a gate dielectric layer is arranged between them, and the part of the fin in contact with the gate dielectric layer is the channel region, and the two ends of the channel region are the source region and the drain region respectively, wherein the first source region and the first drain region of the nMOS
  • the fin portion between the regions is the first channel region, and the fin portion between the second source region and the second drain region of the pMOS is the second channel region.
  • an n-type semiconductor layer 70 with the same doping concentration as the second fins 40 can also be provided under the pMOS second fins 40, so that there are Facilitates the design and performance of FinFET CMOS.
  • the second fin portion 40 of pMOS and the first fin portion 20 of nMOS can select the (100) plane or the (110) crystal plane, or the second fin portion 40 of pMOS and the first fin portion 20 of nMOS can select ( 110) and (100) planes.
  • FIGS. 4a to 4f are schematic diagrams of a fabrication process of a FinFET CMOS structure based on a bulk silicon substrate provided by an embodiment of the present invention. Based on the above content, this embodiment also provides a bulk silicon substrate.
  • a method of fabricating a FinFET CMOS structure the method comprising:
  • Step 4.1 provide bulk silicon.
  • the bulk silicon includes a Si substrate layer 101 and an Si epitaxial layer 102 located on the Si substrate layer 101.
  • the Si substrate layer is a p-type material
  • the Si epitaxial layer is an n-type material.
  • Step 4.2 please refer to FIG. 4b, the Si epitaxial layer 102 of bulk silicon is etched to form the first fins 20 and the second fins 40, and a certain thickness of Si epitaxy should be reserved under all the second fins 40 of the pMOS layer 102, and the remaining Si epitaxial layer 102 is used as the n-type semiconductor layer 70.
  • the Si substrate layer 101 can be etched, so that under each first fin 20 of the nMOS
  • a first transition structure 80 with the same or similar shape and size as the predetermined cross-section of the first fin 20 is reserved.
  • the material of the first transition structure 80 is a p-type semiconductor material, wherein the predetermined cross-section is shown in FIG. 4b.
  • the cross section shown in the horizontal direction is beneficial to the design and performance of FinFET CMOS.
  • Step 4.3 please refer to FIG. 4c, a first insulating layer 60 is provided on the bulk silicon except for the parts where the first fins 20 and the second fins 40 are formed, and the first insulating layer 60 is SiO 2 or SiN and other insulating materials.
  • a gate dielectric layer 90 is formed on the top and sidewall surfaces of all the first fins 20 and the second fins 40, wherein the material of the gate dielectric layer 90 is, for example, a high-k dielectric or SiO 2 or the like.
  • Step 4.5 referring to FIG. 4e , depositing and etching gate electrode material on the gate dielectric layer 90 to form the first gate electrode 30 and the second gate electrode 50 .
  • Step 4.6 please refer to Figure 4f, and then through n-type doping or epitaxy on both sides of the first channel region of nMOS, a first source region and a first drain region are formed, on both sides of the second channel region of pMOS Through p-type doping or epitaxy, the second source region and the second drain region are formed, and finally the metallization connection is realized.
  • FIG. 5 is a schematic structural diagram of another FinFET CMOS based on a bulk silicon substrate provided by an embodiment of the present invention.
  • This embodiment provides another FinFET CMOS structure prepared on bulk silicon on the basis of the second and third embodiments.
  • the nMOS of the FinFET CMOS structure includes a plurality of first fins 20 provided on the bulk silicon, and the pMOS includes A plurality of second fins 40 are provided on bulk silicon, the Si substrate layer 101 of the bulk silicon is made of n-type material, the Si epitaxial layer is made of p-type material, and the materials of the first fins 20 and the second fins 40 are doped p-type semiconductor material with the same concentration; then a first insulating layer 60 is provided on the bulk silicon, the first gate electrode 30 of nMOS and the second gate electrode 50 of pMOS use conductive materials with the same work function, and the gate electrode and fin A gate dielectric layer is arranged between the parts.
  • a p-type semiconductor layer 100 with the same doping concentration as the first fin portion 20 may also be disposed under the first fin portion 20 of the nMOS, which is beneficial to the design and performance of the FinFET CMOS.
  • FIGS. 6a to 6f are schematic diagrams of a fabrication process of another bulk silicon substrate-based FinFET CMOS structure provided by an embodiment of the present invention. Based on the above content, this embodiment also provides an in-body A method of fabricating a FinFET CMOS structure on silicon, the method comprising:
  • Step 5.1 provide bulk silicon.
  • the Si substrate layer 101 of bulk silicon is an n-type material
  • the Si epitaxial layer 102 is a p-type material.
  • Step 5.2 referring to FIG. 6b, the Si epitaxial layer 102 of bulk silicon is etched to form the first fins 20 and the second fins 40, and a certain thickness of Si epitaxy should be reserved under all the first fins 20 of the nMOS layer 102, and the remaining Si epitaxial layer 102 is used as the p-type semiconductor layer 100.
  • the Si substrate layer 101 can be etched, so that the lower portion of each second fin portion 40 of the pMOS is etched to the Si substrate layer 101.
  • a second transition structure 110 with the same or similar shape and size as the predetermined cross-section of the second fin 40 is reserved.
  • the material of the second transition structure 110 is an n-type semiconductor material, wherein the predetermined cross-section is shown in FIG. 6b The horizontal cross section is shown, which facilitates the design and performance of FinFET CMOS.
  • a first insulating layer 60 is provided on the bulk silicon except for the parts where the first fins 20 and the second fins 40 are formed.
  • a gate dielectric layer 90 is formed on the top and sidewall surfaces of all the first fins 20 and the second fins 40 .
  • Step 5.5 referring to FIG. 6e, depositing and etching gate electrode material on the gate dielectric layer 90 to form the first gate electrode 30 and the second gate electrode 50.
  • Step 5.6 please refer to Figure 6f, and then through n-type doping or epitaxy on both sides of the first channel region of nMOS, a first source region and a first drain region are formed, on both sides of the second channel region of pMOS Through p-type doping or epitaxy, the second source region and the second drain region are formed, and finally the metallization connection is realized.
  • FIG. 7 is a schematic structural diagram of a FinFET CMOS based on an SOI substrate provided by an embodiment of the present invention.
  • This embodiment further provides a FinFET CMOS structure prepared on SOI on the basis of Embodiment 2 and Embodiment 3, that is, the semiconductor substrate 10 of this embodiment is SOI, and the nMOS of the FinFET CMOS includes a CMOS structure arranged on the SOI.
  • a plurality of first fins 20, a pMOS includes a plurality of second fins 40 arranged on SOI, the SOI includes a substrate layer 103, a second insulating layer 104 and a surface layer silicon that are stacked in sequence, the surface layer silicon is an n-type material, the first fin The part 20 and the second fin part 40 are made of surface layer silicon, and the materials of the first fin part 20 and the second fin part 40 are n-type semiconductor materials with the same doping concentration;
  • the second gate electrode 50 adopts a conductive material with the same work function, and a gate dielectric layer is further provided between the gate electrode and the fin.
  • FIGS. 8a to 8e are schematic diagrams of a fabrication process of a FinFET CMOS structure based on an SOI substrate provided by an embodiment of the present invention. Based on the above content, this embodiment also provides a fabrication process on SOI.
  • a method of FinFET CMOS structure the method comprising:
  • Step 6.1 Provide SOI.
  • the SOI includes a substrate layer 103 , a second insulating layer 104 , and a surface layer silicon 105 which are sequentially layered, and the surface layer silicon 105 is an n-type material.
  • Step 6.2 referring to FIG. 8b, the surface layer silicon 105 of the SOI is etched to form the first fins 20 and the second fins 40, and an n-type semiconductor layer 70 is provided under all the second fins 40 of the pMOS.
  • Step 6.3 referring to FIG. 8c, a first insulating layer 60 is formed on the portion of the n-type semiconductor layer 70 except for the portion where the second fin portion 40 is formed.
  • Step 6.4 forming a gate dielectric layer 90 on the top and sidewall surfaces of all the first fins 20 and the second fins 40 .
  • Step 6.5 referring to FIG. 8d , depositing and etching gate electrode material on the gate dielectric layer 90 to form the first gate electrode 30 and the second gate electrode 50 .
  • Step 6.6 please refer to Figure 8e, and then through n-type doping or epitaxy on both sides of the first channel region of nMOS, a first source region and a first drain region are formed, on both sides of the second channel region of pMOS Through p-type doping or epitaxy, the second source region and the second drain region are formed, and finally the metallization connection is realized.
  • FIG. 9 is a schematic structural diagram of another SOI substrate-based FinFET CMOS provided by an embodiment of the present invention.
  • This embodiment further provides another FinFET CMOS structure prepared on SOI on the basis of the second and third embodiments.
  • the nMOS of the FinFET CMOS structure includes a plurality of first fins 20 arranged on the SOI, and the pMOS includes a plurality of first fins 20 on the SOI.
  • the surface silicon of the SOI is p-type material
  • the materials of the first fins 20 and the second fins 40 are p-type semiconductor materials with the same doping concentration; and the first gate of the nMOS
  • the electrode 30 and the second gate electrode 50 of the pMOS are made of conductive materials with the same work function, and a gate dielectric layer can also be provided between the gate electrode and the fin.
  • a p-type semiconductor layer 100 with the same doping concentration as the first fin portion 20 may also be disposed under the nMOS first fin portion 20 , except for the portion where the first fin portion 20 is formed on the p-type semiconductor layer 100 A first insulating layer 60 is provided on the part of the .
  • FIGS. 10a to 10e are schematic diagrams of a fabrication process of another SOI substrate-based FinFET CMOS structure provided by an embodiment of the present invention. Based on the above content, this embodiment also provides an SOI-based CMOS structure.
  • a method of fabricating a FinFET CMOS structure the method comprising:
  • Step 7.1 Provide SOI.
  • the surface layer silicon 105 of the SOI is a p-type material.
  • Step 7.2 referring to FIG. 10b, the surface layer silicon 105 is etched to form the first fins 20 and the second fins 40, and a p-type semiconductor layer 100 is provided under all the first fins 20 of the nMOS.
  • Step 7.3 referring to FIG. 10c, a first insulating layer 60 is provided on the p-type semiconductor layer 100 except for the portion where the first fins 20 are formed.
  • Step 7.4 forming a gate dielectric layer 90 on the top and sidewall surfaces of all the first fins 20 and the second fins 40 .
  • Step 7.5 referring to FIG. 10d , deposit and etch gate electrode material on the gate dielectric layer 90 to form the first gate electrode 30 and the second gate electrode 50 .
  • Step 7.6 please refer to Fig. 10e, form a first source region and a first drain region by n-type doping or epitaxy on both sides of the first channel region of nMOS, and pass them on both sides of the second channel region of pMOS p-type doping or epitaxy, forming a second source region and a second drain region, and finally realizing metallization connection.
  • FIG. 11 is a schematic structural diagram of a FinFET CMOS based on a p-type semiconductor substrate provided by an embodiment of the present invention.
  • This embodiment further provides a FinFET CMOS structure prepared on a p-type semiconductor substrate on the basis of the second and third embodiments, that is, the semiconductor substrate 10 of this embodiment is a p-type semiconductor substrate, and the There is an n-type region 106 in the type semiconductor substrate, the nMOST of the FinFET CMOS structure includes a plurality of first fins 20 arranged on the p-type semiconductor substrate, and the pMOS includes a plurality of second fins 40 arranged on the n-type region 106 , an n-type epitaxial layer is arranged on the p-type semiconductor substrate, and the materials of the first fin portion 20 and the second fin portion 40 are n-type semiconductor materials with the same doping concentration; the first gate electrode 30 of nMOS and the first gate electrode 30 of pMOS The two gate electrode
  • FIGS. 12a to 12g are schematic diagrams of a preparation process of a FinFET CMOS structure based on a p-type semiconductor substrate provided by an embodiment of the present invention. Based on the above content, this embodiment also provides a p-type semiconductor substrate.
  • a method for preparing a FinFET CMOS structure on a type semiconductor substrate comprising:
  • Step 8.1 providing a p-type semiconductor substrate.
  • the semiconductor substrate 10 is a p-type semiconductor substrate, and an n-type region 106 is disposed in the p-type semiconductor substrate, for example, the p-type semiconductor substrate is a p-type Si substrate.
  • Step 8.2 referring to FIG. 12b, prepare an n-type epitaxial layer 120 on the p-type semiconductor substrate and the n-type region 106, for example, the n-type epitaxial layer 120 is an n-type Si layer.
  • the first fins 20 are etched, they can be etched into the p-type semiconductor substrate, so that in each of the nMOS
  • a first transition structure 80 with the same or similar shape and size as the predetermined cross-section of the first fin 20 remains at the lower part of a fin 20 .
  • the material of the first transition structure 80 is p-type semiconductor material, wherein the predetermined cross-section is The cross section is a horizontal cross section as shown in Figure 12c.
  • Step 8.4 please refer to FIG. 12d , a first insulating layer 60 is provided on the part except the part where the first fin part 20 and the second fin part 40 are formed.
  • Step 8.5 please refer to FIG. 12e , forming a gate dielectric layer 90 on the top and sidewall surfaces of all the first fins 20 and the second fins 40 .
  • Step 8.6 referring to FIG. 12f, depositing and etching gate electrode material on the gate dielectric layer 90 to form the first gate electrode 30 and the second gate electrode 50.
  • Step 8.7 please refer to Fig. 12g, and then through n-type doping or epitaxy on both sides of the first channel region of nMOS, a first source region and a first drain region are formed, on both sides of the second channel region of pMOS Through p-type doping or epitaxy, the second source region and the second drain region are formed, and finally the metallization connection is realized.
  • FIG. 13 is a schematic structural diagram of a FinFET CMOS based on an n-type semiconductor substrate provided by an embodiment of the present invention.
  • This embodiment further provides a FinFET CMOS structure prepared on an n-type semiconductor substrate on the basis of the second and third embodiments, that is, the semiconductor substrate 10 in this embodiment is an n-type semiconductor substrate, and the There is a p-type region 107 in the type semiconductor substrate, the nMOS of the FinFET CMOS structure includes a plurality of first fins 20 arranged on the p-type region 107, and the pMOS includes a plurality of second fins arranged on the n-type semiconductor substrate 10. 40.
  • a p-type epitaxial layer is provided on the n-type semiconductor substrate, and the materials of the first fin portion 20 and the second fin portion 40 are p-type semiconductor materials with the same doping concentration;
  • the second gate electrode 50 adopts a conductive material with the same work function, and a gate dielectric layer is provided between the gate electrode and the fin.
  • FIGS. 14a to 14g are schematic diagrams of a preparation process of a FinFET CMOS structure based on an n-type semiconductor substrate provided by an embodiment of the present invention. Based on the above content, this embodiment also provides an A method for preparing a FinFET CMOS structure on a type semiconductor substrate, the method comprising:
  • Step 9.1 providing an n-type semiconductor substrate.
  • the semiconductor substrate 10 is an n-type semiconductor substrate, and a p-type region 107 is disposed in the n-type semiconductor substrate, for example, the n-type semiconductor substrate is an n-type Si substrate.
  • a p-type epitaxial layer 130 is prepared on the n-type semiconductor substrate and the p-type region 107.
  • the p-type epitaxial layer 130 is a p-type Si layer.
  • Step 9.3 etch the p-type epitaxial layer 130 to form the first fin portion 20 and the second fin portion 40, wherein, when the first fin portion 20 of the nMOS is etched, the p-type region can be etched Below the surface of 107, and at the same time, p-type regions 107 still remain under all the first fins 20, when the second fins 40 are etched, they can be etched into the n-type semiconductor substrate, so that in each of the pMOS A second transition structure 110 with the same or similar shape and size as the predetermined cross-section of the second fins 40 remains in the lower part of the two fins 40 .
  • the material of the second transition structure 110 is an n-type semiconductor material, wherein the predetermined cross-section is The cross section is a horizontal cross section as shown in Figure 14c.
  • Step 9.4 please refer to FIG. 14d , a first insulating layer 60 is provided on the part except the part where the first fin part 20 and the second fin part 40 are formed.
  • a gate dielectric layer 90 is formed on the top and sidewall surfaces of all the first fins 20 and the second fins 40.
  • Step 9.6 referring to FIG. 14f , deposit and etch gate electrode material on the gate dielectric layer 90 to form the first gate electrode 30 and the second gate electrode 50 .
  • Step 9.7 please refer to Fig. 14g, and then through n-type doping or epitaxy on both sides of the first channel region of nMOS, a first source region and a first drain region are formed, on both sides of the second channel region of pMOS Through p-type doping or epitaxy, the second source region and the second drain region are formed, and finally the metallization connection is realized.
  • FIG. 15 is a schematic structural diagram of an FD CMOS provided by an embodiment of the present invention.
  • this embodiment provides an FD CMOS structure.
  • the semiconductor substrate 10 of the FD CMOS structure includes a substrate layer, an insulating layer and a top semiconductor layer that are stacked in sequence.
  • the nMOS of the FD CMOS structure includes a A plurality of first channel regions 140 formed by the top semiconductor layer of the semiconductor substrate 10 and a first gate electrode 30 disposed on the first channel regions 140
  • the pMOS includes a plurality of second channel regions 140 formed by the top semiconductor layer of the semiconductor substrate 10 The channel region 150 and the second gate electrode 50 disposed on the second channel region 150 .
  • the first channel region 140 and the second channel region 150 are formed of the same conductive type top semiconductor layer material; in addition, the first gate electrode 30 and the second gate electrode 50 are formed of conductive materials with the same work function. It should be emphasized that the thickness and doping concentration of the top semiconductor layer should meet the requirements of complete depletion under the work function of the gate electrode.
  • the range of the work function of the first gate electrode 30 and the second gate electrode 50 is 4.6 ⁇ 5.1eV.
  • the work functions of the first gate electrode 30 and the second gate electrode 50 are in the range of 4.1 ⁇ 4.5 eV.
  • the specific value of the work function of the gate electrode is determined by parameters such as the thickness of the top semiconductor layer and the doping concentration, which is not limited herein.
  • the semiconductor substrate 10 is preferably SOI, in addition, the top semiconductor layer may also be one of Si, SiGe, Ge, SiC, and Group III-IV.
  • the channel regions of the nMOS and pMOS in this embodiment are prepared on the top semiconductor layer of the same conductivity type, and have the same or similar doping concentration, preferably the same doping concentration, so that it is not necessary to specially prepare the n-type region or the p-type region Therefore, the FD CMOS structure of this embodiment can save the process of preparing the n-type region or the p-type region, thereby reducing multiple process steps, which can shorten the process cycle, control the process error, reduce the chip process cost, and improve the The performance and reliability of devices and circuits are extremely beneficial and advantageous.
  • the materials used for the gate electrodes of the nMOS and pMOS in this embodiment are conductive materials with the same work function, preferably the same conductive material, there is no need to prepare the gate electrodes of the nMOS and the gate electrodes of the pMOS separately. This can reduce multiple process steps, shorten the process cycle, control process errors, and reduce chip process costs.
  • the gate electrode of nMOS and the gate electrode of pMOS use the same conductive material with the same work function, and only need to be prepared once, which is beneficial to improve the performance and reliability of the FD CMOS circuit.
  • the present embodiment simplifies the two key process technologies of FD CMOS in the above-mentioned manner, reduces the process steps for preparing FD CMOS, reduces the process and process difficulty, thus can reduce the manufacturing cost, and thus can also improve the Yield, performance and reliability of FD CMOS and its integrated circuits.
  • the FD CMOS structure provided in this embodiment can also increase the threshold voltage regulation dimension and improve the switching speed.
  • an electrode can also be provided on the substrate layer, which together with the gate electrode above controls the turn-on and turn-off of the device, and can fully ensure the depletion of the top semiconductor layer.
  • the present embodiment also provides a method for preparing an FD CMOS structure, and the method for preparing the FD CMOS structure includes:
  • Step 10.1 select a semiconductor substrate 10, the semiconductor substrate includes an insulating layer and a top semiconductor layer located on the insulating layer, and the top semiconductor layer is p-type doped or n-type doped;
  • Step 10.2 forming a gate dielectric layer 90 and a first gate electrode 30 and a second gate electrode 50 with the same work function on the top semiconductor layer;
  • Step 10.3 preparing a first source region 190 and a first drain region 200 on the top semiconductor layer to form an nMOS;
  • Step 10.4 preparing a second source region 210 and a second drain region 220 on the top semiconductor layer to form a pMOS.
  • step 10.2 may specifically include: growing a dielectric material layer on the top semiconductor layer; growing the same gate metal material on the surface of the dielectric material layer to form the gate dielectric layer 90 and the gate dielectric layer 90 on the first gate electrode 30 and the second gate electrode 50 .
  • a dielectric material layer needs to be deposited on the top semiconductor layer first, and the dielectric material layer is used to form the gate dielectric layer 90, and then a layer is formed on the dielectric material layer to form the first gate electrode 30 and the first gate electrode 30.
  • the conductive material of the second gate electrode 50 is etched, and then the conductive material and the dielectric material layer on the dielectric material layer are etched to form the gate dielectric layer 90 and the first gate electrode 30 and the second gate electrode 50 on the gate dielectric layer 90 .
  • step 10.3 may specifically include: using an ion implantation or diffusion method to perform n-type doping on the top semiconductor layer of the nMOS region to form the first source region 190 and the first drain region 200.
  • step 10.4 may specifically include: using ion implantation or diffusion method to p-type doping on the top semiconductor layer of the pMOS region to form the second source region 210 and the second drain region 220.
  • sequence of steps in the preparation method of this embodiment is not the only sequence for realizing the FD CMOS structure provided in Embodiment 1, but is only for the convenience of explaining the preparation method of this embodiment.
  • the second source region and the second drain region are prepared first, and then the first source region and the first drain region are prepared, so the sequence of steps in this embodiment cannot be limited.
  • the process technology involved in the present invention is compatible with the existing CMOS process technology, so this embodiment does not provide all the process processes, and some of the process processes can be changed in order.
  • FIGS. 16a to 16f are schematic diagrams of a fabrication process of an FD CMOS provided by an embodiment of the present invention. On the basis of Embodiment 11, this embodiment also provides a specific preparation method of FD CMOS, and the preparation method includes:
  • Step 11.1 please refer to FIG. 16a , providing the semiconductor substrate 10 .
  • the semiconductor substrate 10 is SOI
  • the top layer Si of the SOI can be an n-type semiconductor or a p-type semiconductor.
  • the process steps of preparing CMOS The same as the process, the only difference in the process is the conductive material used in the subsequent preparation of the gate electrode.
  • the thickness and doping concentration of the top layer Si are prepared according to design requirements.
  • Step 11.2 please refer to FIG. 16b, wherein FIG. 16b is a front view, forming a shallow trench isolation 160 (STI, Shallow trench isolation).
  • STI shallow trench isolation
  • isolation trenches are etched, and a dielectric is deposited in the isolation trenches, and the dielectric is flush with the top layer Si surface to form shallow trench isolation 160 .
  • the function of the shallow trench isolation 160 is to achieve electrical isolation between the nMOS and the pMOS.
  • Step 11.3 depositing a gate dielectric layer and preparing a gate electrode.
  • a dielectric material layer is first deposited on the top layer of Si, and then a gate metal layer is deposited on the dielectric material layer.
  • the work function of the gate metal depends on the conductivity type of the SOI top layer of Si.
  • the specific value of the gate metal work function is determined based on the optimization of electrical parameters and physical parameters of the top layer Si.
  • the gate metal layer and the dielectric material layer are etched to form the nMOS and pMOS gate dielectric layers 90 and the first gate electrode 30 and the second gate electrode 50 located on the gate dielectric layer 90 .
  • Step 11.4 forming LDD (Lightly doped drain implants process, lightly doped drain implants).
  • the device structures in the isolation area are completely identical, it is necessary to first determine which ones are nMOS and which ones are pMOS, and then determine the devices that need to be LDDed according to the conductivity type of the top layer Si, where if the top layer Si is an n-type semiconductor , then only the p-type LDD 170 is formed for the pMOS, as shown in FIG. 16d; if the top layer Si is a p-type semiconductor, the n-type LDD is only formed for the nMOS.
  • Step 11.5 forming a spacer dielectric and forming a source region and a drain region.
  • a spacer dielectric 180 is formed on the sidewalls of the first gate electrode 30 and the second gate electrode 50, and then n-type doping is performed on the top semiconductor layer of the nMOS region by ion implantation or diffusion method,
  • the top semiconductor layer of the pMOS region is p-type doped by ion implantation or diffusion method to prepare the p-type doped second source electrode region 210 and the second drain region 220, wherein the first channel region 140 is located between the first source region 190 and the first drain region 200, and the second channel region 150 is located between the second source region 210 and the first drain region 200 between the second drain regions 220 .
  • Step 11.6 forming metal electrodes.
  • a metal electrode 230 with ohmic contact is formed by depositing dielectric and metal and etching.
  • Step 11.7 FD SOI CMOS metallization.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • the metallization process and method for forming the CMOS are the same as the conventional CMOS process, and will not be repeated here.
  • FIG. 17 is a schematic diagram of a GAA CMOS structure provided by an embodiment of the present invention, wherein FIG. 17(1) and FIG. 17(3) are cross-sectional views of side views, and FIG. 17(2) is a front view. partial cross-section.
  • this embodiment provides a GAA CMOS structure, and the nMOS of the GAA CMOS structure includes a first nanobody structure 240 disposed on the semiconductor substrate 10 and a first nanobody structure 240 surrounding the first nanobody structure 240.
  • a gate electrode 30, the pMOS includes a second nanobody structure 250 disposed on the semiconductor substrate 10 and a second gate electrode 50 surrounding the second nanobody structure 250, wherein the first nanobody structure 240 and the second nanobody structure 250 is formed of a semiconductor material of the same conductivity type; the first gate electrode 30 and the second gate electrode 50 are formed of a conductive material of the same work function. It should be emphasized that the thickness and doping concentration of the first nanobody structure 240 and the second nanobody structure 250 should meet the requirements of complete depletion under the action of the gate electrode work function.
  • the range of the work function of the first gate electrode 30 and the second gate electrode 50 is 4.6 ⁇ 5.1eV.
  • the work function of the first gate electrode 30 and the second gate electrode 50 ranges from 4.1 to 4.5 eV.
  • the specific value of the work function of the gate electrode is determined by parameters such as the thickness of the nanobody structure and the doping concentration, which is not limited herein.
  • the first nanobody structure 240 includes at least one first nanobody
  • the second nanobody structure includes at least one second nanobody, wherein the number of the first nanobody and the second nanobody is greater than or equal to
  • a plurality of first nanobodies or a plurality of second nanobodies are arranged in a stacking manner in the vertical direction, where the vertical direction is shown in Figure 17, and the other is A plurality of first nanobodies or a plurality of second nanobodies are arranged in the same layer in the horizontal direction.
  • the first nanobody and the second nanobody can be in the same layer or adjacent layers.
  • the semiconductor materials used by the first nanobody and the second nanobody are the same, for example, both are Si, Ge or SiGe, etc.
  • the semiconductor materials used by the first nanobody and the second nanobody are different, for example, the material of the first nanobody is Si, and the material of the second nanobody is Ge or SiGe.
  • FIG. 17 and FIG. 18 FIG. 17 is a structure in which the first nanobody and the second nanobody are in the same layer
  • FIG. 18 is a structure in which the first nanobody and the second nanobody are in adjacent layers.
  • Fig. 18(1) and Fig. 18(3) are sectional views in side view
  • Fig. 18(2) is a partial sectional view in front view.
  • first nanobody and the second nanobody are nanosheets or nanowires.
  • the nanosheets or nanowires can be semiconductor materials such as Si, SiGe, Ge, SiC, and III-IV groups.
  • the semiconductor substrate 10 may be a bulk silicon substrate or an SOI substrate.
  • the semiconductor substrate 10 can also be made of semiconductor materials such as Si, SiGe, Ge, SiC, and III-IV groups.
  • the first nanobody structure of nMOS and the second nanobody structure of pMOS in this embodiment are prepared by using semiconductor materials of the same conductivity type, and have the same or similar doping concentration, preferably the same doping concentration, so that the GAA of this embodiment is CMOS can save the process of separately preparing semiconductor materials of different conductivity types, thereby reducing multiple process steps, which can shorten the process cycle, control process errors, reduce chip process costs, and improve the performance and reliability of devices and circuits. is extremely beneficial and beneficial.
  • the materials used for the gate electrodes of the nMOS and pMOS in this embodiment are conductive materials with the same work function, preferably the same conductive material, there is no need to prepare the gate electrodes of the nMOS and the gate electrodes of the pMOS separately. Therefore, although the key process for preparing the gate electrode is reduced, multiple process steps can also be reduced, the process cycle can be shortened, the process error can be controlled, and the chip process cost can be reduced.
  • the gate electrode of nMOS and the gate electrode of pMOS use the same conductive material with the same work function, and only need to be prepared once, which is beneficial to improve the performance and reliability of GAA CMOS circuits.
  • the present embodiment simplifies the two key process technologies of GAA CMOS in the above-mentioned manner, reduces the process steps for preparing GAA CMOS, reduces the process and process difficulty, thus can reduce the manufacturing cost, thereby also improving the Yield, performance and reliability of GAA CMOS and its integrated circuits.
  • the GAA CMOS structure provided by this embodiment can also increase the threshold voltage regulation dimension and improve the switching speed.
  • this embodiment further provides a method for preparing a GAA CMOS structure, and the method for preparing the GAA CMOS structure includes:
  • Step 12.1 select the semiconductor substrate 10
  • Step 12.2 forming a first material stack and a second material stack on the semiconductor substrate 10;
  • Step 12.3 etching the sacrificial layer of the first material stack and the sacrificial layer of the second material stack, correspondingly forming a first nanobody structure 240 with a first source region 190 and a first drain region 200 at both ends, A second nanobody structure 250 with a second source region 210 and a second drain region 220 disposed at both ends;
  • Step 12.4 forming a gate dielectric layer and a first gate electrode 30 and a second gate electrode 50 with the same work function around the first nanobody structure 240 and the second nanobody structure 250 to form nMOS and pMOS, wherein the first nanobody The structure and the second nanobody structure have the same conductivity type.
  • Metal is deposited to achieve metallized connections, as shown in Figures 17 and 18, to form GAA CMOS.
  • step 12.2 may specifically include:
  • Step 12.21 forming alternately stacked first material layers and second material layers on the semiconductor substrate 10;
  • Step 12.22 etching the stacked first material layer and the second material layer to form a first material stack and a second material stack.
  • the stacked first material layer and the second material layer are sequentially formed on the semiconductor substrate 10, and then the stacked first material layer and the second material layer are etched, thereby forming the first nanobody for preparing the first nanobody.
  • step 12.21 may specifically include:
  • first material layer and the second material layer are grown on the semiconductor substrate 10 , alternately stacked first material layers and second material layers having the same conductivity type are formed in combination with the in-situ doping method.
  • step 12.3 may specifically include:
  • Step 12.31 preparing a first source region 190 and a first drain region 200 at both ends of the first material stack, and preparing a second source region 210 and a second drain region 220 at both ends of the second material stack;
  • Step 12.32 etching the sacrificial layer of the first material stack to form the first nanobody structure 240 and etching the sacrificial layer of the second material stack to form the second nanobody structure 250 .
  • the sacrificial layer is the material layer that needs to be removed.
  • nanosheets or nanowires in the same layer can be formed.
  • a nanobody structure 240 and a second nanobody structure 250 when the first material layer of the first material stack and the second material layer of the second material stack are etched away, nanosheets or nanowires can be formed in adjacent layers The first nanobody structure 240 and the second nanobody structure 250 .
  • step 12.4 may specifically include:
  • Step 12.41 growing a dielectric material around the first nanobody structure 240 and the second nanobody structure 250 to form a gate dielectric layer;
  • Step 12.42 growing the same gate electrode material on the surface of the gate dielectric layer to form the first gate electrode 30 and the second gate electrode 50 having the same work function.
  • the sequence of steps in the preparation method of this embodiment is not the only sequence for realizing the GAA CMOS structure provided in Embodiment 1, it is only for the convenience of explaining the preparation method of this embodiment.
  • Prepare the first source region and the first drain region and then prepare the second source region and the second drain region, or prepare the second source region and the second drain region first, and then prepare the first source region , the first drain region.
  • the process technology involved in the present invention is compatible with the existing CMOS process technology, so this embodiment does not provide all the process processes, and some of the process processes can be changed in order.
  • first and second are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • “plurality” means two or more, unless otherwise expressly and specifically defined.

Abstract

一种CMOS结构及FinFET CMOS、FD CMOS、GAA CMOS的制备方法，该CMOS结构，包括nMOS和pMOS，所述nMOS包括在半导体衬底（10）上设置的第一沟道区和第一栅电极（30），所述pMOS包括在所述半导体衬底（10）上设置的第二沟道区和第二栅电极（50），其中，所述第一沟道区与所述第二沟道区由相同导电类型的半导体材料形成；所述第一栅电极（30）与所述第二栅电极（50）由相同功函数的导电材料形成。所述CMOS结构减少了制备CMOS的工艺步骤，缩减了工艺过程，从而可以降低工艺难度和制备成本，由此还有益于提升CMOS及其集成电路的性能与可靠性。

Description

CMOS结构及FinFET CMOS、FD CMOS、GAA CMOS的制备方法 技术领域
本发明属于半导体技术领域，具体涉及一种CMOS结构及FinFET CMOS、FD CMOS、GAA CMOS的制备方法。
背景技术
随着集成电路越来越广泛的应用以及对集成电路功能，尤其是性能要求的增强，作为集成电路基本单元的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)器件，其结构势必需要不断改进，其性能及工艺水平势必需要不断提升。据此，业界研究者提出了多种新型的CMOS结构方案和相应技术，但CMOS仍由nMOS和pMOS构成的基本结构不变。
随着集成电路规模的不断扩大以及特征尺寸的不断缩小，CMOS的结构经历了常规平面CMOS、FinFET CMOS、FD-SOI CMOS和目前处于研究发展中的GAA CMOS等结构历程。
无论上述哪种结构的CMOS，其nMOS和pMOS的沟道区都需要分别采用不同导电类型的半导体材料，同样，nMOS和pMOS的栅电极也需要分别采用不同功函数的导电材料。
为了实现上述二项基本特征，需要复杂的工艺方法与步骤，无疑会对工艺流程、工艺成本、器件与电路性能带来影响。
发明内容
为了解决现有技术中的上述问题，本发明提供了一种CMOS结构及FinFET CMOS、FD CMOS、GAA CMOS的制备方法。本发明要解决的技术问题通过以下技术方案实现：
一种CMOS结构，包括nMOS和pMOS，所述nMOS包括在半导体衬底上设置的第一沟道区和第一栅电极，所述pMOS包括在所述半导体衬底上设置的第二沟道区和第二栅电极，其中，
所述第一沟道区与所述第二沟道区由相同导电类型的半导体材料形成；
所述第一栅电极与所述第二栅电极由相同功函数的导电材料形成。
在本发明的一个实施例中，所述CMOS结构为FinFET CMOS结构，其中，
所述第一沟道区在第一鳍部中形成，所述第二沟道区在第二鳍部中形成，所述第一鳍部和所述第二鳍部由相同导电类型的半导体材料形成；
所述第一栅电极位于所述第一鳍部上，所述第二栅电极位于所述第二鳍部上。
在本发明的一个实施例中，所述CMOS结构为FD CMOS结构，其中，
所述第一沟道区和所述第二沟道区形成于半导体衬底的顶部半导体层中，所述半导体衬底包括绝缘层和顶部半导体层且所述顶部半导体层位于所述绝缘层上；
所述第一栅电极位于所述第一沟道区上，所述第二栅电极位于所述第二沟道区上。
在本发明的一个实施例中，所述CMOS结构为GAA CMOS结构，其中，
所述第一沟道区在第一纳米体结构中形成，所述第二沟道区在第二纳米体结构中形成，所述第一纳米体结构与所述第二纳米体结构由相同导电类型的半导体材料形成；
所述第一栅电极环绕所述第一纳米体结构，所述第二栅电极环绕所述第二纳米体结构。
在本发明的一个实施例中，所述第一沟道区与所述第二沟道区的材料为掺杂浓度相同的n型半导体材料，所述nMOS的第一源极区、第一漏极区为n型掺杂，所述pMOS的第二源极区、第二漏极区为p型掺杂。
在本发明的一个实施例中，所述第一栅电极和所述第二栅电极的功函数的范围为4.6～5.1eV。
在本发明的一个实施例中，所述第一沟道区与所述第二沟道区的材料为掺杂浓度相同的p型半导体材料，所述nMOS的第一源极区、第一漏极区为n型掺杂，所述pMOS的第二源极区、第二漏极区为p型掺杂。
在本发明的一个实施例中，所述第一栅电极和所述第二栅电极的功函数的范围为4.1～4.5eV。
本发明一个实施例还提供一种FinFET CMOS结构的制备方法，所述制备方法包括：
选取半导体衬底；
在所述半导体衬底上形成相同导电类型的第一鳍部和第二鳍部；
在所述第一鳍部和所述第二鳍部的顶部和侧壁表面形成栅介质层和相同功函数的第一栅电极和第二栅电极；
对所述第一鳍部制备第一源极区和第一漏极区以形成nMOS；
对所述第二鳍部制备第二源极区和第二漏极区以形成pMOS。
本发明一个实施例还提供一种FD CMOS结构的制备方法，所述制备方法包括：
选取半导体衬底，所述半导体衬底包括绝缘层和顶部半导体层且所述顶部半导体层位于所述绝缘层上，所述顶层半导体层为p型掺杂或n型掺杂；
在所述顶层半导体层上形成栅介质层和相同功函数的第一栅电极和第二栅电极；
对所述顶层半导体层制备第一源极区和第一漏极区，以形成nMOS；
对所述顶层半导体层制备第二源极区和第二漏极区，以形成pMOS。
本发明一个实施例还提供一种GAA CMOS结构的制备方法，所述制备方法包括：
选取半导体衬底；
在所述半导体衬底上形成第一材料叠层和第二材料叠层；
刻蚀所述第一材料叠层和所述第二材料叠层以形成第一纳米体结构和第二纳米体结构，其中，所述第一纳米体结构和所述第二纳米体结构具有相同的导电类型；
环绕所述第一纳米体结构和所述第二纳米体结构形成栅介质层和相同功函数的第一栅电极和第二栅电极。
本发明的有益效果：
本发明的nMOS和pMOS在相同导电类型(优选相同掺杂浓度)的半导体材料上制备，这样便不需要分别制备n型区或者p型区。同时，由于本发明的nMOS和pMOS的栅电极所采取的材料为相同功函数的导电材料(优选为同一导电材料)，由此不需要分别制备nMOS的栅电极和pMOS的栅电极，所以本发明减少了制备CMOS的工艺步骤，缩减了工艺过程，从而可降低制备成本和工艺难度，由此也可提升CMOS及其集成电路的电学特性以及可靠性。
以下将结合附图及实施例对本发明做进一步详细说明。
附图说明
图1是本发明实施例提供的一种CMOS的原理示意图；
图2是本发明实施例提供的一种FinFET CMOS的结构示意图；
图3是本发明实施例提供的一种基于体硅衬底的FinFET CMOS的结构示意图；
图4a～图4f是本发明实施例提供的一种基于体硅衬底的FinFET CMOS结构的制备过程示意图；
图5是本发明实施例提供的另一种基于体硅衬底的FinFET CMOS的结构示意图；
图6a～图6f是本发明实施例提供的另一种基于体硅衬底的FinFET CMOS结构的制备过程示意图；
图7是本发明实施例提供的一种基于SOI衬底的FinFET CMOS的结构示意图；
图8a～图8e是本发明实施例提供的一种基于SOI衬底的FinFET CMOS结构的制备过程示意图；
图9是本发明实施例提供的另一种基于SOI衬底的FinFET CMOS的结构示意图；
图10a～图10e是本发明实施例提供的另一种基于SOI衬底的FinFET CMOS结构的制备过程示意图；
图11是本发明实施例提供的一种基于p型半导体衬底的FinFET CMOS的结构示意图；
图12a～图12g是本发明实施例提供的一种基于p型半导体衬底的FinFET CMOS结构的制备过程示意图；
图13是本发明实施例提供的一种基于n型半导体衬底的FinFET CMOS的结构示意图；
图14a～图14g是本发明实施例提供的一种基于n型半导体衬底的FinFET CMOS结构的制备过程示意图；
图15是本发明实施例提供的一种FD CMOS的结构示意图；
图16a～图16f是本发明实施例提供的一种FD CMOS的制备过程示意图；
图17是本发明实施例提供的一种GAA CMOS结构的示意图；
图18是本发明实施例提供的另一种GAA CMOS结构的示意图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
为了更好地理解本方案，在介绍本发明所提供的CMOS结构之前，对FinFET CMOS(鳍式场效应晶体管CMOS)、FD-SOI CMOS(全耗尽绝缘体上硅CMOS)和GAA CMOS(环栅CMOS)进行说明。
CMOS是将nMOS的漏极与pMOS的漏极连接在一起、nMOS的栅极与pMOS的栅极连接在一起的结构。而nMOS和pMOS都由被称为源极区、漏极区和栅极区或称为沟道区的三个区域构成，相应的在源极区、漏极区和栅极区各有一个电极，分别被称为源(电)极、漏(电)极和栅(电)极。nMOS的沟道区为p型半导体材料，源极区和漏极区为n型半导体材料。pMOS的沟道区则为n型半导体材料，源极区和漏极区则为p型半导体材料。同时，nMOS和pMOS的栅电极为不同功函数的导电材料。以上表明，对CMOS而言，存在二方面被关注的问题，即：
1.nMOS的沟道区和pMOS的沟道区需要采用不同导电类型的半导体材料；
2.nMOS的栅电极和pMOS的栅电极需要采用不同功函数的导电材料。
对FinFET CMOS，衬底可以是体Si，可以是SOI，与常规CMOS的区别仅在于nMOS和pMOS是三维体结构，且nMOS和pMOS的三维体结构为鳍(Fin)型，故被称为鳍式场效应晶体管，其余特征与常规CMOS相同，其同样存在二方面所关注的问题：
1.在FinFET CMOS中，nMOS的鳍和pMOS的鳍需要采用不同导电类型的半导体材料；
2.在FinFET CMOS中，nMOS的栅电极和pMOS的栅电极需要采用不同功函数的导电材料。
对FD CMOS，衬底是SOI，与常规CMOS的区别在于nMOS和pMOS制备在SOI的顶层半导体薄层材料上，且nMOS和pMOS的沟道区在无偏置电压时全耗尽，但与常规CMOS一样，FD CMOS同样存在二方面所关注的问题：
1.FD CMOS中，nMOS的沟道区和pMOS的沟道区需要采用不同导电类型的半导体材料；
2.FD CMOS中，nMOS的栅电极和pMOS的栅电极需要采用不同功函数的导电材料。
对于GAA CMOS而言，其衬底可以是体Si，也可以是SOI。GAA(gate-all-around)，被称为环栅，或围栅，即意指栅极金属环绕MOS的沟道区，GAA的沟道区材料可以是纳米线，可以是纳米片，前者被称为环栅纳米线CMOS，后者被称为环栅纳米片CMOS。环栅纳米线/片CMOS可以是分布在水平面的单层，可以是三维的多层。当为多层时，即被称为堆叠环栅纳米线/片CMOS。在当前，无论是单层环栅纳米线/片CMOS，还是堆叠环栅纳米线/片CMOS，也都与常规CMOS一样，存在下述二方面的问题：
1.环栅nMOS的纳米线/片和环栅pMOS的纳米线/片需要不同导电类型的半导体材料；
2.环栅纳米线/片nMOS的栅电极和环栅纳米线/片pMOS的栅电极需要不同功函数的导电材料。
由上可见，无论常规CMOS，还是FinFET CMOS、FD-SOI CMOS、GAA CMOS，都存在如上所述的二项被关注的问题，虽然它们仅是二项技术，但要实现上述二项技术却需要较繁杂的工艺过程和步骤，由此会增加工艺的难度和成本，相应的又会影响器件和电路的性能及其可靠性。
实施例一
基于上述原因，本实施例提供了一种CMOS结构，该CMOS结构包括nMOS和pMOS，nMOS包括在半导体衬底上设置的第一沟道区和第一栅电极，pMOS包括在半导体衬底上设置的第二沟道区和第二栅电极，其中，第一沟道区与第二沟道区由相同导电类型的半导体材料形成；第一栅电极与第二栅电极由相同功函数的导电材料形成。
在一个具体实施例中，第一沟道区与第二沟道区的材料为掺杂浓度相同的n型半导体材料，且nMOS的第一源极区、第一漏极区为n型掺杂，pMOS的第二源极区、第二漏极区为p型掺杂。
进一步地，若第一沟道区与第二沟道区都采用掺杂浓度相同的同一n型半导体材料制备，那么，第一栅电极和第二栅电极采用功函数在该n型半导体材料价带顶附近的同一导电材料，且所选取的第一栅电极和第二栅电极功函数要使该沟道区的n型半导体材料完全耗尽，优选地第一栅电极和第二栅电极的功函数的范围为4.6～5.1eV，具体取值以n型半导体材料的厚度和掺杂浓度等参数而定，此处不做任何限定。
在一个具体实施例中，第一沟道区与第二沟道区的材料为掺杂浓度相同的p型半导体材料，nMOS的第一源极区、第一漏极区为n型掺杂，pMOS的第二源极区、第二漏极区为p型掺杂。
进一步地，若第一沟道区与第二沟道区都采用掺杂浓度相同的同一p型半导体材料制备，那么，第一栅电极和第二栅电极采用功函数在该p型半导体材料导带底附近的同一导电材料，且所选取的第一栅电极和第二栅电极功函数要使该沟道区的p型半导体材料完全耗尽，优选地第一栅电极和第二栅电极的功函数的范围为4.1～4.5eV，具体取值以p型半导体材料的厚度和掺杂浓度等参数而定，此处不做任何限定。
请参见图1，图1是本发明实施例提供的一种CMOS的原理示意图。通过本实施例所提供的CMOS结构和图1可知，当电源施加正电压V D，而输入端未接电压，即悬空时，nMOS和pMOS都处于截止状态，CMOS不工作。当输入端接0V时，pMOS导通，输出端高电平。之后，随输入电压由0V逐渐上升，pMOS逐渐向截止过渡，nMOS逐渐向导通过渡，在pMOS截止，nMOS导通时，输出低电平。
本实施例的nMOS和pMOS的沟道区采用同一导电类型的半导体材料制备，且为相同或相近掺杂浓度，优选相同的掺杂浓度，即nMOS的第一沟道区和pMOS的第二沟道区同在一定掺杂浓度的p型半导体上制备，或同在一定掺杂浓度的n型半导体上制备，这样便不需要专门制备n型区或者p型区，从而本实施例的CMOS结构可以省去制备n型区或者p型区的工艺过程，虽然表面上看省去的是制作n型区或者p型区的工艺，但却可以减少多次工序步骤，这对缩短工艺周期，控制工艺误差，降低芯片工艺成本，提升器件和电路的性能及可靠性等是极为有益和有利的，而该问题恰是业界所重视和长期关注的核心问题之一。同时，又由于本实施例的nMOS和pMOS的栅电极所采用的材料为相同功函数的导电材料，优选为同一导电材料，当采用同一导电材料作为栅电极时，则不需要分开制备nMOS的栅电极和pMOS的栅电极，据此，虽然是缩减了制备栅电极的关键工艺，但同样可减少多次工艺步骤，缩短工艺周期，控制工艺误差，降低芯片工艺成本。另外，CMOS的栅电极区域是其敏感区域，栅电极控制CMOS的性能，且栅电极制备的工艺过程会影响CMOS的性能，因此，nMOS的栅电极和pMOS的栅电极采用功函数相同的同一种导电材料，且只需制备一次，有利于提升CMOS电路的性能及可靠性。
综上所述，本实施例通过上述方式简化了CMOS的两项关键工艺技术，减少了制备CMOS的工 艺步骤，缩减了工艺过程、工艺难度，从而可以降低制备成本，由此还可以提升CMOS及其集成电路的成品率、性能与可靠性。另外，本实施例所提供的CMOS结构还可增加阈值电压调控维度，提升开关速度。
需要说明的是，本实施例的CMOS结构可以为FinFET CMOS结构、FD CMOS结构和GAA CMOS结构中的任意一种，也可以是具备类似特性的其他CMOS结构。
实施例二
请参见图2，图2是本发明实施例提供的一种FinFET CMOS的结构示意图。在实施例一的基础上，本实施例提供了一种FinFET CMOS结构，该FinFET CMOS结构包括nMOS和pMOS，nMOS包括在半导体衬底10上设置的若干第一鳍部20和第一栅电极30，pMOS包括在半导体衬底10上设置的若干第二鳍部40和第二栅电极50，其中，第一鳍部20与第二鳍部40由相同导电类型的半导体材料形成，即nMOS的第一沟道区和pMOS的第二沟道区由相同导电类型的第一鳍部20和第二鳍部40形成；第一栅电极30和第二栅电极50分别位于第一鳍部20和第二鳍部40上。需要强调的是，第一鳍部20和第二鳍部40的厚度和掺杂浓度应满足在栅电极功函数作用下完全耗尽的要求。第一栅电极30和第二栅电极50功函数要使鳍部的沟道区完全耗尽。
其中，当第一鳍部20与第二鳍部40的材料为掺杂浓度相同的n型半导体材料时，优选地第一栅电极30和第二栅电极50的功函数的范围为4.6～5.1eV。当第一鳍部20与第二鳍部40的材料为掺杂浓度相同的p型半导体材料时，优选地第一栅电极30和第二栅电极50的功函数的范围为4.1～4.5eV。栅电极功函数的具体取值以鳍的厚度和掺杂浓度等参数而定，此处不做任何限定。
在本实施例中，半导体衬底10可以为体硅衬底或者SOI衬底，因此第一鳍部20与第二鳍部40可以直接通过刻蚀体硅或者SOI的表层硅材料形成，另外，第一鳍部20和第二鳍部40的材料还可以为Ge、SiGe、Ⅲ-Ⅴ族或者SiC等，例如可以在硅材料表面外延生长的方式形成这些材料，通过刻蚀形成第一鳍部20和第二鳍部40。
本实施例的nMOS和pMOS的鳍在同一导电类型的半导体材料上制备，且为相同或相近掺杂浓度，优选相同的掺杂浓度，由此可减少多次工序步骤，这对缩短工艺周期，控制工艺误差，降低芯片工艺成本，提升器件和电路的性能及可靠性等是极为有益和有利的。同时，又由于本实施例的nMOS和pMOS的栅电极所采取的材料为相同功函数的导电材料，优选为同一导电材料，由此可减少多次工艺步骤，缩短工艺周期，控制工艺误差，降低芯片工艺成本。另外，nMOS的栅电极和pMOS的栅电极采用功函数相同的同一种导电材料，且只需制备一次，有利于提升FinFET CMOS电路的性能及可靠性。
综上所述，本实施例通过上述方式简化了FinFET CMOS的两项关键工艺技术，减少了制备FinFET CMOS的工艺步骤，缩减了工艺过程、工艺难度，从而可以降低制备成本，由此还可以提升FinFET及其集成电路的成品率、性能与可靠性。另外，本实施例所提供的FinFET CMOS结构还可增加阈值电压调控维度，及提升开关速度。
实施例三
本实施例在实施例二的基础上，还提供一种FinFET CMOS结构的制备方法，该FinFET CMOS结构的制备方法包括：
步骤3.1、选取半导体衬底10；
步骤3.2、在半导体衬底10上形成相同导电类型的第一鳍部20和第二鳍部40；
步骤3.3、在第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层和相同功函数的第一栅电极30和第二栅电极50；
步骤3.4、对第一鳍部20制备第一源极区和第一漏极区形成nMOS；
步骤3.5、对第二鳍部40制备第二源极区和第二漏极区形成pMOS。
进一步地，在一种具体实施方式中，步骤3.2可以具体包括：刻蚀半导体衬底10，在半导体衬底10上形成相同导电类型的第一鳍部20和第二鳍部40。
具体地，可以直接通过刻蚀半导体衬底10，从而在掺杂浓度相同或相近的同一导电类型的半导体材料上形成第一鳍部20和第二鳍部40，如半导体衬底10为体硅衬底或者SOI衬底,。
进一步地，在另一种具体实施方式中，步骤3.2还可以具体包括：在半导体衬底10上形成鳍材料层；刻蚀鳍材料层，在半导体衬底10上形成第一鳍部20和第二鳍部40。
具体地，通过在半导体衬底10上形成一层用于形成第一鳍部20和第二鳍部40的鳍材料层，然后根据第一鳍部20和第二鳍部40的结构刻蚀鳍材料层，从而可以在半导体衬底10上形成第一鳍部20和第二鳍部40，鳍材料层例如可以为Si、Ge、SiGe、Ⅲ-Ⅴ族或者SiC等。
进一步地，在一种具体实施方式中，步骤3.3可以具体包括：在第一鳍部20和第二鳍部40的顶部和侧壁表面生长介质材料以形成栅介质层；在栅介质层表面生长同一栅电极材料以形成具有相同功函数的第一栅电极30和第二栅电极50。
具体地，在形成第一鳍部20和第二鳍部40之后，首先需要在所有的第一鳍部20和第二鳍部40顶部和侧壁表面形成栅介质层，然后可以在栅介质层上形成一层用于形成第一栅电极30和第二栅电极50的导电材料，第一鳍部20上对应的为第一栅电极30，第二鳍部40上对应的为第二栅电极50。
需要说明的是，本实施例的制备方法的步骤顺序并不是唯一实现实施例一所提供的FinFET CMOS结构的顺序，其仅是为了便于说明本实施例的制备方法，例如在制备过程中还可以先制备第一源极区、第一漏极区、第二源极区和第二漏极区，再制备栅介质层、第一栅电极和第二栅电极，因此并不能以本实施例的步骤顺序进行限定。
应该明白的是，本实施例制备FinFET CMOS所采取的其他具体工艺手段可以通过现有技术实现，在此不再赘述。
本发明所涉及工艺技术与现有CMOS工艺技术兼容，所以本实施例未给出了全部工艺过程，且部分工艺过程可调换顺序。
实施例四
请参见图3，图3是本发明实施例提供的一种基于体硅衬底的FinFET CMOS的结构示意图。本实施例在实施例二和实施例三的基础上还提供一种在体硅上制备的FinFET CMOS结构，即本实施例的半导体衬底10为体硅，则该FinFET CMOS结构的nMOS包括在体硅上设置的若干第一鳍部20，pMOS包括在体硅上设置的若干第二鳍部40，该体硅包括Si衬底层101和位于Si衬底层之上的Si外延层，Si衬底层101为p型材料，Si外延层为n型材料，第一鳍部20和第二鳍部40是利用位于表层的Si外延层制成，因此第一鳍部20和第二鳍部40的材料为掺杂浓度相同的n型半导体材料；然后在体硅上除形成第一鳍部20和第二鳍部40的部位以外的部分设置有一层第一绝缘层60，且在第一鳍部20上设置有第一栅电极30、在第二鳍部40上设置有第二栅电极50，第一栅电极30和第二栅电极50采用同一功函数的导电材料，在栅电极和鳍部之间设置栅介质层，与栅介质层接触的鳍部部分为沟道区，位于沟道区两端的分别为源极区、漏极区，其中，nMOS的第一源极区和第一漏极区之间的鳍部部分为第一沟道区，pMOS的第二源极区、第二漏极区之间的鳍部部分为第二沟道区。
另外，对于鳍部为由n型半导体材料形成的FinFET CMOS结构，在pMOS的第二鳍部40下方还可以设置一层与第二鳍部40掺杂浓度相同的n型半导体层70，这样有利于FinFET CMOS的设计和性能。
进一步地，pMOS的第二鳍部40和nMOS的第一鳍部20可选择(100)面或(110)晶面，或pMOS的第二鳍部40和nMOS的第一鳍部20分别选择(110)和(100)晶面。
请参见图4a～图4f，图4a～图4f是本发明实施例提供的一种基于体硅衬底的FinFET CMOS结构的制备过程示意图，本实施例基于上述内容，还提供一种在体硅上制备FinFET CMOS结构的方法，该方法包括：
步骤4.1、提供体硅。
请参见图4a，体硅包括Si衬底层101和位于Si衬底层101之上的Si外延层102，Si衬底层为p型材料，Si外延层为n型材料。
步骤4.2、请参见图4b，刻蚀体硅的Si外延层102以形成第一鳍部20和第二鳍部40，且在pMOS的所有第二鳍部40的下方应保留一定厚度的Si外延层102，并将所保留的Si外延层102作为n型半导体层70，在刻蚀第一鳍部20时，可以刻蚀至Si衬底层101，从而在nMOS的每个第一鳍部20下部保留一与第一鳍部20的预设横截面的形状和大小相同或相近的第一过渡结构80，第一过渡结构80的材料为p型半导体材料，其中，预设横截面为图4b所示的水平方向的横截面，这样有利于FinFET CMOS的设计和性能。
步骤4.3、请参见图4c，在体硅上除形成第一鳍部20和第二鳍部40的部位以外的部分设置有一层第一绝缘层60，第一绝缘层60如为SiO 2或者SiN等绝缘材料。
步骤4.4、请参见图4d，在所有第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层90，其中栅介质层90的材料例如为高k介质或者SiO 2等。
步骤4.5、请参见图4e，在栅介质层90上淀积和刻蚀栅电极材料以形成第一栅电极30和第二栅电极50。
步骤4.6、请参见图4f，然后在nMOS的第一沟道区两侧通过n型掺杂或外延，形成第一源极区、第一漏极区，在pMOS的第二沟道区两侧通过p型掺杂或外延，形成第二源极区、第二漏极区，最后实现金属化连接。
实施例五
请参见图5，图5是本发明实施例提供的另一种基于体硅衬底的FinFET CMOS的结构示意图。本实施例在实施例二和实施例三的基础上提供另一种在体硅上制备的FinFET CMOS结构，该FinFET CMOS结构的nMOS包括在体硅上设置的若干第一鳍部20，pMOS包括在体硅上设置的若干第二鳍 部40，该体硅的Si衬底层101为n型材料，Si外延层为p型材料，第一鳍部20和第二鳍部40的材料为掺杂浓度相同的p型半导体材料；然后在体硅上设置有一层第一绝缘层60，nMOS的第一栅电极30和pMOS的第二栅电极50采用同一功函数的导电材料，在栅电极和鳍部之间设置有栅介质层。
另外，在nMOS的第一鳍部20下方还可以设置有一层与第一鳍部20掺杂浓度相同的p型半导体层100，这样有利于FinFET CMOS的设计和性能。
请参见图6a～图6f，图6a～图6f是本发明实施例提供的另一种基于体硅衬底的FinFET CMOS结构的制备过程示意图，本实施例基于上述内容，还提供一种在体硅上制备FinFET CMOS结构的方法，该方法包括：
步骤5.1、提供体硅。
请参见图6a，体硅的Si衬底层101为n型材料，Si外延层102为p型材料。
步骤5.2、请参见图6b，刻蚀体硅的Si外延层102以形成第一鳍部20和第二鳍部40，且在nMOS的所有第一鳍部20的下方应保留一定厚度的Si外延层102，并将所保留的Si外延层102作为p型半导体层100，在刻蚀第二鳍部40时，可以刻蚀至Si衬底层101，从而在pMOS的每个第二鳍部40下部保留一与第二鳍部40的预设横截面的形状和大小相同或相近的第二过渡结构110，该第二过渡结构110的材料为n型半导体材料，其中，预设横截面为图6b所示的水平方向的横截面，这样有利于FinFET CMOS的设计和性能。
步骤5.3、请参见图6c，在体硅上除形成第一鳍部20和第二鳍部40的部位以外的部分设置有一层第一绝缘层60。
步骤5.4、请参见图6d，在所有第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层90。
步骤5.5、请参见图6e，在栅介质层90上淀积和刻蚀栅电极材料以形成第一栅电极30和第二栅电极50。
步骤5.6、请参见图6f，然后在nMOS的第一沟道区两侧通过n型掺杂或外延，形成第一源极区、第一漏极区，在pMOS的第二沟道区两侧通过p型掺杂或外延，形成第二源极区、第二漏极区，最后实现金属化连接。
实施例六
请参见图7，图7是本发明实施例提供的一种基于SOI衬底的FinFET CMOS的结构示意图。本实施例在实施例二和实施例三的基础上还提供一种在SOI上制备的FinFET CMOS结构，即本实施例的半导体衬底10为SOI，该FinFET CMOS的nMOS包括在SOI上设置的若干第一鳍部20，pMOS包括在SOI上设置的若干第二鳍部40，SOI包括依次层叠的衬底层103、第二绝缘层104和表层硅，该表层硅为n型材料，第一鳍部20和第二鳍部40利用表层硅制成，第一鳍部20和第二鳍部40的材料为掺杂浓度相同的n型半导体材料；且，nMOS的第一栅电极20和pMOS的第二栅电极50采用同一功函数的导电材料，在栅电极和鳍部之间还设置栅介质层。
请参见图8a～图8e，图8a～图8e是本发明实施例提供的一种基于SOI衬底的FinFET CMOS结构的制备过程示意图，本实施例基于上述内容，还提供一种在SOI上制备FinFET CMOS结构的方法，该方法包括：
步骤6.1、提供SOI。
请参见图8a，该SOI包括依次层的衬底层103、第二绝缘层104、表层硅105，表层硅105为n型材料。
步骤6.2、请参见图8b，刻蚀SOI的表层硅105以形成第一鳍部20和第二鳍部40，且在pMOS的所有第二鳍部40的下方设置有n型半导体层70。
步骤6.3、请参见图8c，在n型半导体层70上除形成第二鳍部40的部位以外的部分形成一层第一绝缘层60。
步骤6.4、在所有第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层90。
步骤6.5、请参见图8d，在栅介质层90上淀积和刻蚀栅电极材料以形成第一栅电极30和第二栅电极50。
步骤6.6、请参见图8e，然后在nMOS的第一沟道区两侧通过n型掺杂或外延，形成第一源极区、第一漏极区，在pMOS的第二沟道区两侧通过p型掺杂或外延，形成第二源极区、第二漏极区，最后实现金属化连接。
实施例七
请参见图9，图9是本发明实施例提供的另一种基于SOI衬底的FinFET CMOS的结构示意图。本实施例在实施例二和实施例三的基础上还提供另一种在SOI上制备的FinFET CMOS结构，该FinFET CMOS结构的nMOS包括在SOI上设置的若干第一鳍部20，pMOS包括在SOI上设置的若干第二鳍部40，SOI的表层硅为p型材料，第一鳍部20和第二鳍部40的材料为掺杂浓度相同的p 型半导体材料；且nMOS的第一栅电极30和pMOS的第二栅电极50采用同一功函数的导电材料，在栅电极和鳍部之间还可设置栅介质层。
另外，在nMOS的第一鳍部20下方还可以设置有一层与第一鳍部20掺杂浓度相同的p型半导体层100，在p型半导体层100上除形成第一鳍部20的部位以外的部分设置有一层第一绝缘层60。
请参见图10a～图10e，图10a～图10e是本发明实施例提供的另一种基于SOI衬底的FinFET CMOS结构的制备过程示意图，本实施例基于上述内容，还提供一种在SOI上制备FinFET CMOS结构的方法，该方法包括：
步骤7.1、提供SOI。
请参见图10a，该SOI的表层硅105为p型材料。
步骤7.2、请参见图10b，刻蚀表层硅105以形成第一鳍部20和第二鳍部40，且在nMOS的所有第一鳍部20的下方设置有p型半导体层100。
步骤7.3、请参见图10c，在p型半导体层100上除形成第一鳍部20的部位以外的部分设置有一层第一绝缘层60。
步骤7.4、在所有第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层90。
步骤7.5、请参见图10d，在栅介质层90上淀积和刻蚀栅电极材料以形成第一栅电极30和第二栅电极50。
步骤7.6、请参见图10e，在nMOS的第一沟道区两侧通过n型掺杂或外延，形成第一源极区、第一漏极区，在pMOS的第二沟道区两侧通过p型掺杂或外延，形成第二源极区、第二漏极区，最后实现金属化连接。
实施例八
请参见图11，图11是本发明实施例提供的一种基于p型半导体衬底的FinFET CMOS的结构示意图。本实施例在实施例二和实施例三的基础上还提供一种在p型半导体衬底上制备的FinFET CMOS结构，即本实施例的半导体衬底10为p型半导体衬底，且在p型半导体衬底内具有n型区106，该FinFET CMOS结构的nMOST包括在p型半导体衬底上设置的若干第一鳍部20，pMOS包括在n型区106上设置的若干第二鳍部40，在p型半导体衬底上设置有一n型外延层，第一鳍部20和第二鳍部40的材料为掺杂浓度相同的n型半导体材料；nMOS的第一栅电极30和pMOS的第二栅电极50采用同一功函数的导电材料，在栅电极和鳍部之间还设置栅介质层。
请参见图12a～图12g，图12a～图12g是本发明实施例提供的一种基于p型半导体衬底的FinFET CMOS结构的制备过程示意图，本实施例基于上述内容，还提供一种在p型半导体衬底上制备FinFET CMOS结构的方法，该方法包括：
步骤8.1、提供p型半导体衬底。
请参见图12a，半导体衬底10为p型半导体衬底，且在p型半导体衬底内设置有n型区106，如p型半导体衬底为p型Si衬底。
步骤8.2、请参见图12b，在p型半导体衬底和n型区106上制备一层n型外延层120，如n型外延层120为n型Si层。
步骤8.3、请参见图12c，刻蚀n型外延层120以形成第一鳍部20和第二鳍部40，其中，在刻蚀pMOS的第二鳍部40时，可以刻蚀至n型区106表面之下，同时所有第二鳍部40的下方仍保留有n型区106，在刻蚀第一鳍部20时，可以刻蚀至p型半导体衬底内，从而在nMOS的每个第一鳍部20下部保留一与第一鳍部20的预设横截面的形状和大小相同或相近的第一过渡结构80，第一过渡结构80的材料为p型半导体材料，其中，预设横截面为图12c所示的水平方向的横截面。
步骤8.4、请参见图12d，在除形成第一鳍部20和第二鳍部40的部位以外的部分设置有一层第一绝缘层60。
步骤8.5、请参见图12e，在所有第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层90。
步骤8.6、请参见图12f，在栅介质层90上淀积和刻蚀栅电极材料以形成第一栅电极30和第二栅电极50。
步骤8.7、请参见图12g，然后在nMOS的第一沟道区两侧通过n型掺杂或外延，形成第一源极区、第一漏极区，在pMOS的第二沟道区两侧通过p型掺杂或外延，形成第二源极区、第二漏极区，最后实现金属化连接。
实施例九
请参见图13，图13是本发明实施例提供的一种基于n型半导体衬底的FinFET CMOS的结构示意图。本实施例在实施例二和实施例三的基础上还提供一种在n型半导体衬底上制备的FinFET CMOS结构，即本实施例的半导体衬底10为n型半导体衬底，且在n型半导体衬底内具有p型区107，该FinFET CMOS结构的nMOS包括在p型区107上设置的若干第一鳍部20，pMOS包括在n型半导体衬底10上设置的若干第二鳍部40，在n型半导体衬底上设置有一p型外延层，第一鳍部 20和第二鳍部40的材料为掺杂浓度相同的p型半导体材料；nMOS的第一栅电极30和pMOS的第二栅电极50采用同一功函数的导电材料，在栅电极和鳍部之间设置栅介质层。
请参见图14a～图14g，图14a～图14g是本发明实施例提供的一种基于n型半导体衬底的FinFET CMOS结构的制备过程示意图，本实施例基于上述内容，还提供一种在n型半导体衬底上制备FinFET CMOS结构的方法，该方法包括：
步骤9.1、提供n型半导体衬底。
请参见图14a，半导体衬底10为n型半导体衬底，且在n型半导体衬底内设置有p型区107，如n型半导体衬底为n型Si衬底。
步骤9.2、请参见图14b，在n型半导体衬底和p型区107上制备一层p型外延层130，如p型外延层130为p型Si层。
步骤9.3、请参见图14c，刻蚀p型外延层130以形成第一鳍部20和第二鳍部40，其中，在刻蚀nMOS的第一鳍部20时，可以刻蚀至p型区107表面之下，同时所有第一鳍部20的下方仍保留有p型区107，在刻蚀第二鳍部40时，可以刻蚀至n型半导体衬底内，从而在pMOS的每个第二鳍部40下部保留一与第二鳍部40的预设横截面的形状和大小相同或相近的第二过渡结构110，第二过渡结构110的材料为n型半导体材料，其中，预设横截面为图14c所示的水平方向的横截面。
步骤9.4、请参见图14d，在除形成第一鳍部20和第二鳍部40的部位以外的部分设置有一层第一绝缘层60。
步骤9.5、请参见图14e，在所有第一鳍部20和第二鳍部40的顶部和侧壁表面形成栅介质层90。
步骤9.6、请参见图14f，在栅介质层90上淀积和刻蚀栅电极材料以形成第一栅电极30和第二栅电极50。
步骤9.7、请参见图14g，然后在nMOS的第一沟道区两侧通过n型掺杂或外延，形成第一源极区、第一漏极区，在pMOS的第二沟道区两侧通过p型掺杂或外延，形成第二源极区、第二漏极区，最后实现金属化连接。
实施例十
请参见图15，图15是本发明实施例提供的一种FD CMOS的结构示意图。在实施例一的基础上，本实施例提供了一种FD CMOS结构，FD CMOS结构的半导体衬底10包括依次层叠设置的衬底层、绝缘层和顶层半导体层，该FD CMOS结构的nMOS包括由半导体衬底10的顶层半导体层形成的若干第一沟道区140和设置在第一沟道区140上的第一栅电极30，pMOS包括由半导体衬底10的顶层半导体层形成的若干第二沟道区150和设置在第二沟道区150上的第二栅电极50。其中，第一沟道区140与第二沟道区150由相同导电类型的顶层半导体层材料形成；另外，第一栅电极30与第二栅电极50由相同功函数的导电材料形成。需要强调的是，顶层半导体层的厚度和掺杂浓度应满足在栅电极功函数作用下完全耗尽的要求。
其中，当第一沟道区140与第二沟道区150的材料为掺杂浓度相同的n型半导体材料时，优选地第一栅电极30和第二栅电极50的功函数的范围为4.6～5.1eV。当第一沟道区140与第二沟道区150的材料为掺杂浓度相同的p型半导体材料时，优选地第一栅电极30和第二栅电极50的功函数的范围为4.1～4.5eV。栅电极功函数的具体取值以顶层半导体层的厚度和掺杂浓度等参数而定，此处不做任何限定。
在本实施例中，半导体衬底10优选地为SOI，另外，顶层半导体层还可以为Si、SiGe、Ge、SiC、Ⅲ-Ⅳ族中的一种。
本实施例的nMOS和pMOS的沟道区在同一导电类型的顶层半导体层上制备，且为相同或相近掺杂浓度，优选相同的掺杂浓度，这样便不需要专门制备n型区或者p型区，从而本实施例的FD CMOS结构可以省去制备n型区或者p型区的工艺过程，由此可以减少多次工序步骤，这对缩短工艺周期，控制工艺误差，降低芯片工艺成本，提升器件和电路的性能及可靠性等是极为有益和有利的。同时，又由于本实施例的nMOS和pMOS的栅电极所采用的材料为相同功函数的导电材料，优选为同一导电材料，由此便不需要分开制备nMOS的栅电极和pMOS的栅电极，据此可减少多次工艺步骤，缩短工艺周期，控制工艺误差，降低芯片工艺成本。另外，nMOS的栅电极和pMOS的栅电极采用功函数相同的同一种导电材料，且只需制备一次，有利于提升FD CMOS电路的性能及可靠性。
综上所述，本实施例通过上述方式简化了FD CMOS的两项关键工艺技术，减少了制备FD CMOS的工艺步骤，缩减了工艺过程、工艺难度，从而可以降低制备成本，由此还可以提升FD CMOS及其集成电路的成品率、性能与可靠性。另外，本实施例所提供的FD CMOS结构还可增加阈值电压调控维度，提升开关速度。
需要说明的是，本实施例的FD CMOS还可以在衬底层设置一个电极，其与上面的栅电极共同控制器件的导通与截止，且可充分保障顶层半导体层的耗尽。
实施例十一
本实施例在实施例十的基础上，还提供一种FD CMOS结构的制备方法，该FD CMOS结构的制备方法包括：
步骤10.1、选取半导体衬底10，半导体衬底包括绝缘层和位于绝缘层之上的顶层半导体层，顶层半导体层为p型掺杂或n型掺杂；
步骤10.2、在顶层半导体层上形成栅介质层90和相同功函数的第一栅电极30和第二栅电极50；
步骤10.3、对顶层半导体层制备第一源极区190和第一漏极区200，以形成nMOS；
步骤10.4、对顶层半导体层制备第二源极区210和第二漏极区220，以形成pMOS。
进一步地，在一种具体实施方式中，步骤10.2可以具体包括：在顶层半导体层上生长介质材料层；在介质材料层表面生长同一栅金属材料，以形成栅介质层90和位于栅介质层90上的第一栅电极30和第二栅电极50。
具体地，首先需要在顶层半导体层上淀积一层介质材料层，该介质材料层用于形成栅介质层90，然后在该介质材料层上形成一层用于形成第一栅电极30和第二栅电极50的导电材料，然后刻蚀位于介质材料层上的导电材料和介质材料层，以形成栅介质层90和位于栅介质层90上的第一栅电极30和第二栅电极50。
进一步地，在一种具体实施方式中，步骤10.3可以具体包括：采用离子注入或扩散方法对nMOS区域的顶层半导体层进行n型掺杂，以形成第一源极区190和第一漏极区200。
进一步地，在一种具体实施方式中，步骤10.4可以具体包括：采用离子注入或扩散方法对pMOS区域的顶层半导体层进行p型掺杂，以形成第二源极区210和第二漏极区220。
需要说明的是，本实施例的制备方法的步骤顺序并不是唯一实现实施例一所提供的FD CMOS结构的顺序，其仅是为了便于说明本实施例的制备方法，例如在制备过程中还可以先制备第二源极区和第二漏极区，再制备第一源极区和第一漏极区，因此并不能以本实施例的步骤顺序进行限定。
应该明白的是，本实施例制备FD CMOS所采取的其他具体工艺手段可以通过现有技术实现，在此不再赘述。
本发明所涉及工艺技术与现有CMOS工艺技术兼容，所以本实施例未给出全部工艺过程，且部分工艺过程可调换顺序。
实施例十二
请参见图16a～图16f，图16a～图16f是本发明实施例提供的一种FD CMOS的制备过程示意图。本实施例在实施例十一的基础上，还提供一种FD CMOS的具体制备方法，该制备方法包括：
步骤11.1、请参见图16a，提供半导体衬底10。
具体地，半导体衬底10为SOI，SOI的顶层Si可以是n型半导体，也可以是p型半导体，在SOI顶层Si为n型Si或者顶层Si为p型Si时，其制备CMOS的工艺步骤和过程相同，工艺的差别仅在后续制备栅电极时所采用的导电材料不同。顶层Si的厚度、掺杂浓度按设计要求制备。
步骤11.2、请参见图16b，其中，图16b为正视图，形成浅沟槽隔离160(STI，Shallow trench isolation)。
具体地，根据nMOS和pMOS的平面布局设计，刻蚀隔离槽，隔离槽内淀积介质，介质与顶层Si表面平齐，以形成浅沟槽隔离160。浅沟槽隔离160的作用是实现nMOS与pMOS的电学隔离。
步骤11.3、淀积栅介质层和制备栅电极。
具体地，请参见图16c，首先在顶层Si上淀介质材料层，然后在介质材料层上淀积栅金属层，栅金属的功函数视SOI顶层Si导电类型而定。栅金属功函数的具体值，基于电学参数和顶层Si物理参数优化确定。最后再刻蚀栅金属层和介质材料层，形成nMOS与pMOS的栅介质层90以及位于栅介质层90之上的第一栅电极30和第二栅电极50。
步骤11.4、形成LDD(Lightly doped drain implants process，轻掺杂漏注入)。
具体地，因为隔离区内的器件结构是完全等同的，因此首先需要确定哪些作为nMOS,哪些作为pMOS，然后依据顶层Si导电类型，确定需要进行LDD的器件，其中，如果顶层Si是n型半导体，则仅对pMOS形成p型LDD170，例如图16d；如果顶层Si是p型半导体，则仅对nMOS形成n型LDD。
步骤11.5、形成侧墙介质和形成源极区、漏极区。
具体地，请参见图16e，首先在第一栅电极30和第二栅电极50的侧壁形成侧墙介质180，然后采用离子注入或扩散方法对nMOS区域的顶层半导体层进行n型掺杂，以制备n型掺杂的第一源极区190和第一漏极区200，采用离子注入或扩散方法对pMOS区域的顶层半导体层进行p型掺杂，以制备p型掺杂的第二源极区210和第二漏极区220，其中，第一沟道区140位于第一源极区190和第一漏极区200之间，第二沟道区150位于第二源极区210和第二漏极区220之间。
步骤11.6、形成金属电极。
具体地，请参见图16f，在nMOS和pMOS的源极区、漏极区和栅电极区，通过淀积介质和金 属以及刻蚀，形成欧姆接触的金属电极230。
步骤11.7、FD SOI CMOS金属化。
具体地，通过金属化连接，实现FD SOI CMOS。形成CMOS的金属化过程和方法与常规CMOS工艺相同，在此不再赘述。
实施例十三
请参见图17，图17是本发明实施例提供的一种GAA CMOS结构的示意图，其中，图17(1)、图17(3)为侧视图的剖面图，图17(2)为正视图的局部剖面图。在实施例一的基础上，本实施例提供了一种GAA CMOS结构，该GAA CMOS结构的nMOS包括在半导体衬底10上设置的第一纳米体结构240和环绕第一纳米体结构240的第一栅电极30，pMOS包括在半导体衬底10上设置的第二纳米体结构250和环绕第二纳米体结构250的第二栅电极50，其中，第一纳米体结构240与第二纳米体结构250由相同导电类型的半导体材料形成；第一栅电极30与第二栅电极50由相同功函数的导电材料形成。需要强调的是，第一纳米体结构240和第二纳米体结构250的厚度和掺杂浓度应满足在栅电极功函数作用下完全耗尽的要求。
其中，当第一纳米体结构240与第二纳米体结构250的材料为掺杂浓度相同的n型半导体材料时，优选地第一栅电极30和第二栅电极50的功函数的范围为4.6～5.1eV。当第一纳米体结构240与第二纳米体结构250的材料为掺杂浓度相同的p型半导体材料时，优选地第一栅电极30和第二栅电极50的功函数的范围为4.1～4.5eV。栅电极功函数的具体取值以纳米体结构的厚度和掺杂浓度等参数而定，此处不做任何限定。
在本实施例中，第一纳米体结构240包括至少一个第一纳米体，第二纳米体结构包括至少一个第二纳米体，其中，在第一纳米体和第二纳米体的数量大于或者等于两个时，其有两种排列方式，一种为多个第一纳米体或者多个第二纳米体在竖直方向呈堆叠方式排列，其中竖直方向如图17所示，另一种为多个第一纳米体或者多个第二纳米体在水平方向处于同一层排列。
另外，第一纳米体与第二纳米体可以处于同一层，也可以处于相邻层，当处于同一层时，第一纳米体与第二纳米体所采用的半导体材料相同，例如均为Si、Ge或者SiGe等，当处于相邻层时，第一纳米体与第二纳米体所采用的半导体材料不同，例如第一纳米体的材料为Si，第二纳米体的材料为Ge或者SiGe。例如，请参见图17和图18，图17为第一纳米体与第二纳米体处于同一层的结构，图18为第一纳米体与第二纳米体处于相邻层的结构，其中，图18(1)、图18(3)为侧视图的剖面图，图18(2)为正视图的局部剖面图。
进一步地，第一纳米体与第二纳米体为纳米片或者纳米线。纳米片或者纳米线可以是Si、SiGe、Ge、SiC、Ⅲ-Ⅳ族等半导体材料。
在本实施例中，半导体衬底10可以为体硅衬底或者SOI衬底。半导体衬底10还可以为Si、SiGe、Ge、SiC、Ⅲ-Ⅳ族等半导体材料。
本实施例的nMOS的第一纳米体结构和pMOS的第二纳米体结构采用相同导电类型的半导体材料制备，且为相同或相近掺杂浓度，优选相同的掺杂浓度，从而本实施例的GAA CMOS可以省去分别制备不同导电类型的半导体材料的工艺过程，由此可减少多次工序步骤，这对缩短工艺周期，控制工艺误差，降低芯片工艺成本，提升器件和电路的性能及可靠性等是极为有益和有利的。同时，又由于本实施例的nMOS和pMOS的栅电极所采取的材料为相同功函数的导电材料，优选为同一导电材料，由此便不需要分开制备nMOS的栅电极和pMOS的栅电极，据此，虽然是缩减了制备栅电极的关键工艺，但同样可减少多次工艺步骤，缩短工艺周期，控制工艺误差，降低芯片工艺成本。另外，nMOS的栅电极和pMOS的栅电极采用功函数相同的同一种导电材料，且只需制备一次，有利于提升GAA CMOS电路的性能及可靠性。
综上所述，本实施例通过上述方式简化了GAA CMOS的两项关键工艺技术，减少了制备GAA CMOS的工艺步骤，缩减了工艺过程、工艺难度，从而可以降低制备成本，由此还可以提升GAA CMOS及其集成电路的成品率、性能与可靠性。另外，本实施例所提供的GAA CMOS结构还可增加阈值电压调控维度和提升开关速度。
实施例十四
请继续参见图17和图18，本实施例在实施例十三的基础上，还提供一种GAA CMOS结构的制备方法，该GAA CMOS结构的制备方法包括：
步骤12.1、选取半导体衬底10；
步骤12.2、在半导体衬底10上形成第一材料叠层和第二材料叠层；
步骤12.3、刻蚀第一材料叠层的牺牲层、第二材料叠层的牺牲层对应形成在两端设置有第一源极区190和第一漏极区200的第一纳米体结构240、在两端设置有第二源极区210和第二漏极区220的第二纳米体结构250；
步骤12.4、环绕第一纳米体结构240和第二纳米体结构250形成栅介质层和相同功函数的第一栅 电极30和第二栅电极50，以形成nMOS和pMOS，其中，第一纳米体结构和第二纳米体结构具有相同的导电类型。
12.5金属化。
淀积金属，实现金属化连接，如图17和图18所示，形成GAA CMOS。
进一步地，在一种具体实施方式中，步骤12.2可以具体包括：
步骤12.21、在半导体衬底10上形成交替层叠设置的第一材料层和第二材料层；
步骤12.22、刻蚀层叠设置的第一材料层和第二材料层形成第一材料叠层和第二材料叠层。
具体地，首先在半导体衬底10上依次形成层叠设置的第一材料层和第二材料层，之后刻蚀层叠设置的第一材料层和第二材料层，从而形成用于制备第一纳米体结构240的第一材料叠层和用于制备第二纳米体结构250的第二材料叠层。
进一步地，步骤12.21可以具体包括：
在半导体衬底10上生长第一材料层和第二材料层时，结合原位掺杂方法形成具有相同导电类型的交替层叠设置的第一材料层和第二材料层。
进一步地，在一种具体实施方式中，步骤12.3可以具体包括：
步骤12.31、在第一材料叠层两端制备第一源极区190和第一漏极区200、在第二材料叠层两端制备第二源极区210和第二漏极区220；
步骤12.32、刻蚀第一材料叠层的牺牲层形成第一纳米体结构240和刻蚀第二材料叠层的牺牲层形成第二纳米体结构250。
其中，牺牲层即为需要去除掉的材料层，当刻蚀掉第一材料叠层的第一材料层和第二材料叠层的第一材料层可以形成纳米片或者纳米线处于同一层的第一纳米体结构240和第二纳米体结构250，当刻蚀掉第一材料叠层的第一材料层和第二材料叠层的第二材料层可以形成纳米片或者纳米线处于相邻层的第一纳米体结构240和第二纳米体结构250。
进一步地，在一种具体实施方式中，步骤12.4可以具体包括：
步骤12.41、环绕第一纳米体结构240和第二纳米体结构250生长介质材料以形成栅介质层；
步骤12.42、在栅介质层表面生长同一栅电极材料，以形成具有相同功函数的第一栅电极30和第二栅电极50。
需要说明的是，本实施例的制备方法的步骤顺序并不是唯一实现实施例一所提供的GAA CMOS结构的顺序，其仅是为了便于说明本实施例的制备方法，例如在制备过程中可以先制备第一源极区、第一漏极区，再制备第二源极区和第二漏极区，也可以先制备第二源极区和第二漏极区，再制备第一源极区、第一漏极区。
应该明白的是，本实施例制备GAA CMOS所采取的其他具体工艺手段可以通过现有技术实现，在此不再赘述。
本发明所涉及工艺技术与现有CMOS工艺技术兼容，所以本实施例未给出全部工艺过程，且部分工艺过程可调换顺序。
在本发明的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特数据点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特数据点可以在任何的一个或多个实施例或示例中以合适的方式结合。此外，本领域的技术人员可以将本说明书中描述的不同实施例或示例进行接合和组合。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (11)

  1. 一种CMOS结构，包括nMOS和pMOS，其特征在于，所述nMOS包括在半导体衬底上设置的第一沟道区和第一栅电极，所述pMOS包括在所述半导体衬底上设置的第二沟道区和第二栅电极，其中，
    所述第一沟道区与所述第二沟道区由相同导电类型的半导体材料形成；
    所述第一栅电极与所述第二栅电极由相同功函数的导电材料形成。
  2. 根据权利要求1所述的CMOS结构，其特征在于，所述CMOS结构为FinFET CMOS结构，其中，
    所述第一沟道区在第一鳍部中形成，所述第二沟道区在第二鳍部中形成，所述第一鳍部和所述第二鳍部由相同导电类型的半导体材料形成；
    所述第一栅电极位于所述第一鳍部上，所述第二栅电极位于所述第二鳍部上。
  3. 根据权利要求1所述的CMOS结构，其特征在于，所述CMOS结构为FD CMOS结构，其中，
    所述第一沟道区和所述第二沟道区形成于半导体衬底的顶部半导体层中，所述半导体衬底包括绝缘层和顶部半导体层且所述顶部半导体层位于所述绝缘层上；
    所述第一栅电极位于所述第一沟道区上，所述第二栅电极位于所述第二沟道区上。
  4. 根据权利要求1所述的CMOS结构，其特征在于，所述CMOS结构为GAA CMOS结构，其中，
    所述第一沟道区在第一纳米体结构中形成，所述第二沟道区在第二纳米体结构中形成，所述第一纳米体结构与所述第二纳米体结构由相同导电类型的半导体材料形成；
    所述第一栅电极环绕所述第一纳米体结构，所述第二栅电极环绕所述第二纳米体结构。
  5. 根据权利要求1至4任一项所述的CMOS结构，其特征在于，所述第一沟道区与所述第二沟道区的材料为掺杂浓度相同的n型半导体材料，所述nMOS的第一源极区、第一漏极区为n型掺杂，所述pMOS的第二源极区、第二漏极区为p型掺杂。
  6. 根据权利要求5所述的CMOS结构，其特征在于，所述第一栅电极和所述第二栅电极的功函数的范围为4.6～5.1eV。
  7. 根据权利要求1至4任一项所述的CMOS结构，其特征在于，所述第一沟道区与所述第二沟道区的材料为掺杂浓度相同的p型半导体材料，所述nMOS的第一源极区、第一漏极区为n型掺杂，所述pMOS的第二源极区、第二漏极区为p型掺杂。
  8. 根据权利要求7所述的CMOS结构，其特征在于，所述第一栅电极和所述第二栅电极的功函数的范围为4.1～4.5eV。
  9. 一种FinFET CMOS结构的制备方法，其特征在于，所述制备方法包括：
    选取半导体衬底；
    在所述半导体衬底上形成相同导电类型的第一鳍部和第二鳍部；
    在所述第一鳍部和所述第二鳍部的顶部和侧壁表面形成栅介质层和相同功函数的第一栅电极和第二栅电极；
    对所述第一鳍部制备第一源极区和第一漏极区，以形成nMOS；
    对所述第二鳍部制备第二源极区和第二漏极区，以形成pMOS。
  10. 一种FD CMOS结构的制备方法，其特征在于，所述制备方法包括：
    选取半导体衬底，所述半导体衬底包括绝缘层和顶部半导体层且所述顶部半导体层位于所述绝缘层上，所述顶部半导体层为p型掺杂或n型掺杂；
    在所述顶部半导体层上形成栅介质层和相同功函数的第一栅电极和第二栅电极；
    对所述顶部半导体层制备第一源极区和第一漏极区，以形成nMOS；
    对所述顶部半导体层制备第二源极区和第二漏极区，以形成pMOS。
  11. 一种GAA CMOS结构的制备方法，其特征在于，所述制备方法包括：
    选取半导体衬底；
    在所述半导体衬底上形成第一材料叠层和第二材料叠层；
    刻蚀所述第一材料叠层和所述第二材料叠层以形成第一纳米体结构和第二纳米体结构，其中，所述第一纳米体结构和所述第二纳米体结构具有相同的导电类型；
    环绕所述第一纳米体结构和所述第二纳米体结构形成栅介质层和相同功函数的第一栅电极和第二栅电极。
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