WO2022052224A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2022052224A1
WO2022052224A1 PCT/CN2020/122857 CN2020122857W WO2022052224A1 WO 2022052224 A1 WO2022052224 A1 WO 2022052224A1 CN 2020122857 W CN2020122857 W CN 2020122857W WO 2022052224 A1 WO2022052224 A1 WO 2022052224A1
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Prior art keywords
electrode
pixel electrode
thin film
film transistor
base substrate
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Ceased
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PCT/CN2020/122857
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English (en)
French (fr)
Inventor
张舰
刘超凡
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/056,760 priority Critical patent/US12080723B2/en
Publication of WO2022052224A1 publication Critical patent/WO2022052224A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof.
  • the curvature of the curved panel is designed to be substantially the same as the curvature of the retina of the human eye. Therefore, compared with the flat panel, the curved panel not only has a larger display area, but also has a sense of presence of the picture, which makes people have a more comfortable viewing feeling.
  • the traditional manufacturing method of the curved panel includes: arranging the red/green/blue resist layer and spacer (Photo Spacer, PS) on the color filter (Color Filter, CF) substrate; Transistor, TFT) array substrates are arranged opposite to form a panel; and the panel is bent to form a curved panel.
  • the radius of curvature of the CF substrate is smaller than that of the TFT array substrate, so the red/green/blue resistive layers and spacers on the CF substrate are prone to displacement, which in turn is prone to cause the thickness of the liquid crystal cell (Liquid Crystal Cell Gap) ) unevenness and uneven color-Mix.
  • the current method generally disposes the red/green/blue resist layers and spacers on the TFT array substrate, that is, the POA (Photo Spacer on Array) technology, to avoid the thickness of the liquid crystal cell (Liquid Crystal Cell Gap) uneven and color mixing (color-Mix) uneven.
  • the POA Photo Spacer on Array
  • a polymer stabilized vertical alignment (polymer) with 8 domains and 3 transistors (3T_8domain) is used.
  • sustained vertical alignment, PSVA) pixels are gradually applied to large panels.
  • the spacer 501 in a pixel of an array substrate 500 using POA technology and PSVA pixels, the spacer 501 usually covers and/or is adjacent to a part of the connection line 511 and a part of the connection part 512 of the main pixel electrode 510 share.
  • the color resist layer 502 is prone to cracks 503 due to abnormal film formation.
  • the external force F will be transmitted to the lower color resist layer 502 through the spacer 501 , so that the crack 503 expands below the connecting wire 511 , and then the connecting wire 511 is peeled off and bent.
  • the present disclosure provides the following solutions.
  • the present disclosure provides an array substrate including a base substrate, a pixel unit and a spacer.
  • the pixel unit is disposed on the base substrate, and includes a master pixel electrode, a slave pixel electrode, and a first thin film transistor disposed between the master pixel electrode and the slave pixel electrode.
  • the main pixel electrode includes a first trunk electrode, a plurality of first branch electrodes, and a plurality of first connection lines.
  • the first trunk electrode includes intersecting first strip electrodes and second strip electrodes.
  • the first branch electrode extends diagonally from the first trunk electrode.
  • Each first connection line extends from the corresponding first branch electrode and is electrically connected to the first thin film transistor.
  • the spacer is disposed on the pixel unit and between the master pixel electrode and the slave pixel electrode. The projection of the spacer on the base substrate does not overlap with the projection of the first connection line on the base substrate, and the two projections are in a direction parallel to the first strip electrode and do not overlap in the direction parallel to the second strip electrode
  • the projection of the spacer on the base substrate and the projection of the first connection line on the base substrate are separated by a second distance in a direction parallel to the first strip electrode. a distance, and a second distance in a direction parallel to the second strip electrodes.
  • the main pixel electrode further includes a U-shaped first frame electrode.
  • One of the first connection lines extends from one end of the first frame electrode and is electrically connected to the first thin film transistor.
  • the main pixel electrode further includes a first connection portion connected to the first connection line.
  • the first thin film transistor includes a first drain and a first drain extension extending from the first drain.
  • the first connection part is electrically connected to the first drain extension part through the first through hole, so that the first connection line is electrically connected to the first thin film transistor.
  • the pixel unit further includes a second thin film transistor disposed between the master pixel electrode and the slave pixel electrode.
  • the slave pixel electrode includes a second trunk electrode, a plurality of second branch electrodes, and a plurality of second connection lines.
  • the second trunk electrode includes intersecting third strip electrodes and fourth strip electrodes.
  • the third strip electrodes are parallel to the first strip electrodes.
  • the second branch electrodes extend diagonally from the second trunk electrode.
  • Each second connection line extends from the corresponding second branch electrode and is electrically connected to the second thin film transistor.
  • the projection of the spacer on the base substrate does not overlap with the projection of the second connection line on the base substrate, and the two projections are in a direction parallel to the third strip electrode and do not overlap in the direction parallel to the fourth strip electrode.
  • the projection of the spacer on the base substrate and the projection of the second connection line on the base substrate are separated by a second distance in a direction parallel to the third strip-shaped electrode. three distances, and a fourth distance in a direction parallel to the fourth strip electrodes.
  • the slave pixel electrode further includes a U-shaped second frame electrode.
  • One of the second connection lines extends from one end of the second frame electrode and is electrically connected to the second thin film transistor.
  • the slave pixel electrode further includes a second connection portion connected to the second connection line.
  • the second thin film transistor includes a second drain and a second drain extension extending from the second drain.
  • the second connection part is electrically connected to the second drain extension part through the second through hole, so that the second connection line is electrically connected to the second thin film transistor.
  • the present disclosure also provides a method for manufacturing an array substrate, which includes providing a base substrate, disposing pixel units on the base substrate, and disposing spacers on the pixel units.
  • the pixel unit includes a master pixel electrode, a slave pixel electrode, and a first thin film transistor disposed between the master pixel electrode and the slave pixel electrode.
  • the main pixel electrode includes a first trunk electrode, a plurality of first branch electrodes, and a plurality of first connection lines.
  • the first trunk electrode includes intersecting first strip electrodes and second strip electrodes.
  • the first branch electrode extends diagonally from the first trunk electrode.
  • Each of the first connection lines extends from the corresponding first branch electrode and is electrically connected to the first thin film transistor.
  • the spacer is disposed on the pixel unit and between the master pixel electrode and the slave pixel electrode.
  • the projection of the spacer on the base substrate does not overlap with the projection of the first connection line on the base substrate, and the two projections are in a direction parallel to the first strip electrode and do not overlap in the direction parallel to the second strip electrodes.
  • the projection of the spacer on the base substrate and the projection of the first connection line on the base substrate are separated by a second distance in a direction parallel to the first strip electrode. a distance, and a second distance in a direction parallel to the second strip electrodes.
  • the main pixel electrode further includes a U-shaped first frame electrode.
  • One of the first connection lines extends from one end of the first frame electrode and is electrically connected to the first thin film transistor.
  • the main pixel electrode further includes a first connection portion connected to the first connection line.
  • the first thin film transistor includes a first drain and a first drain extension extending from the first drain.
  • the first connection part is electrically connected to the first drain extension part through the first through hole, so that the first connection line is electrically connected to the first thin film transistor.
  • the pixel unit further includes a second thin film transistor disposed between the master pixel electrode and the slave pixel electrode.
  • the slave pixel electrode includes a second trunk electrode, a plurality of second branch electrodes, and a plurality of second connection lines.
  • the second trunk electrode includes intersecting third strip electrodes and fourth strip electrodes.
  • the third strip electrodes are parallel to the first strip electrodes.
  • the second branch electrodes extend diagonally from the second trunk electrode.
  • Each second connection line extends from the corresponding second branch electrode and is electrically connected to the second thin film transistor.
  • the projection of the spacer on the base substrate does not overlap with the projection of the second connection line on the base substrate, and the two projections are in a direction parallel to the third strip electrode and do not overlap in the direction parallel to the fourth strip electrode.
  • the projection of the spacer on the base substrate and the projection of the second connection line on the base substrate are separated by a second distance in a direction parallel to the third strip-shaped electrode. three distances, and a fourth distance in a direction parallel to the fourth strip electrodes.
  • the slave pixel electrode further includes a U-shaped second frame electrode.
  • One of the second connection lines extends from one end of the second frame electrode and is electrically connected to the second thin film transistor.
  • the slave pixel electrode further includes a second connection portion connected to the second connection line.
  • the second thin film transistor includes a second drain and a second drain extension extending from the second drain.
  • the second connection part is electrically connected to the second drain extension part through the second through hole, so that the second connection line is electrically connected to the second thin film transistor.
  • the spacer is connected to the main pixel electrode and/or the sub-pixel electrode.
  • the projections of the lines on the base substrate do not overlap, and also do not overlap in the direction parallel to the first/third strip electrodes and in the direction parallel to the second/fourth strip electrodes.
  • the projection of the spacer on the base substrate and the projection of the main pixel electrode and/or the connecting line of the slave pixel electrode on the base substrate are in a direction parallel to the first/third strip electrodes and parallel to the direction of the first/third strip electrodes.
  • the distances in the direction of the second/fourth strip electrodes are all greater than 0 ⁇ m. Thereby, it is difficult for the external force to propagate the crack of the color resist layer to the lower part of the connecting line far away from the spacer through the spacer, thereby preventing the connecting line from breaking. Furthermore, by designing the connection lines of the main pixel electrode and/or the sub-pixel electrode into multiple pieces, when one or two connection lines are broken, the signal can still be transmitted to the main pixel electrode and/or through the other unbroken connection lines. or from pixel electrodes. Therefore, the present invention can effectively avoid poor display of the array substrate.
  • FIG. 1 is a partial schematic diagram of an array substrate in the prior art.
  • FIG. 2A to 2C are schematic cross-sectional views of the array substrate of FIG. 1 along the line A-A, showing a process in which the cracks in the color resist layer gradually expand under the continuous action of external force, causing the connecting lines to bend and then break.
  • FIG. 3 is an electron microscope cross-sectional view of the array substrate of FIG. 1 taken along the line A-A, showing that the connecting lines are broken due to cracks in the color resist layer.
  • FIG. 4 is a schematic diagram of an array substrate according to an embodiment of the disclosure.
  • FIG. 5 is a partial enlarged schematic view of the array substrate of FIG. 4
  • FIG. 6 is a schematic cross-sectional view of the array substrate of FIG. 5 along the line E-E.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, “perpendicular”, “parallel”, “inner”, “outer”, “center” and “side” are based on The orientation or positional relationship shown in the drawings is only for the convenience of describing the present disclosure and simplifying the description. Furthermore, terms such as “first” and “second” are used for descriptive purposes only and should not be construed to indicate or imply relative importance. Features defined by terms such as “first” and “second” may expressly or implicitly include one or more of the stated features.
  • the present disclosure provides an array substrate 100 .
  • the array substrate 100 includes a base substrate 1 , pixel units and spacers 3 .
  • the pixel unit is disposed on the base substrate 1 , and includes a master pixel electrode 10 , a slave pixel electrode 20 , and a first thin film transistor 30 disposed between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the main pixel electrode 10 includes a first main electrode 11 , a plurality of first branch electrodes 12 , and a plurality of first connection lines 13 .
  • the number of the first connection lines 13 is four, but not limited to this.
  • the number of the first connecting lines 13 is at least two.
  • the first trunk electrode 11 includes intersecting first strip electrodes 111 and second strip electrodes 112 .
  • the first strip electrodes 111 and the second strip electrodes 112 may intersect vertically, but not limited thereto.
  • the first branch electrodes 12 extend diagonally from the first trunk electrode 11 .
  • Each first connection line 13 extends from the corresponding first branch electrode 12 and is electrically connected to the first thin film transistor 30 .
  • the main pixel electrode 10 further includes a first connection portion 15 connected to the first connection line 13 .
  • the first thin film transistor 30 includes a first drain electrode 31 , a first drain electrode extension 311 extending from the first drain electrode 31 , and a first source electrode 32 .
  • the first connection portion 15 is electrically connected to the first drain extension portion 311 through the first through hole 91 , so that the first connection line 13 is electrically connected to the first thin film transistor 30 .
  • the spacer 3 is disposed on the pixel unit and between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the projection of the spacer 3 on the base substrate 1 does not overlap with the projection of the first connection line 13 on the base substrate 1 , and the two projections are parallel to the first strip.
  • the direction of the electrodes 111 and the direction parallel to the second strip electrodes 112 do not overlap.
  • the spacer 3 is used to maintain the thickness of the liquid crystal cell after the array substrate 100 and another substrate form a panel. Crystal Cell Gap) homogeneity.
  • the projection of the spacer 3 on the base substrate and the projection of the first connection line 13 on the base substrate 1 are parallel to the first
  • the strip electrodes 111 are separated from each other by a first distance a in a direction and a second distance b in a direction parallel to the second strip electrodes 112 .
  • Both the first distance a and the second distance b are greater than 0 ⁇ m.
  • the first distance a and the second distance b may be the same or different.
  • the first distance a and the second distance b can be adjusted according to actual needs.
  • the main pixel electrode 10 further includes a U-shaped first frame electrode 14 .
  • the U-shaped notch of the first frame electrode 14 faces the slave pixel electrode 20 . That is, both ends of the first frame electrode 14 face the secondary pixel electrode 20 .
  • One of the first connection lines 13 extends from one end of the first frame electrode 14 and is electrically connected to the first thin film transistor 30 .
  • the pixel unit further includes a second thin film transistor 40 , which is disposed between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the slave pixel electrode 20 includes a second trunk electrode 21 , a plurality of second branch electrodes 22 , and a plurality of second connection lines 23 .
  • the number of the second connection lines 23 is two, but not limited to this. In one embodiment, the number of the second connection lines 23 may be 3, 4, or more than 5.
  • the number of the second connection lines 23 is at least two.
  • the second trunk electrode 21 includes a third strip electrode 213 and a fourth strip electrode 214 that intersect with each other.
  • the third strip electrodes 213 and the fourth strip electrodes 214 may intersect vertically, but not limited thereto.
  • the third strip electrodes 213 may be parallel to the first strip electrodes 111 .
  • the fourth strip electrodes 214 may be parallel to the second strip electrodes 112 .
  • the second branch electrode 22 extends diagonally from the second trunk electrode 21 .
  • Each second connection line 23 extends from the corresponding second branch electrode 22 and is electrically connected to the second thin film transistor 40 .
  • the slave pixel electrode 20 further includes a second connection portion 25 for connecting the second connection line 23 .
  • the second thin film transistor 40 includes a second drain electrode 41 , a second drain electrode extension 411 extending from the second drain electrode 41 , and a second source electrode 42 .
  • the second connection portion 25 is electrically connected to the second drain extension portion 411 through the second through hole 92 , so that the second connection line 23 is electrically connected to the second thin film transistor 40 .
  • the projection of the spacer 3 on the base substrate 1 does not overlap with the projection of the second connection line 23 on the base substrate 1, and the two projections are parallel to the third strip.
  • the direction of the electrodes 213 and the direction parallel to the fourth strip electrodes 214 do not overlap.
  • the projection of the spacer 3 on the base substrate 1 and the projection of the second connection line 23 on the base substrate 1 are parallel to the first
  • the three strip electrodes 213 are separated from each other by a third distance c in a direction, and are separated by a fourth distance d in a direction parallel to the fourth strip electrodes 214 .
  • Both the third distance c and the fourth distance d are greater than 0 ⁇ m.
  • the third distance c and the fourth distance d may be the same or different.
  • the third distance c and the fourth distance d can be adjusted according to actual needs.
  • the slave pixel electrode 20 further includes a U-shaped second frame electrode 24 .
  • the U-shaped notch of the second frame electrode 24 faces the main pixel electrode 10 . That is, both ends of the second frame electrode 24 face the main pixel electrode 10 .
  • One of the second connection lines 23 extends from one end of the second frame electrode 24 and is electrically connected to the second thin film transistor 40 .
  • the pixel unit further includes a third thin film transistor 50 disposed between the main pixel electrode 10 and the slave pixel electrode 20 .
  • the third thin film transistor 50 includes a third drain electrode 51 and a third source electrode 52 .
  • the first source electrode 32 of the first thin film transistor 30 and the third source electrode 52 of the third thin film transistor 50 are integrally formed.
  • the pixel unit further includes a gate line 60 , which is disposed on the base substrate 1 and passes through the first thin film transistor 30 , the second thin film transistor 40 and the The third thin film transistor 50 is used as the gate of the first thin film transistor 30 , the second thin film transistor 40 and the third thin film transistor 50 .
  • the pixel unit further includes a first common electrode 71 and a second common electrode 72 .
  • the first common electrode 71 and the second common electrode 72 are provided on the base substrate 1 .
  • the first common electrode 71 , the second common electrode 72 and the gate line 60 are disposed in the same layer, that is, formed by patterning the first metal layer.
  • the patterned first metal layer 201 includes a first common electrode 71 , a second common electrode 72 and the gate line 60 .
  • the first common electrode 71 includes a first electrode 711 and a second electrode 712 .
  • the first electrode 711 is designed in a block structure.
  • the projection of the first electrode 711 on the base substrate 1 surrounds the projection of the main pixel electrode 10 on the base substrate 1 .
  • the projection of the first electrode 711 on the base substrate 1 does not overlap, partially overlap or completely overlap with the projection of the first frame electrode 14 on the base substrate 1 .
  • the second electrodes 712 are designed to connect opposite sides of the first electrodes 711 in a direction parallel to the first strip electrodes 111 .
  • the projection of the second electrode 712 on the base substrate 1 partially overlaps or completely overlaps with the projection of the first strip electrode 111 on the base substrate 1 .
  • the second common electrode 72 is designed to be an I-shaped structure, including a third electrode 723 , a fourth electrode 724 and a fifth electrode 725 .
  • the third electrode 723 and the fourth electrode 724 are parallel to the fourth strip electrode 214 of the slave pixel electrode 20 .
  • the fifth electrode 725 is between the third electrode 723 and the fourth electrode 724 .
  • Two ends of the fifth electrode 725 are respectively connected to the center of the third electrode 723 and the center of the fourth electrode 724 .
  • the projections of the third electrode 723 and the fourth electrode 724 on the base substrate 1 are on two opposite sides of the projection of the sub-pixel electrode 20 on the base substrate 1 .
  • the projection of the fifth electrode 725 on the base substrate 1 partially overlaps or completely overlaps with the projection of the third strip electrodes 213 on the base substrate 1 .
  • the first common electrode 71 can also adopt the shape design of the aforementioned second common electrode 72 .
  • the second common electrode 72 can also be designed in the shape of the aforementioned first common electrode 71 .
  • the first common electrode 71 and the second common electrode 72 can also be designed in other shapes.
  • the pixel unit further includes a first data line 81 and a second data line 82 .
  • the first data line 81, the second data line 82, the first drain 31, the first drain extension 311, the first source 32, the second drain 41, The second drain extension portion 411 , the second source electrode 42 , the third drain electrode 51 and the third source electrode 52 are disposed in the same layer, that is, formed by patterning a second metal layer. Referring to FIG.
  • the patterned second metal layer 202 includes the first data line 81, the second data line 82, the first drain 31, the first drain extension 311, the The first source electrode 32 , the second drain electrode 41 , the second drain extension portion 411 , the second source electrode 42 , the third drain electrode 51 and the third source electrode 52 .
  • the patterned second metal layer 202 is on the patterned first metal layer 201 .
  • a first insulating layer 301 is disposed between the patterned first metal layer 201 and the patterned second metal layer 202 .
  • the first source electrode 32 and the third source electrode 52 may be integrally formed.
  • the first data line 81 , the second data line 82 and the second source electrode 42 can be integrally formed.
  • the second drain 41 , the second drain extension 411 and the third drain 51 may be integrally formed.
  • the first data lines 81 are parallel to the first strip electrodes 111 .
  • the projection of the first data line 81 on the base substrate 1 partially overlaps or completely overlaps with the projection of the first strip electrodes 111 on the base substrate 1 .
  • the second data lines 82 are parallel to the third strip electrodes 213 .
  • the projection of the second data line 82 on the base substrate 1 partially overlaps or completely overlaps with the projection of the third strip electrodes 213 on the base substrate 1 .
  • the array substrate 100 may be a POA type array substrate (Photo Spacer on Array).
  • the pixel unit may be a polymer sustained vertical alignment (PSVA) pixel with 3 T_8 domain transistors.
  • PSVA polymer sustained vertical alignment
  • the master pixel electrode 10 and the slave pixel electrode 20 are disposed in the same layer, that is, formed by patterning the third metal layer.
  • the patterned third metal layer 203 includes a master pixel electrode 10 and a slave pixel electrode 20 .
  • the patterned third metal layer 203 is disposed on the patterned second metal layer 202 .
  • a second insulating layer 302 Between the patterned second metal layer 202 and the patterned third metal layer 203, a second insulating layer 302, a color resist layer 303 and a planarization layer 304 are sequentially disposed from bottom to top.
  • the color resist layer 303 includes red, green and blue color resists.
  • the spacers 3 are disposed on the flat layer 304 and do not cover the patterned third metal layer 203 .
  • the array substrate 100 includes a plurality of the aforementioned pixel units, which are arranged on the base substrate 1 in an array manner. Each pixel unit is provided with one of the aforementioned spacers 3 in the aforementioned manner.
  • the array substrate 100 can be applied to a curved panel.
  • the present disclosure also provides a manufacturing method of the array substrate 100, which includes the following steps.
  • Step 1 Provide the base substrate 1 .
  • Step 2 Disposing pixel units on the base substrate 1 .
  • the pixel unit includes a master pixel electrode 10 , a slave pixel electrode 20 , and a first thin film transistor 30 disposed between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the main pixel electrode 10 includes a first main electrode 11 , a plurality of first branch electrodes 12 , and a plurality of first connection lines 13 .
  • the first trunk electrode 11 includes intersecting first strip electrodes 111 and second strip electrodes 112 . In one embodiment, the first strip electrodes 111 and the second strip electrodes 112 may intersect vertically, but not limited thereto.
  • the first branch electrodes 12 extend diagonally from the first trunk electrode 11 .
  • the number of the first connection lines 13 is four, but not limited to this.
  • the number of the first connecting lines 13 is at least two.
  • Each first connection line 13 extends from the corresponding first branch electrode 12 and is electrically connected to the first thin film transistor 30 .
  • the main pixel electrode 10 further includes a first connection portion 15 connected to the first connection line 13 .
  • the first thin film transistor 30 includes a first drain 31 and a first drain extension 311 extending from the first drain 31 .
  • the first connection portion 15 is electrically connected to the first drain extension portion 311 through the first through hole 91 , so that the first connection line 13 is electrically connected to the first thin film transistor 30 .
  • the spacer 3 is disposed on the pixel unit and between the master pixel electrode 10 and the slave pixel electrode 20 .
  • Step 3 Disposing the spacer 3 on the pixel unit and between the main pixel electrode 10 and the secondary pixel electrode 20 .
  • the projection of the spacer 3 on the base substrate 1 does not overlap with the projection of the first connection line 13 on the base substrate 1 , and the two projections are parallel to the first strip.
  • the direction of the electrodes 111 and the direction parallel to the second strip electrodes 112 do not overlap.
  • the projection of the spacer 3 on the base substrate and the projection of the first connection line 13 on the base substrate 1 are parallel to the first
  • the strip electrodes 111 are separated from each other by a first distance a in a direction and a second distance b in a direction parallel to the second strip electrodes 112 .
  • Both the first distance a and the second distance b are greater than 0 ⁇ m.
  • the first distance a and the second distance b may be the same or different.
  • the first distance a and the second distance b can be adjusted according to actual needs
  • the main pixel electrode 10 further includes a U-shaped first frame electrode 14 .
  • the U-shaped notch of the first frame electrode 14 faces the slave pixel electrode 20 . That is, both ends of the first frame electrode 14 face the secondary pixel electrode 20 .
  • One of the first connection lines 13 extends from one end of the first frame electrode 14 and is electrically connected to the first thin film transistor 30 .
  • the pixel unit further includes a second thin film transistor 40 , which is disposed between the master pixel electrode 10 and the slave pixel electrode 20 .
  • the slave pixel electrode 20 includes a second trunk electrode 21 , a plurality of second branch electrodes 22 , and a plurality of second connection lines 23 .
  • the second trunk electrode 21 includes a third strip electrode 213 and a fourth strip electrode 214 that intersect with each other.
  • the third strip electrodes 213 and the fourth strip electrodes 214 may intersect vertically, but not limited thereto.
  • the third strip electrodes 213 may be parallel to the first strip electrodes 111 .
  • the fourth strip electrodes 214 may be parallel to the second strip electrodes 112 .
  • the second branch electrode 22 extends diagonally from the second trunk electrode 21 .
  • the number of the second connection lines 23 is two, but not limited to this. In one embodiment, the number of the second connection lines 23 may be 3, 4, or more than 5.
  • the number of the second connection lines 23 is at least two.
  • Each second connection line 23 extends from the corresponding second branch electrode 22 and is electrically connected to the second thin film transistor 40 .
  • the slave pixel electrode 20 further includes a second connection portion 25 for connecting the second connection line 23 .
  • the second thin film transistor 40 includes a second drain 41 and a second drain extension 411 extending from the second drain 41 .
  • the second connection portion 25 is electrically connected to the second drain extension portion 411 through the second through hole 92 , so that the second connection line 23 is electrically connected to the second thin film transistor 40 .
  • the projection of the spacer 3 on the base substrate 1 does not overlap with the projection of the second connection line 23 on the base substrate 1, and the two projections are parallel to the third strip.
  • the direction of the electrodes 213 and the direction parallel to the fourth strip electrodes 214 do not overlap.
  • the projection of the spacer 3 on the base substrate 1 and the projection of the second connection line 23 on the base substrate 1 are parallel to the first
  • the three strip electrodes 213 are separated from each other by a third distance c in a direction, and are separated by a fourth distance d in a direction parallel to the fourth strip electrodes 214 .
  • Both the third distance c and the fourth distance d are greater than 0 ⁇ m.
  • the third distance c and the fourth distance d may be the same or different.
  • the third distance c and the fourth distance d can be adjusted according to actual needs.
  • the slave pixel electrode 20 further includes a U-shaped second frame electrode 24 .
  • the U-shaped notch of the second frame electrode 24 faces the main pixel electrode 10 . That is, both ends of the second frame electrode 24 face the main pixel electrode 10 .
  • One of the second connection lines 23 extends from one end of the second frame electrode 24 and is electrically connected to the second thin film transistor 40 .
  • the pixel unit further includes a third thin film transistor 50 , a gate line 60 , a first common electrode 71 , a second common electrode 72 , a first data line 81 and a second data line 82.
  • a third thin film transistor 50 for details of these elements and other details of the array substrate 100 , please refer to the foregoing description, which will not be repeated here.
  • the projection of the spacer on the base substrate and the projection of the first connection line on the base substrate are separated by a second distance in a direction parallel to the first strip electrode. a distance, and a second distance in a direction parallel to the second strip electrodes.
  • the spacer is connected to the main pixel electrode and/or the sub-pixel electrode.
  • the projections of the lines on the base substrate do not overlap, and also do not overlap in the direction parallel to the first/third strip electrodes and in the direction parallel to the second/fourth strip electrodes.
  • the projection of the spacer on the base substrate and the projection of the main pixel electrode and/or the connecting line of the slave pixel electrode on the base substrate are in a direction parallel to the first/third strip electrodes and parallel to the direction of the first/third strip electrodes.
  • the distances in the direction of the second/fourth strip electrodes are all greater than 0 ⁇ m. Thereby, it is difficult for the external force to propagate the crack of the color resist layer to the lower part of the connecting line far away from the spacer through the spacer, thereby preventing the connecting line from breaking. Furthermore, by designing the connection lines of the main pixel electrode and/or the sub-pixel electrode into multiple pieces, when one or two connection lines are broken, the signal can still be transmitted to the main pixel electrode and/or through the other unbroken connection lines. or from pixel electrodes. Therefore, the present invention can effectively avoid poor display of the array substrate.

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Abstract

本揭示公开一种阵列基板及其制造方法。所述阵列基板包含衬底基板、像素单元及间隔子。像素单元设置在衬底基板上，包含主像素电极、从像素电极及设置在主像素电极及从像素电极之间的薄膜晶体管。主像素电极包含主干电极、多个分支电极，以及多个连接线。主干电极包含相交的第一条状电极及第二条状电极。分支电极从主干电极往对角线方向延伸。连接线从分支电极中的多个延伸且电连接至薄膜晶体管。间隔子设置在像素单元上且在主像素电极及从像素电极之间。间隔子与连接线在衬底基板上的投影不重叠，且两投影在平行于第一条状电极的方向上及在平行于第二条状电极的方向上不重叠。

Description

阵列基板及其制造方法 技术领域
本揭示涉及显示技术领域，特别是涉及一种阵列基板及其制造方法。
 背景技术
曲面面板的曲率设计成与人眼的视网膜的曲率实质相同。因此，相较于平面面板，曲面面板不仅具有更大的显示面积，更具有画面临场感，使人有更舒适的观影感觉。
曲面面板的传统制作方法包含：将红/绿/蓝色阻层和间隙子(Photo Spacer，PS)设置在彩膜(Color Filter，CF)基板上；将CF基板和薄膜晶体管(Thin Film Transistor，TFT）阵列基板相对设置，以形成面板；以及弯曲面板，以形成曲面面板。在面板弯曲时，相对于TFT阵列基板，CF基板的曲率半径较小，因此CF基板上的红/绿/蓝色阻层和间隙子易发生位移，进而容易产生液晶盒厚（Liquid Crystal Cell Gap）不均和颜色混合(color-Mix)不均。因此，现今的方法一般会将红/绿/蓝色阻层和间隙子设置在TFT阵列基板上，即POA(Photo Spacer on Array)技术，以避免液晶盒厚（Liquid Crystal Cell Gap）不均和颜色混合(color-Mix)不均。
再者，为了提升面板的视角及改善色偏，具有8畴3晶体管(3T_8domain)的聚合物稳定垂直配向(polymer sustained vertical alignment，PSVA）像素逐渐应用于大尺寸面板。
 技术问题
请参阅图1，在现今采用POA技术和PSVA像素的阵列基板500的像素中，间隙子501通常会覆盖及/或临近主像素电极510的连接线511的一部份及连接部512的一部份。请参阅图2A，色阻层502容易因为成膜异常而产生裂纹503。请参阅图2B，外力F会通过间隙子501传递到下方的色阻层502，使裂纹503扩展到连接线511的下方，进而使得连接线511剥离并弯曲。请参阅图2C及图3，在外力F的持续作用下，微小裂纹503逐渐扩大，使连接线511断裂，导致信号无法传输到主像素区，进而导致阵列基板500显示不良。
 技术解决方案
为了解决现今的阵列基板中间隙子附近的主像素电极的连接线易因色阻层裂纹而断裂的技术问题，本揭示提供下列解决方案。
本揭示提供一种阵列基板，其包含衬底基板、像素单元及间隔子。所述像素单元设置在所述衬底基板上，包含主像素电极、从像素电极及设置在所述主像素电极及所述从像素电极之间的第一薄膜晶体管。所述主像素电极包含第一主干电极、多个第一分支电极，以及多个第一连接线。所述第一主干电极包含相交的第一条状电极及第二条状电极。所述第一分支电极从所述第一主干电极往对角线方向延伸。每个第一连接线从相对应的第一分支电极延伸且电连接至所述第一薄膜晶体管。所述间隔子设置在所述像素单元上且在主像素电极及从像素电极之间。所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第一条状电极的方向上及在平行于所述第二条状电极的方向上不重叠。
在一实施例中，所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影在平行于所述第一条状电极的方向上相距第一距离，以及在平行于所述第二条状电极的方向上相距第二距离。
在一实施例中，所述主像素电极还包含呈U型的第一边框电极。所述第一连接线中的一个从所述第一边框电极的一端延伸且电连接至所述第一薄膜晶体管。
在一实施例中，所述主像素电极还包含第一连接部，连接所述第一连接线。所述第一薄膜晶体管包含第一漏极及从第一漏极延伸的第一漏极延伸部。第一连接部通过第一通孔与第一漏极延伸部电连接，使得所述第一连接线与所述第一薄膜晶体管电连接。
在一实施例中，所述像素单元还包含第二薄膜晶体管，设置在所述主像素电极及所述从像素电极之间。所述从像素电极包含第二主干电极、多个第二分支电极，以及多个第二连接线。所述第二主干电极包含相交的第三条状电极及第四条状电极。所述第三条状电极与所述第一条状电极平行。所述第二分支电极从所述第二主干电极往对角线方向延伸。每个第二连接线从相对应的第二分支电极延伸且电连接至所述第二薄膜晶体管。所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第三条状电极的方向上及在平行于所述第四条状电极的方向上不重叠。
在一实施例中，所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影在平行于所述第三条状电极的方向上相距第三距离，以及在平行于所述第四条状电极的方向上相距第四距离。
在一实施例中，所述从像素电极还包含呈U型的第二边框电极。所述第二连接线中的一个从所述第二边框电极的一端延伸且电连接至所述第二薄膜晶体管。
在一实施例中，所述从像素电极还包含第二连接部，连接所述第二连接线。所述第二薄膜晶体管包含第二漏极及从第二漏极延伸的第二漏极延伸部。第二连接部通过第二通孔与第二漏极延伸部电连接，使得所述第二连接线与所述第二薄膜晶体管电连接。
本揭示还提供一种阵列基板的制造方法，其包含提供衬底基板、设置像素单元于所述衬底基板上，以及设置间隔子于像素单元上。所述像素单元包含主像素电极、从像素电极及设置在所述主像素电极及所述从像素电极之间的第一薄膜晶体管。所述主像素电极包含第一主干电极、多个第一分支电极，以及多个第一连接线。所述第一主干电极包含相交的第一条状电极及第二条状电极。所述第一分支电极从所述第一主干电极往对角线方向延伸。其中每个第一连接线从相对应的第一分支电极延伸且电连接至所述第一薄膜晶体管。所述间隔子设置在所述像素单元上且在主像素电极及从像素电极之间。所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第一条状电极的方向上及在平行于所述第二条状电极的方向上不重叠。
在一实施例中，所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影在平行于所述第一条状电极的方向上相距第一距离，以及在平行于所述第二条状电极的方向上相距第二距离。
在一实施例中，所述主像素电极还包含呈U型的第一边框电极。所述第一连接线中的一个从所述第一边框电极的一端延伸且电连接至所述第一薄膜晶体管。
在一实施例中，所述主像素电极还包含第一连接部，连接所述第一连接线。所述第一薄膜晶体管包含第一漏极及从第一漏极延伸的第一漏极延伸部。第一连接部通过第一通孔与第一漏极延伸部电连接，使得所述第一连接线与所述第一薄膜晶体管电连接。
在一实施例中，所述像素单元还包含第二薄膜晶体管，设置在所述主像素电极及所述从像素电极之间。所述从像素电极包含第二主干电极、多个第二分支电极，以及多个第二连接线。所述第二主干电极包含相交的第三条状电极及第四条状电极。所述第三条状电极与所述第一条状电极平行。所述第二分支电极从所述第二主干电极往对角线方向延伸。每个第二连接线从相对应的第二分支电极延伸且电连接至所述第二薄膜晶体管。所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第三条状电极的方向上及在平行于所述第四条状电极的方向上不重叠。
在一实施例中，所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影在平行于所述第三条状电极的方向上相距第三距离，以及在平行于所述第四条状电极的方向上相距第四距离。
在一实施例中，所述从像素电极还包含呈U型的第二边框电极。所述第二连接线中的一个从所述第二边框电极的一端延伸且电连接至所述第二薄膜晶体管。
在一实施例中，所述从像素电极还包含第二连接部，连接所述第二连接线。所述第二薄膜晶体管包含第二漏极及从第二漏极延伸的第二漏极延伸部。第二连接部通过第二通孔与第二漏极延伸部电连接，使得所述第二连接线与所述第二薄膜晶体管电连接。
 有益效果
在本揭示所提供的阵列基板及其制造方法中，通过将主像素电极及/或从像素电极的连接线设置在远离间隔子处，使得间隔子与主像素电极及/或从像素电极的连接线在衬底基板上的投影不重叠，亦在平行于第一/第三条状电极的方向上及在平行于第二/第四条状电极的方向上不重叠。较佳地，间隔子在衬底基板上的投影与主像素电极及/或从像素电极的连接线在衬底基板上的投影在平行于第一/第三条状电极的方向上及在平行于第二/第四条状电极的方向上的距离皆大于0 μm。藉此，使得外力难以通过间隙子使色阻层裂纹扩展到远离间隙子的连接线的下方，进而避免连接线断裂。再者，通过将主像素电极及/或从像素电极的连接线设计成多个，使得一个或二个连接线断裂时，信号仍可藉由其它未断裂的连接线传输到主像素电极及/或从像素电极。因此，本发明可有效避免阵列基板显示不良。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为先前技术中的阵列基板的局部示意图。
图2A至图2C为图1的阵列基板沿A-A线的剖面示意图，显示在外力的持续作用下，色阻层的裂纹逐渐扩大，使连接线弯曲，进而断裂的过程。
图3为图1的阵列基板沿A-A线的电子显微镜剖面图，显示连接线因色阻层裂纹而断裂。
图4为本揭示实施例的阵列基板的示意图。
图5为图4的阵列基板的局部放大示意图
图6为图5的阵列基板沿E-E线的剖面示意图。
 本发明的实施方式
下面将结合附图，对本揭示实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅仅是本揭示一部分实施例，而非全部的实施例。基于本揭示中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本揭示保护的范围。
在本揭示的描述中，术语“上”、“下”、“垂直”、“平行”、“内”、“外”、“中心”及“侧边”等所指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本揭示和简化描述。再者，“第一”及“第二”等术语仅用于描述目的，而不能理解为指示或暗示相对重要性。以“第一”及“第二”等术语限定的特征可明示或者隐含地包括一个或者更多个所述特征。
请参阅图4，本揭示提供了一种阵列基板100。所述阵列基板100包含衬底基板1、像素单元及间隔子3。所述像素单元设置在所述衬底基板1上，包含主像素电极10、从像素电极20及设置在所述主像素电极10及所述从像素电极20之间的第一薄膜晶体管30。所述主像素电极10包含第一主干电极11、多个第一分支电极12，以及多个第一连接线13。在此实施例中，第一连接线13的数量为4个，但不限于此。第一连接线13的数量至少为二个。所述第一主干电极11包含相交的第一条状电极111及第二条状电极112。在一实施例中，第一条状电极111及第二条状电极112可垂直相交，但不限于此。所述第一分支电极12从所述第一主干电极11往对角线方向延伸。每个第一连接线13从相对应的第一分支电极12延伸且电连接至所述第一薄膜晶体管30。具体地，所述主像素电极10还包含第一连接部15，连接所述第一连接线13。请参阅图5，所述第一薄膜晶体管30包含第一漏极31、从第一漏极31延伸的第一漏极延伸部311，以及第一源极32。第一连接部15通过第一通孔91与第一漏极延伸部311电连接，使得所述第一连接线13与所述第一薄膜晶体管电30连接。所述间隔子3设置在所述像素单元上且在主像素电极10及从像素电极20之间。所述间隔子3在所述衬底基板1上的投影与所述第一连接线13在所述衬底基板1上的投影不重叠，且所述两投影在平行于所述第一条状电极111的方向上及在平行于所述第二条状电极112的方向上不重叠。所述间隔子3是用于在所述阵列基板100与另一基板组成面板后，保持持液晶盒厚（Liquid Crystal Cell Gap）的均一性。
请参阅图4，在一实施例中，所述间隔子3在所述衬底基板上的投影与所述第一连接线13在所述衬底基板1上的投影在平行于所述第一条状电极111的方向上相距第一距离a，以及在平行于所述第二条状电极112的方向上相距第二距离b。第一距离a与第二距离b皆大于0 μm。第一距离a与第二距离b可相同或不同。第一距离a与第二距离b可依实际需要进行调整。
请参阅图4，在一实施例中，所述主像素电极10还包含呈U型的第一边框电极14。所述第一边框电极14的U型缺口朝向所述从像素电极20。亦即，所述第一边框电极14的两端朝向所述从像素电极20。所述第一连接线13中的一个从所述第一边框电极14的一端延伸且电连接至所述第一薄膜晶体管30。
请参阅图4及图5，在一实施例中，所述像素单元还包含第二薄膜晶体管40，设置在所述主像素电极10及所述从像素电极20之间。所述从像素电极20包含第二主干电极21、多个第二分支电极22，以及多个第二连接线23。在此实施例中，第二连接线23的数量为2个，但不限于此。在一实施例中，第二连接线23的数量可为3个、4个或5个以上。第二连接线23的数量至少为二个。所述第二主干电极21包含相交的第三条状电极213及第四条状电极214。在一实施例中，第三条状电极213及第四条状电极214可垂直相交，但不限于此。所述第三条状电极213可与所述第一条状电极111平行。所述第四条状电极214可与所述第二条状电极112平行。所述第二分支电极22从所述第二主干电极21往对角线方向延伸。每个第二连接线23从相对应的第二分支电极22延伸且电连接至所述第二薄膜晶体管40。具体地，所述从像素电极20还包含第二连接部25，连接所述第二连接线23。所述第二薄膜晶体管40包含第二漏极41、从第二漏极41延伸的第二漏极延伸部411，以及第二源极42。第二连接部25通过第二通孔92与第二漏极延伸部411电连接，使得所述第二连接线23与所述第二薄膜晶体管40电连接。所述间隔子3在所述衬底基板1上的投影与所述第二连接线23在所述衬底基板1上的投影不重叠，且所述两投影在平行于所述第三条状电极213的方向上及在平行于所述第四条状电极214的方向上不重叠。
请参阅图4，在一实施例中，所述间隔子3在所述衬底基板1上的投影与所述第二连接线23在所述衬底基板1上的投影在平行于所述第三条状电极213的方向上相距第三距离c，以及在平行于所述第四条状电极214的方向上相距第四距离d。第三距离c与第四距离d皆大于0 μm。第三距离c与第四距离d可相同或不同。第三距离c与第四距离d可依实际需要进行调整。
请参阅图4，在一实施例中，所述从像素电极20还包含呈U型的第二边框电极24。所述第二边框电极24的U型缺口朝向所述主像素电极10。亦即，所述第二边框电极24的两端朝向所述主像素电极10。所述第二连接线23中的一个从所述第二边框电极24的一端延伸且电连接至所述第二薄膜晶体管40。
请参阅图5，在一实施例中，所述像素单元还包含第三薄膜晶体管50，设置在所述主像素电极10及所述从像素电极20之间。所述第三薄膜晶体管50包含第三漏极51及第三源极52。在一实施例中，第一薄膜晶体管30的第一源极32与第三薄膜晶体管50的第三源极52一体成型。
请参阅图5，在一实施例中，所述像素单元还包含栅极线60，设置在衬底基板1上，且通过所述第一薄膜晶体管30、所述第二薄膜晶体管40及所述第三薄膜晶体管50，以作为所述第一薄膜晶体管30、所述第二薄膜晶体管40及所述第三薄膜晶体管50的栅极。
请参阅图5，所述像素单元还包含第一公共电极71及第二公共电极72。第一公共电极71及第二公共电极72设置在衬底基板1上。第一公共电极71、第二公共电极72及所述栅极线60同层设置，亦即由第一金属层图案化形成。请参阅图6，图案化的第一金属层201包含第一公共电极71、第二公共电极72及所述栅极线60。
在本实施例中，第一公共电极71包含第一电极711及第二电极712。所述第一电极711设计成方框结构。所述第一电极711在所述衬底基板1在的投影围绕所述主像素电极10在所述衬底基板1上的投影。所述第一电极711在所述衬底基板1的投影与所述第一边框电极14在所述衬底基板1上的投影不重叠、部分重叠或完全重叠。所述第二电极712设计成在平行于所述第一条状电极111的方向上连接所述第一电极711的相对两侧。所述第二电极712在所述衬底基板1在的投影与所述第一条状电极111在所述衬底基板1上的投影部分重叠或完全重叠。
在本实施例中，第二公共电极72设计成I型结构，包含第三电极723、第四电极724及第五电极725。所述第三电极723及所述第四电极724平行于所述从像素电极20的第四条状电极214。第五电极725于所述第三电极723及所述第四电极724。第五电极725的两端分别连接所述第三电极723的中心及所述第四电极724的中心。所述第三电极723及所述第四电极724在所述衬底基板1的投影在所述从像素电极20在所述衬底基板1上的投影的两相对侧。所述第五电极725在所述衬底基板1在的投影与所述第三条状电极213在所述衬底基板1上的投影部分重叠或完全重叠。
在一实施例中，第一公共电极71亦可采用前述第二公共电极72的形状设计。在一实施例中，第二公共电极72亦可采用前述第一公共电极71的形状设计。在一实施例中，第一公共电极71及第二公共电极72亦可采用其它的形状设计。
请参阅图5，所述像素单元还包含第一数据线81及第二数据线82。所述第一数据线81、所述第二数据线82、所述第一漏极31、所述第一漏极延伸部311、所述第一源极32、所述第二漏极41、所述第二漏极延伸部411、所述第二源极42、所述第三漏极51及所述第三源极52为同层设置，亦即由第二金属层图案化形成。请参阅图6，图案化的的第二金属层202包含所述第一数据线81、所述第二数据线82、所述第一漏极31、所述第一漏极延伸部311、所述第一源极32、所述第二漏极41、所述第二漏极延伸部411、所述第二源极42、所述第三漏极51及所述第三源极52。所述图案化的第二金属层202在所述图案化的第一金属层201上。所述图案化的第一金属层201与所述图案化的第二金属层202之间设有第一绝缘层301。所述第一源极32及所述第三源极52可一体成形。所述第一数据线81、所述第二数据线82及所述第二源极42可一体成形。所述第二漏极41、所述第二漏极延伸部411及所述第三漏极51可一体成形。所述第一数据线81与所述第一条状电极111平行。所述第一数据线81在所述衬底基板1在的投影与所述第一条状电极111在所述衬底基板1上的投影部分重叠或完全重叠。所述第二数据线82与所述第三条状电极213平行。所述第二数据线82在所述衬底基板1在的投影与所述第三条状电极213在所述衬底基板1上的投影部分重叠或完全重叠。
在一实施例中，所述阵列基板100可为POA型阵列基板(Photo Spacer on Array)。所述像素单元可为具有8畴3晶体管(3T_8domain)的聚合物稳定配向(polymer sustained vertical alignment，PSVA）像素。主像素电极10与从像素电极20为同层设置，亦即由第三金属层图案化形成。请参阅图6，所述图案化的第三金属层203包含主像素电极10与从像素电极20。所述图案化的第三金属层203设置在所述图案化的第二金属层202上。所述图案化的第二金属层202与所述图案化的第三金属层203之间由下到上依序设有第二绝缘层302、色阻层303及平坦层304。所述色阻层303包含红色、绿色及蓝色色阻。所述间隔子3设置在所述平坦层304上，不覆盖到所述图案化的第三金属层203。
在一实施例中，所述阵列基板100包含有多个前述像素单元，以阵列方式设置在衬底基板1上。每个像素单元皆以前述方式设有一个前述间隔子3。
在一实施例中，所述阵列基板100可应用于曲面面板。
本揭示还提供了一种阵列基板100的制造方法，其包含下列步骤。
步骤1：提供衬底基板1。
步骤2：设置像素单元于所述衬底基板1上。所述像素单元包含主像素电极10、从像素电极20及设置在所述主像素电极10及所述从像素电极20之间的第一薄膜晶体管30。所述主像素电极10包含第一主干电极11、多个第一分支电极12，以及多个第一连接线13。所述第一主干电极11包含相交的第一条状电极111及第二条状电极112。在一实施例中，第一条状电极111及第二条状电极112可垂直相交，但不限于此。所述第一分支电极12从所述第一主干电极11往对角线方向延伸。在此实施例中，第一连接线13的数量为4个，但不限于此。第一连接线13的数量至少为二个。每个第一连接线13从相对应的第一分支电极12延伸且电连接至所述第一薄膜晶体管30。具体地，所述主像素电极10还包含第一连接部15，连接所述第一连接线13。请参阅图5，所述第一薄膜晶体管30包含第一漏极31及从第一漏极31延伸的第一漏极延伸部311。第一连接部15通过第一通孔91与第一漏极延伸部311电连接，使得所述第一连接线13与所述第一薄膜晶体管电30连接。所述间隔子3设置在所述像素单元上且在主像素电极10及从像素电极20之间。
步骤3：设置间隔子3在所述像素单元上且在主像素电极10及从像素电极20之间。所述间隔子3在所述衬底基板1上的投影与所述第一连接线13在所述衬底基板1上的投影不重叠，且所述两投影在平行于所述第一条状电极111的方向上及在平行于所述第二条状电极112的方向上不重叠。
请参阅图4，在一实施例中，所述间隔子3在所述衬底基板上的投影与所述第一连接线13在所述衬底基板1上的投影在平行于所述第一条状电极111的方向上相距第一距离a，以及在平行于所述第二条状电极112的方向上相距第二距离b。第一距离a与第二距离b皆大于0 μm。第一距离a与第二距离b可相同或不同。第一距离a与第二距离b可依实际需要进行调整
请参阅图4，在一实施例中，所述主像素电极10还包含呈U型的第一边框电极14。所述第一边框电极14的U型缺口朝向所述从像素电极20。亦即，所述第一边框电极14的两端朝向所述从像素电极20。所述第一连接线13中的一个从所述第一边框电极14的一端延伸且电连接至所述第一薄膜晶体管30。
请参阅图4及图5，在一实施例中，所述像素单元还包含第二薄膜晶体管40，设置在所述主像素电极10及所述从像素电极20之间。所述从像素电极20包含第二主干电极21、多个第二分支电极22，以及多个第二连接线23。所述第二主干电极21包含相交的第三条状电极213及第四条状电极214。在一实施例中，第三条状电极213及第四条状电极214可垂直相交，但不限于此。所述第三条状电极213可与所述第一条状电极111平行。所述第四条状电极214可与所述第二条状电极112平行。所述第二分支电极22从所述第二主干电极21往对角线方向延伸。在此实施例中，第二连接线23的数量为2个，但不限于此。在一实施例中，第二连接线23的数量可为3个、4个或5个以上。第二连接线23的数量至少为二个。每个第二连接线23从相对应的第二分支电极22延伸且电连接至所述第二薄膜晶体管40。具体地，所述从像素电极20还包含第二连接部25，连接所述第二连接线23。所述第二薄膜晶体管40包含第二漏极41及从第二漏极41延伸的第二漏极延伸部411。第二连接部25通过第二通孔92与第二漏极延伸部411电连接，使得所述第二连接线23与所述第二薄膜晶体管40电连接。所述间隔子3在所述衬底基板1上的投影与所述第二连接线23在所述衬底基板1上的投影不重叠，且所述两投影在平行于所述第三条状电极213的方向上及在平行于所述第四条状电极214的方向上不重叠。
请参阅图4，在一实施例中，所述间隔子3在所述衬底基板1上的投影与所述第二连接线23在所述衬底基板1上的投影在平行于所述第三条状电极213的方向上相距第三距离c，以及在平行于所述第四条状电极214的方向上相距第四距离d。第三距离c与第四距离d皆大于0 μm。第三距离c与第四距离d可相同或不同。第三距离c与第四距离d可依实际需要进行调整。
请参阅图4，在一实施例中，所述从像素电极20还包含呈U型的第二边框电极24。所述第二边框电极24的U型缺口朝向所述主像素电极10。亦即，所述第二边框电极24的两端朝向所述主像素电极10。所述第二连接线23中的一个从所述第二边框电极24的一端延伸且电连接至所述第二薄膜晶体管40。
请参阅图4，在一实施例中，所述像素单元还包含第三薄膜晶体管50、栅极线60、第一公共电极71、第二公共电极72、第一数据线81及第二数据线82。关于这些元件的细节及阵列基板100的其它细节请参考前面的说明，在此不再赘述。
在一实施例中，所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影在平行于所述第一条状电极的方向上相距第一距离，以及在平行于所述第二条状电极的方向上相距第二距离。
在本揭示所提供的阵列基板及其制造方法中，通过将主像素电极及/或从像素电极的连接线设置在远离间隔子处，使得间隔子与主像素电极及/或从像素电极的连接线在衬底基板上的投影不重叠，亦在平行于第一/第三条状电极的方向上及在平行于第二/第四条状电极的方向上不重叠。较佳地，间隔子在衬底基板上的投影与主像素电极及/或从像素电极的连接线在衬底基板上的投影在平行于第一/第三条状电极的方向上及在平行于第二/第四条状电极的方向上的距离皆大于0 μm。藉此，使得外力难以通过间隙子使色阻层裂纹扩展到远离间隙子的连接线的下方，进而避免连接线断裂。再者，通过将主像素电极及/或从像素电极的连接线设计成多个，使得一个或二个连接线断裂时，信号仍可藉由其它未断裂的连接线传输到主像素电极及/或从像素电极。因此，本发明可有效避免阵列基板显示不良。
虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本发明的保护范围以权利要求界定的范围为准。本领域的普通技术人员，在不脱离本发明的保护范围内，均可作各种更动与润饰。例如，上述实施例是以具有八畴结构的像素单元作为例示，然而本领域的普通技术人员可将本发明的概念应用于具有多畴结构的像素单元中。

Claims (16)

  1. 一种阵列基板，其包含：
    衬底基板；
    像素单元，设置在所述衬底基板上，包含主像素电极、从像素电极及设置在所述主像素电极及所述从像素电极之间的第一薄膜晶体管，其中所述主像素电极包含：
    第一主干电极，包含相交的第一条状电极及第二条状电极；
    多个第一分支电极，从所述第一主干电极往对角线方向延伸；及
    多个第一连接线，其中每个第一连接线从相对应的第一分支电极延伸且电连接至所述第一薄膜晶体管；以及
    间隔子，设置在所述像素单元上且在主像素电极及从像素电极之间，其中所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第一条状电极的方向上及在平行于所述第二条状电极的方向上不重叠。
  2. 根据权利要求1所述的阵列基板，其中：所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影在平行于所述第一条状电极的方向上相距第一距离，以及在平行于所述第二条状电极的方向上相距第二距离。
  3. 根据权利要求1所述的阵列基板，其中：所述主像素电极还包含呈U型的第一边框电极，以及所述第一连接线中的一个从所述第一边框电极的一端延伸且电连接至所述第一薄膜晶体管。
  4. 根据权利要求1所述的阵列基板，其中：
    所述主像素电极还包含第一连接部，连接所述第一连接线；
    所述第一薄膜晶体管包含第一漏极及从第一漏极延伸的第一漏极延伸部；以及
    第一连接部通过第一通孔与第一漏极延伸部电连接，使得所述第一连接线与所述第一薄膜晶体管电连接。
  5. 根据权利要求1所述的阵列基板，其中：
    所述像素单元还包含第二薄膜晶体管，设置在所述主像素电极及所述从像素电极之间；
    所述从像素电极包含：
    第二主干电极，包含相交的第三条状电极及第四条状电极，其中所述第三条状电极与所述第一条状电极平行；
    多个第二分支电极，从所述第二主干电极往对角线方向延伸；及
    多个第二连接线，其中每个第二连接线从相对应的第二分支电极延伸且电连接至所述第二薄膜晶体管；以及
    所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第三条状电极的方向上及在平行于所述第四条状电极的方向上不重叠。
  6. 根据权利要求5所述的阵列基板，其中：所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影在平行于所述第三条状电极的方向上相距第三距离，以及在平行于所述第四条状电极的方向上相距第四距离。
  7. 根据权利要求5所述的阵列基板，其中：所述从像素电极还包含呈U型的第二边框电极，以及所述第二连接线中的一个从所述第二边框电极的一端延伸且电连接至所述第二薄膜晶体管。
  8. 根据权利要求5所述的阵列基板，其中：
    所述从像素电极还包含第二连接部，连接所述第二连接线；
    所述第二薄膜晶体管包含第二漏极及从第二漏极延伸的第二漏极延伸部；以及
    第二连接部通过第二通孔与第二漏极延伸部电连接，使得所述第二连接线与所述第二薄膜晶体管电连接。
  9. 一种阵列基板的制造方法，其包含：
    提供衬底基板；
    设置像素单元于所述衬底基板上，其中所述像素单元包含主像素电极、从像素电极及设置在所述主像素电极及所述从像素电极之间的第一薄膜晶体管，所述主像素电极包含：
    第一主干电极，包含相交的第一条状电极及第二条状电极；
    多个第一分支电极，从所述第一主干电极往对角线方向延伸；及
    多个第一连接线，其中每个第一连接线从相对应的第一分支电极延伸且电连接至所述第一薄膜晶体管；以及
    设置间隔子于所述像素单元上且在主像素电极及从像素电极之间，其中所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第一条状电极的方向上及在平行于所述第二条状电极的方向上不重叠。
  10. 根据权利要求9所述的方法，其中：所述间隔子在所述衬底基板上的投影与所述第一连接线在所述衬底基板上的投影在平行于所述第一条状电极的方向上相距第一距离，以及在平行于所述第二条状电极的方向上相距第二距离。
  11. 根据权利要求9所述的方法，其中：所述主像素电极还包含呈U型的第一边框电极，以及所述第一连接线中的一个从所述第一边框电极的一端延伸且电连接至所述第一薄膜晶体管。
  12. 根据权利要求9所述的阵列方法，其中：
    所述主像素电极还包含第一连接部，连接所述第一连接线；
    所述第一薄膜晶体管包含第一漏极及从第一漏极延伸的第一漏极延伸部；以及
    第一连接部通过第一通孔与第一漏极延伸部电连接，使得所述第一连接线与所述第一薄膜晶体管电连接。
  13. 根据权利要求9所述的方法，其中：
    所述像素单元还包含第二薄膜晶体管，设置在所述主像素电极及所述从像素电极之间；
    所述从像素电极包含：
    第二主干电极，包含相交的第三条状电极及第四条状电极，其中所述第三条状电极与所述第一条状电极平行；
    多个第二分支电极，从所述第二主干电极往对角线方向延伸；及
    多个第二连接线，其中每个第二连接线从相对应的第二分支电极延伸且电连接至所述第二薄膜晶体管；以及
    所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影不重叠，且所述两投影在平行于所述第三条状电极的方向上及在平行于所述第四条状电极的方向上不重叠。
  14. 根据权利要求13所述的方法，其中：所述间隔子在所述衬底基板上的投影与所述第二连接线在所述衬底基板上的投影在平行于所述第三条状电极的方向上相距第三距离，以及在平行于所述第四条状电极的方向上相距第四距离。
  15. 根据权利要求13所述的方法，其中，所述从像素电极还包含呈U型的第二边框电极，以及所述第二连接线中的一个从所述第二边框电极的一端延伸且电连接至所述第二薄膜晶体管。
  16. 根据权利要求13所述的方法，其中：
    所述从像素电极还包含第二连接部，连接所述第二连接线；
    所述第二薄膜晶体管包含第二漏极及从第二漏极延伸的第二漏极延伸部；以及
    第二连接部通过第二通孔与第二漏极延伸部电连接，使得所述第二连接线与所述第二薄膜晶体管电连接。
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