WO2019010996A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2019010996A1
WO2019010996A1 PCT/CN2018/079194 CN2018079194W WO2019010996A1 WO 2019010996 A1 WO2019010996 A1 WO 2019010996A1 CN 2018079194 W CN2018079194 W CN 2018079194W WO 2019010996 A1 WO2019010996 A1 WO 2019010996A1
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Prior art keywords
electrode strip
upper electrode
strip
array substrate
layer
Prior art date
Application number
PCT/CN2018/079194
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English (en)
French (fr)
Inventor
范昊翔
顾可可
栗鹏
李晓吉
李哲
卢俊宏
朱维
秦鹏
刘文亮
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18788991.0A priority Critical patent/EP3654091B1/en
Priority to US16/098,311 priority patent/US11003030B2/en
Publication of WO2019010996A1 publication Critical patent/WO2019010996A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/12—Application of an electrode to the exposed surface of the selenium or tellurium after the selenium or tellurium has been applied to the foundation plate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a display device including the array substrate.
  • Liquid crystal display devices have been widely used in various fields such as monitors, televisions, and notebook computers.
  • the liquid crystal display device includes a common electrode and a pixel electrode, and the deflection of the liquid crystal molecules is controlled by an electric field formed between the common electrode and the pixel electrode.
  • a liquid crystal display device using an ADS (Advanced Super Dimension Switch) display mode is widely used due to its wide viewing angle.
  • the pixel electrode and the common electrode are respectively located in different layers included in the array substrate of the liquid crystal display device, thereby forming a fringe electric field therebetween.
  • the liquid crystal display device may employ other display modes.
  • IPS In-plane Switching
  • the pixel electrode and the common electrode are located in the same layer included in the array substrate, thereby forming an IPS electric field therebetween.
  • Embodiments of the present disclosure provide an array substrate and a method of fabricating the same, and a display device including the array substrate, which can improve transmittance of a display device including the array substrate.
  • At least one embodiment of the present disclosure provides an array substrate including: a substrate substrate; an upper electrode layer on the substrate substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer, Located between the base substrate and the upper electrode layer, wherein the lower electrode layer includes the first upper electrode strip and the first electrode strip in a direction perpendicular to an upper surface of the base substrate The portion where the second upper electrode strips do not overlap.
  • the array substrate includes a pixel electrode strip and a common electrode strip disposed in the same layer, and the pixel electrode strip and the common electrode strip both correspond to between the first upper electrode strip and the second upper electrode strip region.
  • a central position of a region between the first upper electrode strip and the second upper electrode strip corresponds to a region between the pixel electrode strip and the common electrode strip, the center position to the first The distance between the adjacent edges of an upper electrode strip and the second upper electrode strip is equal.
  • the lower electrode layer includes a first lower electrode strip and a second lower electrode strip; the first lower electrode strip and the second lower electrode strip in a direction perpendicular to an upper surface of the base substrate Both include portions that do not overlap the first upper electrode strip and the second upper electrode strip.
  • the first lower electrode strip is a lower pixel electrode strip
  • the second lower electrode strip is a lower common electrode strip
  • the first upper electrode strip is an upper common electrode strip
  • the second upper electrode strip is upper Pixel electrode strip.
  • a portion of the first lower electrode strip serves as the pixel electrode strip, and a portion of the second lower electrode strip serves as the common electrode strip.
  • the first lower electrode strip includes a first convex portion that protrudes toward the upper electrode layer, the first convex portion serves as the pixel electrode strip; and the second lower electrode strip includes a convex surface a second raised portion of the upper electrode layer, the second raised portion serving as the common electrode strip.
  • the array substrate further includes: a first insulating layer including a protrusion supporting the first protrusion and the second protrusion.
  • the center of the protrusion corresponds to the center of the area between the first upper electrode strip and the second upper electrode strip.
  • the array substrate further includes a second insulating layer between the lower electrode layer and the upper electrode layer, and an upper surface of the second insulating layer includes a planar portion, the planar portion corresponding to at least a first upper electrode strip, the second upper electrode strip, and a region between the first upper electrode strip and the second upper electrode strip.
  • a distance between a tip end of the first convex portion and a top end of the second convex portion to a lower surface of the upper electrode layer is greater than or equal to 1000 angstroms.
  • the first upper electrode strip is adjacent to the second upper electrode strip, and the first lower electrode strip and the second lower electrode strip are adjacent.
  • the pixel electrode strip and the common electrode strip are located in the lower electrode layer and are spaced apart from both the first lower electrode strip and the second lower electrode strip.
  • the first upper electrode strip and the second upper electrode strip are adjacent.
  • the pixel electrode strip and the common electrode strip are located in the upper electrode layer and are spaced apart from both the first upper electrode strip and the second upper electrode strip.
  • a width of the pixel electrode strip, a width of the common electrode strip, and a sum of distances between the pixel electrode strip and the common electrode strip and the first upper electrode strip and the second upper surface is 1/4-1/3.
  • the pixel electrode strip and the common electrode strip are adjacent.
  • the first upper electrode strip, the second upper electrode strip, the pixel electrode strip, and the common electrode strip extend in the same direction.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming a lower electrode layer on a base substrate; forming an upper electrode layer above the lower electrode layer to include a first upper electrode strip And a second upper electrode strip.
  • the lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate;
  • the array substrate includes a pixel electrode strip and a common electrode strip formed by the same film, and the pixel electrode strip and the common electrode strip both correspond to between the first upper electrode strip and the second upper electrode strip Area.
  • the manufacturing method further includes forming a first insulating layer including a bump.
  • forming the lower electrode layer includes forming a first lower electrode strip and a second lower electrode strip; the first lower electrode strip includes a first raised portion formed on the protrusion, the first A raised portion includes the pixel electrode strip; the second lower electrode strip includes a second raised portion formed on the protrusion, and the second raised portion includes the common electrode strip.
  • the manufacturing method further includes forming a second insulating layer covering the lower electrode layer before forming the upper electrode layer.
  • the upper surface of the second insulating layer includes a planar portion corresponding to at least the first upper electrode strip, the second upper electrode strip, and the first upper electrode strip and a region between the second upper electrode strips.
  • At least one embodiment of the present disclosure is a display device comprising the array substrate according to any of the above.
  • FIG. 1 is a schematic cross-sectional view showing a liquid crystal display device
  • FIG. 2A is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • 2B is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • 2C is a schematic top view of an upper electrode layer in an array substrate according to an embodiment of the present disclosure.
  • 3A is a comparison diagram of the electro-optic characteristic curve of the structure shown in FIG. 2A and the structure shown in FIG. 1;
  • 3B is a comparison diagram of electro-optic characteristic curves when the structures have different heights as shown in FIG. 2A;
  • FIG. 4 is a cross-sectional view of an array substrate according to another embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view of an array substrate according to another embodiment of the present disclosure.
  • 6A is a cross-sectional view of an array substrate according to still another embodiment of the present disclosure.
  • 6B is a schematic top view of an upper electrode layer in an array substrate according to still another embodiment of the present disclosure.
  • FIGS. 7A to 7E are schematic diagrams showing steps in a method of fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure.
  • the liquid crystal display device includes opposite substrates 01 and 02, and a plate electrode 05, an insulating layer 48 (for example, a gate insulating layer and a passivation insulating layer), and a plurality of strip electrodes therebetween. 06, alignment film 09 and liquid crystal layer 03.
  • One of the plate electrode 05 and the strip electrode 06 is a common electrode and the other is a pixel electrode.
  • a common voltage is applied to the common electrode, a pixel voltage is applied to the pixel electrode, and a voltage difference exists between the common voltage and the pixel voltage, so that a fringe electric field can be formed between the common electrode and the pixel electrode.
  • the electric field can be used to control the deflection of the liquid crystal in the liquid crystal layer 03.
  • the inventors of the present application have noted in the study that during the operation of the ADS mode liquid crystal display device shown in FIG. 1, the electric field intensity at the edge of the strip electrode 06 is the strongest, and the transmittance at the position is also relatively highest, and The electric field is weak at the intermediate position of the gap between the strip electrodes 06, in particular, the transverse electric field component is relatively small, so the transmittance at this position is relatively low and is a display weak region of the ADS display mode.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device including the array substrate.
  • the array substrate 100 includes a base substrate 10, and an upper electrode layer 60 and a lower electrode layer 50 thereon;
  • the electrode layer 60 includes adjacent first upper electrode strips 61 and second upper electrode strips 62.
  • the first upper electrode strips 61 and the second upper electrode strips 62 extend substantially in the same direction with strips formed therebetween.
  • the lower electrode layer 50 includes a portion that does not overlap with the first upper electrode strip 61 and the second upper electrode strip 62 in a direction perpendicular to the upper surface 10a of the base substrate 10 (for example, the portion is located on the first side) Between the mutually adjacent edges of the electrode strip 61 and the second upper electrode strip 62, a fringe electric field is formed between each of the first upper electrode strip 61 and the second upper electrode strip 62 and the lower electrode layer 50.
  • the array substrate includes a pixel electrode strip 71 and a common electrode strip 72 disposed in the same layer and adjacent to each other, and the pixel electrode strip 71 and the common electrode strip 72 are respectively applied with a pixel voltage and a common voltage during operation and both correspond to the first A region between the electrode strip 61 and the second upper electrode strip 62 forms an IPS electric field between the first upper electrode strip 61 and the second upper electrode strip 62.
  • the pixel electrode strip 71 and the common electrode strip 72 extending substantially along the extending direction of the first and second electrode strips are disposed between the first upper electrode strip 61 and the second upper electrode strip 62 (ie, An upper electrode strip 61, a second upper electrode strip 62, a pixel electrode strip 71 and a common electrode strip 72 extend substantially the same direction to form a lateral IPS electric field, so that the embodiment of the present disclosure can effectively raise the adjacent first upper layer.
  • the transmittance of the region between the electrode strip 61 and the second upper electrode strip 62; and the structure still has a strong electric field at the edge of the ADS mode, so that the transmittance of the entire device can be improved.
  • the center position of the region between the first upper electrode strip 61 and the second upper electrode strip 62 corresponds to the pixel electrode strip 71 and the common electrode strip
  • the area between 72 is equal to the distance from the mutually adjacent edges 61a, 62a of the first upper electrode strip 61 and the second upper electrode strip 62.
  • the center position of the region between the first upper electrode strip 61 and the second upper electrode strip 62 corresponds to the center position of the region between the pixel electrode strip 71 and the common electrode strip 72.
  • the electrode strip refers to a strip shape in which the electrode has a planar shape (that is, a plan view shape and an orthographic projection of the electrode strip on the base substrate 10).
  • the component A corresponding to the component B means that there is an overlapping portion between the component A and the component B in a direction perpendicular to the upper surface 10a of the base substrate 10.
  • the adjacent pixel electrode strip 71 and the common electrode strip 72 mean that no other pixel electrode or common electrode is disposed between the two.
  • the first upper electrode strip 61 and the second upper electrode strip 62 are adjacent to each other, and the other upper electrode strips included in the upper electrode layer are not disposed in the same direction.
  • the distance from the upper electrode layer 60 to the base substrate 10 of the array substrate in the embodiment of the present disclosure is greater than the distance 10 from the lower electrode layer 50 to the base substrate, that is, the base substrate 10 serves as a reference bottom surface.
  • the same layer arrangement of the pixel electrode strip 71 and the common electrode strip 72 means that the two are located side by side in the same layer.
  • both the pixel electrode strip 71 and the common electrode strip 72 may be located in the lower electrode layer 50 (see FIGS. 2A, 4, and 5), or both in the upper electrode layer 60 (see FIG. 6A), or in other conductive layers. in.
  • both the pixel electrode strip 71 and the common electrode strip 72 are located in the same transparent conductive layer or the same metal conductive layer (ie, both formed by a thin film forming the conductive layer).
  • the pixel electrode strip 71 and the common electrode strip 72 are located in the same pixel opening region of the array substrate for transmitting the imaging light, and the pixel electrode strip 71 and the common electrode strip 72 can be fabricated by using the transparent conductive layer. Affect the display effect.
  • both the pixel electrode strip 71 and the common electrode strip 72 may be located in the lower electrode layer 50. Some examples are specifically described below.
  • the lower electrode layer 50 includes a first lower electrode strip 51 and a second lower electrode strip 52, and in a direction perpendicular to the upper surface 10a of the base substrate 10, the first lower electrode strip 51 and the second lower electrode strip 52 Both include portions that do not overlap the first upper electrode strip 61 and the second upper electrode strip 62, which portions are used to form a fringe electric field with the upper electrode layer 60.
  • the first lower electrode strip 51 corresponds to the first upper electrode strip 61 to form a fringe electric field therebetween (for example, one of the first lower electrode strip 51 and the first upper electrode strip 61 is input pixel voltage and the other One is input with a common voltage), and the second lower electrode strip 52 corresponds to the second upper electrode strip 62 to form a fringe electric field therebetween (for example, one of the second lower electrode strip 52 and the second upper electrode strip 62 is The pixel voltage is input and the other is input to the common voltage).
  • the pixel electrode strip 71 and the common electrode strip 72 may be part of the first lower electrode strip 51 and the second lower electrode strip 52, respectively (as shown in FIGS. 2A and 4), and the portion is located on the first upper electrode strip 61. Between the second upper electrode strip 62 and the second upper electrode strip 62; or both the pixel electrode strip 71 and the common electrode strip 72 are spaced apart from the first lower electrode strip 51 and the second lower electrode strip 52 (as shown in FIG. 5).
  • the first lower electrode strip 51 is a lower pixel electrode strip that is input with a pixel voltage during operation
  • the second lower electrode strip 52 is a lower common electrode that is input with a common voltage during operation.
  • the first upper electrode strip 61 is an upper common electrode strip that is input with a common voltage during operation
  • the second upper electrode strip 62 is an upper pixel that is input with a pixel voltage during operation.
  • an edge electric field is formed between the upper electrode layer 60 and the lower electrode layer 50, and an IPS electric field is formed between the electrode strips included in each of the upper electrode layer 60 and the lower electrode layer 50, which is more advantageous for improvement. Transmittance.
  • first lower electrode strip 51 is a lower pixel electrode strip and the second lower electrode strip 52 is a lower common electrode strip
  • a part of the first lower electrode strip 51 serves as the pixel electrode strip 71 and a second lower electrode.
  • a portion of the strip 52 serves as the common electrode strip 72 (as shown in Figures 2A and 4).
  • the pixel electrode strip 71 and the common electrode strip 72 may also be located in the upper electrode layer 60 and spaced apart from both the first upper electrode strip 61 and the second upper electrode strip 62 (as shown in FIG. 6A).
  • both the upper electrode layer 60 and the lower electrode layer 50 may be transparent electrode layers, and the materials thereof may be indium tin oxide, indium zinc oxide, indium gallium zinc oxide or the like.
  • both the upper electrode layer 60 and the lower electrode layer 50 may be metal electrode layers, in which case the array substrate may be used, for example, in a reflective display device.
  • the lower electrode layer 50 includes adjacent first lower electrode strips 51 and second lower electrode strips 52 and the pixel electrode strips 71 and the common electrode strips 72 serve as first lower electrode strips, respectively.
  • At least one embodiment of the present disclosure provides an array substrate 100 including a substrate substrate 10 and a lower electrode layer 50 and an upper electrode layer 60 sequentially disposed on the substrate substrate 10.
  • the upper electrode layer 60 includes adjacent first upper electrode strips 61 and second upper electrode strips 62, the first upper electrode strip 61 is an upper common electrode strip, and the second upper electrode strip 62 is an upper pixel electrode strip.
  • the upper electrode layer 60 includes a plurality of first upper electrode strips 61, a plurality of second upper electrode strips 62, a first upper connecting portion 610, and a second upper connecting portion 620, and a first upper connecting portion.
  • the second upper connection portion 620 extends along the direction in which the plurality of second upper electrode strips 62 are arranged and The plurality of second upper electrode strips 62 are connected.
  • the lower electrode layer 50 includes adjacent first lower electrode strips 51 and second lower electrode strips 52.
  • the first lower electrode strip 51 is a lower pixel electrode strip; in a direction perpendicular to the upper surface 10a of the base substrate 10, the first lower electrode strip 51 overlaps the first upper electrode strip 61 and the first lower electrode strip 51 includes A portion of the first upper electrode strip 61 is exceeded to form a fringe electric field therebetween.
  • the second lower electrode strip 52 is a lower common electrode strip that overlaps the second upper electrode strip 62 and includes a portion that extends beyond the second upper electrode strip 62 to form a fringing electric field therebetween.
  • the first lower electrode strip 51 and the second upper electrode strip 62 may be connected together by applying a pixel voltage during operation, for example, through a via connection; the second lower electrode strip 52 and the first The upper electrode strips 61 can be connected together because they are applied with a common voltage during operation, for example, by via connections.
  • a portion of the first lower electrode strip 51 close to the second lower electrode strip 52 serves as a pixel electrode strip 71
  • a portion of the second lower electrode strip 52 close to the first lower electrode strip 51 serves as a common electrode.
  • the strip 72 that is, the pixel electrode strip 71 and the common electrode strip 72 are respectively a part of the first lower electrode strip 51 and the second lower electrode strip 52 in the lower electrode layer 50. Both the pixel electrode strip 71 and the common electrode strip 72 correspond to a region between the first upper electrode strip 61 and the second upper electrode strip 62, and an IPS electric field can be formed at a position corresponding to the region.
  • the center position A of the region between the first upper electrode strip 61 and the second upper electrode strip 62 is located between the pixel electrode strip 71 and the common electrode strip 72.
  • the first lower electrode strip 51 includes a first convex portion 510 protruding from the upper electrode layer 60 and a flat portion connected to the first convex portion 510 and corresponding to the first upper electrode strip 61, the first convex portion 510 serving as a pixel electrode strip 71 (the pixel electrode strip 71 from the bottom end of the first boss portion 510 to the top end thereof);
  • the second lower electrode strip 52 includes a second boss portion 520 protruding from the upper electrode layer 60 and the second boss portion 520 is connected and corresponds to the flat portion of the second upper electrode strip 62, and the second raised portion 520 serves as a common electrode strip 72 (the common electrode strip 72 is from the bottom end of the second raised portion 520 to the top end thereof).
  • the upper electrode layer 60 and the lower electrode layer 50 are located on the same side of the liquid crystal layer of the liquid crystal display device, and the pixel electrode strip is present due to the presence of the first protrusion portion 510 and the second protrusion portion 520 71 and the common electrode strip 72 are closer to the liquid crystal layer, so that a strong transverse electric field can be formed at a position corresponding to the region between the first upper electrode strip 61 and the second upper electrode strip 62, thereby effectively raising the position Transmittance rate.
  • the structure still has the characteristics that the edge electric field of the ADS mode is strong, the transmittance of the entire display device is improved.
  • the array substrate 100 further includes a first insulating layer 40 including protrusions 41 protruding from the upper electrode layer 60 (three protrusions 41 are shown in FIG. 2A), the protrusions 41 extends along a region between the first upper electrode strip 61 and the second upper electrode strip 62 and includes two inclined side walls that support the first raised portion 510 and the second raised portion 520, respectively.
  • the array substrate may include a thin film transistor, a gate insulating layer separating the gate of the thin film transistor and the active layer, the first insulating layer may be a gate insulating layer, and an organic material or an inorganic material or an organic material may be used. The layer is laminated with the inorganic material layer.
  • the pixel electrode strip 71 and the common electrode strip 72 included in the lower electrode layer 50 are raised by forming the first insulating layer 40 to form the bumps 41.
  • the pixel electrode strip 71 and the common electrode strip 72 may also be raised by other means.
  • the center position of the projection 41 substantially corresponds to the center position of the region between the first upper electrode strip 61 and the second upper electrode strip 62, and the gap between the adjacent projections 41
  • the center position substantially corresponds to the center position of the corresponding first upper electrode strip 61 or second upper electrode strip 62.
  • the cross-sectional shape of the projection 41 is trapezoidal.
  • the upper bottom of the trapezoid close to the upper electrode layer 50 substantially corresponds to the center position of the region between the first upper electrode strip 61 and the second upper electrode strip 62.
  • the IPS electric field formed by the pixel electrode strip 71 and the common electrode strip 72 respectively deposited on the inclined sidewalls of the projection 41 corresponds to the center of the region between the first upper electrode strip 61 and the second upper electrode strip 62, Thereby it is beneficial to increase the transmittance.
  • the pixel electrode strip 71 and the common electrode strip 72 may further include a portion formed at the top of the bump 41 to obtain a stronger IPS electric field.
  • the cross-sectional shape of the projections 41 may be semi-circular, triangular or any other shape.
  • the array substrate 100 may further include a second insulating layer 80 between the lower electrode layer 50 and the upper electrode layer 60, and the upper surface 81 of the second insulating layer 80 includes a planar portion, the planar portion being at least Corresponding to the first upper electrode strip 61, the second upper electrode strip 62, and a region between the first upper electrode strip 61 and the second upper electrode strip 62.
  • the planar portion it is advantageous to ensure the uniformity of the electric field formed by the upper and lower electrode layers.
  • the distance d between the top end 510a of the first boss portion 510 and the top end 520a of the second boss portion 520 to the lower surface 60a of the upper electrode layer 60 is greater than or equal to 1000 angstroms.
  • the thickness of the second insulating layer 80 at a position corresponding to the top of the protrusion 41 is greater than or equal to 1000 angstroms. This is advantageous in preventing the pixel electrode strip 71 and the common electrode strip 72 from affecting the fringe electric field formed between the upper and lower electrode layers.
  • the liquid crystal display device shown in Fig. 1 has a width of 2 ⁇ m and a distance between the strip electrodes 06 of 6 ⁇ m as shown in Fig. 1 .
  • a comparison curve of the structure shown in Fig. 2A and the electro-optical characteristic curve (VT curve) of the structure shown in Fig. 1 is shown in Fig. 3A.
  • the transmittance of the structure shown in FIG. 2A is significantly improved as shown in FIG. 1, and the transmittance of the entire display device is increased from 0.333 to 0.36, which is about 8%.
  • an electro-optical characteristic curve (VT curve) when the structures have different heights as shown in FIG. 2A is as shown in FIG. 3B.
  • VT curve electro-optical characteristic curve
  • the lower electrode layer 50 includes a first lower electrode strip 51 and a second lower electrode strip 52, and the pixel electrode strip 71 and the common electrode strip 72 are the first of the lower electrode layer 50, respectively. A portion of the lower electrode strip 51 and the second lower electrode strip 52.
  • the first lower electrode strip 51 and the second lower electrode strip 52 included in the lower electrode layer 50 are a lower pixel electrode strip and a lower common electrode strip, respectively, and the upper electrode layer 60 includes adjacent first upper electrodes.
  • the strip 61 and the second upper electrode strip 62 are an upper common electrode strip and an upper pixel electrode strip, respectively.
  • the main difference between this embodiment and the embodiment shown in FIG. 2A is that the first lower electrode strip 51 and the second lower electrode strip 52 do not include the convex portion, that is, the entire first lower electrode strip 51 and the entire second lower electrode strip.
  • the pixel electrode strip 71 a portion of the first lower electrode strip 51 adjacent to the second lower electrode strip 52 (the portion beyond the first upper electrode strip 61) serves as the pixel electrode strip 71, and the second lower electrode strip A portion of the 52 adjacent to the first lower electrode strip 51 (the portion exceeding the second upper electrode strip 62) serves as a common electrode strip 72, and the pixel electrode strip 71 and the common electrode strip 72 are located in the same layer as the first and second lower electrode strips side by side. And an IPS electric field is formed between the pixel electrode strip 71 and the common electrode strip 72.
  • the lower electrode layer 50 includes a first lower electrode strip 51, a second lower electrode strip 52, and further includes a space spaced apart from both the first and second lower electrode strips.
  • the pixel electrode strip 71 and the common electrode strip 72, the entire pixel electrode strip 71 and the entire common electrode strip 72 correspond to the area between the adjacent first upper electrode strip 61 and the second upper electrode strip 62.
  • the first lower electrode strip 51 and the second lower electrode strip 52 included in the lower electrode layer 50 are a lower pixel electrode strip and a lower common electrode strip, respectively
  • the upper electrode layer 60 includes a first upper electrode strip 61 and a second upper electrode.
  • the strip 62 is an upper common electrode strip and an upper pixel electrode strip, respectively; or the first lower electrode strip 51 and the second lower electrode strip 52 included in the lower electrode layer 50 are both lower common electrode strips, and the first electrode layer 60 is first.
  • the upper electrode strip 61 and the second upper electrode strip 62 are both upper pixel electrode strips; or the first lower electrode strip 51 and the second lower electrode strip 52 included in the lower electrode layer 50 are both lower pixel electrode strips, and the upper electrode layer
  • the first upper electrode strip 61 and the second upper electrode strip 62 of 60 are both upper common electrode strips.
  • a fringe electric field can be formed between the upper electrode layer 60 and the lower electrode layer 50.
  • the lower electrode layer 50 includes a continuous plate electrode and both the pixel electrode strip 71 and the common electrode strip 72 are located in the upper electrode layer 60.
  • the lower electrode layer 50 includes a plate electrode
  • the upper electrode layer 60 includes a first upper electrode strip 61 and a second upper electrode strip 62 overlapping the plate electrode.
  • the upper electrode layer 60 further includes a pixel electrode strip 71 and a common electrode strip 72 between the first upper electrode strip 61 and the second upper electrode strip 62 and forming a gap therebetween to form an IPS electric field.
  • the lower electrode layer 50 includes a plate electrode as a pixel electrode and the upper electrode layer 60 includes first and second upper electrode strips as a common electrode; or the lower electrode layer 50 includes a plate electrode as a common electrode and an upper electrode layer.
  • the first and second upper electrode strips included in the 60 are pixel electrodes. This can form a fringe electric field between the upper and lower electrode layers.
  • the upper electrode layer further includes an upper connecting portion 65 extending in the direction in which the first upper electrode strip 61 and the second upper electrode strip 62 are arranged and combined with the first upper electrode strip 61 and The two upper electrode strips 62 are connected.
  • the common electrode strip 72 may be connected to the upper connecting portion 65.
  • the pixel electrode strip 72 may be connected to the upper connection portion 65.
  • the upper electrode layer 65 may include a plurality of pixel electrode strips 71 and a connection portion 710 extending in the direction in which the plurality of pixel electrode strips 71 are arranged and connected to the plurality of pixel electrode strips 71.
  • a set of the pixel electrode strips 71 and the common electrode strips 72 are disposed between the adjacent first upper electrode strips 61 and the second upper electrode strips 62.
  • the width of the pixel electrode strip 71, the width of the common electrode strip 72, and the distance between the two are not too small in consideration of fabrication difficulty;
  • the transmittance of the region between the first upper electrode strip 61 and the second upper electrode strip 62 is preferably increased, and the distance between the pixel electrode strip 71 and the common electrode strip 72 is not too large.
  • the width of the pixel electrode strip 71, the width of the common electrode strip 72, and the sum of the distance between the pixel electrode strip 71 and the common electrode strip 72 are
  • the ratio of the distance between the first upper electrode strip 61 and the second upper electrode strip 62 is 1/4 to 1/3.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate 100, such as the array substrate shown in FIGS. 2A and 2B, the method includes: forming a lower electrode layer 50 on the substrate substrate 10; The upper electrode layer 60 located above the lower electrode layer 50 is formed to include the first upper electrode strip 61 and the second upper electrode strip 62.
  • the lower electrode layer 50 includes a portion that does not overlap the first upper electrode strip 61 and the second upper electrode strip 62 in a direction perpendicular to the upper surface 10a of the base substrate 10;
  • the array substrate 100 includes The pixel electrode strip 71 and the common electrode strip 72 formed by the same film, and the pixel electrode strip 71 and the common electrode strip 72 correspond to a region between the first upper electrode strip 61 and the second upper electrode strip 62.
  • the fabrication method may further include forming the first insulating layer 40 including the bumps 41.
  • forming the lower electrode layer 50 includes forming a first lower electrode strip 51 and a second lower electrode strip 52; the first lower electrode strip 51 includes a first convex portion 510 formed on the protrusion 41, the first convex portion
  • the starting portion 510 includes a pixel electrode strip 71; the second lower electrode strip 52 includes a second raised portion 520 formed on the protrusion 41, and the second raised portion 520 includes a common electrode strip 72.
  • the fabrication method further includes forming a second insulating layer 80 covering the lower electrode layer 50 before forming the upper electrode layer 60.
  • the upper surface 81 of the second insulating layer 80 includes a planar portion corresponding at least to the first upper electrode strip 61, the second upper electrode strip 62, and the first upper electrode strip 61 and the second upper electrode The area between strips 62.
  • the method of fabricating the array substrate shown in FIGS. 2A and 2B includes the following steps S71 to S74.
  • Step S71 As shown in FIG. 7A, a first insulating layer 40 including a plurality of bumps 41 is formed.
  • Step S72 As shown in FIG. 7B, a lower electrode film 50' covering the protrusions 41 is formed, and patterned to form a lower electrode layer 50 as shown in FIG. 7C so as to be adjacent to the lower electrode layer 50.
  • the first lower electrode strip 51 and the second lower electrode strip 52 are formed on at least two side walls of the same protrusion 41, respectively, to obtain a pixel electrode strip 71 and a common electrode strip 72.
  • Step S73 As shown in FIG. 7D, a second insulating layer 80 covering the lower electrode layer 50 is formed.
  • Step S74 As shown in FIG. 7E, an upper electrode film 60' covering the second insulating layer 80 is formed, and patterned to form an upper electrode layer 60 as shown in FIGS. 2A and 2B, so that the pixel electrode strip
  • the 71 and the common electrode strip 72 correspond to a region between the first upper electrode strip 61 and the second upper electrode strip 62 included in the upper electrode layer.
  • At least one embodiment of the present disclosure further provides a display device including the array substrate 100 according to any of the above embodiments.
  • the display device of the embodiment of the present disclosure may include an array substrate 100 and a counter substrate 200, and the array substrate 100 and the opposite substrate 200 are opposed to each other and formed by a sealant to form a liquid crystal cell.
  • a liquid crystal layer 300 is disposed therein and an alignment film 09 is disposed on both sides of the liquid crystal layer 300.
  • the counter substrate 200 is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate 100 is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the display device further includes a backlight that provides backlighting for the array substrate 100.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure can effectively improve the transmittance of the region between the first upper electrode strip and the second upper electrode strip; and the structure still has a strong electric field at the edge of the ADS mode. Features, so the transmittance of the entire display device can be improved.

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Abstract

一种阵列基板以及包括该阵列基板的显示装置，该阵列基板 (100) 包括：上电极层 (60)，其位于衬底基板 (10) 上并且包括第一上电极条 (61) 和第二上电极条 (62)；下电极层 (50)，其位于所述衬底基板 (10) 与所述上电极层(60) 之间。在垂直于所述衬底基板 (10) 的上表面 (10a) 的方向上，所述下电极层 (50) 包括与所述第一上电极条 (61) 和所述第二上电极条 (62) 都不交叠的部分。所述阵列基板 (100) 包括同层设置的像素电极条 (71) 和公共电极条 (72)，并且所述像素电极条 (71) 和所述公共电极条 (72) 都对应于所述第一上电极条 (61) 和所述第二上电极条 (62) 之间的区域。该阵列基板 (100) 可以提高包括该阵列基板 (100) 的显示装置的透过率。

Description

阵列基板及显示装置 技术领域
本公开实施例涉及阵列基板以及包括该阵列基板的显示装置。
背景技术
液晶显示装置已经在监视器、电视、笔记本电脑等各领域得到了广泛的应用。液晶显示装置包括公共电极和像素电极，通过公共电极和像素电极之间形成的电场来控制液晶分子的偏转。
采用ADS(Advanced Super Dimension Switch)显示模式的液晶显示装置由于其宽视角而被广泛应用。在ADS显示模式中，像素电极和公共电极分别位于液晶显示装置的阵列基板包括的不同层中，从而在二者之间形成边缘电场。
此外，液晶显示装置也可以采用其它显示模式，例如，在IPS(In-plane Switching)显示模式中，像素电极和公共电极位于阵列基板包括的同一层中，从而在二者之间形成IPS电场。
发明内容
本公开实施例提供一种阵列基板及其制作方法、以及包括该阵列基板的显示装置，该阵列基板可以提高包括该阵列基板的显示装置的透过率。
本公开的至少一个实施例提供一种阵列基板，其包括：衬底基板；上电极层，其位于所述衬底基板上并且包括第一上电极条和第二上电极条；下电极层，其位于所述衬底基板与所述上电极层之间，其中，在垂直于所述衬底基板的上表面的方向上，所述下电极层包括与所述第一上电极条和所述第二上电极条都不交叠的部分。所述阵列基板包括同层设置的像素电极条和公共电极条，并且所述像素电极条和所述公共电极条都对应于所述第一上电极条和所述第二上电极条之间的区域。
例如，所述第一上电极条和所述第二上电极条之间的区域的中心位置对应于所述像素电极条和所述公共电极条之间的区域，所述中心位置到所述第 一上电极条和所述第二上电极条的相互靠近的边缘的距离相等。
例如，所述下电极层包括第一下电极条和第二下电极条；在垂直于所述衬底基板的上表面的方向上，所述第一下电极条和所述第二下电极条都包括与所述第一上电极条和所述第二上电极条都不交叠的部分。
例如，所述第一下电极条为下像素电极条，所述第二下电极条为下公共电极条；所述第一上电极条为上公共电极条，所述第二上电极条为上像素电极条。
例如，所述第一下电极条的一部分作为所述像素电极条，所述第二下电极条的一部分作为所述公共电极条。
例如，所述第一下电极条包括凸向所述上电极层的第一凸起部，所述第一凸起部作为所述像素电极条；所述第二下电极条包括凸向所述上电极层的第二凸起部，所述第二凸起部作为所述公共电极条。
例如，所述的阵列基板还包括：第一绝缘层，其包括凸起，所述凸起支撑所述第一凸起部和所述第二凸起部。
例如，所述凸起的中心与所述第一上电极条和所述第二上电极条之间的区域的中心对应。
例如，所述的阵列基板还包括位于所述下电极层和所述上电极层之间的第二绝缘层，所述第二绝缘层的上表面包括平面部分，所述平面部分至少对应于所述第一上电极条、所述第二上电极条、以及所述第一上电极条和所述第二上电极条之间的区域。
例如，所述第一凸起部的顶端和所述第二凸起部的顶端到所述上电极层的下表面的距离都大于或等于1000埃。
例如，在以上任一实施例中，所述第一上电极条与所述第二上电极条相邻，并且所述第一下电极条和所述第二下电极条相邻。
例如，所述像素电极条和所述公共电极条位于所述下电极层中并且与所述第一下电极条和所述第二下电极条都间隔开。例如，所述第一上电极条和所述第二上电极条相邻。
例如，所述像素电极条和所述公共电极条位于所述上电极层中并且与所述第一上电极条和所述第二上电极条都间隔开。
例如，所述像素电极条的宽度、所述公共电极条的宽度、以及所述像素 电极条与所述公共电极条之间的距离之和与所述第一上电极条和所述第二上电极条之间的距离之比为1/4-1/3。
例如，所述像素电极条和所述公共电极条相邻。
例如，所述第一上电极条、所述第二上电极条、所述像素电极条和所述公共电极条的延伸方向相同。
本公开的至少一个实施例提供一种阵列基板的制作方法，其包括：在衬底基板上形成下电极层；形成位于所述下电极层上方的上电极层，使其包括第一上电极条和第二上电极条。在该方法中，在垂直于所述衬底基板的上表面的方向上，所述下电极层包括与所述第一上电极条和所述第二上电极条都不交叠的部分；所述阵列基板包括由通过同一薄膜形成的像素电极条和公共电极条，并且所述像素电极条和所述公共电极条都对应于所述第一上电极条和所述第二上电极条之间的区域。
例如，所述的制作方法还包括：形成包括凸起的第一绝缘层。在该方法中，形成所述下电极层包括形成第一下电极条和第二下电极条；所述第一下电极条包括形成在所述凸起上的第一凸起部，所述第一凸起部包括所述像素电极条；所述第二下电极条包括形成在所述凸起上的第二凸起部，所述第二凸起部包括所述公共电极条。
例如，所述的制作方法还包括：在形成所述上电极层之前，形成覆盖所述下电极层的第二绝缘层。在该方法中，所述第二绝缘层的上表面包括平面部分，所述平面部分至少对应于所述第一上电极条、所述第二上电极条、以及所述第一上电极条和所述第二上电极条之间的区域。
本公开的至少一个实施例一种显示装置，包括根据以上任一项所述的阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种液晶显示装置的剖视示意图；
图2A为本公开实施例提供的阵列基板的剖视示意图；
图2B为本公开实施例提供的阵列基板的俯视示意图；
图2C为本公开实施例提供的阵列基板中上电极层的俯视示意图；
图3A为如图2A所示结构与如图1所示结构的电光特性曲线的对比图；
图3B为如图2A所示结构具有不同高度的凸起时的电光特性曲线对比图；
图4为本公开另一实施例提供的阵列基板的剖视示意图；
图5为本公开另一实施例提供的阵列基板的剖视示意图；
图6A为本公开再一实施例提供的阵列基板的剖视示意图；
图6B为本公开实施例再一实施例提供的阵列基板中上电极层的俯视示意图；
图7A至图7E为本公开实施例提供的阵列基板的制作方法中各步骤的示意图；
图8为本公开实施例提供的显示装置的剖视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种ADS模式液晶显示装置的剖视示意图。如图1所示，该液 晶显示装置包括相对的基板01和02、以及位于二者之间的板状电极05、绝缘层48(例如栅绝缘层和钝化绝缘层)、多个条状电极06、配向膜09和液晶层03。板状电极05和条状电极06中的一个为公共电极且另一个为像素电极。在液晶显示装置的工作过程中，公共电极被施加公共电压，像素电极被施加像素电压，由于公共电压与像素电压之间存在电压差，从而公共电极与像素电极之间可形成边缘电场，该边缘电场可用于控制液晶层03中的液晶的偏转。
本申请的发明人在研究中注意到，在图1所示的ADS模式液晶显示装置在工作过程中，条状电极06边缘的电场强度最强，该位置处的透过率也相对最高，而在条状电极06之间的间隙的中间位置处电场较弱，特别是横向电场分量比较小，因此该位置处的透过率相对较低并且是ADS显示模式的显示弱区。
本公开实施例提供一种阵列基板、其制作方法、以及包括该阵列基板的显示装置。
在本公开的至少一个实施例中，如图2A、图4、图5和图6A所示，阵列基板100包括衬底基板10、以及位于其上的上电极层60和下电极层50；上电极层60包括相邻的第一上电极条61和第二上电极条62，例如，第一上电极条61和第二上电极条62的延伸方向大致相同且二者之间形成有条状开口；下电极层50包括与第一上电极条61和第二上电极条62在垂直于衬底基板10的上表面10a的方向上都不交叠的部分(例如，该部分位于第一上电极条61和第二上电极条62的相互靠近的边缘之间)，以在第一上电极条61和第二上电极条62中的每个与下电极层50之间形成边缘电场。而且，该阵列基板包括同层设置且相邻的像素电极条71和公共电极条72，像素电极条71和公共电极条72在工作时分别被施加像素电压和公共电压并且都对应于第一上电极条61和第二上电极条62之间的区域，以在第一上电极条61和第二上电极条62之间形成IPS电场。
在本公开实施例中，由于在第一上电极条61和第二上电极条62之间设置大致沿第一、二电极条的延伸方向延伸的像素电极条71和公共电极条72(即第一上电极条61、第二上电极条62、像素电极条71和公共电极条72的延伸方向大致相同)，以形成横向的IPS电场，因而本公开实施例可以有 效提升相邻的第一上电极条61和第二上电极条62之间区域的透过率；并且该结构依然具有ADS模式边缘电场较强的特点，因此整个装置的透过率可得到提升。
例如，在本公开的至少一个实施例中，第一上电极条61和第二上电极条62之间区域的中心位置(参见图2A中的位置A)对应于像素电极条71和公共电极条72之间的区域，该中心位置到第一上电极条61和第二上电极条62的相互靠近的边缘61a、62a的距离相等。例如，第一上电极条61和第二上电极条62之间区域的中心位置对应于像素电极条71和公共电极条72之间区域的中心位置。这样有利于使像素电极条71和公共电极条72之间形成的IPS电场位于第一上电极条61和第二上电极条62之间区域的中部，从而更有利于提高透过率。
在本公开的实施例中，有以下几点需要说明。
第一，电极条是指电极的平面形状(即俯视形状，也为电极条在衬底基板10上的正投影的形状)为条状。
第二，元件A对应于元件B是指在垂直于衬底基板10的上表面10a的方向上元件A与元件B之间有交叠部分。
第三，像素电极条71和公共电极条72相邻是指二者之间未设置其它像素电极或公共电极。类似地，第一上电极条61和第二上电极条62相邻是指二者之间未设置上电极层包括的与之延伸方向相同的其它上电极条。
第四，本公开实施例中的上电极层60到阵列基板的衬底基板10的距离大于下电极层50到该衬底基板的距离10，即该衬底基板10作为参照底面。
第五，像素电极条71和公共电极条72同层设置是指二者并排位于同一层中。例如，像素电极条71和公共电极条72都可以位于下电极层50中(参见图2A、图4和图5)，或者都位于上电极层60中(参见图6A)，或者位于其它导电层中。
例如，在本公开的至少一个实施例中，像素电极条71和公共电极条72都位于同一透明导电层或同一金属导电层中(即都通过形成该导电层的薄膜形成)。
在本公开实施例中，像素电极条71和公共电极条72位于阵列基板的用于透过成像光线的同一像素开口区，通过采用透明导电层制作像素电极条71 和公共电极条72，可以避免影响显示效果。
例如，像素电极条71和公共电极条72都可以位于下电极层50中。一些示例具体说明如下。
例如，下电极层50包括第一下电极条51和第二下电极条52，并且在垂直于衬底基板10的上表面10a的方向上，第一下电极条51和第二下电极条52都包括与第一上电极条61和第二上电极条62都不交叠的部分，该部分用于与上电极层60之间形成边缘电场。例如，第一下电极条51对应于第一上电极条61以在二者之间形成边缘电场(例如第一下电极条51和第一上电极条61中的一个为被输入像素电压且另一个被输入公共电压)，并且第二下电极条52对应于第二上电极条62以在二者之间形成边缘电场(例如第二下电极条52和第二上电极条62中的一个被输入像素电压且另一个被输入公共电压)。
例如，像素电极条71和公共电极条72可以分别为第一下电极条51和第二下电极条52的一部分(如图2A和图4所示)，并且该部分位于第一上电极条61和第二上电极条62之间；或者，像素电极条71和公共电极条72都与第一下电极条51和第二下电极条52间隔开(如图5所示)。
例如，在本公开的至少一个实施例中，第一下电极条51为在工作时被输入像素电压的下像素电极条，第二下电极条52为在工作时被输入公共电压的下公共电极条，从而在二者之间可以形成IPS电场；第一上电极条61为在工作时被输入公共电压的上公共电极条，第二上电极条62为在工作时被输入像素电压的上像素电极条，从而在二者之间可以形成IPS电场。在本公开实施例中，上电极层60、下电极层50之间形成有边缘电场，并且上电极层60、下电极层50各自包括的电极条之间形成有IPS电场，这样更有利于提高透过率。
例如，在第一下电极条51为下像素电极条并且第二下电极条52为下公共电极条的情况下，第一下电极条51的一部分作为所述像素电极条71，第二下电极条52的一部分作为所述公共电极条72(如图2A和图4所示)。
例如，像素电极条71和公共电极条72也可以都位于上电极层60中并且与第一上电极条61和第二上电极条62都间隔开(如图6A所示)。
例如，在本公开的上述任一实施例中，上电极层60和下电极层50都可 以为透明电极层，其材料都可以采用氧化铟锡、氧化铟锌、氧化铟镓锌或类似透明导电材料；或者，上电极层60和下电极层50都可以为金属电极层，在这种情况下，阵列基板例如可以用于反射式显示装置中。
下面结合附图，对本公开实施例提供的阵列基板、其制作方法和显示装置进行详细描述。
例如，在本公开的至少一个实施例中，下电极层50包括相邻的第一下电极条51和第二下电极条52并且像素电极条71和公共电极条72分别作为第一下电极条51和第二下电极条52的一部分，并且第一下电极条51和第二下电极条52都包括相连的凸起部分和平坦部分(例如凸起部分和平坦部分一体形成)。
例如，如图2A至图2C所示，本公开的至少一个实施例提供一种阵列基板100，其包括衬底基板10和依次位于衬底基板10上的下电极层50和上电极层60。
上电极层60包括相邻的第一上电极条61和第二上电极条62，第一上电极条61为上公共电极条，第二上电极条62为上像素电极条。例如，如图2C所示，上电极层60包括多个第一上电极条61、多个第二上电极条62、第一上连接部610和第二上连接部620，第一上连接部610沿该多个第一上电极条61的排列方向延伸并且与该多个第一上电极条61连接，第二上连接部620沿该多个第二上电极条62的排列方向延伸并且与该多个第二上电极条62连接。
下电极层50包括相邻的第一下电极条51和第二下电极条52。第一下电极条51为下像素电极条；在垂直于衬底基板10的上表面10a的方向上，第一下电极条51与第一上电极条61交叠并且第一下电极条51包括超出第一上电极条61的部分，以在二者之间形成边缘电场。类似地，第二下电极条52为下公共电极条，与第二上电极条62交叠并且包括超出第二上电极条62的部分以在二者之间形成边缘电场。在本公开实施例中，第一下电极条51与第二上电极条62由于在工作时都被施加像素电压而可以连接在一起，例如通过过孔连接；第二下电极条52与第一上电极条61由于在工作时都被施加公共电压而可以连接在一起，例如通过过孔连接。
如图2A和图2B所示，第一下电极条51的靠近第二下电极条52的部分 作为像素电极条71，第二下电极条52的靠近第一下电极条51的部分作为公共电极条72，也就是说，像素电极条71和公共电极条72分别为下电极层50中的第一下电极条51和第二下电极条52的一部分。像素电极条71和公共电极条72都对应于第一上电极条61和第二上电极条62之间的区域，可以在对应于该区域的位置处形成IPS电场。
例如，第一上电极条61和第二上电极条62之间的区域的中心位置A位于像素电极条71和公共电极条72之间。这样有利于使像素电极条71和公共电极条72之间形成的IPS电场位于第一上电极条61和第二上电极条62之间区域的中部，从而有利于提高透过率。
例如，第一下电极条51包括凸向上电极层60的第一凸起部510以及与第一凸起部510连接且对应于第一上电极条61的平坦部分，第一凸起部510作为像素电极条71(像素电极条71从第一凸起部510的底端到其顶端)；第二下电极条52包括凸向上电极层60的第二凸起部520以及与第二凸起部520连接且对应于第二上电极条62的平坦部分，第二凸起部520作为公共电极条72(公共电极条72从第二凸起部520的底端到其顶端)。在阵列基板应用于液晶显示装置时，上电极层60和下电极层50位于液晶显示装置的液晶层的同一侧，由于第一凸起部510和第二凸起部520的存在，像素电极条71和公共电极条72到液晶层的距离更近，因而可以在对应于第一上电极条61和第二上电极条62之间区域位置处形成较强的横向电场，从而有效提升该位置处的透过率。此外，由于该结构依然具有ADS模式边缘电场较强的特点，因此整个显示装置的透过率都得到了提升。
例如，如图2A和图2B所示，阵列基板100还包括第一绝缘层40，其包括凸向上电极层60的凸起41(图2A中示出了3个凸起41)，该凸起41沿第一上电极条61和第二上电极条62之间的区域延伸并且包括两个倾斜的侧壁，该侧壁分别支撑第一凸起部510和第二凸起部520。例如，阵列基板可以包括薄膜晶体管、将该薄膜晶体管的栅极和有源层间隔开的栅绝缘层，该第一绝缘层可以为栅绝缘层，并且可以采用有机材料或无机材料或有机材料层与无机材料层的叠层制作。
例如，在本公开的至少一个实施例中，通过使第一绝缘层40形成凸起41的方式抬高下电极层50包括的像素电极条71和公共电极条72。在本公开 的其它实施例中，也可以通过其它方式抬高像素电极条71和公共电极条72。
例如，如图2A中的虚线所示，凸起41的中心位置与第一上电极条61和第二上电极条62之间区域的中心位置大致对应，并且相邻凸起41之间的间隙中心位置与相应的第一上电极条61或第二上电极条62的中心位置大致对应。例如，凸起41的截面形状为梯形。例如，该梯形的靠近上电极层50的上底与第一上电极条61和第二上电极条62之间区域的中心位置大致对应。这样有利于使分别沉积在凸起41两倾斜侧壁上的像素电极条71和公共电极条72形成的IPS电场对应于第一上电极条61和第二上电极条62之间区域的中心，从而有利于提高透过率。
例如，在凸起41的截面形状为梯形的情况下，像素电极条71和公共电极条72还可以包括形成在凸起41的顶部的部分，以获得更强的IPS电场。本公开实施例不限定凸起41的形状。例如，凸起41的剖面形状可以为半圆形、三角形或其它任意形状。
例如，如图2A所示，阵列基板100还可以包括位于下电极层50和上电极层60之间的第二绝缘层80，第二绝缘层80的上表面81包括平面部分，该平面部分至少对应于第一上电极条61、第二上电极条62、以及第一上电极条61和第二上电极条62之间的区域。通过形成该平面部分，有利于保证上、下电极层形成的电场的均匀性。
例如，第一凸起部510的顶端510a和第二凸起部520的顶端520a到上电极层60的下表面60a的距离d大于或等于1000埃。以图2A所示的结构为例，第二绝缘层80在凸起41的顶部对应的位置处的厚度大于或等于1000埃。这样有利于避免像素电极条71和公共电极条72影响上、下电极层之间形成的边缘电场。
下面结合TechWiz LCD软件对于本公开的至少一个实施例的模拟结果，对各电极层包括的电极的尺寸的示例进行说明。
示例1
如图2A所示，第一下电极条51和第二下电极条52的宽度W 5＝7μm，第一下电极条51和第二下电极条52之间的距离W 7＝1μm，第一上电极条61的宽度W 61＝第二上电极条62的宽度W 62＝2μm，第一上电极条61和第二上电极条62之间的距离W 6＝6μm；梯形截面的凸起41的上底宽度D 2、下底宽 度D 1和高度H(图2A中未标出D 2、D 1和H)分别为：D 2＝1μm，D 1＝2μm，H＝0.5μm。如图1所示的液晶显示装置作为对比项，如图1所示，条状电极06的宽度为2μm且条状电极06之间的距离为6μm。
在该示例中，如图2A所示结构与如图1所示结构的电光特性曲线(VT曲线)的对比曲线如图3A所示。从图3A可以看出，如图2A所示结构的透过率比如图1所示结构有明显提升，整个显示装置的透过率由0.333提高到0.36，提升幅度大约8％。
示例2
对于如图2A所示结构，W 5＝7μm，W 7＝1μm，W 61＝W 62＝2μm，W 6＝6μm；D 2＝1μm，D 1＝2μm，H＝0.3～0.5μm。
在该示例中，如图2A所示结构具有不同高度的凸起时的电光特性曲线(VT曲线)如图3B所示。从图3B可以看出，随着凸起高度的提升，驱动电压略微下降，透过率略有上升，但差异不大。
例如，在本公开的至少一个实施例中，下电极层50包括第一下电极条51和第二下电极条52，并且像素电极条71和公共电极条72分别为下电极层50的第一下电极条51和第二下电极条52的一部分。
如图4所示，下电极层50包括的第一下电极条51和第二下电极条52分别为下像素电极条和下公共电极条，上电极层60包括的相邻的第一上电极条61和第二上电极条62分别为上公共电极条和上像素电极条。本实施例与如图2A所示实施例的主要区别在于：第一下电极条51和第二下电极条52不包括凸起部，即整个第一下电极条51和整个第二下电极条52都是平坦的；在该实施例中，第一下电极条51的靠近第二下电极条52的部分(该部分超出第一上电极条61)作为像素电极条71，第二下电极条52的靠近第一下电极条51的部分(该部分超出第二上电极条62)作为公共电极条72，像素电极条71和公共电极条72与第一、二下电极条并排位于同一层中并且像素电极条71和公共电极条72之间形成IPS电场。
例如，在本公开的至少一个实施例中，如图5所示，下电极层50包括第一下电极条51、第二下电极条52并且还包括与第一、二下电极条都间隔开的像素电极条71和公共电极条72，整个像素电极条71和整个公共电极条72都对应于相邻的第一上电极条61和第二上电极条62之间的区域。
例如，下电极层50包括的第一下电极条51和第二下电极条52分别为下像素电极条和下公共电极条，上电极层60包括的第一上电极条61和第二上电极条62分别为上公共电极条和上像素电极条；或者，下电极层50包括的第一下电极条51和第二下电极条52都为下公共电极条，并且上电极层60的第一上电极条61和第二上电极条62都为上像素电极条；或者，下电极层50包括的第一下电极条51和第二下电极条52都为下像素电极条，并且上电极层60的第一上电极条61和第二上电极条62都为上公共电极条。这样，在上电极层60和下电极层50之间可以形成边缘电场。
例如，在本公开的至少一个实施例中，下电极层50包括连续的板状电极并且像素电极条71和公共电极条72都位于上电极层60中。
如图6A所示，下电极层50包括板状电极，上电极层60包括与该板状电极交叠的第一上电极条61和第二上电极条62。上电极层60还包括位于第一上电极条61和第二上电极条62之间且与二者之间形成间隙的像素电极条71和公共电极条72，以形成IPS电场。
例如，下电极层50包括的板状电极为像素电极并且上电极层60包括的第一、二上电极条为公共电极；或者，下电极层50包括的板状电极为公共电极并且上电极层60包括的第一、二上电极条为像素电极。这样可以在上、下电极层之间形成边缘电场。
由于第一、二上电极条都为像素电极或者都为公共电极，因此二者可以彼此连接。例如，如图6B所示，上电极层还包括上连接部65，上连接部65沿第一上电极条61和第二上电极条62的排列方向延伸并且与第一上电极条61和第二上电极条62连接。
例如，如图6B所示，在第一、二上电极条都为公共电极的情况下，公共电极条72也可以与上连接部65连接。例如，在第一、二上电极条都为像素电极的情况下，像素电极条72也可以与上连接部65连接。
例如，上电极层65可以包括多个像素电极条71以及连接部710，连接部710沿该多个像素电极条71的排列方向延伸并且与该多个像素电极条71连接。在这种情况下，如图6B所示，相邻的第一上电极条61和第二上电极条62之间设置有一组像素电极条71和公共电极条72。
在本公开的如图6A和图6B所示的实施例中，考虑到制作难度，像素电 极条71的宽度、公共电极条72的宽度以及二者之间的距离不宜太小；此外，为了更好地提高第一上电极条61和第二上电极条62之间区域的透过率，像素电极条71和公共电极条72之间的距离也不宜太大。综合考虑，例如，沿像素电极条71和公共电极条72的排列方向，像素电极条71的宽度、公共电极条72的宽度、以及像素电极条71与公共电极条72之间的距离之和与第一上电极条61和第二上电极条62之间的距离之比为1/4～1/3。
例如，本公开的至少一个实施例提供一种阵列基板100的制作方法，以如图2A和图2B所示的阵列基板为例，该方法包括：在衬底基板10上形成下电极层50；形成位于下电极层50上方的上电极层60，使其包括第一上电极条61和第二上电极条62。在该方法中，在垂直于衬底基板10的上表面10a的方向上，下电极层50包括与第一上电极条61和第二上电极条62都不交叠的部分；阵列基板100包括由通过同一薄膜形成的像素电极条71和公共电极条72，并且像素电极条71和公共电极条72都对应于第一上电极条61和第二上电极条62之间的区域。
例如，该制作方法还可以包括形成包括凸起41的第一绝缘层40。在该方法中，形成下电极层50包括形成第一下电极条51和第二下电极条52；第一下电极条51包括形成在凸起41上的第一凸起部510，第一凸起部510包括像素电极条71；第二下电极条52包括形成在凸起41上的第二凸起部520，第二凸起部520包括公共电极条72。
例如，该制作方法还包括：在形成上电极层60之前，形成覆盖下电极层50的第二绝缘层80。在该方法中，第二绝缘层80的上表面81包括平面部分，该平面部分至少对应于第一上电极条61、第二上电极条62、以及第一上电极条61和第二上电极条62之间的区域。
例如，如图7A至图7E所示，如图2A和图2B所示的阵列基板的制作方法包括以下步骤S71至步骤S74。
步骤S71：如图7A所示，形成包括多个凸起41的第一绝缘层40。
步骤S72：如图7B所示，形成覆盖凸起41的下电极薄膜50’，并且对其进行图案化处理后形成如图7C所示的下电极层50，使下电极层50中相邻的第一下电极条51和第二下电极条52分别至少形成在同一凸起41的两个侧壁上，以得到像素电极条71和公共电极条72。
步骤S73：如图7D所示，形成覆盖下电极层50的第二绝缘层80。
步骤S74：如图7E所示，形成覆盖第二绝缘层80的上电极薄膜60’，并且对其进行图案化处理后形成如图2A和图2B所示的上电极层60，使像素电极条71和公共电极条72对应于上电极层包括的第一上电极条61、第二上电极条62之间的区域。
例如，本公开的至少一个实施例还提供一种显示装置，其包括根据以上任一项实施例所述的阵列基板100。
例如，如图8所示，本公开实施例的显示装置可以包括阵列基板100与对置基板200，阵列基板100与对置基板200彼此对置且通过封框胶以形成液晶盒，在液晶盒中设置有液晶层300并且在液晶层300两侧设置有配向膜09。该对置基板200例如为彩膜基板。阵列基板100的每个像素单元的像素电极用于施加电场以对液晶材料的旋转程度进行控制从而进行显示操作。在一些实施例中，该显示装置还包括为阵列基板100提供背光的背光源。
例如，该显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例提供的阵列基板及其制作方法和显示装置中，由于在第一上电极条和第二上电极条之间设置沿第一、二电极条的延伸方向延伸的像素电极条和公共电极条，以形成横向的IPS电场，因而本公开实施例可以有效提升第一上电极条和第二上电极条之间区域的透过率；并且该结构依然具有ADS模式边缘电场较强的特点，因此整个显示装置的透过率可得到提升。
有以下几点需要说明：(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计；(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度并非按照实际比例绘制，而是被一定程度放大；(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2017年7月11日递交的中国专利申请第201710561133.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板；
    上电极层，其位于所述衬底基板上并且包括第一上电极条和第二上电极条；
    下电极层，其位于所述衬底基板与所述上电极层之间，其中，在垂直于所述衬底基板的上表面的方向上，所述下电极层包括与所述第一上电极条和所述第二上电极条都不交叠的部分，
    其中，所述阵列基板包括同层设置的像素电极条和公共电极条，所述像素电极条和所述公共电极条都对应于所述第一上电极条和所述第二上电极条之间的区域。
  2. 根据权利要求1所述的阵列基板，其中，所述第一上电极条和所述第二上电极条之间的区域的中心位置对应于所述像素电极条和所述公共电极条之间的区域，所述中心位置到所述第一上电极条和所述第二上电极条的相互靠近的边缘的距离相等。
  3. 根据权利要求1或2所述的阵列基板，其中，
    所述下电极层包括第一下电极条和第二下电极条；在垂直于所述衬底基板的上表面的方向上，所述第一下电极条和所述第二下电极条都包括与所述第一上电极条和所述第二上电极条都不交叠的部分。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一下电极条为下像素电极条，所述第二下电极条为下公共电极条；
    所述第一上电极条为上公共电极条，所述第二上电极条为上像素电极条。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第一下电极条的一部分作为所述像素电极条，所述第二下电极条的一部分作为所述公共电极条。
  6. 根据权利要求4或5所述的阵列基板，其中，
    所述第一下电极条包括凸向所述上电极层的第一凸起部，所述第一凸起部作为所述像素电极条；
    所述第二下电极条包括凸向所述上电极层的第二凸起部，所述第二凸起 部作为所述公共电极条。
  7. 根据权利要求6所述的阵列基板，还包括：
    第一绝缘层，其包括凸起，所述凸起支撑所述第一凸起部和所述第二凸起部。
  8. 根据权利要求6或7所述的阵列基板，还包括位于所述下电极层和所述上电极层之间的第二绝缘层，
    其中，所述第二绝缘层的上表面包括平面部分，所述平面部分至少对应于所述第一上电极条、所述第二上电极条、以及所述第一上电极条和所述第二上电极条之间的区域。
  9. 根据权利要求6-8中任一项所述的阵列基板，其中，所述第一凸起部的顶端和所述第二凸起部的顶端到所述上电极层的下表面的距离都大于或等于1000埃。
  10. 根据权利要求4-9中任一项所述的阵列基板，其中，所述第一上电极条与所述第二上电极条相邻，并且所述第一下电极条和所述第二下电极条相邻。
  11. 根据权利要求3或4所述的阵列基板，其中，所述像素电极条和所述公共电极条位于所述下电极层中并且与所述第一下电极条和所述第二下电极条都间隔开。
  12. 根据权利要求11所述的阵列基板，其中，所述第一上电极条和所述第二上电极条相邻。
  13. 根据权利要求1-4中任一项所述的阵列基板，其中，所述像素电极条和所述公共电极条位于所述上电极层中并且与所述第一上电极条和所述第二上电极条都间隔开。
  14. 根据权利要求13所述的阵列基板，其中，所述像素电极条的宽度、所述公共电极条的宽度、以及所述像素电极条与所述公共电极条之间的距离之和与所述第一上电极条和所述第二上电极条之间的距离之比为1/4-1/3。
  15. 根据权利要求1-14中任一项所述的阵列基板，其中，所述像素电极条和所述公共电极条相邻。
  16. 根据权利要求1-15中任一项所述的阵列基板，其中，所述第一上电极条、所述第二上电极条、所述像素电极条和所述公共电极条的延伸方向相 同。
  17. 一种显示装置，包括根据权利要求1-16中任一项所述的阵列基板。
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