WO2022048249A1 - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
WO2022048249A1
WO2022048249A1 PCT/CN2021/101270 CN2021101270W WO2022048249A1 WO 2022048249 A1 WO2022048249 A1 WO 2022048249A1 CN 2021101270 W CN2021101270 W CN 2021101270W WO 2022048249 A1 WO2022048249 A1 WO 2022048249A1
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Prior art keywords
line contact
bit line
wire
semiconductor structure
wires
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Ceased
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PCT/CN2021/101270
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English (en)
French (fr)
Inventor
黄晨
蔡孟峯
舒月姣
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/479,154 priority Critical patent/US12218016B2/en
Publication of WO2022048249A1 publication Critical patent/WO2022048249A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a semiconductor structure.
  • the semiconductor manufacturing process is divided into a front-end device process and a back-end metal interconnect process.
  • the function of the back-end metal interconnect layer in the back-end metal interconnect process is to lead out the front-end device in the front-end device process for testing or work.
  • short-circuit failure or open-circuit failure often occurs in the back-end metal interconnect lines, which are mainly due to design problems and process problems.
  • the complex product structure is extracted separately or reorganized into a repeating, large-area, and easy-to-test structure by using the structure as a unit. A large number of corresponding electrical parameters are obtained, and these electrical parameters are analyzed to find and solve problems in advance. This structure is called a test key (Test-key). Test keys are found at almost all levels in the manufacturing process, and are characterized by ease of testing and ease of failure analysis.
  • the contact resistance of the bit line contact structure (BLC) connecting the bit line and the active region is an important factor affecting the performance of the semiconductor structure. Therefore, the contact of the bit line contact structure (BLC) is usually tested by the test key. resistance. However, the test key has a large error when testing the contact resistance of the bit line contact structure, which cannot meet the requirements.
  • the present application provides a semiconductor structure capable of reducing measurement errors and improving test accuracy.
  • the application provides a semiconductor structure with a test area, and in the test area, the semiconductor structure includes:
  • the semiconductor substrate has a plurality of independently arranged active regions, the active regions extending along a first direction;
  • each active region is electrically connected to two bit line contact structures
  • a plurality of wire groups are arranged along the second direction, each wire group includes a plurality of wires, the wires extend along a third direction, and in the third direction, each wire connects two bits on adjacent active regions
  • the wire contact structure makes the wire groups match in pairs to form a conductive path.
  • the wires of the same wire group or the wires of different wire groups have the same length.
  • the wires are arranged at equal intervals.
  • the wires of different wire groups are staggered along the fourth direction.
  • the plurality of wires of each wire group are cut from a whole wire at a set distance along the fourth direction, and the ends of the wires are inclined along the fourth direction.
  • the angle between the fourth direction and the second direction is a preset value, and the preset value is set according to the arrangement of the bit line contact structure, so as to avoid damaging the bit line contact during cutting structure.
  • the preset value is 30 to 50 degrees.
  • the included angle between the second direction and the third direction is 90 degrees.
  • the bit line contact structure forms a plurality of bit line contact structure groups, and the bit line contact structure groups are arranged along the second direction.
  • bit line contact structures in each of the bit line contact structure groups are arranged along the third direction.
  • the semiconductor structure further includes an array area, and the length of the active area located in the test area is greater than the length of the active area located in the array area.
  • the advantage of the present application is that adjacent wire groups, their corresponding bit line contact structures and active regions form a conductive path, and the resistances formed by them are connected in series. As the number of resistors connected in series increases, the total resistance of the conductive path will become larger and larger, the influence of external interference on the measurement result will become smaller and smaller, the error of the semiconductor structure test is reduced, and the accuracy of the semiconductor structure test is improved.
  • FIG. 1 is a schematic top view of a test key structure used for testing the contact resistance of a bit line contact structure in the related art
  • Fig. 2 is the equivalent circuit of the arrow passing region in the test key structure shown in Fig. 1;
  • FIG. 3 is a schematic top view of the structure of the first embodiment of the exemplary semiconductor structure provided by the embodiments of the present application;
  • FIG. 5 is an equivalent circuit diagram of the region passed by the arrow in the semiconductor structure shown in the present application.
  • FIG. 6 is a schematic plan view of a second embodiment of the semiconductor structure of the present application.
  • FIG. 10 is electrically connected to the two bit line contact structures 11, and in the third direction C, the wire 12 electrically connects all the bit line contact structures located in this direction.
  • a voltage is applied to adjacent wires so that two bit line contact structures 11 on the same active region 10 form a conductive path, so that the resistance of the bit line contact structures 11 can be measured.
  • a voltage is applied to the adjacent Nth wire and the N+1th wire, the Nth wire is used as the positive electrode, the N+1th wire is used as the negative electrode, and the Nth wire has the same
  • the bit line contact structures 111 and 112 electrically connected to the source region 10 and the N+1th wire form a conductive path (as shown by the arrow in FIG.
  • the electrically connected bit line contact structures 113 and 114 and the N+1th wire form another conductive path (as shown by the arrow in FIG. 1 ), and its resistance is R2; and so on, a plurality of conductive paths are formed, and its resistance They are R1, R2, R3 and R4, respectively.
  • These conductive paths are in a parallel relationship, and the equivalent circuit formed by them is shown in Figure 2.
  • the present application provides a semiconductor structure capable of reducing measurement errors and improving test accuracy.
  • FIG. 3 is a schematic top view of the semiconductor structure according to the first embodiment of the present application. Please refer to FIG. 3 .
  • the semiconductor structure includes a semiconductor substrate 40 , a plurality of bit line contact structures 60 and a plurality of wire sets.
  • the semiconductor substrate 40 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes many of these semiconductors.
  • the layer structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like.
  • the constituent material of the semiconductor substrate 40 is single crystal silicon.
  • the semiconductor substrate 40 is isolated by the shallow trench isolation structure to form a plurality of independently arranged active regions 41 , and the active regions 41 extend along the first direction A. As shown in FIG. In the embodiment of the present application, the active region 41 extends along the first direction A, and the plurality of active regions 41 are arranged along the first direction A. Since the active region is covered by a dielectric layer and the like above it, the active region 41 is depicted by a dashed line in the drawings. In the embodiment of the present application, the first direction A is a direction that forms an acute angle with the horizontal direction.
  • the semiconductor structure further includes an array region (not shown in the drawings).
  • the semiconductor substrate of the array region is also isolated by the shallow trench isolation structure to form a plurality of independently arranged active regions.
  • the length of the active area located in the test area is greater than the length of the active area located in the array area.
  • the length of the active area located in the test area is twice the length of the active area located in the array area.
  • bit line contact structures 60 are provided on the semiconductor substrate 40 .
  • the bit line contact structure 60 is a conductive structure, which can be formed in the same step as the bit line contact structure of the array region of the semiconductor structure, so as to be used as a test key for testing the resistance of the bit line contact structure of the array region. Since the bit line contact structure 60 is shielded by the wires, in the drawings, the bit line contact structure 60 is shown with a dotted line.
  • each of the active regions 41 is electrically connected to two bit line contact structures 60 .
  • each active region 41 is electrically connected to the two bit line contact structures 60 located above it.
  • the set spacing may depend on the distance of the region in the active region that needs to be connected to the bit line, and can be designed by those skilled in the art according to actual requirements. For example, in some embodiments of the present application, both ends of the active region 41 need to be electrically connected to the bit line contact structure 60 , and the distance between the two bit line contact structures 60 is equal to the two ends of the active region 41 . the distance between.
  • the plurality of wire groups are arranged along the second direction B.
  • the second direction B is a horizontal direction, and a plurality of wire groups are arranged along the horizontal direction.
  • the number of the wire groups can be set according to actual requirements, and only 7 wire groups are schematically shown in FIG. 3 , which should not be regarded as a limitation of the present application.
  • Each wire group includes a plurality of wires 70 , the wires 70 extend along the third direction C, and the plurality of wires 70 are arranged in sequence along the third direction C.
  • the included angle between the second direction B and the third direction C is 90 degrees, that is, the two directions are perpendicular.
  • the second direction B is a horizontal direction
  • the third direction C is a vertical direction, and the two are vertical.
  • the included angle between the second direction B and the third direction C may also be an acute angle.
  • each wire 70 is connected to two bit line contact structures 60 on adjacent active regions 41 , so that adjacent wire groups are matched in pairs to form conductive paths during testing.
  • the wire groups corresponding to the active regions arranged in sequence on the third direction C are paired in pairs, and during testing, a conductive path is formed with the bit line contact structure and the active region.
  • the active regions 410 , 411 , 412 , 413 , 414 , 415 , and 416 are arranged in sequence along the third direction C, then the Nth wire group and the Nth wire group corresponding to these active regions
  • the +1 wire group forms a conductive path with the bit line contact structure and the active area.
  • the Nth wire group includes wires 701 , 702 , 703 , and 704
  • the N+1th wire group includes wires 705 , 706 , and 707 .
  • the wire 701 is electrically connected to two bit line contact structures, and only one bit line contact structure 601 is shown in FIG.
  • the bit line contact structure 601 is electrically connected to the active region 410 ;
  • the wire 702 is electrically connected to two bit line contact structures 602 and 603 which are electrically connected to the active regions 411 and 412 respectively;
  • the wire 703 is electrically connected to the two bit line contact structures 604 and 605 connected, the bit line contact structures 604 and 605 are electrically connected to the active regions 413 and 414 respectively;
  • the wire 704 is electrically connected to two bit line contact structures, only one bit line contact structure 606 is shown in FIG.
  • the bit line contact structure 606 is electrically connected to the active region 415; the wire 705 is electrically connected to two bit line contact structures 607 and 608, which are electrically connected to the active regions 412 and 413, respectively connection; the wire 706 is electrically connected to two bit line contact structures 609 and 610, which are electrically connected to the active regions 414 and 415, respectively; the wire 707 is electrically connected to the two bit line contact structures
  • the bit line contact structure 611 is electrically connected to the active region 416 .
  • FIG. 4 is a schematic diagram of the connection relationship between the wire and the bit line contact structure and the active area. Please refer to FIG. 3 and FIG. 4. As shown by the arrows in FIG.
  • the wire 702, the bit line contact structure 603, the active region 412, the bit line contact structure 607, the wire 705, the bit line contact structure 608, the active region 413, the bit line contact structure 604, the wire 703, the bit line Contact structure 605, active region 414, bit line contact structure 609, wire 706, bit line contact structure 610, active region 415, bit line contact structure 606, and wire 704 form conductive paths.
  • FIG. 5 is an equivalent circuit diagram of the area where the arrows pass through the semiconductor structure shown in FIG. 3 .
  • the wire 702 passes between the bit line contact structure 603 , the active region 412 , the bit line contact structure 607 and the wire 705 .
  • the resistance is R1, the resistance between the wire 705 through the bit line contact structure 608, the active region 413, the bit line contact structure 604 to the wire 703 is R2, and the wire 703 passes through the bit line contact structure 605, the active region. 414.
  • the resistance between the bit line contact structure 609 and the wire 706 is R3, and the resistance between the wire 706 through the bit line contact structure 610, the active region 415, the bit line contact structure 606 and the wire 704 is R4.
  • the resistors R1, R2, R3 and R4 are connected in series.
  • this embodiment only shows the four resistors formed by the conducting wire, the bit line contact structure and the active region. It is understood that the conducting wire, the bit line contact structure and the active region can form multiple resistors. resistors, which are connected in series to form a conductive path. As more and more resistances are connected in series, the total resistance of the conductive path will become larger and larger, and the influence of external interference on the measurement results will become smaller and smaller, which reduces the error of the semiconductor structure test and improves the semiconductor structure test. accuracy.
  • the wires 70 are of equal length.
  • the wires 70 in the same wire group are of the same length, or the wires 70 in different wire groups are of the same length, so as to minimize the influence of the wires 70 on the resistance.
  • the wires 70 in different wire groups are of equal length, that is, all wires have the same length, while in other embodiments of the present application, the wires in the same wire group have the same length, and the wires in different wire groups The lengths of the wires are not equal.
  • the wires 70 are arranged at equal intervals, and the interval of the wires 70 may depend on the distance between adjacent active regions in the direction of extension of the wires.
  • the distance between the wires 70 depends on the distance between adjacent active regions in the third direction C. The larger the distance is, the greater the distance between the wires 70 is, and the smaller the distance is, the higher the distance between the wires 70 is. 70 is the smaller the spacing.
  • the distances of all the wires 70 are equal.
  • the wires of different wire groups are staggered along the fourth direction.
  • the wires of different wire groups are arranged in a staggered position.
  • the conducting wire 702 of the Nth conducting wire group and the conducting wire 705 of the N+1 th conducting wire group are not on the same standard line, but are arranged staggered.
  • the bit line contact structure 60 forms a plurality of bit line contact structure groups, and the bit line contact structure groups are arranged along the second direction.
  • the bit line contact structures 601, 602, 603, 604, 605, 606 form one bit line contact structure group
  • the bit line contact structures 607, 608, 609, 610, 611 form another A bit line contact structure group
  • the two bit line contact structure groups are arranged in sequence along the second direction B.
  • the bit line contact structures in each of the bit line contact structure groups are arranged along a third direction.
  • the bit line contact structures in the same bit line contact structure group are aligned along the third direction C. In other embodiments of the present application, the bit line contact structures in the same bit line contact structure group may be approximately along the The third direction C is arranged, not aligned.
  • the ends of the wires are inclined along a fourth direction.
  • FIG. 6 is a schematic top-view structural diagram of a second embodiment of the semiconductor structure of the present application.
  • a plurality of wires of each wire group are cut from a whole wire at a set distance along the fourth direction.
  • the ends of the wires are inclined along the fourth direction.
  • the wires of the Nth wire group are cut from a whole wire along the fourth direction D at a set distance, and after cutting, the ends of the wires are inclined along the fourth direction D.
  • the ends of the wires 701 are inclined in the fourth direction D.
  • the set distance is set so that the formed wires can connect the bit line contact structures of two adjacent active regions.
  • the angle between the fourth direction D and the second direction B is a preset value, and the preset value is based on the angle of the bit line contact structure.
  • the arrangement is arranged to avoid damage to the bit line contact structure during cutting.
  • the preset value may be 30 to 50 degrees. If the preset value is too large or too small, the bit line contact structure may be passed through during cutting, thereby destroying the bit line contact structure. It can be understood that, in order to avoid damaging the bit line contact structure during cutting, the preset value can also be selected according to the actual process.
  • An embodiment of the present application provides a semiconductor structure, which has a test area, and in the test area, the semiconductor structure includes: a semiconductor substrate, the semiconductor substrate has a plurality of independently arranged active regions, and the active regions extend along a first direction; A plurality of bit line contact structures are arranged on the semiconductor substrate, in the first direction, each active region is electrically connected with two bit line contact structures; a plurality of wire groups are arranged along the second direction, each wire The group includes a plurality of wires extending along a third direction. In the third direction, each wire connects two bit line contact structures on adjacent active regions, so that the wire groups are matched in pairs to form conductive paths.
  • adjacent wire groups form conductive paths with the bit line contact structure and the active area, and their resistances are connected in series.
  • the influence of the semiconductor structure is getting smaller and smaller, the test error of the semiconductor structure is reduced, and the test accuracy of the semiconductor structure is improved.

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Abstract

本申请提供一种半导体结构，其具有测试区域，在测试区域，半导体结构包括：半导体衬底，半导体衬底具有多个独立设置的有源区，有源区沿第一方向延伸；多个位线接触结构，设置在半导体衬底上，在第一方向上，每一有源区与两个位线接触结构电连接；多个导线组，沿第二方向排布，每一导线组包括多个导线，导线沿第三方向延伸，在第三方向上，每一导线连接相邻的有源区上的两个位线接触结构，以使得导线组两两匹配，形成导电通路。本申请相邻的导线组与位线接触结构及有源区形成导电通路，其电阻串联，随着串联电阻数量越来越多，导电通路总电阻越来越大，外界干扰对测量结果的影响越来越小，降低了半导体结构测试误差，提高了半导体结构测试准确度。

Description

半导体结构
相关申请的交叉引用
本申请基于申请号为202010919564.0、申请日为2020年09月04日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构。
背景技术
半导体制造工艺分为前段器件工艺和后段金属互联工艺，后段金属互联工艺中的后段金属互联层的作用是将前段器件工艺中的前段器件引出以便进行测试或者工作。在半导体制造过程中，后段金属互联线经常会出现短路失效或者开路失效，这主要是源自于设计问题和工艺问题。为了评估设计结构和监控线上工艺稳定度，将复杂的产品结构单独提取出来或者以此结构为单元重组成重复的、大面积的、便于测试的结构，通过对这些测试结构进行电性测试以得到大量相应的电性参数，对这些电性参数进行分析以提前发现问题并解决问题，这种结构被称为测试键(Test-key)。测试键几乎遍及制造工艺中的所有层次，且其具有易于测试和易于失效分析等特点。
在半导体结构中，连接位线与有源区的位线接触结构(BLC)的接触电阻是影响半导体结构性能的一个重要因素，因此，通常会通过测试键测试位线接触结构(BLC)的接触电阻。但是，测试键在测试位线接触结构的接触电阻时存在较大误差，不能满足需求。
发明内容
本申请提供了一种半导体结构，其能够减小测量误差，提高测试准确度。
本申请提供了一种半导体结构，具有测试区域，在所述测试区域，所述半导体结构包括：
半导体衬底，所述半导体衬底具有多个独立设置的有源区，所述有源区沿第一方向延伸；
多个位线接触结构，设置在所述半导体衬底上，在第一方向上，每一有源区与两个位线接触结构电连接；
多个导线组，沿第二方向排布，每一导线组包括多个导线，所述导线沿第三方向延伸，在第三方向上，每一导线连接相邻的有源区上的两个位线接触结构，以使得导线组两两匹配，形成导电通路。
上述方案中，同一导线组的导线或者不同导线组的导线长度相等。
上述方案中，在同一导线组中，所述导线等间距设置。
上述方案中，不同导线组的导线沿第四方向错位设置。
上述方案中，每一导线组的多个导线由一整根导线沿第四方向按设定距离切割而成，所述导线的端部沿第四方向倾斜。
上述方案中，所述第四方向与所述第二方向的夹角为预设值，所述预设值根据所述位线接触结构的排布而设置，以避免在切割时破坏位线接触结构。
上述方案中，所述预设值为30～50度。
上述方案中，所述第二方向与所述第三方向的夹角为90度。
上述方案中，所述位线接触结构形成多个位线接触结构组，所述位线接触结构组沿第二方向排布。
上述方案中，每一所述位线接触结构组内的位线接触结构沿第三方向排布。
上述方案中，所述半导体结构还包括阵列区，位于所述测试区的有源区的长度大于位于所述阵列区的有源区的长度。
本申请的优点在于，相邻的导线组与其对应的位线接触结构及有源区形成一个导电通路，其形成的电阻串联，随着串联的电阻数量越来越多，该导电通路的总电阻会越来越大，则外界的干扰对测量结果的影响会越来越小，降低了半导体结构测试的误差，提高了半导体结构测试的准确度。
附图说明
图1为相关技术中用于测试位线接触结构的接触电阻的测试键结构俯视示意图；
图2是图1所示测试键结构中箭头经过区域的等效电路；
图3是本申请实施例提供的示例性的半导体结构的第一实施例的俯视结构示意；
图4是本申请导线与位线接触结构及有源区连接关系示意图；
图5是本申请所示半导体结构中箭头所经过区域的等效电路图；
图6是本申请半导体结构的第二实施例的俯视结构示意。
具体实施方式
下面结合附图对本申请提供的半导体结构的具体实施方式做详细说明。
图1为相关技术中用于测试位线接触结构的接触电阻的测试键结构俯视示意图，请参阅图1，在有源区10的延伸方向上，即第一方向A上，每一有源区10与两个位线接触结构11电连接，在第三方向C上，导线12将位于该方向上的所有位线接触结构电连接延伸。
当需要进行测试时，对相邻的导线施加电压，以使得同一有源区10上的两个位线接触结构11形成一个导电通路，进而可测量位线接触结构11的电 阻。例如，在需要进行测试时，对相邻的第N个导线及第N+1个导线施加电压，第N个导线作为正极，第N+1个导线作为负极，第N个导线与同一个有源区10电连接的位线接触结构111及112、第N+1个导线形成一个导电通路(如图1中箭头所示)，其电阻为R1；第N个导线、与同一个有源区10电连接的位线接触结构113及114、第N+1个导线形成另一个导电通路(如图1中箭头所示)，其电阻为R2；依此类推，形成多个导电通路，其电阻分别为R1、R2、R3及R4。这些导电通路为并联关系，其形成的等效电路如图2所示，在第N个导线及第N+1个导线上施加电压，能够获得这些导电通路的电阻，即能够测量所述位线接触结构的电阻。
但是，随着并联的导电通路数目的增加，测量误差较大，不能满足需求。造成该种现象的原因在于，随着并联的导电通路数目的增加，并联后的总电阻的数值越来越小，外界微小的干扰都会影响测量结果，造成较大的测量误差。
因此，本申请提供了一种半导体结构，其能够减小测量误差，提高测试准确度。
图3是本申请半导体结构的第一实施例的俯视结构示意，请参阅图3，所述半导体结构包括半导体衬底40、多个位线接触结构60及多个导线组。
所述半导体衬底40可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本申请实施例中，半导体衬底40的构成材料选用单晶硅。
所述半导体衬底40被浅沟槽隔离结构隔离，形成多个独立设置的有源区41，所述有源区41沿第一方向A延伸。在本申请实施例中，所述有源区41沿第一方向A延伸，且多个有源区41沿第一方向A排布。由于所述有源区被其上方的介质层等覆盖，因此，在附图中采用虚线绘示所述有源区41。在本申请实施例中，所述第一方向A为与水平方向呈一锐角夹角的方向。
在本申请的一些实施例中，所述半导体结构还包括阵列区(附图中未绘 示)。所述阵列区的半导体衬底也被浅沟槽隔离结构隔离形成多个独立设置的有源区。其中，位于所述测试区的有源区的长度大于位于所述阵列区的有源区的长度。例如，在本申请的一些实施例中，位于所述测试区的有源区长度为位于所述阵列区的有源区长度的二倍。
多个位线接触结构60设置在所述半导体衬底40上。所述位线接触结构60为导电结构，其可与半导体结构的阵列区的位线接触结构在同一步骤中形成，从而能够用于作为测试阵列区的位线接触结构的电阻的测试键。由于所述位线接触结构60被导线遮挡，因此，在附图中，所述位线接触结构60采用虚线绘示。
其中，在第一方向A上，即在所述有源区41的延伸方向上，每一所述有源区41与两个位线接触结构60电连接。在本申请实施例中，在第一方向A上，每一有源区41与位于其上方的两个位线接触结构60电连接。
其中，在第一方向A上，两个所述位线接触结构60之间具有设定间距。该设定间距可取决于有源区中需要与位线连接的区域的距离，本领域技术人员可根据实际需求设计。例如，在本申请的一些实施例中，所述有源区41的两端需要与位线接触结构60电连接，则两个位线接触结构60的间距即为所述有源区41两端之间的距离。
多个导线组沿第二方向B排布。在本申请实施例中，所述第二方向B为水平方向，多个导线组沿水平方向排布。所述导线组的数量可根据实际需求设置，在图3中仅示意性地绘示了7个导线组，其不应被视为对本申请的限制。
每一导线组包括多个导线70，所述导线70沿第三方向C延伸，多个所述导线70沿第三方向C依次设置。在本申请的一些实施例中，所述第二方向B与所述第三方向C的夹角为90度，即两个方向垂直。在本申请实施例中，所述第二方向B为水平方向，则所述第三方向C为竖直方向，两者垂直。在本申请其他实施例中，所述第二方向B与第三方向C的夹角也可为一锐角。
在第三方向C上，每一导线70连接相邻的有源区41上的两个位线接触结构60，以使得相邻的导线组两两匹配，在测试时形成导电通路。在第三方 向C上依次排列的有源区所对应的导线组两两配对，在测试时与位线接触结构及有源区形成导电通路。例如，在本申请实施例中，所述有源区410、411、412、413、414、415、416沿第三方向C依次排列，则这些有源区对应的第N个导线组及第N+1个导线组与位线接触结构及有源区形成导电通路。
例如，在本申请实施例中，所述第N个导线组包括导线701、702、703、704，所述第N+1个导线组包括导线705、706、707。请参阅图3，所述导线701与两个位线接触结构电连接，在图3中仅绘示一个位线接触结构601，所述位线接触结构601与有源区410电连接；所述导线702与两个位线接触结构602及603电连接，所述位线接触结构602及603分别与有源区411及412电连接；所述导线703与两个位线接触结构604及605电连接，所述位线接触结构604及605分别与有源区413及414电连接；所述导线704与两个位线接触结构电连接，在图3中仅绘示一个位线接触结构606，所述位线接触结构606与有源区415电连接；所述导线705与两个位线接触结构607及608电连接，所述位线接触结构607及608分别与有源区412及413电连接；所述导线706与两个位线接触结构609及610电连接，所述位线接触结构609及610分别与有源区414及415电连接；所述导线707与两个位线接触结构电连接，在图3中仅绘示一个位线接触结构611，所述位线接触结构611与有源区416电连接。
本申请实施例中，当在第N个导线组及第N+1个导线组上施加电压时，与所述第N个导线组及第N+1个导线组对应的位线接触结构及有源区会形成一个导电通路。图4是导线与位线接触结构及有源区连接关系示意图，请参阅图3及图4，如图3中箭头所示，当在第N个导线组及第N+1个导线组上施加电压时，导线702、所述位线接触结构603、有源区412、位线接触结构607、导线705、位线接触结构608、有源区413、位线接触结构604、导线703、位线接触结构605、有源区414、位线接触结构609、导线706、位线接触结构610、有源区415、位线接触结构606及导线704形成导电通路。
图5为图3所述半导体结构中箭头所经过区域的等效电路图，请参阅图5，导线702经所述位线接触结构603、有源区412、位线接触结构607至导线705 之间的电阻为R1，导线705经所述位线接触结构608、有源区413、位线接触结构604至导线703之间的电阻为R2，导线703经所述位线接触结构605、有源区414、位线接触结构609至导线706之间的电阻为R3，导线706经所述位线接触结构610、有源区415、位线接触结构606至导线704之间的电阻为R4。所述电阻R1、R2、R3及R4为串联结构。
为了清楚解释本申请技术方案，该实施例仅绘示了导线、位线接触结构及有源区形成的四个电阻，可以理解的是，导线、位线接触结构及有源区能够形成多个电阻，这些电阻串联连接形成一个导电通路。随着串联的电阻越来越多，该导电通路的总电阻会越来越大，则外界的干扰对测量结果的影响会越来越小，降低了半导体结构测试的误差，提高了半导体结构测试的准确度。
在本申请的一些实施例中，所述导线70长度相等。位于同一导线组内的导线70等长，或者位于不同导线组内的导线70均等长，以尽量减小导线70对电阻的影响。例如，在本申请实施例中，位于不同导线组内的导线70均等长，即所有导线的长度相等，而在本申请其他实施例中，同一导线组内的导线长度相等，不同导线组内的导线的长度不相等。
在本申请的一些实施例中，在同一导线组中，所述导线70等间距设置，所述导线70的间距可取决于相邻有源区在导线延伸方向上的距离。例如，在本申请实施例中，所述导线70的间距取决于相邻的有源区在第三方向C上的距离，该距离越大，导线70的间距越大，该距离越小，导线70的间距越小。在本申请其他实施例中，在第三方向C，所有导线70的间距均相等。
在本申请的一些实施例中，不同导线组的导线沿第四方向错位设置。在沿第四方向D方向上，不同导线组的导线错位设置。例如，在沿第四方向D方向上，第N个导线组的导线702与第N+1个导线组的导线705不在同一标准线上，而是错位设置。
在本申请的一些实施例中，在本申请实施例中，所述位线接触结构60形成多个位线接触结构组，所述位线接触结构组沿第二方向排布。例如，请参阅图3，所述位线接触结构601、602、603、604、605、606形成一个位线接 触结构组，所述位线接触结构607、608、609、610、611形成另一个位线接触结构组，该两个位线接触结构组沿第二方向B依次排列。
在本申请的一些实施例中，每一所述位线接触结构组内的位线接触结构沿第三方向排布。例如，在所述位线接触结构601、602、603、604、605、606形成的位线接触结构组中，所述位线接触结构601、602、603、604、605、606沿第三方向C依次排列；在所述位线接触结构607、608、609、610、611形成的位线接触结构组中，所述位线接触结构607、608、609、610、611沿第三方向C依次排列。在本申请实施例中，同一位线接触结构组内的位线接触结构沿第三方向C对齐排列，在本申请其他实施例中，同一位线接触结构组内的位线接触结构可大致沿第三方向C排列，而并非是对齐排列。
在本申请另一实施例中，所述导线的端部沿第四方向倾斜。请参阅图6，其为本申请半导体结构第二实施例的俯视结构示意图，在该实施例中，每一导线组的多个导线由一整根导线沿第四方向按设定距离切割而成，所述导线的端部沿第四方向倾斜。第N个导线组的导线由一整根导线沿第四方向D按设定距离切割而成，则切割后，所述导线的端部沿第四方向D倾斜。例如，导线701的端部(如图中箭头所示)沿第四方向D倾斜。所述设定距离设置为，使形成的导线能够连接相邻的两个有源区的位线接触结构。
在本申请的一些实施例中，在第二实施例中，所述第四方向D与所述第二方向B的夹角为预设值，所述预设值根据所述位线接触结构的排布而设置，以避免在切割时破坏位线接触结构。所述预设值可为30～50度，若所述预设值过大或者过小均可能会在切割时经过位线接触结构，进而破坏所述位线接触结构。可以理解的是，为了避免在切割时破坏所述位线接触结构，所述预设值也可根据实际工艺制程选择。
以上所述仅是本申请的一些实施例，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。
工业实用性
本申请实施例提供了一种半导体结构，其具有测试区域，在测试区域，半导体结构包括：半导体衬底，半导体衬底具有多个独立设置的有源区，有源区沿第一方向延伸；多个位线接触结构，设置在半导体衬底上，在第一方向上，每一有源区与两个位线接触结构电连接；多个导线组，沿第二方向排布，每一导线组包括多个导线，导线沿第三方向延伸，在第三方向上，每一导线连接相邻的有源区上的两个位线接触结构，以使得导线组两两匹配，形成导电通路。上述结构中，相邻的导线组与位线接触结构及有源区形成导电通路，其电阻串联，随着串联电阻数量越来越多，导电通路总电阻越来越大，外界干扰对测量结果的影响越来越小，降低了半导体结构测试误差，提高了半导体结构测试准确度。

Claims (11)

  1. 一种半导体结构，具有测试区域，在所述测试区域，所述半导体结构包括：
    半导体衬底，所述半导体衬底具有多个独立设置的有源区，所述有源区沿第一方向延伸；
    多个位线接触结构，设置在所述半导体衬底上，在第一方向上，每一有源区与两个位线接触结构电连接；
    多个导线组，沿第二方向排布，每一导线组包括多个导线，所述导线沿第三方向延伸，在第三方向上，每一导线连接相邻的有源区上的两个位线接触结构，以使得导线组两两匹配，形成导电通路。
  2. 根据权利要求1所述的半导体结构，其中，同一导线组的导线或者不同导线组的导线长度相等。
  3. 根据权利要求1所述的半导体结构，其中，在同一导线组中，所述导线等间距设置。
  4. 根据权利要求1所述的半导体结构，其中，不同导线组的导线沿第四方向错位设置。
  5. 根据权利要求4所述的半导体结构，其中，每一导线组的多个导线由一整根导线沿第四方向按设定距离切割而成，所述导线的端部沿第四方向倾斜。
  6. 根据权利要求5所述的半导体结构，其中，所述第四方向与所述第二方向的夹角为预设值，所述预设值根据所述位线接触结构的排布而设置，以避免在切割时破坏位线接触结构。
  7. 根据权利要求6所述的半导体结构，其中，所述预设值为30～50度。
  8. 根据权利要求1所述的半导体结构，其中，所述第二方向与所述第三方向的夹角为90度。
  9. 根据权利要求1所述的半导体结构，其中，所述位线接触结构形成多个位线接触结构组，所述位线接触结构组沿第二方向排布。
  10. 根据权利要求9所述的半导体结构，其中，每一所述位线接触结构组内的位线接触结构沿第三方向排布。
  11. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括阵列区，位于所述测试区的有源区的长度大于位于所述阵列区的有源区的长度。
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