WO2022048246A1 - 驱动电路 - Google Patents

驱动电路 Download PDF

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Publication number
WO2022048246A1
WO2022048246A1 PCT/CN2021/100824 CN2021100824W WO2022048246A1 WO 2022048246 A1 WO2022048246 A1 WO 2022048246A1 CN 2021100824 W CN2021100824 W CN 2021100824W WO 2022048246 A1 WO2022048246 A1 WO 2022048246A1
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WO
WIPO (PCT)
Prior art keywords
pull
transistor
circuit
control
signal
Prior art date
Application number
PCT/CN2021/100824
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English (en)
French (fr)
Inventor
张良
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/402,708 priority Critical patent/US11444619B2/en
Publication of WO2022048246A1 publication Critical patent/WO2022048246A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Definitions

  • the present application relates to a driving circuit.
  • DRAM Dynamic Random Access Memory
  • DRAM random access memory
  • a driving circuit comprising:
  • a pull-up transistor and a pull-down transistor the first end of the pull-up transistor is connected to the power supply, the second end of the pull-up transistor is connected to the first end of the pull-down transistor, so as to jointly output a driving signal, the pull-down transistor the second end of the is connected to ground;
  • a control circuit connected to the control terminals of the pull-up transistor and/or the pull-down transistor, respectively, for controlling the turn-on or turn-off of the pull-up transistor and/or the pull-down transistor to change the drive signal;
  • the pull-up transistor and the pull-down transistor are not turned on at the same time under the control of the control circuit.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment.
  • FIG. 2 is a schematic structural diagram of a driving circuit according to another embodiment.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to another embodiment.
  • FIG. 4 is a schematic structural diagram of a driving circuit according to still another embodiment.
  • FIG. 5 is a timing diagram of a process in which the pull-down transistor is turned off and the pull-up transistor is turned on according to an embodiment.
  • FIG. 6 is a timing diagram of a process in which the pull-up transistor is turned off and the pull-down transistor is turned on according to an embodiment.
  • Control circuit 100; Pull-up transistor: 200; Pull-down transistor: 300; First inverter: 101; Pull-up control circuit: 110; First selection circuit: 111; First transmission gate: 1111; Second transmission gate: 1112; pull-down control circuit: 120; second selection circuit: 121; third transmission gate: 1211; fourth transmission gate: 1212; delay circuit: 200; second inverter: 210
  • DRAM consumes a lot of power when reading and writing data, so it needs to consume a lot of power, which leads to fast battery consumption of mobile devices, which greatly affects the user experience.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment.
  • the driving circuit includes a pull-up transistor T1, a pull-down transistor T2, and a control circuit 100.
  • the pull-up transistor T1 and the pull-down transistor T2 is not turned on at the same time under the control of the control circuit 100 .
  • the control end of the pull-up transistor T1 is connected to the output end of the control circuit 100, the first end of the pull-up transistor T1 is connected to the power supply Vcc, the second end of the pull-up transistor T1 is connected to the first end of the pull-down transistor T2, and the pull-up transistor T1 is connected to the first end of the pull-up transistor T2.
  • T1 is controlled by the control circuit 100 to change the voltage output by the second terminal of the pull-up transistor T1.
  • the control circuit 100 controls the pull-up transistor T1 to be turned on, the first end and the second end of the pull-up transistor T1 are turned on, and the power supply Vcc can pull up the output of the second end of the pull-up transistor T1 to the power supply Vcc;
  • the control circuit 100 controls the pull-up transistor T1 to be turned off, the first end and the second end of the pull-up transistor T1 are turned off.
  • the control end of the pull-down transistor T2 is connected to the output end of the control circuit 100, the first end of the pull-down transistor T2 is connected to the second end of the pull-down transistor T2, the second end of the pull-down transistor T2 is connected to the ground Vss, and the pull-down transistor T2 is controlled by the control circuit
  • the control of 100 changes the voltage output by the first terminal of the pull-down transistor T2.
  • the control circuit 100 controls the pull-down transistor T2 to be turned on, and the second end and the first end of the pull-down transistor T2 are turned on, the output of the first end of the pull-down transistor T2 can be pulled down to the ground Vss; when the control circuit 100 controls When the pull-down transistor T2 is turned off, the second end and the first end of the pull-down transistor T2 are turned off.
  • the control circuit 100 controls When the pull-down transistor T2 is turned off, the second end and the first end of the pull-down transistor T2 are turned off.
  • the control circuit 100 is connected to the control terminals of the pull-up transistor T1 and/or the pull-down transistor T2 respectively, and is used to control the turn-on or turn-off of the pull-up transistor T1 and/or the pull-down transistor T2, so as to change the the driving signal Q.
  • the control circuit 100 can change the level state of the driving signal Q by controlling the pull-up transistor T1 and the pull-down transistor T2, for example, switching from a high level to a low level, or from a low level to a high level.
  • the switching of the on or off state of the transistor is in response to the signal input from the control terminal.
  • the signal switching of the control terminal is usually a gradual switching, not a step type. switch.
  • the signal voltage at the control terminal is gradually raised to 3.5V within a certain time period, that is, the relationship between the signal voltage and time has a certain slope.
  • the switching between the on and off states of the transistor is based on a threshold voltage as a critical point, for example, the threshold voltage may be 0.7V.
  • the low-level enabled pull-up transistor T1 shown in Figure 1 it switches to the conducting state when the voltage at the control terminal drops to 0.7V, and when the voltage at the control terminal rises to 0.7V switched to the disconnected state. Therefore, the reliability of the on-off of the transistor itself is insufficient, and one of the pull-up transistor T1 and the pull-down transistor T2 has been turned on, but the other has not been turned off. There is an intermediate state, the pull-up transistor T1 and the pull-down transistor T2 are turned on at the same time, so that a DC path from the power supply Vcc to the ground will appear every time it is turned over, thereby causing a relatively large ineffective power consumption, resulting in the drive circuit described in the background. high consumption problem.
  • the pull-up transistor T1 and the pull-down transistor T2 are not turned on at the same time through the control signal output by the control circuit 100, that is, one of the pull-up transistor T1 and the pull-down transistor T2 is switched to the off state first, Switching the other one to a conducting state can prevent a DC path from being formed between the power supply Vcc and the ground Vss, thereby saving ineffective power consumption. Moreover, the competition state when the two transistors are turned on at the same time can be avoided, the current burr phenomenon generated when the two transistors are turned on at the same time can be eliminated, and the stability of the output driving signal Q can be improved. Therefore, this embodiment provides a driving circuit with lower power consumption and better signal stability through the above structure.
  • the pull-up transistor T1 is enabled at a low level, and the pull-down transistor T2 is enabled at a high level.
  • a high-level enabled pull-up transistor T1 and a low-level enabled pull-down transistor T2 may be employed. It is also possible to use transistors with the same enable mode as the pull-up transistor T1 and the pull-down transistor T2, and the control circuit 100 generates two control signals with different level states, and respectively inputs them to the pull-up transistor T1 and the pull-down transistor T2 in a one-to-one correspondence. .
  • the pull-up transistor T1 and the pull-down transistor T2 in FIG. 1 are only used for exemplary illustration, and are not used to limit the protection scope of the present application, as long as one of the two transistors can be disconnected first, and the other It only needs to be turned on.
  • Other transistor structures or control logics of the control circuit 100 that can realize the above functions also belong to the protection scope of the present application.
  • FIG. 2 is a schematic structural diagram of a driving circuit according to another embodiment.
  • the driving circuit includes a control circuit 100 , a pull-up transistor T1 , a pull-down transistor T2 and a delay circuit 200 .
  • the structures and connection manners of the control circuit 100 , the pull-up transistor T1 and the pull-down transistor T2 are the same as those in the embodiment of FIG. 1 , and will not be repeated here.
  • a delay circuit 200 connected to the control circuit 100, is configured to receive an input signal D, and perform a preset delay on the input signal D to generate a delayed input signal DD, wherein the input signal D and the delayed input
  • the signals DD are all used for input to the control circuit 100 .
  • the delay circuit 200 may be a fixed delay chain.
  • the fixed delay chain may include a plurality of transmission gates connected in series, and each transmission gate is configured with a fixed delay time. Therefore, a corresponding number of transmission gates may be set according to the preset delay time required to be generated by the delay circuit 200, thereby The preset delay time to generate the target.
  • the fixed delay chain may also include an even number of inverters connected in series. By setting an even number of inverters, it can be ensured that the output delayed input signal DD corresponds to the level state of the input signal D, and only exists The difference in timing is similar to the fixed delay chain formed by the transmission gates. A corresponding number of inverters can be set according to the preset delay time required by the delay circuit 200 to generate the target preset delay time.
  • Delay circuit 200 may also be a variable delay chain. It can be understood that the on-off characteristics of the pull-up transistor T1 and the pull-down transistor T2, as well as the transmission speed on the signal transmission path, will change with the temperature of the use environment and other conditions. Therefore, if the conditions of the usage environment change, there is a risk that an error occurs in the on-off timing of the pull-up transistor T1 and the pull-down transistor T2.
  • the delay circuit 200 composed of a variable delay chain, and setting up a corresponding detection structure, through the detection structure, the condition change of the use environment of the driving circuit can be detected and adjusted according to the detection result.
  • the delay time of the variable delay chain thus avoiding the on-off timing error of the pull-up transistor T1 and the pull-down transistor T2, thereby avoiding the formation of a DC path between the power supply Vcc and the ground Vss, and preventing the invalid power consumption of the drive circuit, that is, , providing a drive circuit with lower power consumption.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to another embodiment.
  • the driving circuit includes a control circuit 100 , a pull-up transistor T1 , a pull-down transistor T2 and a delay circuit 200 .
  • the structures and connection manners of the delay circuit 200 , the pull-up transistor T1 and the pull-down transistor T2 are the same as those in the embodiment of FIG. 2 , which will not be repeated here.
  • the control circuit 100 specifically includes a pull-up control circuit 110 and a pull-down control circuit 120 .
  • the pull-up control circuit 110 is connected to the control terminal of the pull-up transistor T1, and is used to control the turn-on or turn-off of the pull-up transistor T1, wherein the pull-up control circuit 110 receives the input signal D and the delayed input signal DD, And the pull-up control signal A0 is generated according to the input signal D and the delayed input signal DD.
  • the pull-down control circuit 120 is connected to the control terminal of the pull-down transistor T2, and is used to control the turn-on or turn-off of the pull-down transistor T2.
  • the pull-down control circuit 120 receives the input signal D and the delayed input signal DD, and according to the input signal D and The delayed input signal DD generates the pull-up control signal A1.
  • the timings of the pull-up control signal A0 and the pull-up control signal A1 are different, and the timing difference between the two can make one of the pull-up transistor T1 and the pull-down transistor T2 be turned off first, and the other one is turned on again, that is, the two
  • the timing relationship between the control signals corresponds to the on-off sequence of the two transistors.
  • control circuit 100 is further configured to receive the driving signal Q, and select and output the input signal D or the delayed input signal DD according to the driving signal Q, so as to control the pull-up transistor T1 and pull-down transistor T1
  • the transistors T2 are sequentially turned on or off according to a preset sequence.
  • the pull-up control circuit 110 includes a first selection circuit 111, and one input terminal of the first selection circuit 111 is used to receive the input signal D, so the The other input terminal of the first selection circuit 111 is used to receive the delayed input signal DD, the control terminal of the first selection circuit 111 is used to receive the drive signal Q, and the output terminal of the first selection circuit 111 connected to the control terminal of the pull-up transistor T1.
  • the first selection circuit 111 is used to select one of the input signal D and the delayed input signal DD as the pull-up control signal A0 according to the drive signal Q, so as to control the turn-on or turn-off of the pull-up transistor T1, so as to realize the control of the drive signal Q. adjustment.
  • the driving circuit of this embodiment is used to invert the level state of the driving signal Q, that is, the level state of the driving signal Q after the inversion is the same as the level state of the driving signal Q before the inversion. Quite the opposite. Therefore, in this embodiment, the driving signal Q is input to the control circuit 100 again, so that a feedback loop can be formed between the driving circuit and the pull-up transistor T1 and the pull-down transistor T2, without additionally inputting other selection signals. The output of the first selection circuit 111 is selected, thereby realizing a driving circuit with a simpler control method and higher reliability.
  • the pull-down control circuit 120 includes a second selection circuit 121, one input terminal of the second selection circuit 121 is used to receive the input signal D, and the other input terminal of the second selection circuit 121 is used to receive the input signal D.
  • the input signal DD is delayed
  • the control terminal of the second selection circuit 121 is used for receiving the driving signal Q
  • the output terminal of the second selection circuit 121 is connected to the control terminal of the pull-down transistor T2.
  • the second selection circuit 121 is used to select one of the input signal D and the delayed input signal DD as the pull-up control signal A1 according to the driving signal Q, so as to control the conduction or the pull-down of the pull-down transistor T2. It is turned off, so as to realize the adjustment of the driving signal Q.
  • the pull-up control signal A0 and the pull-up control signal A1 are different, and are one of the input signal D and the delayed input signal DD, respectively.
  • FIG. 4 is a schematic structural diagram of a driving circuit according to another embodiment.
  • the first selection circuit 111 and the second selection circuit 121 each include two transmission gates, and one control terminal of the transmission gate is used for The driving signal Q is input, the other control terminal of the transmission gate is used to input the inverted signal QN of the driving signal, and the signals input by the two control terminals of the transmission gate are jointly used to control the transmission gate. on or off.
  • the driving circuit further includes a first inverter 101, and the input terminal of the first inverter 101 is connected to the second terminal of the pull-up transistor T1 to invert the driving signal Q, thereby generating an inverted signal of the driving signal qn.
  • the first selection circuit 111 includes a first transmission gate 1111 and a second transmission gate 1112
  • the second selection circuit 121 includes a third transmission gate 1211 and a fourth transmission gate 1212
  • the first selection circuit The hardware structures of 111 and the second selection circuit 121 are the same.
  • the first selection circuit 111 is used as an example for description.
  • the hardware structures of the first transmission gate 1111 and the second transmission gate 1112 are the same, and both are configured with one input terminal and two control terminals.
  • the second control terminal is enabled by a low level, and the second control terminal is enabled by a high level.
  • the input terminal of the first transmission gate 1111 is used to input the delayed input signal DD
  • the first control terminal of the first transmission gate 1111 is used to input the driving signal Q
  • the second control terminal of the first transmission gate 1111 is used to input the inversion of the driving signal.
  • the phase signal QN, the input terminal of the second transmission gate 1112 is used to input the input signal D
  • the first control terminal of the second transmission gate 1112 is used to input the inverted signal QN of the driving signal
  • the second control terminal of the second transmission gate 1112 Used to input the drive signal Q.
  • the driving signal Q changes, the switching speeds of the on-off states of the two transistors in each transmission gate are different, and only the two transistors of the transmission gate only need When one is turned on, the required pull-up control signal A0 can be output, thereby increasing the output speed of the first selection circuit 111 .
  • the third transmission gate 1211 of the second selection circuit 121 corresponds to the aforementioned first transmission gate 1111
  • the fourth transmission gate 1212 corresponds to the aforementioned second transmission gate 1112. Therefore, for the operation of the second selection circuit 121, reference may be made to the aforementioned first transmission gate 1212. An operation mode of the selection circuit 111 will not be repeated here.
  • the first selection circuit 111 and the second selection circuit 121 are not limited to the structures shown in the embodiment of FIG. 4 , and in other embodiments, the first selection circuit 111 and the second selection circuit 121 may also be other The structure of the multiplexer that realizes the function of choosing one from two.
  • the delay circuit 200 includes two second inverters 210 connected in series to generate a delayed input signal DD, and the phase difference between the delayed input signal DD and the input signal D is equal to two inversions The sum of the delay times of the device.
  • the pull-up transistor T1 is a P-type transistor
  • the pull-down transistor T2 is an N-type transistor.
  • DDR4 has lower requirements on transmission speed and driving performance, so a P-type transistor can be used.
  • the pull-up transistor T1 is an N-type transistor
  • the pull-down transistor T2 is an N-type transistor.
  • LPDDR4 has higher performance requirements for the drive circuit.
  • the N-type transistor The pull-up transistor T1 can transmit signals lower than the power supply Vcc.
  • the driving circuit of the present embodiment can transmit a signal with a smaller output voltage swing than the driving circuit in which the pull-up transistor T1 is a P-type transistor, thereby realizing more Low power consumption.
  • using an N-type transistor as the pull-up transistor T1 can effectively reduce the size of the driving circuit compared to a P-type transistor.
  • the pull-up transistor T1 and the pull-down transistor T2 can use the same N-type transistor, thereby improving the symmetry characteristics of the pull-up transistor T1 and the pull-down transistor T2, and further improving the performance of the driving circuit.
  • FIG. 5 is a timing diagram of a process in which the pull-down transistor T2 is turned off and the pull-up transistor T1 is turned on in an embodiment.
  • the pull-up transistor T1 is switched from the off state to the state of the pull-up transistor T1 at time t1.
  • On state it is defined that the pull-down transistor T2 is switched from the on-state to the off-state at time t2; wherein, in a process in which the pull-down transistor T2 is turned off and the pull-up transistor T1 is turned on, the t2 is earlier at the t1.
  • the pull-down transistor T2 can be turned off first, and then the pull-up transistor T1 can be turned on, thereby preventing the formation of a DC path between the power supply Vcc and the ground Vss, thereby preventing invalid power consumption.
  • the purpose of the above state switching can be achieved by adjusting the timing of the input signals D of the control terminals of the two transistors.
  • the response speeds of the pull-up transistor T1 and the pull-down transistor T2 are the same, that is, the time required for the pull-up control signal A0 to switch from a high level to a low level is the same as the time required for the pull-up control signal A1 to change from a high level to a low level. It takes the same amount of time to switch from level to low.
  • the start time of the signal input from the control terminal of the pull-up transistor T1 changes from a high level to a low level as t5
  • the signal input from the control terminal of the pull-down transistor T2 is defined to change from a high level to a low level.
  • the start time of the low-level transition is t6; wherein, in a process in which the pull-down transistor T2 is turned off and the pull-up transistor T1 is turned on, the t6 is earlier than the t5.
  • the state switching time of the pull-up transistor T1 and the pull-down transistor T2 can be controlled, thereby realizing a simple control logic. , and the drive circuit with accurate inversion result of the Q level state of the drive signal. Further, in this embodiment, t2 and t5 are set to be the same time, so as to further ensure the reliability of the timing sequence.
  • FIG. 6 is a timing diagram of a process in which the pull-up transistor T1 is turned off and the pull-down transistor T2 is turned on in an embodiment.
  • the pull-up transistor T1 is switched from the on state to the on state at time t3.
  • the off state defines that the pull-down transistor T2 is switched from the off-state to the on-state at time t4; wherein, in a process in which the pull-up transistor T1 is turned off and the pull-down transistor T2 is turned on, the t3 early at said t4.
  • the pull-up transistor T1 can be turned off first, and then the pull-down transistor T2 can be turned on, thereby preventing the formation of a DC path between the power supply Vcc and the ground Vss, thereby preventing invalid power consumption.
  • the purpose of the above state switching can be achieved by adjusting the timing of the input signals of the control terminals of the two transistors.
  • the start time of the transition of the signal input from the terminal from low level to high level is t8; wherein, in a process in which the pull-up transistor T1 is turned off and the pull-down transistor T2 is turned on, the t7 is earlier than the t8.
  • the state switching time of the pull-up transistor T1 and the pull-down transistor T2 can be controlled, thereby realizing a simple control logic. , and the drive circuit with accurate inversion result of the Q level state of the drive signal.

Abstract

一种驱动电路，包括：上拉晶体管和下拉晶体管，上拉晶体管的第一端与电源连接，上拉晶体管的第二端与下拉晶体管的第一端连接，以共同输出驱动信号，下拉晶体管的第二端与地连接；以及控制电路，分别于上拉晶体管和/或下拉晶体管的控制端连接，用于控制上拉晶体管和/或下拉晶体管的导通或关断，以改变驱动信号；其中，上拉晶体管和下拉晶体管在控制电路的控制下，不同时导通。

Description

驱动电路
相关申请交叉引用
本申请要求2020年09月07日递交的、标题为“驱动电路”、申请号为2020109287680的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本申请涉及一种驱动电路。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是现在重要的记忆存储元件之一，由于DRAM功能多、且制造成本低廉，被广泛应用于电脑、通讯及家电等领域。
随着智能手机、平板电脑等移动设备的逐渐普及，在现在的移动设备中，大都使用随机存取存储器(DRAM)作为内存。
发明内容
根据多个实施例，本申请第一方面提供一种驱动电路，包括：
上拉晶体管和下拉晶体管，所述上拉晶体管的第一端与电源连接，所述上拉晶体管的第二端与所述下拉晶体管的第一端连接，以共同输出驱动信号，所述下拉晶体管的第二端与地连接；以及
控制电路，分别于所述上拉晶体管和/或所述下拉晶体管的控制端连接，用于控制所述上拉晶体管和/或下拉晶体管的导通或关断，以改变所述驱动信 号；
其中，所述上拉晶体管和所述下拉晶体管在所述控制电路的控制下，不同时导通。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例的驱动电路的结构示意图。
图2为另一实施例的驱动电路的结构示意图。
图3为又一实施例的驱动电路的结构示意图。
图4为再一实施例的驱动电路的结构示意图。
图5为一实施例的下拉晶体管关断且上拉晶体管导通过程的时序图。
图6为一实施例的上拉晶体管关断且下拉晶体管导通过程的时序图。
元件标号说明：
控制电路：100；上拉晶体管：200；下拉晶体管：300；第一反相器：101；上拉控制电路：110；第一选择电路：111；第一传输门：1111；第二传输门：1112；下拉控制电路：120；第二选择电路：121；第三传输门：1211；第四传输门：1212；延迟电路：200；第二反相器：210
具体实施方式
DRAM在进行数据读写时功耗较高，因此需要消耗大量的电能，从而导致移动设备的电池消耗快，大大影响了用户体验。
为了便于理解本申请实施例，下面将参照相关附图对本申请实施例进行更全面的描述。附图中给出了本申请实施例的首选实施例。但是，本申请实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请实施例的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请实施例的限制。
图1为一实施例的驱动电路的结构示意图，参考图1，在本实施例中，驱动电路包括上拉晶体管T1、下拉晶体管T2和控制电路100，所述上拉晶体管T1和所述下拉晶体管T2在所述控制电路100的控制下，不同时导通。
上拉晶体管T1的控制端与控制电路100的输出端连接，上拉晶体管T1的第一端与电源Vcc连接，上拉晶体管T1的第二端与下拉晶体管T2的第一 端连接，上拉晶体管T1受控制电路100的控制，改变上拉晶体管T1的第二端输出的电压。具体地，当控制电路100控制上拉晶体管T1导通时，上拉晶体管T1的第一端和第二端导通，则电源Vcc可以将上拉晶体管T1第二端的输出上拉至电源Vcc；当控制电路100控制上拉晶体管T1断开时，上拉晶体管T1的第一端和第二端断开。
下拉晶体管T2的控制端与控制电路100的输出端连接，下拉晶体管T2的第一端与下拉晶体管T2的第二端连接，下拉晶体管T2的第二端与地Vss连接，下拉晶体管T2受控制电路100的控制，改变下拉晶体管T2的第一端输出的电压。具体地，当控制电路100控制下拉晶体管T2导通时，下拉晶体管T2的第二端和第一端导通，则可以将下拉晶体管T2第一端的输出下拉至地Vss；当控制电路100控制下拉晶体管T2断开时，下拉晶体管T2的第二端和第一端断开。其中，通过将上拉晶体管T1的第二端与下拉晶体管T2的第一端连接，以共同输出驱动信号Q，可以实现更快的驱动信号Q的电平翻转速度。
控制电路100，分别与所述上拉晶体管T1和/或所述下拉晶体管T2的控制端连接，用于控制所述上拉晶体管T1和/或下拉晶体管T2的导通或关断，以改变所述驱动信号Q。具体地，控制电路100通过控制上拉晶体管T1和下拉晶体管T2，可以改变驱动信号Q的电平状态，例如从高电平切换至低电平，或从低电平切换至高电平。
可以理解的是，晶体管的导通或关断的状态切换是响应于控制端输入的信号的，但是，在驱动电路中，控制端的信号切换通常是一个渐变式的切换，而非阶跃式的切换。示例性地，假设控制端的信号需要由0V切换至3.5V，则控制端的信号电压是在一定的时间端内逐渐抬升至3.5V的，即信号电压与时 间之间的关系曲线具有一定斜率。而晶体管的通断状态之间的切换是以一阈值电压作为临界点的，例如阈值电压可以为0.7V。以图1中所示的低电平使能的上拉晶体管T1为例，是在控制端的电压降低至0.7V时才切换至导通状态的，并且是在控制端的电压升高至0.7V时才切换至断开状态的。因此，晶体管自身的通断的可靠性是不足的，会发生上拉晶体管T1和下拉晶体管T2中的一个已经打开，但另一个仍未关闭的情况，即在驱动信号Q的翻转过程中，会存在一中间状态，上拉晶体管T1和下拉晶体管T2同时打开，这样每次翻转都会出现从电源Vcc到地的直流通路，从而引起比较大的无效功耗，造成背景技术中描述的驱动电路的功耗较高的问题。
在本实施例中，通过控制电路100输出的控制信号，使上拉晶体管T1和下拉晶体管T2不同时导通，即，使上拉晶体管T1和下拉晶体管T2中的一个先切换至断开状态，再使另一个切换至导通状态，可以防止电源Vcc与地Vss之间形成直流通路，从而节省了无效功耗。而且，还可以避免两个晶体管同时打开时的竞争状态，消除了同时打开时产生的电流毛刺现象，改善了输出的驱动信号Q的稳定性。因此，本实施例通过上述结构，提供了一种功耗更低、信号稳定性更好的驱动电路。
在图1所示的实施例中，上拉晶体管T1为低电平使能，下拉晶体管T2为高电平使能。在其他实施例中，可以采用高电平使能的上拉晶体管T1和低电平使能的下拉晶体管T2。也可以采用使能方式相同的晶体管作为上拉晶体管T1和下拉晶体管T2，通过控制电路100分别生成两路电平状态不同的控制信号，并分别一一对应地输入至上拉晶体管T1和下拉晶体管T2。还可以选择断开的响应速度快于导通的响应速度的晶体管作为上拉晶体管T1和下拉晶体管T2，从而实现需要的断开和导通的时序。需要说明的是，图1中的 上拉晶体管T1和下拉晶体管T2仅用于示例性说明，而不用于限定本申请的保护范围，只要可以实现两个晶体管中的一个先断开、另一个再导通即可，其它可以实现上述功能的晶体管结构或控制电路100的控制逻辑，也属于本申请的保护范围。
图2为另一实施例的驱动电路的结构示意图，参考图2，在本实施例中，驱动电路包括控制电路100、上拉晶体管T1、下拉晶体管T2和延迟电路200。其中，控制电路100、上拉晶体管T1和下拉晶体管T2的结构和连接方式与图1实施例相同，此处不再进行赘述。
延迟电路200，与所述控制电路100连接，用于接收输入信号D，并对所述输入信号D进行预设延迟，以生成延迟输入信号DD，其中，所述输入信号D和所述延迟输入信号DD均用于输入至所述控制电路100。
具体地，延迟电路200可以为固定延迟链。示例性地，固定延迟链可以包括多个串联的传输门，每个传输门配置有固定的延迟时间，因此，可以根据延迟电路200所需产生的预设延迟时间设置相应数量的传输门，从而产生目标的预设延迟时间。另一示例性地，固定延迟链也可以包括偶数个串联的反相器，通过设置偶数个反相器，可以确保输出的延迟输入信号DD与输入信号D的电平状态相对应，且只存在时序上的差异，与前述传输门构成的固定延迟链相似地，可以根据延迟电路200所需产生的预设延迟时间设置相应数量的反相器，从而产生目标的预设延迟时间。
延迟电路200也可以为可变延迟链。可以理解的是，上拉晶体管T1和下拉晶体管T2的通断特性，以及信号传输路径上的传输速度，都会随着使用环境的温度等条件的变化而发生改变。因此，若使用环境的条件变化，会存在导致上拉晶体管T1和下拉晶体管T2的通断时序发生错误的风险。在本实施 例中，通过设置由可变延迟链构成的延迟电路200，并设置一相应的检测结构，通过检测结构，可以对驱动电路的使用环境的条件变化情况进行检测，并根据检测结果调节可变延迟链的延迟时间，从而避免了上拉晶体管T1和下拉晶体管T2的通断时序发生错误，进而避免了电源Vcc与地Vss之间形成直流通路，防止了驱动电路的无效功耗，即，提供了一种功耗更低的驱动电路。
图3为又一实施例的驱动电路的结构示意图，参考图3，在本实施例中，所述驱动电路包括控制电路100、上拉晶体管T1、下拉晶体管T2和延迟电路200。其中，延迟电路200、上拉晶体管T1和下拉晶体管T2的结构和连接方式与图2实施例相同，此处不再进行赘述。
在本实施例中，控制电路100具体包括上拉控制电路110和下拉控制电路120。上拉控制电路110与所述上拉晶体管T1的控制端连接，用于控制所述上拉晶体管T1的导通或关断，其中，上拉控制电路110接收输入信号D和延迟输入信号DD，并根据输入信号D和延迟输入信号DD生成上拉控制信号A0。下拉控制电路120与所述下拉晶体管T2的控制端连接，用于控制所述下拉晶体管T2的导通或关断，下拉控制电路120接收输入信号D和延迟输入信号DD，并根据输入信号D和延迟输入信号DD生成上拉控制信号A1。其中，上拉控制信号A0与上拉控制信号A1的时序不同，且二者的时序差异可以使上拉晶体管T1和下拉晶体管T2中的一个先断开、且另一个再导通，即，两个控制信号之间的时序关系与两个晶体管的通断顺序相对应。
进一步地，所述控制电路100还用于接收所述驱动信号Q，并根据所述驱动信号Q选择输出所述输入信号D或所述延迟输入信号DD，以控制所述上拉晶体管T1和下拉晶体管T2根据预设顺序依次导通或关断。
具体地，继续参考图3，在其中一个实施例中，所述上拉控制电路110 包括第一选择电路111，所述第一选择电路111的一个输入端用于接收所述输入信号D，所述第一选择电路111的另一个输入端用于接收所述延迟输入信号DD，所述第一选择电路111的控制端用于接收所述驱动信号Q，所述第一选择电路111的输出端与所述上拉晶体管T1的控制端连接。第一选择电路111用于根据驱动信号Q，选择输入信号D和延迟输入信号DD中的一个作为上拉控制信号A0，以控制上拉晶体管T1的导通或关断，从而实现对驱动信号Q的调节。
可以理解的是，本实施例的驱动电路用于实现对驱动信号Q的电平状态的翻转，即，翻转后的驱动信号Q的电平状态是与翻转前的驱动信号Q的电平状态的完全相反的。因此，在本实施例中将驱动信号Q再输入至控制电路100，可以使驱动电路与上拉晶体管T1、下拉晶体管T2之间构成一反馈回路，而无需额外输入其它的选择信号，即可对第一选择电路111的输出进行选择，从而实现了控制方法更加简单、且可靠性更高的驱动电路。
所述下拉控制电路120包括第二选择电路121，所述第二选择电路121的一个输入端用于接收所述输入信号D，所述第二选择电路121的另一个输入端用于接收所述延迟输入信号DD，所述第二选择电路121的控制端用于接收所述驱动信号Q，所述第二选择电路121的输出端与所述下拉晶体管T2的控制端连接。与前述第一选择电路111相似地，第二选择电路121用于根据驱动信号Q，选择输入信号D和延迟输入信号DD中的一个作为上拉控制信号A1，以控制下拉晶体管T2的导通或关断，从而实现对驱动信号Q的调节。其中，上拉控制信号A0和上拉控制信号A1不同，且分别为输入信号D和延迟输入信号DD中的一个。
图4为再一实施例的驱动电路的结构示意图，参考图4，所述第一选择 电路111和所述第二选择电路121均包括两个传输门，所述传输门的一个控制端用于输入所述驱动信号Q，所述传输门的另一个控制端用于输入所述驱动信号的反相信号QN，所述传输门的两个控制端输入的信号共同用于控制所述传输门的导通或断开。其中，驱动电路还包括第一反相器101，第一反相器101的输入端与上拉晶体管T1的第二端连接，以对驱动信号Q进行反相，从而生成驱动信号的反相信号QN。具体地，在本实施例中，第一选择电路111包括第一传输门1111和第二传输门1112，第二选择电路121包括第三传输门1211和第四传输门1212，且第一选择电路111和第二选择电路121的硬件结构相同。
此处以第一选择电路111作为示例进行说明，第一传输门1111和第二传输门1112的硬件结构相同，均配置有一个输入端和两个控制端，且两个控制端中的第一控制端为低电平使能，第二控制端为高电平使能。第一传输门1111的输入端用于输入延迟输入信号DD，第一传输门1111的第一控制端用于输入驱动信号Q，第一传输门1111的第二控制端用于输入驱动信号的反相信号QN，第二传输门1112的输入端用于输入输入信号D，第二传输门1112的第一控制端用于输入驱动信号的反相信号QN，第二传输门1112的第二控制端用于输入驱动信号Q。
可以理解的是，基于上述结构，在同一时刻，第一传输门1111和第二传输门1112中只有一个能输出信号，从而实现了信号的选择功能。而且，晶体管由导通状态向断开状态的切换速度与由断开状态向导通状态的切换速度是不同的，因此，本实施例通过在传输门中设置两个使能方式不同的晶体管，并将两个晶体管的输出端分别一一对应连接，当驱动信号Q发生改变时，每个传输门中的两个晶体管的通断状态的切换速度是不同的，而且传输门的两 个晶体管中只要有一个导通即可输出所需的上拉控制信号A0，从而提高了第一选择电路111的输出速度。
第二选择电路121的第三传输门1211与前述第一传输门1111相对应，第四传输门1212与前述第二传输门1112相对应，因此，第二选择电路121的运行方式可参考前述第一选择电路111的运行方式，此处不再进行赘述。需要说明的是，第一选择电路111和第二选择电路121不局限于图4实施例中示出的结构，在其他实施例中，第一选择电路111和第二选择电路121也可以为其他结构的实现二选一功能的多路选择器。
继续参考图4，在本实施例中，延迟电路200包括串联连接的两个第二反相器210，以生成延迟输入信号DD，延迟输入信号DD与输入信号D的相位差等于两个反相器的延迟时间之和。
进一步地，若存储器为DDR4，则所述上拉晶体管T1为P型晶体管，所述下拉晶体管T2为N型晶体管，DDR4对传输速度和驱动性能的要求较低，因此可以采用P型晶体管。若存储器为LPDDR4，则所述上拉晶体管T1为N型晶体管，所述下拉晶体管T2为N型晶体管，LPDDR4对驱动电路的性能要求更高，与P型的上拉晶体管T1相比，N型的上拉晶体管T1可以传输低于电源Vcc的信号。因此，与上拉晶体管T1为P型晶体管的驱动电路相比，本实施例的驱动电路可以传输比上拉晶体管T1为P型晶体管的驱动电路的输出电压摆幅更小的信号，从而实现更低的功耗。此外，与P型晶体管相比，使用N型晶体管作为上拉晶体管T1可以有效地减小驱动电路的尺寸。再进一步地，可以使上拉晶体管T1和下拉晶体管T2采用相同的N型晶体管，从而提高上拉晶体管T1和下拉晶体管T2的对称特性，以进一步提升驱动电路的性能。
图5为一实施例的下拉晶体管T2关断且上拉晶体管T1导通过程的时序图，参考图5，在本实施例中，定义所述上拉晶体管T1在t1时刻由关断状态切换至导通状态，定义所述下拉晶体管T2在t2时刻由导通状态切换至关断状态；其中，在一次所述下拉晶体管T2关断且所述上拉晶体管T1导通过程中，所述t2早于所述t1。通过上述时序关系，即可先关断下拉晶体管T2、后打开上拉晶体管T1，从而防止电源Vcc与地Vss之间形成直流通路，进而防止无效功耗。
进一步地，可以通过调节两个晶体管的控制端输入信号D的时序实现上述状态切换的目的。具体地，在本实施例中，上拉晶体管T1和下拉晶体管T2的响应速度相同，即上拉控制信号A0由高电平切换至低电平所需的时间与上拉控制信号A1由高电平切换至低电平所需的时间相同。继续参考图5，定义所述上拉晶体管T1的控制端输入的信号从高电平向低电平转换的开始时刻为t5，定义所述下拉晶体管T2的控制端输入的信号从高电平向低电平转换的开始时刻为t6；其中，在一次所述下拉晶体管T2关断且所述上拉晶体管T1导通的过程中，所述t6早于所述t5。在本实施例中，基于相同响应速度的上拉晶体管T1和下拉晶体管T2，通过设置相应的信号输入时间，即可控制上拉晶体管T1和下拉晶体管T2的状态切换时间，从而实现了控制逻辑简单、且驱动信号Q电平状态翻转结果准确的驱动电路。进一步地，本实施例设置t2和t5为同一时刻，从而进一步确保时序的可靠性。
图6为一实施例的上拉晶体管T1关断且下拉晶体管T2导通过程的时序图，参考图6，在本实施例中，定义所述上拉晶体管T1在t3时刻由导通状态切换至关断状态，定义所述下拉晶体管T2在t4时刻由关断状态切换至导通状态；其中，在一次所述上拉晶体管T1关断且所述下拉晶体管T2导通过程 中，所述t3早于所述t4。通过上述时序关系，即可先关断上拉晶体管T1、后打开下拉晶体管T2，从而防止电源Vcc与地Vss之间形成直流通路，进而防止无效功耗。
进一步地，可以通过调节两个晶体管的控制端输入信号的时序实现上述状态切换的目的。具体地，在本实施例中，继续参考图6，定义所述上拉晶体管T1的控制端输入的信号从低电平向高电平转换的开始时刻为t7，定义所述下拉晶体管T2的控制端输入的信号从低电平向高电平转换的开始时刻为t8；其中，在一次所述上拉晶体管T1关断且所述下拉晶体管T2导通的过程中，所述t7早于所述t8。在本实施例中，基于相同响应速度的上拉晶体管T1和下拉晶体管T2，通过设置相应的信号输入时间，即可控制上拉晶体管T1和下拉晶体管T2的状态切换时间，从而实现了控制逻辑简单、且驱动信号Q电平状态翻转结果准确的驱动电路。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请实施例构思的前提下，还可以做出若干变形和改进，这些都属于本申请实施例的保护范围。因此，本申请实施例专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种驱动电路，包括：
    上拉晶体管和下拉晶体管，所述上拉晶体管的第一端与电源连接，所述上拉晶体管的第二端与所述下拉晶体管的第一端连接，以共同输出驱动信号，所述下拉晶体管的第二端与地连接；以及
    控制电路，分别于所述上拉晶体管和/或所述下拉晶体管的控制端连接，用于控制所述上拉晶体管和/或下拉晶体管的导通或关断，以改变所述驱动信号；
    其中，所述上拉晶体管和所述下拉晶体管在所述控制电路的控制下，不同时导通。
  2. 根据权利要求1所述的驱动电路，还包括：
    延迟电路，与所述控制电路连接，用于接收输入信号，并对所述输入信号进行预设延迟，以生成延迟输入信号；
    其中，所述输入信号和所述延迟输入信号均用于输入至所述控制电路。
  3. 根据权利要求2所述的驱动电路，其中所述控制电路还用于接收所述驱动信号，并根据所述驱动信号选择输出所述输入信号或所述延迟输入信号，以控制所述上拉晶体管和下拉晶体管根据预设顺序依次导通或关断。
  4. 根据权利要求3所述的驱动电路，其中所述控制电路包括：
    上拉控制电路，与所述上拉晶体管的控制端连接，用于控制所述上拉晶体管的导通或关断；
    下拉控制电路，与所述下拉晶体管的控制端连接，用于控制所述下拉晶体管的导通或关断。
  5. 根据权利要求4所述的驱动电路，其中所述上拉控制电路包括第一选 择电路，所述第一选择电路的一个输入端用于接收所述输入信号，所述第一选择电路的另一个输入端用于接收所述延迟输入信号，所述第一选择电路的控制端用于接收所述驱动信号，所述第一选择电路的输出端与所述上拉晶体管的控制端连接；
    所述下拉控制电路包括第二选择电路，所述第二选择电路的一个输入端用于接收所述输入信号，所述第二选择电路的另一个输入端用于接收所述延迟输入信号，所述第二选择电路的控制端用于接收所述驱动信号，所述第二选择电路的输出端与所述下拉晶体管的控制端连接。
  6. 根据权利要求5所述的驱动电路，其中所述第一选择电路和所述第二选择电路均包括两个传输门，所述传输门的一个控制端用于输入所述驱动信号，所述传输门的另一个控制端用于输入所述驱动信号的反相信号，所述传输门的两个控制端输入的信号共同用于控制所述传输门的导通或断开。
  7. 根据权利要求1所述的驱动电路，其中所述上拉晶体管为N型晶体管或P型晶体管，所述下拉晶体管为N型晶体管。
  8. 根据权利要求1所述的驱动电路，其中定义所述上拉晶体管在t1时刻由关断状态切换至导通状态，定义所述下拉晶体管在t2时刻由导通状态切换至关断状态；
    其中，在一次所述下拉晶体管关断且所述上拉晶体管导通过程中，所述t2早于所述t1。
  9. 根据权利要求1所述的驱动电路，其中定义所述上拉晶体管在t3时刻由导通状态切换至关断状态，定义所述下拉晶体管在t4时刻由关断状态切换至导通状态；
    其中，在一次所述上拉晶体管关断且所述下拉晶体管导通过程中，所述 t3早于所述t4。
  10. 根据权利要求1所述的驱动电路，其中定义所述上拉晶体管的控制端输入的信号从高电平向低电平转换的开始时刻为t5，定义所述下拉晶体管的控制端输入的信号从高电平向低电平转换的开始时刻为t6；
    其中，在一次所述下拉晶体管关断且所述上拉晶体管导通的过程中，所述t6早于所述t5。
  11. 根据权利要求1所述的驱动电路，其中定义所述上拉晶体管的控制端输入的信号从低电平向高电平转换的开始时刻为t7，定义所述下拉晶体管的控制端输入的信号从低电平向高电平转换的开始时刻为t8；
    其中，在一次所述上拉晶体管关断且所述下拉晶体管导通的过程中，所述t7早于所述t8。
  12. 根据权利要求2所述的驱动电路，其中所述延迟电路为固定延迟链。
  13. 根据权利要求12所述的驱动电路，其中所述固定延迟链包括多个串联的传输门，每个传输门配置有固定的延迟时间。
  14. 根据权利要求12所述的驱动电路，其中所述固定延迟链包括偶数个串联的反相器。
  15. 据权利要求2所述的驱动电路，其中所述延迟电路为可变延迟链。
PCT/CN2021/100824 2020-09-07 2021-06-18 驱动电路 WO2022048246A1 (zh)

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