WO2022041975A1 - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
WO2022041975A1
WO2022041975A1 PCT/CN2021/101434 CN2021101434W WO2022041975A1 WO 2022041975 A1 WO2022041975 A1 WO 2022041975A1 CN 2021101434 W CN2021101434 W CN 2021101434W WO 2022041975 A1 WO2022041975 A1 WO 2022041975A1
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region
drain
source
mask
ions
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PCT/CN2021/101434
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English (en)
French (fr)
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黄炜
骆晓东
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长鑫存储技术有限公司
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Priority to US17/404,087 priority Critical patent/US11855183B2/en
Publication of WO2022041975A1 publication Critical patent/WO2022041975A1/zh

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    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a method for manufacturing a semiconductor device.
  • the size and width of the source and drain active regions of the transistor continue to shrink, resulting in the continuous increase of the series resistance of the active region of the device and the contact resistance of a single contact hole.
  • a metal layer is deposited on the polysilicon gate and active area by physical vapor deposition, and then a heat treatment step is performed to make the metal layer react with the silicon of the active area and the polysilicon gate.
  • Metal silicides are formed on the active area and the polysilicon surface.
  • the peripheral region MOS transistors are implanted in the source and drain ions to form the source region.
  • tungsten contact holes are first formed in the substrates of the source region and drain region through photolithography and etching processes, and then metal silicide and metal tungsten are deposited in the tungsten contact holes.
  • the distance from the edge of the pole region is affected by the feature size of the gate, the feature size of the tungsten contact hole photolithography process, and the alignment deviation of the tungsten contact hole and the gate; with the continuous improvement of the integration of semiconductor devices, the gate size gradually decreases. Small, the distance between the metal silicide and the edge of the drain region decreases, and the junction leakage current increases gradually, which in turn affects the performance and power consumption of the semiconductor device.
  • a method of fabricating a semiconductor device is provided.
  • a method of manufacturing a semiconductor device comprising:
  • the first mask pattern exposes a source electrode preset area and a drain electrode preset area defined on both sides of the gate structure
  • first ion implantation is performed on the source preset region and the drain preset region to form a pre-amorphized region
  • a third doping process is performed on the second doped region to form a heavily doped source region and heavily doped drain region.
  • a mask is used to form a first mask pattern on a substrate, and the first mask pattern exposes the source electrode preset region and the drain electrode preset region located on both sides of the gate structure ;
  • the first ion implantation is performed on the source preset region and the drain preset region to form a pre-amorphized region in an amorphous state, reducing Small follow-up implantation depth and implantation width of ions in the pre-amorphized region; then second ion implantation into the pre-amorphized region, the second ions will occupy the interstitial vacancies between atoms to form an amorphized region;
  • the second doping region is formed by the second doping process on the amorphized region, the lateral diffusion and vertical diffusion of doping ions in the second doping region are suppressed, and the heavily doped drain region and drain The effective distance to the edge of the region will increase, thereby reducing the junction leakage
  • the above-mentioned semiconductor device is manufactured by any one of the above-mentioned manufacturing methods, and the pre-amorphized region in the amorphous state will reduce the implantation depth and implantation width of the subsequent ion implantation to the pre-amorphized region;
  • the dopant ions of the ions will occupy the interstitial vacancies between atoms, so that the lateral diffusion and vertical diffusion of the dopant ions in the lightly doped region are suppressed, and the effective distance between the heavily doped drain region and the edge of the drain region will increase. Further, the purpose of reducing the junction leakage current, reducing the distance between the metal silicide and the edge of the drain region and reducing the influence on the junction leakage current is achieved.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor device in one embodiment
  • FIG. 2 is a cross-sectional view of a semiconductor device after forming a pre-amorphized region in one embodiment
  • FIG. 3 is a cross-sectional view of a semiconductor device after forming an amorphized region in one embodiment
  • FIG. 4 is a cross-sectional view of a semiconductor device after forming a first spacer in an embodiment
  • FIG. 5 is a flow chart of forming a second doped region in one embodiment
  • FIG. 6 is a cross-sectional view of a semiconductor device after forming a second doped region in an embodiment
  • FIG. 7 is a cross-sectional view of a semiconductor device after forming a heavily doped source region and a heavily doped drain region in one embodiment
  • FIG. 8 is a flow chart of a method for manufacturing a semiconductor device in another embodiment
  • FIG. 9 is a cross-sectional view of a semiconductor device after forming source contact holes and drain contact holes in one embodiment.
  • first doping type becomes the second doping type
  • second doping type can be the first doping type
  • the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the invention.
  • Metal silicide is a metal compound formed by a chemical reaction between metal and silicon, and its electrical conductivity is between metal and silicon.
  • the silicon of the gate reacts to form metal silicide, and the metal will not react with the contacting dielectric materials such as SiO2, Si3N4, and SiON.
  • the technology of aligning the polysilicon gate and forming metal silicide on the active area and the polysilicon gate at the same time is called Self Aligned Silicide (Salicide).
  • the metal silicide parts of the source and drain regions of the MOS transistors in the peripheral region are located in the contact holes formed in the source and drain regions of the substrate; with the continuous improvement of the integration of semiconductor devices, the gate The size gradually decreases, the distance between the metal silicide and the edge of the drain region decreases, and the junction leakage current increases gradually.
  • a method for manufacturing a semiconductor device including:
  • the substrate may be a silicon substrate, a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), a silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI), etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • germanium-on-insulator germanium-on-insulator
  • the gate structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer; the gate dielectric layer may be silicon oxide (SiO2) or silicon oxynitride (SiNO).
  • the gate dielectric layer is preferably a high dielectric constant (high-k) material.
  • the high-k materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium oxide silicon, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. .
  • hafnium oxide, zirconium oxide and aluminum oxide are desirable embodiments.
  • the formation process of the gate dielectric layer may adopt any prior art known to those skilled in the art, such as chemical vapor deposition.
  • the gate structure is a gate oxide layer, a polysilicon layer, a titanium nitride layer, a tungsten metal layer, and a silicon nitride layer in order from the substrate. S104, forming pre-amorphization regions on both sides of the gate structure.
  • a mask pattern is used to form a first mask pattern on the substrate, and the first mask pattern exposes the source electrode preset region and the drain electrode preset region located on both sides of the gate structure.
  • the mask is a mask for defining lightly doped regions (ie, LDD photo), and a first mask pattern is formed on the substrate through the LDD photo, and the first mask pattern exposes two parts of the gate structure.
  • the source preset area and the drain preset area on the side.
  • first ion implantation is performed on the source preset region and the drain preset region to form a pre-amorphized region, and the pre-amorphized region is located at the gate both sides of the pole structure.
  • a second ion implantation is performed on the pre-amorphized region to form an amorphized region.
  • S108 forming first spacers on both sides of the gate structure.
  • S110 performing a second doping process to form a second doping region in the amorphized region.
  • a second mask pattern is formed on the substrate by using the mask, that is, a second mask pattern is formed on the substrate using the mask used for forming the first mask pattern, and the second mask pattern is formed on the substrate.
  • the pattern exposes the source predetermined region and the drain predetermined region located on both sides of the gate structure, and the first spacers located on both sides of the gate structure in the source predetermined region and the drain predetermined region.
  • a second doping process is performed on the amorphized region to form a second doping region.
  • S112 forming second sidewalls on both sides of the first sidewall.
  • S114 forming heavily doped source and drain regions in the second doped region.
  • a third mask pattern is formed on the substrate using the mask, that is, a third mask pattern is formed on the substrate using the mask used for forming the first mask pattern, and the third mask pattern is formed on the substrate.
  • the pattern exposes the source pre-set area and the drain pre-set area on both sides of the gate structure, and the first spacer and the second spacer on both sides of the gate structure in the source pre-set area and the drain pre-set area. side wall.
  • a third doping process is performed on the second doping region to form a heavy doping source electrode region and heavily doped drain region.
  • the first mask pattern, the second mask pattern and the third mask pattern are formed by the same mask, which reduces the number of photoresist plates used in the manufacturing process of the semiconductor device and saves the production cost.
  • the first mask pattern, the second mask pattern, and the third mask pattern include at least one of a photoresist pattern and a hard mask layer pattern.
  • the first mask pattern, the second mask pattern, and the third mask pattern are used as photoresist patterns for illustration below.
  • a cross-sectional view of the semiconductor device after the pre-amorphization region is formed.
  • a lightly doped mask is used to form a first photoresist pattern (not shown in the figure) on the substrate 100, and the first photoresist pattern is exposed on the gate structure.
  • the shallow doped regions 102 on both sides of the gate structure 104 namely the source pre-set regions and the drain pre-set regions on both sides of the gate structure 104 .
  • a first ion implantation is performed on the shallow doped region 102 exposed by the first photoresist pattern to form a pre-amorphized region 106 in the shallow doped region 102.
  • the substrate of the pre-amorphized region is in an amorphous state, which reduces the implantation depth and implantation width of the dopant ions during subsequent ion implantation into the pre-amorphized region.
  • step S106 includes: the first step, using the first photoresist pattern as a mask, to perform a first step on the pre-amorphized region 106 .
  • Two ion implantation forms an amorphized region 108 in the pre-amorphized region 106 ; in the second step, the first photoresist pattern on the substrate 100 is removed.
  • the implanted second ions will occupy the interstitial vacancies between the substrate atoms in the pre-amorphized region, thereby inhibiting the doped region formed in the pre-amorphized region.
  • the diffusion of doping ions increases the effective distance between the surface of the doping region and the edge of the doping region, thereby achieving the purpose of reducing junction leakage current.
  • first spacers 110 are formed on the substrate 100 on both sides of the gate structure 104 , and the first spacers 110 are located in a part of the amorphized region 108 close to the gate structure 104 superior.
  • the material of the first spacer 110 may be insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the first spacer 110 may be a combination of silicon nitride and silicon oxide, and further, may be an ON structure formed by sequentially formed silicon oxide and silicon nitride, or may be formed by sequentially formed oxide ONO structure composed of silicon, silicon nitride and silicon oxide.
  • the step of forming the first spacer 110 on the substrate 100 on both sides of the gate structure 104 includes: a first step, forming a first spacer film on the surface of the substrate 100; A photoresist pattern covering the first sidewall film to be retained is formed on the bottom surface; in the third step, after etching and removing the first sidewall film exposed by the photoresist pattern, the photoresist pattern on the surface of the substrate is removed, A first sidewall 110 composed of the remaining first sidewall film is obtained.
  • the step of forming the second doped region includes:
  • a third ion implantation is performed on the amorphization region 108 to form a pocket implantation region 112 in the amorphization region 108;
  • the third ion implantation is opposite to the doping type of the third doping process.
  • a fourth ion implantation is performed on the pocket-shaped implantation region 112, and light doping is formed in the pocket-shaped implantation region 112 respectively
  • the lightly doped source region 114 and the drain region 116 are surrounded by the pocket-shaped implantation region 112, and the depletion regions on both sides of the source region and the drain region close to the channel region are narrowed by the pocket-shaped implantation region 112, so that the source region and the drain region are narrowed. for the purpose of alleviating the short channel effect.
  • the second doped region includes a pocket-shaped implantation region 112 and a lightly-doped source region 114 and a lightly-doped drain region 116 located in the pocket-shaped implantation region 112 .
  • the third ion implantation adopts an oblique ion implantation process, and the angle between the implantation direction of the oblique ion implantation process and the surface normal of the substrate is 10° ⁇ 25°, for example, 15 degrees. , 20 degrees, etc.
  • the third ion is a P-type dopant ion, such as boron fluoride ion, boron ion, indium ion, etc.; the fourth ion is an N-type dopant ion, such as phosphorus ion, arsenic ion Wait.
  • P-type dopant ion such as boron fluoride ion, boron ion, indium ion, etc.
  • the fourth ion is an N-type dopant ion, such as phosphorus ion, arsenic ion Wait.
  • the third ions are N-type doping ions
  • the fourth ions are P-type doping ions.
  • a second spacer 118 is formed on both sides of the first spacer 110 , and then a third doping process is performed on the second doping region to form a heavily doped source located in the lightly doped source region 114 Pole region 120 and heavily doped drain region 122 in lightly doped drain region 116 .
  • the step further includes: forming an interlayer dielectric layer 124 on the substrate 100.
  • the method further includes:
  • An interlayer dielectric layer 124 is formed on the substrate 100 , and the interlayer dielectric layer 124 is located on the substrate 100 and the first spacers 110 on the heavily doped source region 120 and the heavily doped drain region 122 , the second spacer 118 and the gate structure 104 , the thickness of the interlayer dielectric layer 124 on the heavily doped drain region 122 is equal to the thickness of the gate structure 104 and the layer above the gate structure 104 The sum of the thicknesses of the intermediate dielectric layers 124 .
  • the interlayer dielectric layer 124 includes an oxide layer and a silicon nitride layer.
  • An etching process is performed on the interlayer insulating layer 124, and a source contact hole 126 and a drain contact hole 128 are formed in the heavily doped source region 120 and the heavily doped drain region 122, respectively, that is, separately formed.
  • the source contact hole 126 of the heavily doped source region 120 is partially exposed and the drain contact hole 128 of the heavily doped drain region 122 is partially exposed.
  • the bottoms of the source contact hole 126 and the drain contact hole 128 are in the heavily doped source region 120 and the heavily doped drain region 122 respectively, that is, the source contact hole 126 is formed
  • the etching process for the drain contact hole 128 is an over-etching process, so as to remove the gap between the source contact hole 126 and the heavily doped source region 120 and between the drain contact hole 128 and the heavily doped drain region 122 .
  • the purpose of the interlayer insulating layer 124 is to eliminate the interlayer insulating layer between the source contact hole 126 and the heavily doped source region 120 and between the drain contact hole 128 and the heavily doped drain region 122 caused by process variation. 124 Residual purpose.
  • a source contact hole 126 and a drain contact hole 128 are respectively formed in the heavily doped source region 120 and the heavily doped drain region 122 through a wet etching process.
  • a source contact hole 126 and a drain contact hole 128 are respectively formed in the heavily doped source region 120 and the heavily doped drain region 122 through a dry etching process.
  • step S306 includes:
  • a source metal silicide and a drain metal silicide are formed in the source contact hole 126 and the drain contact hole 128; a source contact structure is formed on the source metal silicide, and a source contact structure is formed on the drain A drain contact structure is formed on the metal silicide.
  • the pre-amorphized region, the amorphized region and the pocket-shaped implanted region formed in the substrate play a role in inhibiting the diffusion of doping ions in the lightly doped region, and are located in the drain contact hole on the heavily doped drain region 122
  • the equivalent distance between the formed drain metal silicide (not shown in the figure) and the doping boundary of the drain region (that is, the doping boundary of the lightly doped drain region) (as shown in FIG.
  • the boundary position between the doped drain region 116 and the pocket implanted region 112 is increased, that is, the equivalent distance between the metal silicide of the drain region and the doped boundary of the drain region is increased, which substantially reduces the junction leakage current.
  • the first ions include at least one of germanium ions, silicon ions, fluoride ions and antimony ions.
  • the second ions include at least one of carbon ions, nitrogen ions and fluorine ions.
  • the energy of the first ion implantation is greater than or equal to 6 keV and less than or equal to 14 keV, for example, 6.5 keV, 7 keV, 8 keV, 10 keV Electron Volts, 12 keV, etc.
  • the dose of the first ion implantation is greater than or equal to 1*10 14 atom/cm 2 and less than or equal to 5*10 14 atom/cm 2 , for example, 1.5*10 14 atom/cm 2 , 2.0*10 14 atom/cm 2 , 2.5*10 14 atom/cm 2 , 3*10 14 atom/cm 2 and so on.
  • the energy of the second ion implantation is greater than or equal to 2 keV and less than or equal to 4 keV
  • the dose of the second ion implantation is greater than or equal to 1*10 14 atom/cm 2 and less than or equal to 5*10 14 atom/cm 2 , such as 1.5*10 14 atom/cm 2 , 2.0*10 14 atom/cm 2 , 2.5*10 14 atom/cm 2 , 3*10 14 atom/cm 2 , etc. Wait.
  • the doping performed by the third doping process and the fourth ion implantation is ions of the same doping type, for example, both are N-type impurity ions, and both are P-type impurity ions.
  • the doping ions of the third doping process and the fourth ions are the same impurity ions.
  • the implantation angle of the first ion implantation and the second ion implantation is 0 degrees, and the implantation angle refers to the angle between the implantation direction and the normal line of the substrate surface.
  • the first ion implantation and the second ion implantation do not affect the substrate under the gate structure while reducing the depth and width of the ion implantation on both sides of the gate structure and the speed of ion diffusion.
  • ICs integrated circuits
  • memory circuits such as random access memory (RAM), synchronous DRAM (SDRAM), static RAM (SRAM), or read only memory (ROM) Wait.
  • RAM random access memory
  • SDRAM synchronous DRAM
  • SRAM static RAM
  • ROM read only memory
  • PDA programmable logic array
  • ASIC application specific integrated circuit
  • buried DRAM combined DRAM logic integrated circuit
  • radio frequency circuit and the like.
  • a mask is used to form a first mask pattern on a substrate, and the first mask pattern exposes the source electrode preset region and the drain electrode preset region located on both sides of the gate structure ;
  • the first ion implantation is performed on the source preset region and the drain preset region to form a pre-amorphized region in an amorphous state, reducing Small follow-up implantation depth and implantation width of ions in the pre-amorphized region; then second ion implantation into the pre-amorphized region, the second ions will occupy the interstitial vacancies between atoms to form an amorphized region;
  • the second doping region is formed by the second doping process on the amorphized region, the lateral diffusion and vertical diffusion of doping ions in the second doping region are suppressed, and the heavily doped drain region and drain The effective distance to the edge of the region will increase, thereby reducing the junction leakage
  • a semiconductor device fabricated by any one of the above-described manufacturing methods.
  • the semiconductor device includes a PMOS transistor, a dynamic random access memory device.
  • an electronic device including the above-described semiconductor device.
  • the above semiconductor device is manufactured by the manufacturing method described in any one of the above, and the pre-amorphized region in an amorphous state will reduce the implantation depth and implantation width of the subsequent ion implantation to the pre-amorphized region; in the amorphized region
  • the doping ions will occupy the interstitial vacancies between atoms, so that the lateral diffusion and vertical diffusion of the doped ions in the lightly doped region are suppressed, and the effective distance between the heavily doped drain region and the edge of the drain region will increase. , thereby achieving the purpose of reducing the junction leakage current, reducing the distance between the metal silicide and the edge of the drain region and reducing the influence on the junction leakage current.

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Abstract

一种半导体器件的制造方法，包括：获取衬底，所述衬底上形成有栅极结构；对衬底进行第一离子注入，在栅极结构两侧形成预非晶化区；对预非晶化区进行第二离子注入，在所述预非晶化区中形成非晶化区；在栅极结构两侧形成第一侧墙；进行第二掺杂工艺，在所述非晶化区中形成第二掺杂区；在第一侧墙两侧形成第二侧墙；及在所述第二掺杂区中形成重掺杂的源极区和漏极区。

Description

半导体器件的制造方法
相关申请的交叉引用
本申请要求于2020年8月28日提交中国专利局、申请号为202010887738X、发明名称为“半导体器件的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体器件的制造方法。
背景技术
随着半导体工艺的特征尺寸的缩小，晶体管源和漏有源区的尺寸宽度不断缩小，导致器件的有源区串联电阻和单个接触孔的接触电阻不断增大，为了降低有源区的串联电阻和接触电阻，在完成源和漏离子注入之后，利用物理气相沉积在多晶硅栅和有源区上沉积一层金属层，然后进行热处理步骤使金属层与有源区和多晶硅栅的硅反应，在有源区和多晶硅表面形成金属硅化物。
与逻辑芯片制造工艺的自对准金属硅化物相比，典型的动态随机存取存储器件(Dynamic Random Access Memory，DRAM)的制造工艺中，外围区域MOS晶体管在源和漏离子注入形成源极区和漏极区之后，先通过光刻、刻蚀工艺在源极区和漏极区的衬底中形成钨接触孔，然后在钨接触孔中沉积金属硅化物和金属钨，金属硅化物与漏极区边缘的距离受栅极的特征尺寸、钨接触孔光刻工艺的特征尺寸以及钨接触孔和栅极的对准偏差的影响；随着半 导体器件集成度的不断提高，栅极尺寸逐渐减小，金属硅化物与漏极区边缘的距离减小，结漏电流逐渐增大，进而影响半导体器件的性能和功耗。
发明内容
根据各种实施例，提供一种半导体器件的制造方法。
一种半导体器件的制造方法，包括：
获取衬底，所述衬底上形成有栅极结构；
使用掩膜版在所述衬底上形成第一掩膜图形，所述第一掩膜图形露出定义位于所述栅极结构两侧的源极预设区域和漏极预设区域；
以所述第一掩膜图形为第一掩膜，对所述源极预设区域和漏极预设区域进行第一离子注入，形成预非晶化区；
对所述预非晶化区进行第二离子注入，形成非晶化区；
在所述栅极结构两侧形成第一侧墙；
使用所述掩膜版在所述衬底上形成第二掩膜图形；
以所述第二掩膜图形和所述第一侧墙为第二掩膜，对所述非晶化区进行第二掺杂工艺，形成第二掺杂区；
在所述第一侧墙两侧形成第二侧墙；
使用所述掩膜版在所述衬底上形成第三掩膜图形；及
以所述第三掩膜图形、所述第一侧墙和所述第二侧墙为第三掩膜，对所述第二掺杂区进行第三掺杂工艺，形成重掺杂源极区和重掺杂漏极区。
上述半导体器件的制造方法，使用掩膜版在衬底上形成第一掩膜图形，所述第一掩膜图形露出位于所述栅极结构两侧的源极预设区域和漏极预设区域；首先，以所述第一掩膜图形为第一掩膜，对所述源极预设区域和漏极预 设区域进行第一离子注入，形成处于非晶状态的预非晶化区，减小后续对预非晶化区进行注入时离子的注入深度和注入宽度；然后对预非晶化区进行第二离子注入，第二离子会占据原子之间的间隙空位，形成非晶化区；在对非晶化区进行第二掺杂工艺形成的第二掺杂区后，第二掺杂区的掺杂离子的横向扩散、纵向扩散均会被抑制，重掺杂漏极区与漏极区边缘的有效距离会增大，进而达到降低结漏电流，减小金属硅化物与漏极区边缘的距离减小对结漏电流的影响的目的。
一种半导体器件，所述半导体器件由上述任一项所述的制造方法制成。
上述半导体器件由上述任一项所述的制造方法制成，非晶状态的预非晶化区会减小后续对预非晶化区进行离子注入的注入深度和注入宽度；非晶化区中的掺杂离子会占据原子之间的间隙空位，使得轻掺杂区的掺杂离子的横向扩散、纵向扩散均被抑制，重掺杂漏极区与漏极区边缘的有效距离会增大，进而达到降低结漏电流，减小金属硅化物与漏极区边缘的距离减小对结漏电流的影响的目的。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中半导体器件的制造方法的流程图；
图2为一实施例中形成预非晶化区后半导体器件的剖视图；
图3为一实施例中形成非晶化区后半导体器件的剖视图；
图4为一实施例中形成第一侧墙后半导体器件的剖视图；
图5为一实施例中形成第二掺杂区的流程图；
图6为一实施例中形成第二掺杂区后半导体器件的剖视图；
图7为一实施例中形成重掺杂源极区和重掺杂漏极区后半导体器件的剖视图；
图8为另一实施例中半导体器件的制造方法的流程图；
图9为一实施例中形成源极接触孔和漏极接触孔后半导体器件的剖视图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、 部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来 描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
金属硅化物是由金属和硅经过化学反应形成的一种金属化合物，其导电特性介于金属和硅之间，典型的金属硅化物(Silicide)工艺是利用金属与直接接触的有源区和多晶硅栅的硅反应形成金属硅化物，金属不会与接触的SiO2、Si3N4和SiON等介质材料发生反应，因此，在有源区和多晶硅栅表面形成的金属硅化物能够很好地与有源区和多晶硅栅对准，同时在有源区和多晶硅栅上形成金属硅化物的技术被称之为自对准金属硅化物(Self Aligned Silicide，Salicide)。
在DRAM工艺中，外围区域MOS晶体管源极区和漏极区的金属硅化物部分位于源极区和漏极区衬底中形成的接触孔内；随着半导体器件集成度的不断提高，栅极尺寸逐渐减小，金属硅化物与漏极区边缘之间的距离减小，结漏电流逐渐增大。
如图1所示，在其中一个实施例中，提供一种半导体器件的制造方法，包括：
S102，获取衬底，所述衬底上形成有栅极结构。
所述衬底可以是硅衬底、绝缘体上硅衬底(SOI)、绝缘体上层叠硅衬底(SSOI)、绝缘体上层叠锗化硅衬底(S-SiGeOI)、绝缘体上锗化硅衬底 (SiGeOI)以及绝缘体上锗衬底(GeOI)等。
在其中一个实施例中，所述栅极结构包括栅介质层和位于栅介质层上的栅极导电层；所述栅介质层可以为氧化硅(SiO2)或氮氧化硅(SiNO)。在65nm以下的工艺节点，栅极结构的特征尺寸很小，栅介质层优选高介电层常数(高k)材料。所述高k材料包括氧化铪、氧化铪硅、氮氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化铝等。理想实施例中的是氧化铪、氧化锆和氧化铝。栅介电层的形成工艺可以采用本领域技术人员熟知的任何现有技术，例如化学气相沉积法。
在其中一个实施例中，所述栅极结构自衬底而上依次为栅氧层、多晶硅层、氮化钛层、钨金属层、氮化硅层。S104，在栅极结构两侧形成预非晶化区。
使用掩膜版在衬底上形成第一掩膜图形，所述第一掩膜图形露出位于所述栅极结构两侧的源极预设区域和漏极预设区域。所述掩膜版为用于定义轻掺杂区域的掩膜版(即LDD photo)，通过LDD photo在衬底上形成第一掩膜图形，所述第一掩膜图形露出位于栅极结构两侧的源极预设区域和漏极预设区域。以所述第一掩膜图形为第一掩膜，对所述源极预设区域和漏极预设区域进行第一离子注入，形成预非晶化区，所述预非晶化区位于栅极结构的两侧。
S106，在所述预非晶化区中形成非晶化区。
以第一掩膜图形为掩膜，对所述预非晶化区进行第二离子注入，形成非晶化区。S108，在所述栅极结构两侧形成第一侧墙。S110，进行第二掺杂工艺，在所述非晶化区中形成第二掺杂区。
首先，使用所述掩膜版在所述衬底上形成第二掩膜图形，即使用形成第 一掩膜图形的掩膜版在衬底上形成第二掩膜图形，所述第二掩膜图形露出位于所述栅极结构两侧的源极预设区域和漏极预设区域，以及源极预设区域和漏极预设区域中位于栅极结构两侧的第一侧墙。
其次，以所述第二掩膜图形和所述第一侧墙为第二掩膜，对所述非晶化区进行第二掺杂工艺，形成第二掺杂区。
S112，在所述第一侧墙两侧形成第二侧墙。S114，在所述第二掺杂区中形成重掺杂的源极区和漏极区。
首先，使用所述掩膜版在所述衬底上形成第三掩膜图形，即使用形成第一掩膜图形的掩膜版在衬底上形成第三掩膜图形，所述第三掩膜图形露出位于所述栅极结构两侧的源极预设区域和漏极预设区域，以及源极预设区域和漏极预设区域中位于栅极结构两侧的第一侧墙和第二侧墙。
其次，以所述第三掩膜图形、所述第一侧墙和所述第二侧墙为第三掩膜，对所述第二掺杂区进行第三掺杂工艺，形成重掺杂源极区和重掺杂漏极区。
第一掩膜图形、第二掩膜图形和第三掩膜图形是通过同一个掩膜版形成的，减少了半导体器件制造工艺中使用的光刻版的数量，节约了生产成本。
在其中一个实施例中，所述第一掩膜图形、第二掩膜图形、第三掩膜图形至少包括光刻胶图形、硬掩膜层图形中的一种。以下以第一掩膜图形、第二掩膜图形、第三掩膜图形为光刻胶图形进行举例说明。
如图2所示，为一实施例中，形成预非晶化区后半导体器件的剖视图。第具体为，第一步，使用轻掺杂掩膜版在衬底100上形成第一光刻胶图形(图中未示出)，所述第一光刻胶图形露出位于所述栅极结构104两侧的浅掺杂区102，即位于栅极结构104两侧的源极预设区域和漏极预设区域。第二步，对所述第一光刻胶图形露出的浅掺杂区102进行第一离子注入，形成位于浅掺 杂区102中的预非晶化区106。通过第一离子注入使得预非晶化区的衬底处于非晶状态，减小了后续对预非晶化区进行离子注入时掺杂离子的注入深度和注入宽度。
如图3所示，为一实施例中形成非晶化区后半导体器件的剖视图，步骤S106包括：第一步，以第一光刻胶图形为掩膜，对预非晶化区106进行第二离子注入，在预非晶化区106中形成非晶化区108；第二步，去除衬底100上的第一光刻胶图形。在对预非晶化区进行第二离子注入时，注入的第二离子会占据预非晶化区中衬底原子之间的间隙空位，从而抑制在预非晶化区形成的掺杂区中掺杂离子的扩散，增大掺杂区表面与掺杂区边缘的有效距离，进而达到降低结漏电流的目的。
如图4所示，在栅极结构104两侧的衬底100上形成第一侧墙110，所述第一侧墙110位于所述非晶化区108靠近所述栅极结构104的部分区域上。第一侧墙110的材料可以是氮化硅、氧化硅、氮氧化硅等绝缘材料。在一个实施方式中，第一侧墙110可以是氮化硅和氧化硅的组合，进一步地，可以是由依次形成的氧化硅和氮化硅构成的ON结构，也可以是由依次形成的氧化硅、氮化硅和氧化硅构成的ONO结构。
在其中一个实施中，在栅极结构104两侧的衬底100上形成第一侧墙110的步骤包括：第一步，在衬底100表面形成第一侧墙薄膜；第二步，在衬底表面形成覆盖在需要保留的第一侧墙薄膜上的光刻胶图形；第三步，刻蚀去除光刻胶图形露出的第一侧墙薄膜后，去除衬底表面的光刻胶图形，得到由剩余第一侧墙薄膜构成的第一侧墙110。
如图5，图6所示，在其中一个实施例中，所述形成第二掺杂区的步骤包括：
S202，在所述非晶化区形成袋状注入区。
以所述第二掩膜图形和所述第一侧墙110为第二掩膜，对所述非晶化区108进行第三离子注入，在非晶化区108中形成袋状注入区112；所述第三离子注入与所述第三掺杂工艺的掺杂类型相反。
S204，在所述袋状注入区中形成轻掺杂的源极区和漏极区。
以所述第二掩膜图形和所述第一侧墙110为第二掩膜，对所述袋状注入区112进行第四离子注入，在所述袋状注入区112中分别形成轻掺杂源极区114和轻掺杂漏极区116；其中，所述第三离子与所述第四离子的掺杂类型相反。轻掺杂的源极区114和漏极区116被袋状注入区112包围，通过袋状注入区112使得源极区和漏极区靠近沟道区的两侧的耗尽区变窄，起到缓解短沟道效应的目的。
其中，第二掺杂区包括袋状注入区112和位于袋状注入区112中的轻掺杂源极区114和轻掺杂漏极区116。
在其中一个实施例中，所述第三离子注入采用倾斜离子注入工艺，所述倾斜离子注入工艺的注入方向和所述衬底表面法线之间的角度为10°～25°，例如15度、20度等等。
在其中一个实施例中，所述第三离子为P型掺杂离子，例如氟化硼离子、硼离子、铟离子等；所述第四离子为N型掺杂离子，例如磷离子、砷离子等。
在另一个实施例中，所述第三离子为N型掺杂离子，所述第四离子为P型掺杂离子。
如图7所示，在第一侧墙110两侧形成第二侧墙118，然后对第二掺杂区进行第三掺杂工艺，形成位于轻掺杂源极区114中的重掺杂源极区120和位于轻掺杂漏极区116中的重掺杂漏极区122。在其中一个实施例中，形成重 掺杂源极区120和重掺杂漏极区122之后还包括：在衬底100上形成层间介质层124的步骤。
如图8、图9所示，在其中一个实施例中，所述方法还包括：
S302，在衬底100上形成层间介质层124。
在衬底100上形成层间介质层124，所述层间介质层124位于所述重掺杂源极区120和重掺杂漏极区122上的衬底100、所述第一侧墙110、第二侧墙118以及所述栅极结构104上，所述重掺杂漏极区122上层间介质层124的厚度等于所述栅极结构104的厚度与位于栅极结构104上方的层间介质层124的厚度之和。
在其中一个实施例中，所述层间介质层124包括氧化层和氮化硅层。
S304，形成源极接触孔和漏极接触孔。
对所述层间绝缘层124进行刻蚀工艺，分别在所述重掺杂源极区120和所述重掺杂漏极区122形成源极接触孔126和漏极接触孔128，即别形成暴露出部分所述重掺杂源极区120的源极接触孔126和暴露出部分所述重掺杂漏极区122的漏极接触孔128。在其中一个实施例中，所述源极接触孔126和漏极接触孔128的底部分别在所述重掺杂源极区120和重掺杂漏极区122中，即形成源极接触孔126和漏极接触孔128的刻蚀工艺为过刻蚀工艺，达到去除源极接触孔126与重掺杂源极区120之间、漏极接触孔128和重掺杂漏极区122之间的层间绝缘层124的目的，消除了工艺偏差引起的源极接触孔126与重掺杂源极区120之间、漏极接触孔128和重掺杂漏极区122之间的层间绝缘层124残留的目的。
在其中一个实施例中，通过湿法刻蚀工艺分别在所述重掺杂源极区120和所述重掺杂漏极区122形成源极接触孔126和漏极接触孔128。
在其中一个实施例中，通过干法刻蚀工艺分别在所述重掺杂源极区120和所述重掺杂漏极区122形成源极接触孔126和漏极接触孔128。
S306，在所述源极接触孔和所述漏极接触孔中依次形成源极接触结构和漏极接触结构。
在其中一个实施例中，步骤S306包括：
在所述源极接触孔126和所述漏接触孔128中形成源极金属硅化物和漏极金属硅化物；分别在所述源极金属硅化物上形成源极接触结构、在所述漏极金属硅化物上形成漏极接触结构。
衬底中形成的预非晶化区、非晶化区以及袋状注入区对轻掺杂区掺杂离子的扩散起到抑制的作用，位于重掺杂漏极区122上的漏接触孔中形成的漏极金属硅化物(图中未示出)与漏极区的掺杂边界(即轻掺杂漏极区的掺杂边界)之间的等效距离(如图9所示，为轻掺杂漏极区116与袋状注入区112的边界位置)有所增加，即增加了漏极区的金属硅化物与漏极区的掺杂边界之间的等效距离，实质上降低了结漏电流。
在其中一个实施例中，所述第一离子至少包括锗离子、硅离子、氟离子和锑离子中的一种。
在其中一个实施例中，所述第二离子至少包括碳离子、氮离子和氟离子中的一种。
在其中一个实施例中，所述第一离子注入的能量大于或等于6千电子伏且小于或等于14千电子伏，例如，6.5千电子伏特、7千电子伏特、8千电子伏特、10千电子伏特、12千电子伏特等等。所述第一离子注入的剂量大于或等于1*10 14atom/cm 2且小于或等于5*10 14atom/cm 2，例如1.5*10 14atom/cm 2、2.0*10 14atom/cm 2、2.5*10 14atom/cm 2、3*10 14atom/cm 2等等。
在其中一个实施例中，所述第二离子注入的能量大于或等于2千电子伏且小于或等于4千电子伏，所述第二离子注入的剂量大或等于1*10 14atom/cm 2且小于或等于5*10 14atom/cm 2，例如1.5*10 14atom/cm 2、2.0*10 14atom/cm 2、2.5*10 14atom/cm 2、3*10 14atom/cm 2等等。
在其中一个实施例中，所述第三掺杂工艺和所述第四离子注入进行的掺杂为掺杂类型相同的离子，例如均为N型杂质离子，均为P型杂质离子。
在其中一个实施例中，所述第三掺杂工艺的掺杂离子和所述第四离子为相同的杂质离子。
在其中一个实施例中，所述第一离子注入和所述第二离子注入的注入角度为0度，所述注入角度是指注入方向和所述衬底表面法线之间的角度。使得第一离子注入和第二离子注入在降低栅极结构两侧离子注入的深度、宽度、和离子扩散的速度的同时，不对栅极结构下方的衬底产生影响。
上述半导体器件的制造方法可以应用于多种集成电路(IC)中，例如存储器电路，如随机存取存储器(RAM)、同步DRAM(SDRAM)、静态RAM(SRAM)、或只读存储器(ROM)等。又例如可以是逻辑器件，如可编程逻辑阵列(PLA)、专用集成电路(ASIC)、合并式DRAM逻辑集成电路(掩埋式DRAM)、射频电路等。
上述半导体器件的制造方法，使用掩膜版在衬底上形成第一掩膜图形，所述第一掩膜图形露出位于所述栅极结构两侧的源极预设区域和漏极预设区域；首先，以所述第一掩膜图形为第一掩膜，对所述源极预设区域和漏极预设区域进行第一离子注入，形成处于非晶状态的预非晶化区，减小后续对预非晶化区进行注入时离子的注入深度和注入宽度；然后对预非晶化区进行第二离子注入，第二离子会占据原子之间的间隙空位，形成非晶化区；在对非 晶化区进行第二掺杂工艺形成的第二掺杂区后，第二掺杂区的掺杂离子的横向扩散、纵向扩散均会被抑制，重掺杂漏极区与漏极区边缘的有效距离会增大，进而达到降低结漏电流，减小金属硅化物与漏极区边缘的距离减小对结漏电流的影响的目的。
在其中一个实施例中，提供一种半导体器件，所述半导体器件由上述任一项所述的制造方法制成。
在其中一个实施例中，所述半导体器件包括PMOS晶体管、动态随机存取存储器件。
在其中一个实施中，提供一种电子设备，所述电子设备包括上述半导体器件。
上述半导体器件，上述任一项所述的制造方法制成，非晶状态的预非晶化区会减小后续对预非晶化区进行离子注入的注入深度和注入宽度；非晶化区中的掺杂离子会占据原子之间的间隙空位，使得轻掺杂区的掺杂的离子的横向扩散、纵向扩散均被抑制，重掺杂漏极区与漏极区边缘的有效距离会增大，进而达到降低结漏电流，减小金属硅化物与漏极区边缘的距离减小对结漏电流的影响的目的。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种半导体器件的制造方法，包括：
    获取衬底，所述衬底上形成有栅极结构；
    使用掩膜版在所述衬底上形成第一掩膜图形，所述第一掩膜图形露出位于所述栅极结构两侧的源极预设区域和漏极预设区域；
    以所述第一掩膜图形为第一掩膜，对所述源极预设区域和漏极预设区域进行第一离子注入，形成预非晶化区；
    对所述预非晶化区进行第二离子注入，形成非晶化区；在所述栅极结构两侧形成第一侧墙；
    使用所述掩膜版在所述衬底上形成第二掩膜图形；
    以所述第二掩膜图形和所述第一侧墙为第二掩膜，对所述非晶化区进行第二掺杂工艺，形成第二掺杂区；
    在所述第一侧墙两侧形成第二侧墙；
    使用所述掩膜版在所述衬底上形成第三掩膜图形；及
    以所述第三掩膜图形、所述第一侧墙和所述第二侧墙为第三掩膜，对所述第二掺杂区进行第三掺杂工艺，形成重掺杂源极区和重掺杂漏极区。
  2. 根据权利要求1所述的方法，其中所述形成第二掺杂区包括：
    以所述第二掩膜图形和所述第一侧墙为第二掩膜，对所述非晶化区进行第三离子注入，形成袋状注入区；
    以所述第二掩膜图形和所述第一侧墙为第二掩膜，对所述袋状注入区进行第四离子注入，形成轻掺杂源极区和轻掺杂漏极区；
    其中，所述第三离子与所述第四离子的掺杂类型相反。
  3. 根据权利要求2所述的方法，其中所述第三离子注入采用倾斜离子注 入工艺，所述倾斜离子注入工艺的注入方向和所述衬底表面法线之间的角度为10°～25°。
  4. 根据权利要求1所述的方法，其中所述第一离子至少包括锗离子、硅离子、氟离子和锑离子中的一种。
  5. 根据权利要求1所述的方法，其中所述第二离子至少包括碳离子、氮离子和氟离子中的一种。
  6. 根据权利要求1所述的方法，其中所述第一离子注入的能量大于或等于6千电子伏且小于或等于14千电子伏，所述第一离子注入的剂量大于或等于1*10 14atom/cm 2且小于或等于5*10 14atom/cm 2。
  7. 根据权利要求1所述的方法，其中所述第二离子注入的能量大于或等于2千电子伏且小于或等于4千电子伏，所述第二离子注入的剂量大或等于1*10 14atom/cm 2且小于或等于5*10 14atom/cm 2。
  8. 根据权利要求3所述的方法，其中所述第三离子为N型杂质离子，所述第四离子为P型杂质离子。
  9. 根据权利要求1所述的方法，还包括：
    在所述衬底上形成层间绝缘层；
    对所述层间绝缘层进行刻蚀工艺，分别形成暴露出部分所述重掺杂源极区的源极接触孔和暴露出部分所述重掺杂漏极区的漏极接触孔；及
    在所述源极接触孔和所述漏接触孔中形成源极接触结构和漏极接触结构。
  10. 根据权利要求9所述的方法，其中在所述源极接触孔和所述漏接触孔中形成源极接触结构和漏极接触结构包括：
    在所述源极接触孔和所述漏接触孔中形成源极金属硅化物和漏极金属硅 化物；
    分别在所述源极金属硅化物上形成源极接触结构、在所述漏极金属硅化物上形成漏极接触结构。
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