TWI822155B - 電晶體結構及其製造方法 - Google Patents

電晶體結構及其製造方法 Download PDF

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TWI822155B
TWI822155B TW111124467A TW111124467A TWI822155B TW I822155 B TWI822155 B TW I822155B TW 111124467 A TW111124467 A TW 111124467A TW 111124467 A TW111124467 A TW 111124467A TW I822155 B TWI822155 B TW I822155B
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pocket
drain
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廖政華
柯宗杰
林幸如
謝榮裕
楊令武
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旺宏電子股份有限公司
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Abstract

一種電晶體結構，包括基底、閘極結構、多個第一口袋摻雜區、多個第二口袋摻雜區、多個源極/汲極延伸區與多個源極/汲極區。閘極結構位在基底上。多個第一口袋摻雜區位在閘極結構旁的基底中。第一口袋摻雜區的摻質包括IVA族元素。多個第二口袋摻雜區位在閘極結構旁的基底中。第二口袋摻雜區的深度大於第一口袋摻雜區的深度。多個源極/汲極延伸區位在多個第一口袋摻雜區中。多個源極/汲極區位在閘極結構旁的基底中。源極/汲極延伸區位在源極/汲極區與閘極結構之間。

Description

電晶體結構及其製造方法
本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種電晶體結構及其製造方法。
隨著半導體技術的進步，電晶體元件的尺寸也不斷地縮小。然而，電晶體元件的摻雜區中的摻質容易因為熱製程而擴散。如此一來，會造成電晶體元件有效通道長度的縮減，而發生短通道效應(short channel effect)，進而降低電晶體元件的電性表現。
本發明提供一種電晶體結構及其製造方法，其可有效地抑制短通道效應。
本發明提出一種電晶體結構，包括基底、閘極結構、多個第一口袋摻雜區(pocket doped region)、多個第二口袋摻雜區、多個源極/汲極延伸區(source/drain extension (SDE) region)與多個源極/汲極區。閘極結構位在基底上。多個第一口袋摻雜區位在閘極結構旁的基底中。第一口袋摻雜區的摻質包括IVA族元素。多個第二口袋摻雜區位在閘極結構旁的基底中。第二口袋摻雜區的深度大於第一口袋摻雜區的深度。多個源極/汲極延伸區位在多個第一口袋摻雜區中。多個源極/汲極區位在閘極結構旁的基底中。源極/汲極延伸區位在源極/汲極區與閘極結構之間。
依照本發明的一實施例所述，在上述電晶體結構中，第一口袋摻雜區的摻質包括可為碳(C)或鍺(Ge)。
依照本發明的一實施例所述，在上述電晶體結構中，源極/汲極區可連接於源極/汲極延伸區。上述電晶體結構更可包括多個間隙壁。多個間隙壁位在閘極結構的側壁上。源極/汲極延伸區可位在間隙壁下方。
依照本發明的一實施例所述，在上述電晶體結構中，更可包括多個第一接觸窗摻雜區(contact doped region)與多個第二接觸窗摻雜區。多個第一接觸窗摻雜區位在閘極結構旁的基底中。源極/汲極區可位在第一接觸窗摻雜區中。第一接觸窗摻雜區的摻質可包括IVA族元素。第二接觸窗摻雜區位在多個第一接觸窗摻雜區中。第二接觸窗摻雜區的深度可大於源極/汲極區的深度。
本發明提出另一種電晶體結構，包括基底、閘極結構、多個源極/汲極區與多個接觸窗摻雜區。閘極結構位在基底上。多個源極/汲極區位在閘極結構旁的基底中。多個接觸窗摻雜區位在閘極結構旁的基底中。源極/汲極區位在接觸窗摻雜區中。接觸窗摻雜區的摻質包括IVA族元素。
本發明提出一種電晶體結構的製造方法，包括以下步驟。提供基底。在基底上形成閘極結構。在閘極結構旁的基底中形成多個第一口袋摻雜區。第一口袋摻雜區的摻質包括IVA族元素。在閘極結構旁的基底中形成多個第二口袋摻雜區。第二口袋摻雜區的深度大於第一口袋摻雜區的深度。在多個第一口袋摻雜區中形成多個源極/汲極延伸區。在閘極結構旁的基底中形成多個源極/汲極區。源極/汲極延伸區位在源極/汲極區與閘極結構之間。
依照本發明的一實施例所述，在上述電晶體結構的製造方法中，第一口袋摻雜區的形成方法可為冷植入(cold implant)。冷植入的溫度可為-20℃至-100℃。
依照本發明的一實施例所述，在上述電晶體結構的製造方法中，更可包括以下步驟。在閘極結構旁的基底中形成多個第一接觸窗摻雜區。源極/汲極區位在第一接觸窗摻雜區中。第一接觸窗摻雜區的摻質可包括IVA族元素。
依照本發明的一實施例所述，在上述電晶體結構的製造方法中，第一接觸窗摻雜區的形成方法可為冷植入。冷植入的溫度可為-20℃至-100℃。
依照本發明的一實施例所述，在上述電晶體結構的製造方法中，更可包括以下步驟。在多個第一接觸窗摻雜區中形成多個第二接觸窗摻雜區。第二接觸窗摻雜區的深度可大於源極/汲極區的深度。
基於上述，在本發明的一些實施例的電晶體結構中，多個源極/汲極延伸區位在多個第一口袋摻雜區中，且第一口袋摻雜區的摻雜包括IVA族元素。因此，可藉由第一口袋摻雜區來抑制源極/汲極延伸區中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應(punch through effect)，且可降低漏電流。在本發明的一些實施例的電晶體結構中，源極/汲極區位在接觸窗摻雜區中，且接觸窗摻雜區的摻質包括IVA族元素。因此，可藉由接觸窗摻雜區來抑制源極/汲極區中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應，且可降低阻值。在本發明的一些實施例的電晶體結構的製造方法中，在多個第一口袋摻雜區中形成多個源極/汲極延伸區，且第一口袋摻雜區的摻質包括IVA族元素。因此，可藉由第一口袋摻雜區來抑制源極/汲極延伸區中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應，且可降低漏電流。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
下文列舉實施例並配合附圖來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。為了方便理解，在下述說明中相同的構件將以相同的符號標示來說明。此外，附圖僅以說明為目的，並未依照原尺寸作圖。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A至圖1F為根據本發明的一些實施例的電晶體結構的製造流程剖面圖。
請參照圖1A，提供基底100。基底100可為半導體基底，如矽基底。在一些實施例中，可在基底100中形成隔離結構102。隔離結構102例如是淺溝渠隔離(shallow trench isolation，STI)結構。隔離結構102的材料例如是氧化矽。
接著，在基底100上形成閘極結構104。閘極結構104可包括介電層106與導電層108。介電層106位在基底100上。介電層106可用以做為閘介電層。介電層106的材料例如是氧化矽。導電層108位在介電層106上。導電層108可用以作為閘極。導電層108的材料例如是摻雜多晶矽。在一些實施例中，閘極結構104更可包括金屬矽化物層110與硬罩幕層112中的至少一者。金屬矽化物層110位在導電層108上。金屬矽化物層110的材料例如是矽化鎢(WSi)。硬罩幕層112位在金屬矽化物層110上。硬罩幕層112的材料例如是氧化矽。
在一些實施例中，介電層106、導電層108、金屬矽化物層110與硬罩幕層112的形成方法可包括以下步驟。首先，可依序在基底100上形成介電材料層(未示出)、導電材料層(未示出)、金屬矽化物材料層(未示出)與硬罩幕材料層(未示出)。接著，可藉由微影製程與蝕刻製程對硬罩幕材料層、金屬矽化物材料層、導電材料層與介電材料層進行圖案化，而形成硬罩幕層112、金屬矽化物層110、導電層108與介電層106。
請參照圖1B，在閘極結構104旁的基底100中形成多個口袋摻雜區114。在一些實施例中，口袋摻雜區114的深度例如是170埃(Å)至300埃。口袋摻雜區114的摻質包括IVA族元素。口袋摻雜區114的摻質可包括碳、矽、鍺、錫或鉛。在一些實施例中，口袋摻雜區114的摻質可為碳或鍺。在本實施例中，口袋摻雜區114的摻質是以碳為例，但本發明並不以此為限。口袋摻雜區114的形成方法可為冷植入。在本文中，術語「冷植入」是指在低溫下進行的離子植入製程。在一些實施例中，用以形成口袋摻雜區114的冷植入的溫度可為-20℃至-100℃。在一些實施例中，用以形成口袋摻雜區114的冷植入的植入能量可為5千電子伏特至15千電子伏特。在一些實施例中，用以形成口袋摻雜區114的冷植入的植入劑量可為5×10 13原子/平方公分至5×10 15原子/平方公分。在一些實施例中，用以形成口袋摻雜區114的冷植入的傾斜角可為3度至15度。在一些實施例中，當口袋摻雜區114的摻質為碳時，冷植入的氣體源可為二氧化碳氣體(CO 2gas)。
接著，在閘極結構104旁的基底100中形成多個口袋摻雜區116。口袋摻雜區116的深度大於口袋摻雜區114的深度。口袋摻雜區116可具有第一導電型(如，N型導電型)。以下，第一導電型與第二導電型可分別為N型導電型與P型導電型中的一者與另一者。在本實施例中，第一導電型是以N型導電型為例，且第二導電型是以P型導電型為例，但本發明並不以此為限。在另一些實施例中，第一導電型可為P型導電型，且第二導電型可為N型導電型。在本實施例中，口袋摻雜區116可具有N型導電型，且口袋摻雜區116的摻質例如是砷(As)。口袋摻雜區116的形成方法例如是離子植入法。
然後，在多個口袋摻雜區114中形成多個源極/汲極延伸區118。在一些實施例中，源極/汲極延伸區亦可稱為「輕摻雜汲極(lightly doped drain，LDD)區」。源極/汲極延伸區118可具有第二導電型(如，P型導電型)。在本實施例中，源極/汲極延伸區118可具有P型導電型，且源極/汲極延伸區118的摻質例如是硼(B)或二氟化硼(BF 2)。源極/汲極延伸區118的形成方法例如是離子植入法。
請參照圖1C，可在閘極結構104的側壁上形成多個間隙壁120。間隙壁120可為單層結構或多層結構。間隙壁120的材料例如是氧化矽、氮化矽或其組合。在一些實施例中，間隙壁120的形成方法可包括以下步驟。首先，可在基底100、隔離結構102與閘極結構104上共形地形成間隙壁材料層(未示出)。接著，再對間隙壁材料層進行回蝕刻製程(如，乾式蝕刻製程)，而形成間隙壁120。
然後，在閘極結構104旁的基底100中形成多個源極/汲極區122。源極/汲極延伸區118位在源極/汲極區122與閘極結構104之間。源極/汲極區122可連接於源極/汲極延伸區118。源極/汲極區122的深度可大於源極/汲極延伸區118的深度。源極/汲極區122可具有第二導電型(如，P型導電型)。在本實施例中，源極/汲極區122可具有P型導電型，且源極/汲極區122的摻質例如是硼(B)或二氟化硼(BF 2)。源極/汲極區122的形成方法例如是離子植入法。
請參照圖1D，可在基底100、隔離結構102、閘極結構104與間隙壁120上形成介電層124。介電層124可為單層結構或多層結構。介電層124的材料例如是氧化矽、氮化矽或其組合。介電層124的形成方法例如是化學氣相沉積法。
請參照圖1E，可在介電層124中形成多個開口OP。開口OP可暴露出源極/汲極區122。在一些實施例中，可藉由微影製程與蝕刻製程移除部分介電層124而形成開口OP。在一些實施例中，在形成開口OP的製程中，可能移除部分源極/汲極區122。
請參照圖1F，可在閘極結構104旁的基底100中形成多個接觸窗摻雜區126。源極/汲極區122位在接觸窗摻雜區126中。在一些實施例中，接觸窗摻雜區126的深度例如是250埃至400埃。接觸窗摻雜區126的摻質可包括IVA族元素。接觸窗摻雜區126的摻質可包括碳、矽、鍺、錫或鉛。在一些實施例中，接觸窗摻雜區126的摻質可為碳或鍺。在本實施例中，接觸窗摻雜區126的摻質是以碳為例，但本發明並不以此為限。接觸窗摻雜區126的形成方法可為冷植入。在一些實施例中，用以形成接觸窗摻雜區126的冷植入的溫度可為-20℃至-100℃。在一些實施例中，用以形成接觸窗摻雜區126的冷植入的植入能量可為10千電子伏特至20千電子伏特。在一些實施例中，用以形成接觸窗摻雜區126的冷植入的植入劑量可為1×10 14原子/平方公分至1×10 16原子/平方公分。在一些實施例中，用以形成接觸窗摻雜區126的冷植入的傾斜角可為0度。在一些實施例中，當接觸窗摻雜區126的摻質碳時，冷植入的氣體源可為二氧化碳氣體。
接著，可在多個接觸窗摻雜區126中形成多個接觸窗摻雜區128。接觸窗摻雜區128的深度可大於源極/汲極區122的深度。在一些實施例中，接觸窗摻雜區128的深度例如是100埃至200埃。接觸窗摻雜區128可具有第二導電型(如，P型導電型)。在本實施例中，接觸窗摻雜區128可具有P型導電型，且接觸窗摻雜區128的摻質例如是硼(B)或二氟化硼(BF 2)。接觸窗摻雜區128的形成方法例如是離子植入法。
基於上述可知，在一些實施例的電晶體結構10的製造方法中，在多個口袋摻雜區114中形成多個源極/汲極延伸區118，且口袋摻雜區114的摻質包括IVA族元素。因此，可藉由口袋摻雜區114來抑制源極/汲極延伸區118中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應，且可降低漏電流。此外，在一些實施例的電晶體結構10的製造方法中，在閘極結構104旁的基底100中形成多個接觸窗摻雜區126，源極/汲極區122位在接觸窗摻雜區126中，且接觸窗摻雜區126的摻質可包括IVA族元素。因此，可藉由接觸窗摻雜區126來抑制源極/汲極區122中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應，且可降低阻值。在一些實施例中，電晶體結構10的製造方法更可包括在多個接觸窗摻雜區126中形成多個接觸窗摻雜區128。由於接觸窗摻雜區126可抑制接觸窗摻雜區128中的摻質擴散出去，因此可有效地抑制短通道效應與擊穿效應，且可降低阻值。
以下，藉由圖1F來說明上述實施例的電晶體結構10。此外，雖然電晶體結構10的形成方法是以上述方法為例來進行說明，但本發明並不以此為限。
請參照圖1F，電晶體結構10包括基底100、閘極結構104、多個口袋摻雜區114、多個口袋摻雜區116、多個源極/汲極延伸區118與多個源極/汲極區122。電晶體結構10可為P型金屬氧化物半導體(P-type metal oxide semiconductor，PMOS)電晶體結構或N型金屬氧化物半導體(N-type metal oxide semiconductor，NMOS)電晶體結構。在本實施例中，電晶體結構10是以P型金屬氧化物半導體電晶體結構為例，但本發明並不以此為限。閘極結構104位在基底100上。多個口袋摻雜區114位在閘極結構104旁的基底100中。口袋摻雜區114的摻質包括IVA族元素。多個口袋摻雜區116位在閘極結構104旁的基底100中。口袋摻雜區116的深度大於口袋摻雜區114的深度。多個源極/汲極延伸區118位在多個口袋摻雜區114中。多個源極/汲極區122位在閘極結構104旁的基底100中。源極/汲極延伸區118位在源極/汲極區122與閘極結構104之間。
在一些實施例中，電晶體結構10更可包括多個接觸窗摻雜區126。多個接觸窗摻雜區126位在閘極結構104旁的基底100中。源極/汲極區122可位在接觸窗摻雜區126中。接觸窗摻雜區126的摻質可包括IVA族元素。在一些實施例中，電晶體結構10更可包括多個接觸窗摻雜區128。多個接觸窗摻雜區128位在多個接觸窗摻雜區126中。接觸窗摻雜區128的深度可大於源極/汲極區122的深度。在一些實施例中，電晶體結構10更可包括多個間隙壁120。多個間隙壁120位在閘極結構104的側壁上。源極/汲極延伸區118可位在間隙壁120下方。
在上述實施例中，雖然電晶體結構10同時包括口袋摻雜區114與接觸窗摻雜區126，但本發明並不以此為限。在另一些實施例中，電晶體結構10包括口袋摻雜區114，但不包括接觸窗摻雜區126。在另一些實施例中，電晶體結構10包括接觸窗摻雜區126，但不包括口袋摻雜區114。
在一些實施例中，電晶體結構10可應用於陣列下互補式金屬氧化物半導體(complementary metal oxide semiconductor (CMOS) under array，CuA)的架構或鄰近陣列的互補式金屬氧化物半導體(CMOS near array，CnA)的架構中。
此外，電晶體結構10中的其餘構件可參照上述實施例的說明。另外，電晶體結構10中的各構件的詳細內容(如，材料與形成方法等)已於上述實施例進行詳盡地說明，於此不再說明。
基於上述可知，在一些實施例的電晶體結構10中，多個源極/汲極延伸區118位在多個口袋摻雜區114中，且口袋摻雜區114的摻雜包括IVA族元素。因此，可藉由口袋摻雜區114來抑制源極/汲極延伸區118中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應，且可降低漏電流。在一些實施例的電晶體結構10中，源極/汲極區122位在接觸窗摻雜區126中，且接觸窗摻雜區126的摻質包括IVA族元素。因此，可藉由接觸窗摻雜區126來抑制源極/汲極區122中的摻質擴散出去，藉此可有效地抑制短通道效應與擊穿效應，且可降低阻值。在一些實施例中，電晶體結構10更可包括多個接觸窗摻雜區128，且多個接觸窗摻雜區128位在多個接觸窗摻雜區126中。由於接觸窗摻雜區126可抑制接觸窗摻雜區128中的摻質擴散出去，因此可有效地抑制短通道效應與擊穿效應，且可降低阻值。
綜上所述，在上述實施例的電晶體結構及其製造方法中，由於包括IVA族元素的摻雜區可抑制源極/汲極延伸區及/或源極/汲極區中的摻質擴散出去，因此可有效地抑制短通道效應。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10: 電晶體結構 100: 基底 102: 隔離結構 104: 閘極結構 106, 124: 介電層 108: 導電層 110: 金屬矽化物層 112: 硬罩幕層 114, 116: 口袋摻雜區 118: 源極/汲極延伸區 120: 間隙壁 122: 源極/汲極區 126, 128: 接觸窗摻雜區 OP: 開口
圖1A至圖1F為根據本發明的一些實施例的電晶體結構的製造流程剖面圖。
10: 電晶體結構 100: 基底 102: 隔離結構 104: 閘極結構 106, 124: 介電層 108: 導電層 110: 金屬矽化物層 112: 硬罩幕層 114, 116: 口袋摻雜區 118: 源極/汲極延伸區 120: 間隙壁 122: 源極/汲極區 126, 128: 接觸窗摻雜區 OP: 開口

Claims (8)

  1. 一種電晶體結構，包括：基底；閘極結構，位在所述基底上；多個第一口袋摻雜區，位在所述閘極結構旁的所述基底中，其中所述第一口袋摻雜區的摻質包括IVA族元素；多個第二口袋摻雜區，位在所述閘極結構旁的所述基底中，其中所述第二口袋摻雜區的深度大於所述第一口袋摻雜區的深度；多個源極/汲極延伸區，位在多個所述第一口袋摻雜區中；多個源極/汲極區，位在所述閘極結構旁的所述基底中，其中所述源極/汲極延伸區位在所述源極/汲極區與所述閘極結構之間；以及多個第一接觸窗摻雜區，位在所述閘極結構旁的所述基底中，其中所述源極/汲極區位在所述第一接觸窗摻雜區中，且所述第一接觸窗摻雜區的摻質包括所述IVA族元素。
  2. 如請求項1所述的電晶體結構，其中所述第一口袋摻雜區的摻質包括碳或鍺。
  3. 如請求項1所述的電晶體結構，其中所述源極/汲極區連接於所述源極/汲極延伸區，且所述電晶體結構更包括：多個間隙壁，位在所述閘極結構的側壁上，其中所述源極/汲極延伸區位在所述間隙壁下方。
  4. 如請求項1所述的電晶體結構，更包括：多個第二接觸窗摻雜區，位在多個所述第一接觸窗摻雜區中，其中所述第二接觸窗摻雜區的深度大於所述源極/汲極區的深度。
  5. 一種電晶體結構的製造方法，包括：提供基底；在所述基底上形成閘極結構；在所述閘極結構旁的所述基底中形成多個第一口袋摻雜區，其中所述第一口袋摻雜區的摻質包括IVA族元素；在所述閘極結構旁的所述基底中形成多個第二口袋摻雜區，其中所述第二口袋摻雜區的深度大於所述第一口袋摻雜區的深度；在多個所述第一口袋摻雜區中形成多個源極/汲極延伸區；在所述閘極結構旁的基底中形成多個源極/汲極區，其中所述源極/汲極延伸區位在所述源極/汲極區與所述閘極結構之間；以及在所述閘極結構旁的所述基底中形成多個第一接觸窗摻雜區，其中所述源極/汲極區位在所述第一接觸窗摻雜區中，且所述第一接觸窗摻雜區的摻質包括所述IVA族元素。
  6. 如請求項5所述的電晶體結構的製造方法，其中所述第一口袋摻雜區的形成方法包括冷植入，且所述冷植入的溫度為-20℃至-100℃。
  7. 如請求項5所述的電晶體結構的製造方法，其中所述第一接觸窗摻雜區的形成方法包括冷植入，且所述冷植入的溫度為-20℃至-100℃。
  8. 如請求項5所述的電晶體結構的製造方法，更包括：在多個所述第一接觸窗摻雜區中形成多個第二接觸窗摻雜區，其中所述第二接觸窗摻雜區的深度大於所述源極/汲極區的深度。
TW111124467A 2022-04-08 2022-06-30 電晶體結構及其製造方法 TWI822155B (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1463101A2 (en) * 2003-03-20 2004-09-29 Texas Instruments Incorporated Semiconductor device fabrication methods for inhibiting carbon out-diffusion from the semiconductor wafer
US20060244080A1 (en) * 2005-04-25 2006-11-02 Chien-Hao Chen Profile confinement to improve transistor performance
US20110034013A1 (en) * 2009-08-07 2011-02-10 Varian Semiconductor Equipment Associates, Inc. Low Temperature Ion Implantation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7169675B2 (en) * 2004-07-07 2007-01-30 Chartered Semiconductor Manufacturing, Ltd Material architecture for the fabrication of low temperature transistor
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
US9312189B2 (en) * 2014-04-03 2016-04-12 GlobalFoundries, Inc. Methods for fabricating integrated circuits with improved implantation processes

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1463101A2 (en) * 2003-03-20 2004-09-29 Texas Instruments Incorporated Semiconductor device fabrication methods for inhibiting carbon out-diffusion from the semiconductor wafer
US20060244080A1 (en) * 2005-04-25 2006-11-02 Chien-Hao Chen Profile confinement to improve transistor performance
US20110034013A1 (en) * 2009-08-07 2011-02-10 Varian Semiconductor Equipment Associates, Inc. Low Temperature Ion Implantation

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