CN108807533B - 半导体装置及其形成方法 - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Abstract
本发明公开了一种半导体装置及其形成方法，装置包括设置于半导体基板上的栅极结构、设置于上述栅极结构侧壁上的侧壁间隔物、形成于上述栅极结构两侧的半导体基板中的轻掺杂源极/漏极区、形成于上述侧壁间隔物两侧的半导体基板中的源极/漏极区、形成于上述栅极结构下的半导体基板中且邻近于上述轻掺杂源极/漏极区的晕状植入(halo implant)区、形成于上述栅极结构下的半导体基板中且位于上述轻掺杂源极/漏极区及晕状植入区之间的反向掺杂区(counter‑doping region)。上述反向掺杂区的掺杂浓度低于晕状植入区的掺杂浓度。
Description
技术领域
本发明是有关于一种半导体装置，且特别有关于一种具有晕状植入区的半导体装置及其形成方法。
背景技术
半导体装置已广泛地使用于各种电子产品中，举例而言，诸如个人电脑、手机、以及数位相机…等。半导体装置的制造通常是藉由在半导体基板上依序沉积绝缘层或介电层材料、导电层材料以及半导体层材料，接着使用微影制作工艺图案化所形成的各种材料层，藉以在此半导体基板的上形成电路零件及组件。
在半导体装置演进的过程，持续降低的几何尺寸为半导体的制造带来一些挑战，例如源极与漏极间的漏电流(leakage current)以及逆短通道效应(reverse shortchannel effect)。上述的漏电流若太大，将降低装置的寿命。一般而言，可提高井区的掺杂浓度以降低漏电流，然而这将使得半导体装置的临界电压变大而不利于操作。此外，若上述的逆短通道效应太过严重，会使得半导体装置在短通道及长通道的临界电压的差异增加，造成设计上的困难。
因此，虽然现行的半导体装置及其制造普遍地满足其预期的用途，但并非在各层面都令人满意。
发明内容
本发明提供一种半导体装置，包括:半导体基板；栅极结构，设置于上述半导体基板之上；侧壁间隔物，设置于上述栅极结构的侧壁上；轻掺杂源极/漏极区，形成于上述栅极结构两侧的半导体基板中；源极/漏极区，形成于上述侧壁间隔物两侧的半导体基板中；晕状植入(halo implant)区，形成于上述栅极结构下的半导体基板中且邻近于上述轻掺杂源极/漏极区；反向掺杂区(counter-doping region)，形成于上述栅极结构下的半导体基板中且位于上述轻掺杂源极/漏极区及晕状植入区之间。上述反向掺杂区的掺杂浓度低于晕状植入区的掺杂浓度。
本发明亦提供一种半导体装置的形成方法，包括:提供半导体基板；形成栅极结构于上述半导体基板之上；形成晕状植入区于上述栅极结构周围及栅极结构下的半导体基板中；形成轻掺杂源极/漏极区于上述栅极结构两侧的半导体基板中，其中上述晕状植入区邻近于轻掺杂源极/漏极区；形成侧壁间隔物于上述栅极结构的侧壁上；形成源极/漏极区于上述侧壁间隔物两侧的半导体基板中；以及形成反向掺杂区(counter-doping region)于上述栅极结构下的半导体基板中且位于上述轻掺杂源极/漏极区及晕状植入区之间。上述反向掺杂区的掺杂浓度低于晕状植入区的掺杂浓度。
附图说明
以下将配合所附图式详述本发明的实施例。应注意的是，各种特征并未按照比例绘制且仅用以说明例示。事实上，元件的尺寸可能经放大或缩小，以清楚地表现出本发明的技术特征。
图1-图6、图7A、图7B、图8为一系列剖面图，用以说明本发明实施例的半导体装置的制造流程。
符号说明：
100～半导体基板；
200～井区；
300～栅极结构；
302～栅极介电层；
304～栅极电极；
400～晕状植入区；
600～轻掺杂源极/漏极区；
700～侧壁间隔物；
702～反向掺杂区；
800～源极/漏极区；
C～栅极结构中心线；
D～第一杂质。
具体实施方式
以下的揭露内容提供许多不同的实施例或范例以实施本案的不同特征。以下的揭露内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本揭露书叙述了一第一特征形成于一第二特征之上或上方，即表示其可能包含上述第一特征与上述第二特征是直接接触的实施例，亦可能包含了有附加特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与第二特征可能未直接接触的实施例。另外，以下不同的实施例可能重复使用相同的参考符号及/或标记。这些重复系为了简化与便于理解的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。应可理解的是，额外的操作步骤可实施于所述方法之前、之间或之后，且在所述方法的其他实施例中，部分的操作步骤可被取代或省略。
本发明的半导装置的形成方法，系藉由形成反向掺杂区(counter-dopingregion)于栅极结构下的半导体基板中，并使上述反向掺杂区的掺杂浓度低于晕状植入区的掺杂浓度，藉此可降低逆短通道效应。此外，如前文所述，为降低源极与漏极之间的漏电流(或提高Ion/Ioff的比值)，井区的掺杂浓度须足够，而本发明的半导体装置于栅极介电层的下部中所形成的正电荷则可避免或减少因井区的掺杂浓度增加而造成的半导体装置的临界电压上升。在下文中将以N型金属氧化物半导体场效晶体管(NMOS)为例进行说明，应理解的是，此技艺人士亦可将的应用于P型氧化物半导体场效晶体管(PMOS)、互补式金属氧化物半导体晶体管(CMOS)、高压晶体管、水平扩散金氧半场效晶体管(LDMOS)、或其他合适的半导体元件。
图1绘示出本发明一实施例的起始步骤。首先，提供半导体基板100。举例而言，半导体基板100可包括硅。在一些其他的实施例中，半导体基板100可包括硅以外的元素半导体，例如:锗；化合物半导体，例如:碳化硅(silicon carbide,SiC)、砷化镓(galliumarsenic,GaAs)、砷化铟(indium arsenide,InAs)或磷化铟(indium phosphide,InP)；合金半导体，例如:硅锗(Silicon germanium,SiGe)、硅碳化锗(silicon germanium carbide,SiGeC)、砷磷化镓(gallium arsenic phosphide,GaAsP)或磷化镓铟(gallium indiumphosphide,GaInP)。半导体基板100亦可包括绝缘层上半导体基板(semiconductor-on-insulator，简称SOI)，上述绝缘层上半导体基板可包括底板、设置于底板上的埋藏氧化层、以及设于埋藏氧化层上的半导体层。
接着，如图2所示，于半导体基板100中植入井区杂质以形成井区200。井区200的井区杂质型态系配合后续于井区200中欲形成的半导体元件的导电型态。在本实施例中，后续将于井区200中形成N型场效晶体管(NMOS)，因此井区200的井区杂质为P型杂质，举例而言，可注入(implant)硼离子、铟离子或二氟化硼离子(BF2 +)于部分的半导体基板100中以形成掺杂浓度为1E12-7E13atoms/cm2的P型井区200。举例而言，井区200的深度可为0.03um-0.75um，但不以此为限。
接着，如图3所示，形成栅极结构300于井区200之上。栅极结构300可包括栅极介电层302以及设置于栅极介电层302上的栅极电极304。举例而言，栅极介电层302可包括氧化硅或高介电常数介电材料，例如:氧化铪(hafnium oxide；HfO2)、氧化硅铪(hafniumsilicon oxide；HfSiO)、氮氧化硅铪(hafnium silicon oxynitride；HfSiON)、氧化钽铪(hafnium tantalum oxide；HfTaO)、氧化钛铪(hafnium titanium oxide；HfTiO)、氧化锆铪(hafnium zirconium oxide；HfZrO)、氮化硅(silicon nitride)、氮氧化硅(siliconoxynitride)、氧化锆(zirconium oxide)、氧化钛(titanium oxide)、氧化铝(aluminumoxide)、二氧化铪-氧化铝(hafnium dioxide-alumina；HfO2-Al2O3)合金、或其他适合的介电材料，但并非以此为限。举例而言，栅极电极304可包括多晶硅、铝、铜、钨、钛、钽、氮化钛(titanium nitride)、氮化钽(tantalum nitride)、硅化镍(nickel silicide)、硅化钴(cobalt silicide)、碳化钽(TaC)、氮硅化钽(TaSiN)、氮碳化钽(TaCN)、钛铝(TiAl)、氮化钛铝(TiAlN)、或其他适合的材料。
形成栅极结构300的制作工艺可包括沉积、光微影图案化及蚀刻制作工艺。沉积制作工艺可包括化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度电浆化学气相沉积(high density plasma CVD；HDPCVD)、金属有机化学气相沉积(metal organicCVD；MOCVD)、或电浆强化化学气相沉积(plasma enhanced CVD；PECVD)。光微影图案化制作工艺可包括光阻涂布(例如：旋转涂布)、软烤、罩幕对准、曝光、曝光后烤(post-exposurebaking)、光阻显影、清洗、干燥(例如：硬烤)、及/或其他适合的制作工艺。蚀刻制作工艺可包括干蚀刻、湿蚀刻、及/或其他蚀刻方法(例如：反应性离子蚀刻(reactive ionetching))。
接着，如图4所示，形成晕状植入区400于栅极结构300周围及栅极结构300下的半导体基板100中。晕状植入区400包括与井区200相同导电型态的杂质。在本实施例中，晕状植入区400包括P型杂质，举例而言，可以斜角注入(tilt implant)制作工艺将硼离子、铟离子或二氟化硼离子(BF2 +)注入于半导体基板100中而形成掺杂浓度为1E13-4.5E13atoms/cm2的晕状植入区400，且其离子入射方向与半导体基板的上表面的法线的夹角可为20°-50°。在一些实施例中，晕状植入区400的掺杂浓度朝着栅极结构的中心线C逐渐减少。
接着，如图5所示，注入第一杂质D于栅极电极304及半导体基板100中。举例而言，第一杂质D可包括氮离子。在本实施例中，可以注入制作工艺将氮离子注入于栅极电极304及半导体基板100中。上述注入制作工艺的注入能量若太高则会影响较深层井区的部分，可能导致元件深层漏电或降低与邻近井区隔绝效果，若太低则---会影响元件特性，举例而言，上述注入制作工艺的注入能量可为6keV～40keV，较佳为10keV～30keV。上述注入制作工艺的注入剂量若太高则会使得原件临界电压迅速将低，而造成长/短通道元件临界电压差异增加，若太低则成效不彰，举例而言，上述注入制作工艺的注入剂量可为1E14-1E16atoms/cm2，较佳为5E14-6E15atoms/cm2。
接着，请参照图6，形成轻掺杂源极/漏极区600于栅极结构300两侧的半导体基板100中，且其邻近于晕状植入区400。轻掺杂源极/漏极区600包括与井区200相反导电型态的杂质。在本实施例中，轻掺杂源极/漏极区600包括N型杂质。举例而言，可以栅极结构300充当注入罩幕，注入磷离子或砷离子于栅极结构300两侧的半导体基板100中以形成掺杂浓度为1E14-6E14atoms/cm2的N型轻掺杂源极/漏极区600。应注意的是，虽然于本实施例中，前述图5中注入氮离子于栅极电极304及半导体基板100中的步骤系于形成轻掺杂源极/漏极区600的步骤前进行，在一些其他的实施例中，则可于形成轻掺杂源极/漏极区600的步骤后进行上述注入氮离子的步骤。
接着，请参照图7A，形成侧壁间隔物700于栅极结构300的侧壁上。举例而言，侧壁间隔物700包括一或多层的绝缘材料(例如:SiO2、SiN、SiON、SiOCN或SiCN)，其可以化学气相沉积制作工艺(CVD)、物理气相沉积制作工艺(PVD)、原子层气相沉积制作工艺(ALD)、电子束蒸镀制作工艺(e-beam evaporation)、或其他合适的制作工艺沉积一间隔物层，再经非等向性的回蚀刻制作工艺(例如:电浆蚀刻制作工艺)而形成。在本实施例中，沉积侧壁间隔物层的制作工艺系在625-750℃的温度下进行，因此不需要另外的热处步骤即可将前述图5中注入于半导体基板100中的氮离子扩散驱入(drive in)晕状植入区400邻近于轻掺杂源极/漏极区600的部分中而形成反向掺杂区(counter-doping region)702，如图7B所示。
于反向掺杂区702中，扩散驱入的氮离子可使原来晕状植入区中的P型杂质的掺杂浓度适当地降低为原来的15％-80％，在一些实施例中，其降低为原来的40％-80％而适用于一般临界电压(例如:临界电压为0.37-0.45伏特)半导体，在另一些实施例中，其降低为原来的15％-50％而适用于低临界电压(例如:临界电压为0.21-0.285伏特)半导体。在一些实施例中，扩散驱入的氮离子可使原来晕状植入区中的P型杂质的掺杂浓度适当地降低为原来的15％-80％，而降低逆通道效应的影响。举例而言，晕状植入区400及反向掺杂区702的掺杂浓度比为20:3至20:16，较佳为20:8至20:16，或较佳为20:3至20:10。在一些实施例中，不同于晕状植入区400，反向掺杂区702的掺杂浓度朝着栅极结构300的中心线C逐渐增加。
此外，请继续参照图7B，本实施例中形成侧壁间隔物制作工艺的温度亦可使得前述图5中注入于栅极电极304中的氮离子扩散驱入栅极介电层302而于栅极介电层302的下部形成正电荷。上述正电荷可避免或减少因井区200的掺杂浓度增加(例如:为了降低源极与漏极间的漏电流)而造成的半导体装置的临界电压上升。
应注意的是，虽然于本实施例是于形成侧壁间隔物700的制作工艺中，以其制作工艺温度形成反向掺杂区702以及栅极介电层302下部中的正电荷，然而在一些其他的实施例中，亦可进行额外的热处理步骤以达到相同的目的。
接着，请参照图8，形成源极/漏极区800于侧壁间隔物700两侧的半导体基板100中。在本实施例中，源极/漏极区800包括N型杂质，举例而言，可以栅极结构300与侧壁间隔物700充当注入罩幕，注入磷离子或砷离子于侧壁间隔物700两侧的半导体基板100中，接着进行热处理步骤以对掺杂物进行活化而形成掺杂浓度为8E13-4.5E15atoms/cm2的N型源极/漏极区800。举例而言，上述热处理步骤可为快速热处理制作工艺(rapid thermalprocess，简称RTP)，其热处理温度可为1000-1100℃，时间可为1s-20s。上述热处理步骤亦可为炉管退火制作工艺(furnace anneal)、非熔式雷射瞬间退火(Laser SpikeAnnealing，简称LSA)制作工艺、熔化式雷射热处理(Laser Thermal Processing，简称LTP)或其他适当的热处理制作工艺。在一些实施例中，上述热处理制作工艺亦可将前述图5中所注入的氮离子扩散驱入晕状植入区400及栅极介电层302中。
综合上述，本发明的半导装置，系于栅极结构下的半导体基板中以及轻掺杂源极/漏极区与晕状植入区之间形成反向掺杂区(counter-doping region)，并使上述反向掺杂区的掺杂浓度低于晕状植入区的掺杂浓度，而可降低逆短通道效应。此外，本发明的半导体装置于栅极介电层的下部中所形成的正电荷则可避免或减少因井区的掺杂浓度增加而造成的半导体装置的临界电压上升。
前述内文概述了许多实施例的特征，使本技术领域中具有通常知识者可以从各个方面更佳地了解本发明。本技术领域中具有通常知识者应可理解，且可轻易地以本发明为基础来设计或修饰其他制作工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本发明的发明精神与范围。在不背离本发明的发明精神与范围的前提下，可对本发明进行各种改变、置换或修改，因此本发明的保护范围当以本申请权利要求范围所界定者为准。另外，虽然本发明已以数个较佳实施例揭露如上，然其并非用以限定本发明，且并非所有优点都已于此详加说明。
Claims (7)
1.一种半导体装置的形成方法，其特征在于，所述的方法包括：
提供一半导体基板；
形成一栅极结构于所述半导体基板之上，其中所述的栅极结构包括:
一栅极介电层；
一栅极电极，形成于所述栅极介电层之上；
形成一晕状植入区于所述栅极结构周围及所述栅极结构下的半导体基板中，其中形成所述晕状植入区的步骤包括：
斜角注入一P型杂质以形成所述晕状植入区于所述栅极结构周围及所述栅极结构下的半导体基板中；
形成一轻掺杂源极/漏极区于所述栅极结构两侧的半导体基板中，其中所述晕状植入区邻近于所述轻掺杂源极/漏极区；
形成一反向掺杂区于所述栅极结构下的半导体基板中且位于所述轻掺杂源极/漏极区及所述晕状植入区之间；
其中形成所述反向掺杂区的步骤包括：
注入一第一杂质于所述栅极电极及所述半导体基板中，所述的第一杂质包括氮离子；以及
进行一热处理以将所述第一杂质扩散驱入所述晕状植入区邻近于所述轻掺杂源极/漏极区的一部分中而形成所述反向掺杂区；
形成一侧壁间隔物于所述栅极结构的侧壁上；
形成一源极/漏极区于所述侧壁间隔物两侧的半导体基板中； 以及
其中所述反向掺杂区的掺杂浓度低于所述晕状植入区的掺杂浓度，所述的晕状植入区及所述反向掺杂区的掺杂浓度比为20:3至20:16，且其中所述反向掺杂区分隔所述晕状植入区与所述栅极结构；
所述的反向掺杂区的掺杂浓度朝着所述栅极结构的中心线逐渐增加。
2.如权利要求1所述的半导体装置的形成方法，其特征在于，所述的半导体装置系为NMOS装置，且所述源极/漏极区系为N型掺杂区，所述晕状植入区及所述反向掺杂区系为P型掺杂区。
3.如权利要求2所述的半导体装置的形成方法，其特征在于，所述的方法更包括：
注入一井区P型杂质以形成一P型井区于所述半导体基板中；
其中所述NMOS装置系形成于所述P型井区中。
4.如权利要求1所述的半导体装置的形成方法，其特征在于，形成所述侧壁间隔物的步骤包括：
在625-750℃下沉积所述侧壁间隔物于所述栅极结构的侧壁上；其中所述热处理是通过沉积所述侧壁间隔物时的温度进行。
5.如权利要求1所述的半导体装置的形成方法，其特征在于，注入所述第一杂质于所述栅极电极及所述半导体基板中的步骤的注入能量为6keV~40keV且注入剂量为1E14-1E16atoms/cm2。
6.如权利要求1所述的半导体装置的形成方法，其特征在于，所述的栅极介电层的一下部具有正电荷。
7.如权利要求6所述的半导体装置的形成方法，其特征在于，所述的栅极介电层的下部的正电荷是通过所述热处理形成。
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| JP2005093815A (ja) * | 2003-09-18 | 2005-04-07 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
| WO2009157237A1 (ja) * | 2008-06-23 | 2009-12-30 | 日本電気株式会社 | 半導体装置およびその製造方法 |
| CN103545218A (zh) * | 2012-07-17 | 2014-01-29 | 德克萨斯仪器股份有限公司 | 用于栅极边缘二极管泄漏电流减少的袋状反向掺杂 |
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