WO2022033165A1 - 位线结构制造方法、半导体结构制造方法及半导体结构 - Google Patents

位线结构制造方法、半导体结构制造方法及半导体结构 Download PDF

Info

Publication number
WO2022033165A1
WO2022033165A1 PCT/CN2021/100459 CN2021100459W WO2022033165A1 WO 2022033165 A1 WO2022033165 A1 WO 2022033165A1 CN 2021100459 W CN2021100459 W CN 2021100459W WO 2022033165 A1 WO2022033165 A1 WO 2022033165A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
bit line
barrier layer
manufacturing
thin film
Prior art date
Application number
PCT/CN2021/100459
Other languages
English (en)
French (fr)
Inventor
郗宁
王沛萌
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21855220.6A priority Critical patent/EP4027377A4/en
Priority to KR1020227021263A priority patent/KR102710233B1/ko
Priority to JP2022539177A priority patent/JP2023509403A/ja
Priority to US17/446,445 priority patent/US11985814B2/en
Publication of WO2022033165A1 publication Critical patent/WO2022033165A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a bit line structure, a method for manufacturing a semiconductor structure, and a semiconductor structure.
  • the sacrificial layer 150 eg silicon nitride, Si 3 N 4
  • the barrier layer 140 For example, the etching selectivity ratio of silicon oxide, SiO2) (ie, the ratio of the rate at which the sacrificial layer 150 is etched by the etchant to the rate at which the barrier layer 140 is etched by the etchant) is small, so that the etchant strips the sacrificial layer 150 when the etchant is cleaned.
  • the barrier layer 140 is easily etched and removed, thereby partially removing the protective layer 130 and causing etching damage 121 (W Missing, W is tungsten) to the conductive layer 120 in the barrier layer 140 .
  • a main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a method for manufacturing a bit line structure that can prevent the conductive layer from being damaged by an etching solution.
  • Another main purpose of the present disclosure is to overcome at least one defect of the above-mentioned prior art, and to provide a method for manufacturing a semiconductor structure using the above-mentioned method for manufacturing a bit line structure.
  • Another main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a semiconductor structure fabricated by the above-mentioned semiconductor structure manufacturing method.
  • a method for manufacturing a bit line structure includes the following steps:
  • bit line conductive layer is partially located in the groove on the surface of the semiconductor substrate
  • a sacrificial layer is formed on the surface of the first barrier layer, the sacrificial layer has a filling portion filled in the groove;
  • the portion of the sacrificial layer other than the filling portion is removed by cleaning with an etchant.
  • the passivation treatment includes plasma treatment, ion implantation or thermal oxidation treatment.
  • the first barrier layer after passivation treatment includes two-layer thin film structures, which are a first thin film layer adjacent to the first protective layer and a layer far from the first protective layer, respectively.
  • the second thin film layer wherein, the etching selectivity ratio between the sacrificial layer and the second thin film layer is greater than the etching selectivity ratio between the sacrificial layer and the first thin film layer.
  • the material of the first barrier layer includes silicon oxide; wherein, the passivation treatment includes nitrogen plasma treatment, and the material of the second thin film layer includes silicon oxynitride.
  • the thickness of the first protective layer is 1 nm ⁇ 3 nm; and/or the thickness of the first blocking layer is 2 nm ⁇ 8 nm.
  • the material of the first protective layer includes silicon nitride; and/or the material of the first barrier layer includes silicon oxide; and/or the material of the sacrificial layer includes nitrogen Silicone.
  • the etching solution includes a phosphoric acid solution; wherein, the temperature of the etching solution is 100°C to 120°C; and/or the concentration of the etching solution is 40% to 60%.
  • the following steps are further included:
  • a second protective layer is formed on the surface of the second barrier layer.
  • the following steps are included:
  • the sacrificial layer is washed with a phosphoric acid solution to remove the portion of the sacrificial layer other than the filling portion.
  • a method for manufacturing a semiconductor structure includes the following steps:
  • a bit line structure is formed on the semiconductor substrate using the method for fabricating the bit line structure proposed by the present disclosure and described in the above-mentioned embodiments.
  • the passivation treatment includes plasma treatment; wherein, when the passivation treatment is performed on the first barrier layer, the following steps are included:
  • the semiconductor structure includes a semiconductor substrate, a bit line conductive layer, and a bit line plug spacer layer; the surface of the semiconductor substrate has grooves; the The bit line conductive layer is partially located in the groove on the surface of the semiconductor substrate; the bit line plug spacer layer is filled in the groove, and the bit line plug spacer layer includes a first protective layer, via The first barrier layer and the filling part after passivation treatment.
  • the thickness of the first protective layer is 1 nm ⁇ 3 nm; and/or the thickness of the first blocking layer is 2 nm ⁇ 8 nm.
  • the material of the first protective layer includes silicon nitride; and/or the material of the first barrier layer includes silicon oxide; and/or the material of the filling portion includes nitrogen Silicone.
  • the first barrier layer after passivation treatment includes two-layer thin film structures, which are a first thin film layer adjacent to the first protective layer and a layer far from the first protective layer, respectively.
  • the second thin film layer wherein, the etching selectivity ratio between the filling portion and the second thin film layer is greater than the etching selectivity ratio between the filling portion and the first thin film layer.
  • the material of the first thin film layer includes silicon oxide
  • the material of the second thin film layer includes silicon oxynitride
  • the present disclosure by performing passivation treatment on the first barrier layer, the etching selection ratio of the etchant to the sacrificial layer and to the first barrier layer is increased, so that when the sacrificial layer is removed by cleaning with the etchant, the inside of the first barrier layer will not be damaged the conductive layer.
  • the present disclosure does not need to add an active agent to the etching solution, so the cleaning process of the present disclosure is relatively simple and does not affect product yield.
  • the present disclosure does not need to increase the thickness of the first barrier layer, can ensure the filling quality of the groove, and further meet the design requirements of miniaturization and thinning of key dimensions of semiconductor products.
  • FIG. 1 is a schematic diagram of a semiconductor structure of a step in a conventional method for manufacturing a bit line structure
  • FIG. 2 is an enlarged comparison diagram of a part of the structure of the bit line structure shown in FIG. 1 before and after etching and removing the sacrificial layer;
  • FIG. 3 is a schematic diagram of a semiconductor structure during one of the steps of a method for manufacturing a bit line structure according to an exemplary embodiment
  • FIG. 4 is an enlarged schematic diagram of a bit line structure of a semiconductor structure shown in one step of a method for manufacturing a bit line structure according to an exemplary embodiment
  • FIG. 5 is an enlarged schematic view of a bit line structure of a semiconductor structure in one step of a method for manufacturing a bit line structure according to an exemplary embodiment
  • FIG. 6 is an enlarged schematic diagram of a bit line structure of a semiconductor structure shown in one step of a method for manufacturing a bit line structure according to an exemplary embodiment
  • FIG. 7 is an enlarged schematic view of a bit line structure of a semiconductor structure shown in one step of a method for manufacturing a bit line structure according to an exemplary embodiment
  • FIG. 8 is an enlarged schematic view of a bit line structure of a semiconductor structure shown in one step of a method for manufacturing a bit line structure according to an exemplary embodiment
  • Bit line conductive layer
  • bit line plug
  • Titanium nitride
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 3 to FIG. 8 schematic diagrams of semiconductor structures under various steps in the method for manufacturing a bit line structure proposed in the present disclosure are respectively shown representatively.
  • the method for fabricating the bit line structure proposed by the present disclosure is described by taking the fabrication of the bit line applied to the dynamic random access memory as an example. It will be easily understood by those skilled in the art that, in order to apply the related designs of the present disclosure to the fabrication methods of other types of semiconductor structures, various modifications, additions, substitutions, deletions or other modifications may be made to the following specific embodiments. variations, which are still within the scope of the principles of the bit line structure fabrication method presented in this disclosure.
  • the method for manufacturing a bit line structure proposed by the present disclosure includes the following steps:
  • a bit line conductive layer 220 is formed on the surface of the semiconductor substrate 210, and the bit line conductive layer 220 is partially located in the groove 211 on the surface of the semiconductor substrate 210;
  • a first protective layer 230 is formed on the surface of the bit line conductive layer 220 and the semiconductor substrate 210;
  • first barrier layer 240 on the surface of the first protective layer 230;
  • a sacrificial layer 250 is formed on the surface of the first barrier layer 240.
  • the sacrificial layer 250 has a filling portion 251 filled in the groove 211;
  • the semiconductor bit line is basically prepared.
  • the present disclosure performs passivation treatment on the first barrier layer 240 to increase the etching selectivity ratio of the etchant to the sacrificial layer 250 and to the first barrier layer 240, so that when the sacrificial layer 250 is removed by cleaning with the etchant, The bit line conductive layer 220 in the first barrier layer 240 will not be damaged. Moreover, compared with the prior art, the present disclosure does not need to add an active agent to the etching solution, nor does it need to increase the thickness of the first barrier layer 240 .
  • FIG. 3 it specifically shows a semiconductor layered structure, which can be used as a representative example of the semiconductor structure in the step of “forming the bit line conductive layer 220 ” in this embodiment.
  • the surface of the semiconductor substrate 210 has grooves 211 .
  • the bit line conductive layer 220 is formed at the groove 211 on the surface of the semiconductor substrate 210, and the bit line conductive layer 220 includes a metal layer 221, a bit line plug 222, and also includes titanium nitride 223 (TiN) and nitride Silicon cap layer.
  • the bit line plug 222 is formed in the groove 211 on the surface of the semiconductor substrate 210, a layer of titanium nitride 223 is formed on the bit line plug 222, the metal layer 221 is formed on the layer of titanium nitride 223, and the metal layer 221 is further A layer of silicon nitride is formed.
  • FIG. 4 it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line in the step of “forming the first protective layer 230 ” in this embodiment.
  • the first protective layer 230 is formed on the surface of the bit line conductive layer 220 and the surface of the semiconductor substrate 210 (the part where the bit line conductive layer 220 is not provided), that is, the groove wall of the groove 211 and the bit line not provided
  • a first protective layer 230 is formed on a part of the bottom of the groove of the conductive layer 220 (bit line plug 222 ).
  • the thickness of the first protective layer 230 may preferably be 1 nm ⁇ 3 nm, such as 1 nm, 1.5 nm, 2 nm, 3 nm, and the like. In other embodiments, the thickness of the first protective layer 230 may also be less than 1 nm, or may be greater than 3 nm, such as 0.8 nm, 4 nm, 5 nm, etc., which is not limited to this embodiment.
  • the material of the first protective layer 230 may preferably include silicon nitride.
  • the material of the sacrificial layer 250 can also preferably include silicon nitride.
  • the silicon nitride layer when used as the first protective layer 230, it can be called Inner SiN, Then, when silicon nitride is used as the sacrificial layer 250, it can be called Outer SiN.
  • the first barrier layer 240 is formed on the surface of the first protective layer 230 , that is, the groove wall of the groove 211 and the part of the groove bottom where the bit line conductive layer 220 (bit line plug 222 ) is not provided are formed in sequence.
  • the material of the first barrier layer 240 may include, but is not limited to, silicon oxide.
  • FIG. 6 it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line structure in the “passivation treatment” step in this embodiment.
  • the surface of the first barrier layer 240 is subjected to passivation treatment.
  • the passivation treatment performed on the first barrier layer 240 may preferably include plasma treatment.
  • the plasma treatment may preferably be nitrogen (N 2 ) plasma treatment.
  • the passivation treatment on the first barrier layer 240 may also adopt other passivation processes or combinations, such as ion implantation, thermal oxidation treatment, etc., which is not limited to this embodiment.
  • the surface of the first barrier layer 240 roughly includes a two-layer thin film structure after passivation treatment.
  • the two thin film structures are defined as the first thin film layer 241 and the second thin film layer 242 in this specification, respectively.
  • the first thin film layer 241 is adjacent to the first protective layer 230, and the second thin film layer 242 is far away from the first protective layer 230 (ie, adjacent to the sacrificial layer 250 formed in the subsequent process).
  • the first thin film layer 241 can also be understood as a layered structure that roughly maintains the same property state as the first barrier layer 240 without passivation treatment, and the second thin film layer 242 is a
  • the barrier layer 240 is a layer in which the property state of the barrier layer 240 is changed without passivation treatment.
  • the above-mentioned changes of the second thin film layer 242 include: the etching selectivity ratio between the sacrificial layer 250 and the second thin film layer 242 is greater than the etching selectivity ratio between the sacrificial layer 250 and the first thin film layer 241, that is, the first barrier layer 240 passes through the passivation layer.
  • the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240 is increased.
  • the first barrier layer 240 can also be formed into a thin film structure of two or more layers, and at least one thin film structure of the sacrificial layer 250 and the first barrier layer 240 The etching selectivity ratio is greater than the etching selectivity ratio between the sacrificial layer 250 and other thin film structures.
  • the first barrier layer 240 after passivation treatment can maintain a single-layer thin film structure, and the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 after treatment is greater than that of the sacrificial layer 250 and the first barrier layer before treatment 240 etch selectivity ratio. That is, after the passivation treatment, the first barrier layer 240 can form various possible layered film structures, and the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240 is increased after the passivation treatment of the first barrier layer 240. Big.
  • the second thin film layer is The material of 242 includes silicon oxynitride (SiON). Accordingly, taking the material of the sacrificial layer 250 including silicon nitride as an example, the etching selectivity ratio of silicon nitride and silicon oxynitride is greater than the etching selectivity ratio of silicon nitride and silicon oxide, that is, the first barrier layer 240 is subjected to nitrogen plasma. After the processing, the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 is increased.
  • the thickness of the first barrier layer 240 may preferably be 2 nm to 8 nm, such as 2 nm, 3 nm, 4 nm, 5 nm, and the like. In other embodiments, the thickness of the first barrier layer 240 may also be less than 2 nm, such as 1 nm, 1.5 nm, etc., which is not limited to this embodiment. It should be noted that, because the present disclosure adopts the process step of passivating the first barrier layer 240, the etching selectivity ratio of the sacrificial layer 250 and the first barrier layer 240 formed in the subsequent process is increased.
  • the thickness required for forming the first barrier layer 240 in the present disclosure is smaller than that for forming the barrier layer in the prior art. Thickness required. That is, the preferred range of the thickness of the first barrier layer 240 in this embodiment is actually unrealizable by the existing process, rather than a simple selection of the data range.
  • the passivation treatment on the first barrier layer 240 may preferably include the following specific steps:
  • a treatment equipment such as a plasma surface treatment apparatus can be preferably used for the plasma treatment of the first barrier layer 240.
  • the semiconductor structure is put into the processing chamber of the plasma surface treatment apparatus, and the processing chamber is preheated before the semiconductor structure is put in.
  • a reaction medium eg nitrogen, etc.
  • the surface of the first barrier layer 240 of the semiconductor structure is subjected to plasma treatment with the reaction medium.
  • the processing chamber in which the semiconductor structure is placed is cooled, and finally the cooled semiconductor structure is taken out from the processing chamber.
  • the specific steps and procedures of the passivation treatment can also be flexibly selected, and the This embodiment is limited.
  • FIG. 7 it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line structure in the step of “forming a sacrificial layer 250 ” in this embodiment.
  • the sacrificial layer 250 is formed on the surface of the first barrier layer 240 after passivation treatment. And, the filling part 251 of the sacrificial layer 250 is filled in the groove 211 (the part where the first protective layer 230 and the first barrier layer 240 are not formed).
  • bit line plug spacers 260 are formed in the grooves 211 on both sides of the bit line plug 222 of the semiconductor structure.
  • the bit line plug spacer layer 260 includes the first protective layer 230 , the first barrier layer 240 and the unremoved sacrificial layer 250 (filling portion 251 ).
  • the material of the sacrificial layer 250 may include, but is not limited to, silicon nitride (when the material of the first protective layer 230 also includes silicon nitride, the silicon nitride of the sacrificial layer 250 is Outer SiN).
  • the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240 is increased.
  • the specific meaning of the above-mentioned etching selection ratio includes: under the same etching conditions, the ratio of the etching rate of the etching solution to the former and the etching rate of the etching solution to the latter.
  • the "etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240" is the etching rate of the sacrificial layer 250 by the etching solution and the etching rate of the first barrier layer 240 by the etching solution, and the increase of the ratio , that is, under the same etching conditions, the etching rate of the sacrificial layer 250 by the etching solution is faster.
  • the present disclosure can realize the cleaning and removal of the sacrificial layer 250, and can reduce or avoid the etching of the first barrier layer 240, thereby protecting the first barrier layer
  • the first protective layer 230 (usually comprising the same material as the sacrificial layer 250, such as silicon nitride) inside the layer 240 will not be removed by etching, thereby protecting the bit line conductive layer 220 inside the first protective layer 230 from etching damage .
  • FIG. 8 it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line structure in the step of “cleaning and removing the sacrificial layer 250” in this embodiment.
  • this step is to wet clean the semiconductor structure after the sacrificial layer 250 is formed with an etchant, so that the rest of the sacrificial layer 250 except the filling portion 251 is etched away by the etchant.
  • the semiconductor structure after the sacrificial layer 250 is cleaned and removed the groove 211 of the semiconductor structure is still fully filled with the first protective layer 230, the first barrier layer 240 and the filling portion 251 of the sacrificial layer 250, which can prevent short circuits to the greatest extent. adverse effects. So far, the semiconductor bit line is basically prepared.
  • the etching solution may preferably contain a phosphoric acid solution.
  • the etching liquid can also be selected from other types of etching liquids or solutions, which is not limited to this embodiment.
  • the temperature of the etching solution may preferably be 100°C to 120°C, for example, 100°C, 105°C. °C, 110 °C, 120 °C, etc. In other embodiments, the temperature of the etching solution may also be lower than 100°C, or may be higher than 120°C, such as 95°C, 125°C, 150°C, 160°C, etc., which is not limited to this embodiment.
  • the present disclosure adopts the process step of passivating the first barrier layer 240, the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240 formed in the subsequent process is increased.
  • the temperature of the etching solution is lower than the temperature of the etching solution in the prior art, so as to achieve a larger etching selectivity ratio.
  • the present disclosure can also adopt the temperature of the etching solution similar to the existing process. That is, the preferred range of the temperature of the etching solution in this embodiment is actually unrealizable by the existing process, rather than a simple selection of the data range.
  • the concentration of the etching solution may preferably be 40% to 60% °C, such as 40%. , 45%, 50%, 60%, etc. In other embodiments, the concentration of the etching solution may also be less than 40%, or may be greater than 60%, such as 38%, 65%, 70%, 85%, etc., which is not limited to this embodiment. It should be noted that since the present disclosure adopts the process step of passivating the first barrier layer 240, the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240 formed in the subsequent process is increased.
  • the concentration of the etching solution may be lower than that of the etching solution in the prior art, so as to achieve a larger etching selectivity ratio.
  • the present disclosure can also adopt the concentration of the etching solution similar to that of the prior art. That is, the preferred range of the concentration of the etching solution in this embodiment is actually unrealizable by the existing process, rather than a simple selection of the data range.
  • the etching and cleaning of the sacrificial layer 250 may preferably include the following specific steps:
  • the sacrificial layer 250 is washed with a phosphoric acid solution, and the portion of the sacrificial layer 250 other than the filling portion 251 is removed.
  • a native oxide layer may be formed on the surface of the sacrificial layer 250 .
  • the present disclosure can effectively remove the native oxide layer formed on the surface of the sacrificial layer 250 by adding a pre-cleaning step before using the etching solution to clean the sacrificial layer 250, so that the cleaning and removal of the sacrificial layer 250 by using the etching solution is more effective. Better stability and controllability.
  • the specific steps of etching and cleaning the sacrificial layer 250 can preferably be performed by using a trough-type wet process machine.
  • the surface of the sacrificial layer 250 may be pre-cleaned for 5s to 15s by using a hydrofluoric acid solution diluted by 200:1. Then, the pre-cleaned semiconductor structure is put into a tank-type wet process machine, and a low-temperature and low-concentration phosphoric acid solution (such as a temperature of 100° C. to 120° C. and a concentration of 40% to 60%) is used for tank type wet cleaning, and then After washing with water and drying with isopropanol, the dried semiconductor structure was taken out from the tank-type wet process machine.
  • a low-temperature and low-concentration phosphoric acid solution such as a temperature of 100° C. to 120° C. and a concentration of 40% to 60%
  • the comparison between the present disclosure and the existing technology is based on "whether to carry out pre-cleaning", "the concentration of etching solution using phosphoric acid as an example”, “the temperature of etching solution using phosphoric acid as an example”, “a nitrogen plasma
  • the “passivation treatment” is the process condition, and the comparison result is the “etch select ratio” between the sacrificial layer and the barrier layer (the first barrier layer in the present disclosure) of the semiconductor bit line structure obtained by each process.
  • the existing process the process of performing nitrogen plasma treatment on the barrier layer is not used, the phosphoric acid concentration is relatively high 75% to 88%, and the phosphoric acid temperature is relatively high 150°C to 165°C, and the The sacrificial layer is pre-cleaned, and the etching selectivity ratio between the sacrificial layer and the barrier layer is about 5:1.
  • Embodiment 1 of the present disclosure the first barrier layer is treated with nitrogen plasma, the phosphoric acid concentration and the phosphoric acid temperature are the same as those of the existing process, and the process of pre-cleaning the sacrificial layer is also not used.
  • the layer to barrier etch selectivity ratio is approximately 16:1.
  • the semiconductor bit line structure prepared by the method for manufacturing the bit line structure proposed in the present disclosure can indeed increase the etching selectivity ratio between the sacrificial layer and the first barrier layer, so that the thickness of the first barrier layer can indeed be higher than that of the first barrier layer. It is ensured that the sacrificial layer is cleaned and removed by the etching solution without damaging the conductive layer in the first barrier layer.
  • Embodiment 1 of the present disclosure pre-cleaning no no DHF 200:1; 10s Phosphoric acid concentration 75% ⁇ 88% 75% ⁇ 88% 40% ⁇ 60% Phosphoric acid temperature 150°C ⁇ 165°C 150°C ⁇ 165°C 100°C ⁇ 120°C N2 plasma treatment no Yes Yes Etch selectivity 5:1 16:1 32:1
  • bit line structure fabrication methods shown in the drawings and described in this specification are but a few examples of the many fabrication methods that can employ the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are by no means limited to any detail or any step of a method of fabricating a bit line structure illustrated in the drawings or described in this specification.
  • the method for fabricating a semiconductor structure proposed by the present disclosure includes the following steps:
  • the surface of the semiconductor substrate has grooves
  • a bit line structure is formed on a semiconductor substrate using the method for fabricating the bit line structure proposed in the present disclosure and described in the above-mentioned embodiments.
  • bit line structure proposed by the present disclosure
  • various possible process steps may be used before and after the formation of the bit line structure, thereby forming various semiconductor structures.
  • the required functional structure or process structure is not limited to this embodiment.
  • the first barrier layer may be removed, and then functional structures such as the second barrier layer and the second protective layer are sequentially formed.
  • functional structures such as the second barrier layer and the second protective layer are sequentially formed.
  • it can still be realized by processes such as deposition (Dep) and etching (Etch), and in the process of performing the above-mentioned processes, it can still be layered by processes such as silicon oxide and silicon nitride. Processes such as patterning of the structure are not limited to this embodiment.
  • the semiconductor structure proposed in the present disclosure is fabricated through the semiconductor structure fabrication method proposed in the present disclosure and described in the above-mentioned embodiments.
  • the semiconductor structure proposed by the present disclosure includes a semiconductor substrate 210 , a bit line conductive layer 220 , and a bit line plug spacer layer 260 .
  • the surface of the semiconductor substrate 210 has grooves 211 .
  • the bit line conductive layer 220 is partially located in the groove 211 on the surface of the semiconductor substrate.
  • the bit line plug spacer layer 260 is filled in the groove, and the bit line plug spacer layer includes a first protective layer 230 , a passivation-treated first barrier layer 240 and a filling portion 251 .
  • the thickness of the first protective layer 230 may preferably be 1 nm ⁇ 3 nm.
  • the thickness of the first barrier layer 240 may preferably be 2 nm ⁇ 8 nm.
  • the material of the first protective layer 230 may preferably include silicon nitride.
  • the material of the first barrier layer 240 may preferably include silicon oxide.
  • the material of the filling portion 251 may preferably include silicon nitride.
  • the first barrier layer 240 after passivation treatment includes two thin film structures, namely the first thin film layer 241 adjacent to the first protective layer 230 and the second thin film layer 241 away from the first protective layer 230 .
  • Two thin film layers 242 wherein, the etching selectivity ratio between the filling portion 251 and the second thin film layer 242 is greater than the etching selectivity ratio between the filling portion 251 and the first thin film layer 241 .
  • the material of the first thin film layer 241 includes silicon oxide
  • the material of the second thin film layer 242 includes silicon oxynitride.
  • the present disclosure by performing passivation treatment on the first barrier layer, the etching selectivity ratio of the etchant to the sacrificial layer and to the first barrier layer is increased, so that the sacrificial layer will not be damaged when the etchant is used to clean and remove the sacrificial layer.
  • a conductive layer within the first barrier layer Moreover, on the basis of achieving the above-mentioned effects, compared with the prior art, the present disclosure does not need to add an active agent to the etching solution, so the cleaning process of the present disclosure is relatively simple and does not affect product yield. In addition, the present disclosure does not need to increase the thickness of the first barrier layer, and can further meet the design requirements of miniaturization and thinning of the critical dimensions of semiconductor products.

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开实施例提出一种位线结构制造方法、半导体结构制造方法及半导体结构，位线结构制造方法包含以下步骤：在半导体衬底的表面形成位线导电层，位线导电层部分位于半导体衬底表面的凹槽内；在位线导电层和半导体衬底的表面形成第一保护层；在第一保护层的表面形成第一阻挡层；对第一阻挡层的表面进行钝化处理；在第一阻挡层的表面形成牺牲层，牺牲层具有填充于凹槽内的填充部；利用蚀刻液清洗去除牺牲层的除填充部以外的部分。本公开通过对第一阻挡层进行钝化处理，使得蚀刻液对牺牲层与对第一阻挡层蚀刻选择比增大，从而在利用蚀刻液清洗去除牺牲层时，不会损伤第一阻挡层内的导电层。

Description

位线结构制造方法、半导体结构制造方法及半导体结构
相关申请的交叉引用
本公开要求基于2020年8月13日提交的申请号为202010811435.X的中国申请“位线结构制造方法、半导体结构制造方法及半导体结构”的优先权，通过援引将其全部内容并入本文中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种位线结构制造方法、半导体结构制造方法及半导体结构。
背景技术
随着近年来半导体行业内纳米器件的飞速发展，芯片生产中特征尺寸不断缩小，整个技术仍然继续朝着关键尺寸进一步微细化的方向发展。例如，在先进动态随机存取存储器(DRAM)的制程工艺中，位线(bit line)的制程工艺水平会严重影响后期芯片的电性，良率(yield)和可靠性。特别地，随着关键尺寸的不断缩小，对牺牲层的微细化以及稳定性要求也越来越高。其中，位线的牺牲层的去除方法变得越来越重要。
如图1和图2所示，在现有工艺制程中，由于蚀刻液(例如磷酸溶液，H 3PO 4)对牺牲层150(例如氮化硅，Si 3N 4)与对阻挡层140(例如氧化硅，SiO2)的蚀刻选择比(即牺牲层150被蚀刻液蚀刻的速率与阻挡层140被蚀刻液蚀刻的速率的比值)较小，使得蚀刻液在清洗去除(strip)牺牲层150时，容易将阻挡层140蚀刻去除，从而部分去除保护层130，并对阻挡层140内的导电层120产生蚀刻损伤121(W Missing，W即为钨)。
针对上述问题，需要对位线结构的制造方法进行优化。
发明内容
本公开的一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种能够避免导电层被蚀刻液损伤的位线结构制造方法。
本公开的另一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种采用上述位线结构制造方法的半导体结构制造方法。
本公开的又一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种经由上述 的半导体结构制造方法制成的半导体结构。
为实现上述目的，本公开采用如下技术方案：
根据本公开的一个方面，提供一种位线结构制造方法；其中，所述位线结构制造方法包含以下步骤：
在半导体衬底的表面形成位线导电层，所述位线导电层部分位于所述半导体衬底表面的凹槽内；
在所述位线导电层和所述半导体衬底的表面形成第一保护层；
在所述第一保护层的表面形成第一阻挡层；
对所述第一阻挡层的表面进行钝化处理；
在所述第一阻挡层的表面形成牺牲层，所述牺牲层具有填充于所述凹槽内的填充部；以及
利用蚀刻液清洗去除所述牺牲层的除所述填充部以外的部分。
根据本公开的其中一个实施方式，所述钝化处理包含等离子体处理、离子注入或者热氧化处理。
根据本公开的其中一个实施方式，经由钝化处理后的所述第一阻挡层包含两层薄膜结构，分别为邻接所述第一保护层的第一薄膜层和远离所述第一保护层的第二薄膜层；其中，所述牺牲层与所述第二薄膜层的蚀刻选择比大于所述牺牲层与所述第一薄膜层的蚀刻选择比。
根据本公开的其中一个实施方式，所述第一阻挡层的材质包含氧化硅；其中，所述钝化处理包含氮气等离子体处理，所述第二薄膜层的材质包含氮氧化硅。
根据本公开的其中一个实施方式，所述第一保护层的厚度为1nm～3nm；和/或，所述第一阻挡层的厚度为2nm～8nm。
根据本公开的其中一个实施方式，所述第一保护层的材质包含氮化硅；和/或，所述第一阻挡层的材质包含氧化硅；和/或，所述牺牲层的材质包含氮化硅。
根据本公开的其中一个实施方式，所述蚀刻液包含磷酸溶液；其中，所述蚀刻液的温度为100℃～120℃；和/或，所述蚀刻液的浓度为40％～60％。
根据本公开的其中一个实施方式，利用所述蚀刻液清洗去除所述牺牲层的除所述填充部以外的部分之后，还包含以下步骤：
去除暴露的所述第一阻挡层；
在所述位线导电层和所述半导体衬底的表面形成第二阻挡层；
在所述第二阻挡层的表面形成第二保护层。
根据本公开的其中一个实施方式，利用所述蚀刻液清洗去除所述牺牲层时，包含以下步骤：
利用稀释过的氢氟酸溶液对所述牺牲层的表面进行预清洗，去除所述牺牲层表面的氧化层；以及
利用磷酸溶液清洗所述牺牲层，去除所述牺牲层的除所述填充部以外的部分。
根据本公开的另一个方面，提供一种半导体结构制造方法；其中，所述半导体结构制造方法包含以下步骤：
提供半导体衬底，所述半导体衬底的表面具有凹槽；
利用本公开提出的并在上述实施方式中所述的位线结构制造方法，在所述半导体衬底上形成位线结构。
根据本公开的其中一个实施方式，所述钝化处理包含等离子体处理；其中，对所述第一阻挡层进行钝化处理时，包含以下步骤：
对处理设备的处理腔室进行预热；
将形成有所述第一阻挡层的半导体结构放入处理腔室；
输入反应介质并对所述第一阻挡层的表面进行等离子体处理；
对处理腔室进行冷却；以及
取出半导体结构。
根据本公开的又一个方面，提供一种半导体结构；其中，所述半导体结构包含半导体衬底、位线导电层以及位线插塞间隔层；所述半导体衬底的表面具有凹槽；所述位线导电层部分位于所述半导体衬底表面的凹槽内；所述所述位线插塞间隔层填充于所述凹槽内，所述位线插塞间隔层包含第一保护层、经由钝化处理后的第一阻挡层以及填充部。
根据本公开的其中一个实施方式，所述第一保护层的厚度为1nm～3nm；和/或，所述第一阻挡层的厚度为2nm～8nm。
根据本公开的其中一个实施方式，所述第一保护层的材质包含氮化硅；和/或，所述第一阻挡层的材质包含氧化硅；和/或，所述填充部的材质包含氮化硅。
根据本公开的其中一个实施方式，经由钝化处理后的所述第一阻挡层包含两层薄膜结构，分别为邻接所述第一保护层的第一薄膜层和远离所述第一保护层的第二薄膜层；其中，所述填充部与所述第二薄膜层的蚀刻选择比大于所述填充部与所述第一薄膜层的蚀刻选择比。
根据本公开的其中一个实施方式，所述第一薄膜层的材质包含氧化硅，所述第二薄膜层的材质包含氮氧化硅。
由上述技术方案可知，本公开提出的位线结构制造方法的优点和积极效果在于：
本公开通过对第一阻挡层进行钝化处理，使得蚀刻液对牺牲层与对第一阻挡层蚀刻选择比增大，从而在利用蚀刻液清洗去除牺牲层时，不会损伤第一阻挡层内的导电层。并且，在实现上述功效的基础上，相比于现有工艺，本公开无需在蚀刻液中加入活性剂，因此本公开的清洗工艺的较为简单，也不会影响产品良率。另外，本公开无需增大第一阻挡层的厚度，能够保证凹槽的填充质量，进一步满足半导体产品关键尺寸的微细化、薄型化的设计要求。
附图说明
图1是一种现有的位线结构制造方法中一步骤的半导体结构示意图；
图2是图1示出的位线结构在蚀刻去除牺牲层前后的部分结构的放大对比图；
图3是根据一示例性实施方式示出的一种位线结构制造方法的其中一个步骤时的半导体结构示意图；
图4是根据一示例性实施方式示出的位线结构制造方法的其中一个步骤时的半导体结构的一个位线结构的放大示意图；
图5是根据一示例性实施方式示出的位线结构制造方法的其中一个步骤时的半导体结构的一个位线结构的放大示意图；
图6是根据一示例性实施方式示出的位线结构制造方法的其中一个步骤时的半导体结构的一个位线结构的放大示意图；
图7是根据一示例性实施方式示出的位线结构制造方法的其中一个步骤时的半导体结构的一个位线结构的放大示意图；
图8是根据一示例性实施方式示出的位线结构制造方法的其中一个步骤时的半导体结构的一个位线结构的放大示意图；
附图标记说明如下：
111.凹槽；
120.导电层；
121.蚀刻损伤；
130.保护层；
140.阻挡层；
150.牺牲层；
210.半导体衬底；
211.凹槽；
220.位线导电层；
221.金属层；
222.位线插塞；
223.氮化钛；
230.第一保护层；
240.第一阻挡层；
241.第一薄膜层；
242.第二薄膜层；
250.牺牲层；
251.填充部；
260.位线插塞间隔层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
参阅图3至图8，其分别代表性地示出了本公开提出的位线结构制造方法中各步骤下的半导体结构示意图。在该示例性实施方式中，本公开提出的位线结构制造方法是以应用于动态随机存取存储器的位线制备为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的半导体结构的制造方法中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的位线结构制造方法的原理的范围内。
如图3至图8所示，在本实施方式中，本公开提出的位线结构制造方法包含以下步骤：
在半导体衬底210的表面形成位线导电层220，位线导电层220部分位于半导体衬底210表面的凹槽211内；
在位线导电层220和半导体衬底210的表面形成第一保护层230；
在第一保护层230的表面形成第一阻挡层240；
对第一阻挡层240的表面进行钝化处理；
在第一阻挡层240的表面形成牺牲层250，牺牲层250具有填充于凹槽211内的填充部251；利用蚀刻液清洗去除牺牲层250的除填充部251以外的部分。
至此，半导体位线基本制备完成。
通过上述设计，本公开通过对第一阻挡层240进行钝化处理，使得蚀刻液对牺牲层250与对第一阻挡层240蚀刻选择比增大，从而在利用蚀刻液清洗去除牺牲层250时，不会损伤第一阻挡层240内的位线导电层220。并且，相比于现有工艺，本公开无需在蚀刻液中加入活性剂，也无需增大第一阻挡层240的厚度。
具体地，如图3所示，其具体示出了一种半导体层状结构，其可以作为本实施方式中的“形成位线导电层220”步骤中的半导体结构的代表性示例。其中，该半导体衬底210的表面具有凹槽211。该位线导电层220形成于半导体衬底210的表面的凹槽211处，且位线导电层220包含金属层221、位线插塞222，还包含可以氮化钛223(TiN)和氮化硅盖层。位线插塞222形成于半导体衬底210的表面的凹槽211，位线插塞222上形成有一层氮化钛223，金属层221形成于该层氮化钛223上，金属层221上还形成有一层氮化硅。
具体地，如图4所示，其具体示出了一个半导体位线的放大层状结构，其可以作为本实施方式中的“形成第一保护层230”步骤中的位线的代表性示例。其中，该第一保护层230是形成于位线导电层220的表面和半导体衬底210的表面(未设置位线导电层220的部分)，即，凹槽211的槽壁和未设置位线导电层220(位线插塞222)的部分槽底，均形成有第一保护层230。
较佳地，在本实施方式中，对于“形成第一保护层230”的步骤而言，第一保护层230的厚度可以优选为1nm～3nm，例如1nm、1.5nm、2nm、3nm等。在其他实施方式中，第一保护层230的厚度亦可小于1nm，或可大于3nm，例如0.8nm、4nm、5nm等，并不以本实施方式为限。
较佳地，在本实施方式中，对于“形成第一保护层230”的步骤而言，第一保护层230的材质可以优选地包含氮化硅。其中，由于在“形成牺牲层250”的步骤中，牺牲层250的材质也可以优选地包含氮化硅，为了便于区分，氮化硅层作为第一保护层230时，可以称为Inner SiN，则氮化硅作为牺牲层250时，可以称为Outer SiN。
具体地，如图5所示，其具体示出了一个半导体位线的放大层状结构，其可以作为本 实施方式中的“形成第一阻挡层240”步骤中的位线的代表性示例。其中，该第一阻挡层240是形成于第一保护层230的表面，即，凹槽211的槽壁和未设置位线导电层220(位线插塞222)的部分槽底，均依次形成有第一保护层230和第一阻挡层240。其中，在本实施方式中，该第一阻挡层240的材质可以但不限于包含氧化硅。
具体地，如图6所示，其具体示出了一个半导体位线的放大层状结构，其可以作为本实施方式中的“钝化处理”步骤中的位线结构的代表性示例。其中，该步骤是在第一保护层230表面形成第一阻挡层240之后，对第一阻挡层240的表面进行钝化处理。
较佳地，在本实施方式中，对于“钝化处理”的步骤而言，对第一阻挡层240进行的钝化处理可以优选地包含等离子体处理。进一步地，该等离子体处理可以优选为氮气(N 2)等离子体处理。在其他实施方式中，对第一阻挡层240进行的钝化处理亦可采用其他钝化工艺或者组合，例如离子注入、热氧化处理等，并不以本实施方式为限。
较佳地，如图6所示，在本实施方式中，对于“钝化处理”的步骤而言，第一阻挡层240的表面在经由钝化处理后大致包含两层薄膜结构。为了便于理解和说明，本说明书中是将这两层薄膜结构分别定义为第一薄膜层241和第二薄膜层242。其中，第一薄膜层241邻接第一保护层230，第二薄膜层242远离第一保护层230(即邻接于后序制程形成的牺牲层250)。在此基础上，亦可将第一薄膜层241理解为大致保持与第一阻挡层240未经钝化处理时的性质状态相同的层状结构，则第二薄膜层242即为相比第一阻挡层240未经钝化处理时的性质状态产生变化的一层。其中，第二薄膜层242的上述变化包含：牺牲层250与第二薄膜层242的蚀刻选择比大于牺牲层250与第一薄膜层241的蚀刻选择比，即，第一阻挡层240在经由钝化处理后，牺牲层250与第一阻挡层240的蚀刻选择比增大。在其他实施方式中，基于不同类型的钝化处理，第一阻挡层240亦可形成两层或者两层以上的薄膜结构，且牺牲层250与第一阻挡层240的其中至少一层薄膜结构的蚀刻选择比大于牺牲层250与其他层薄膜结构的蚀刻选择比。或者，经由钝化处理后的第一阻挡层240还可保持单层薄膜结构，且牺牲层250与处理后的第一阻挡层240的蚀刻选择比大于牺牲层250与处理前的第一阻挡层240的蚀刻选择比。即，经由钝化处理后，第一阻挡层240可以形成各种可能的层状薄膜结构，牺牲层250与第一阻挡层240的蚀刻选择比是在第一阻挡层240经由钝化处理后增大。
举例而言，基于第一阻挡层240的材质包含氧化硅，同时基于钝化处理包含氮气等离子体处理的设计，在本实施方式中，该氧化硅经由氮气等离子体处理后，其第二薄膜层242的材质包含氮氧化硅(SiON)。据此，以牺牲层250的材质包含氮化硅为例，氮化硅 与氮氧化硅的蚀刻选择比大于氮化硅与氧化硅的蚀刻选择比，即，第一阻挡层240经由氮气等离子体处理后，牺牲层250与第一阻挡层240的蚀刻选择比增大。
较佳地，在本实施方式中，对于“形成第一阻挡层240”的步骤而言，第一阻挡层240的厚度可以优选为2nm～8nm，例如2nm、3nm、4nm、5nm等。在其他实施方式中，第一阻挡层240的厚度亦可小于2nm，例如1nm、1.5nm等，并不以本实施方式为限。需说明的是，由于本公开采用对第一阻挡层240进行钝化处理的工艺步骤，使得后序制程形成的牺牲层250与第一阻挡层240的蚀刻选择比增大，因此，在相同的蚀刻条件下(例如蚀刻液的温度和浓度、清洗时间均相同)，如欲达到相同的蚀刻去除效果，本公开形成第一阻挡层240的所需厚度是小于现有工艺中形成阻挡层的所需厚度。亦即，本实施方式对上述第一阻挡层240的厚度的优选范围，实际上是现有工艺无法实现的，而非数据范围的简单选择。
较佳地，基于钝化处理包含等离子体处理的设计，在本实施方式中，对于“钝化处理”的步骤而言，对第一阻挡层240进行钝化处理可以优选地包含以下具体步骤：
对处理设备的处理腔室进行预热；
将形成有所述第一阻挡层240的半导体结构放入处理腔室；
输入反应介质并对所述第一阻挡层240的表面进行等离子体处理；
对处理腔室进行冷却；
取出半导体结构。
承上，对第一阻挡层240的等离子体处理，可以优选地采用等离子体表面处理仪等处理设备。在此基础上，是将半导体结构放入等离子体表面处理仪的处理腔室内，且在放入半导体结构之前，是先对处理腔室进行预热。将半导体结构放入预热的处理腔室之后，向处理腔室内容输入反应介质(例如氮气等)，并利用反应介质对半导体结构的第一阻挡层240的表面进行等离子体处理。待处理完成后，对放置有半导体结构的处理腔室进行冷却，最后再将冷却后的半导体结构由处理腔室取出。在其他实施方式中，对于“钝化处理”的步骤而言，当采用其他类型的等离子体处理工艺或者其他类型的钝化工艺时，亦可灵活选择钝化处理的具体步骤和流程，并不以本实施方式为限。
具体地，如图7所示，其具体示出了一个半导体位线的放大层状结构，其可以作为本实施方式中的“形成牺牲层250”步骤中的位线结构的代表性示例。其中，该牺牲层250是形成于经过钝化处理后的第一阻挡层240的表面。并且，牺牲层250的填充部251填充于凹槽211(未形成第一保护层230和第一阻挡层240的部分)中。即，在凹槽211槽腔 的未设置位线导电层220(位线插塞222)的部分中，槽壁和部分槽底均依次形成有第一保护层230和第一阻挡层240，且该部分其余的槽腔均由牺牲层250(填充部251)填充。在此基础上，半导体结构的位线插塞222两侧的凹槽211中，形成有位线插塞间隔层260。该位线插塞间隔层260是包含第一保护层230、第一阻挡层240和未去除的牺牲层250(填充部251)。其中，在本实施方式中，该牺牲层250的材质可以但不限于包含氮化硅(当第一保护层230的材质也包含氮化硅时，牺牲层250的氮化硅即Outer SiN)。
承上，由于本公开在形成牺牲层250之前，是对第一阻挡层240进行了钝化处理，从而使得牺牲层250与第一阻挡层240的蚀刻选择比增大。具体而言，上述蚀刻选择比的具体含义包含：在相同的蚀刻条件下，蚀刻液对前者的蚀刻速率与蚀刻液对后者的蚀刻速率的比值。据此，“牺牲层250与第一阻挡层240的蚀刻选择比”，即为蚀刻液对牺牲层250的蚀刻速率与蚀刻液对第一阻挡层240的蚀刻速率，并且，该比值的增大，即相当于在相同的蚀刻条件下，蚀刻液对牺牲层250的蚀刻速率更快。因此，在之后的“清洗去除牺牲层250”的一个蚀刻清洗步骤中，本公开能够实现对牺牲层250的清洗去除，并能够减少或者避免对第一阻挡层240的蚀刻，从而保护第一阻挡层240内部的第一保护层230(通常包含与牺牲层250相同的材质，例如氮化硅)不会被蚀刻去除，进而保护第一保护层230内部的位线导电层220不会产生蚀刻损伤。
具体地，如图8所示，其具体示出了一个半导体位线的放大层状结构，其可以作为本实施方式中的“清洗去除牺牲层250”步骤中的位线结构的代表性示例。其中，该步骤是利用蚀刻液对形成牺牲层250之后的半导体结构进行湿法清洗(Wet Clean)，使得牺牲层250的除填充部251以外的其余部分被蚀刻液蚀刻去除。据此，清洗去除牺牲层250之后的半导体结构，其凹槽211内仍充分填充有第一保护层230、第一阻挡层240和牺牲层250的填充部251，最大程度地起到了防止短路等不良产生的功效。至此，半导体位线基本制备完成。
较佳地，在本实施方式中，对于“清洗去除牺牲层250”的步骤而言，蚀刻液可以优选地包含磷酸溶液。在其他实施方式中，蚀刻液亦可选择其他种类的蚀刻性液体或溶液，并不以本实施方式为限。
较佳地，在本实施方式中，对于“清洗去除牺牲层250”的步骤而言，以蚀刻液包含磷酸溶液为例，蚀刻液的温度可以优选为100℃～120℃，例如100℃、105℃、110℃、120℃等。在其他实施方式中，蚀刻液的温度亦可小于100℃，或可大于120℃，例如95℃、125℃、150℃、160℃等，并不以本实施方式为限。需说明的是，由于本公开采用对第一 阻挡层240进行钝化处理的工艺步骤，使得后序制程形成的牺牲层250与第一阻挡层240的蚀刻选择比增大，本公开所采用的蚀刻液的温度低于现有工艺中蚀刻液的温度，以实现更大的刻蚀选择比。当然，在其他实施方式中，本公开亦可采用与现有工艺类似的蚀刻液的温度。亦即，本实施方式对蚀刻液的温度的优选范围，实际上是现有工艺无法实现的，而非数据范围的简单选择。
较佳地，在本实施方式中，对于“清洗去除牺牲层250”的步骤而言，，以蚀刻液包含磷酸溶液为例，蚀刻液的浓度可以优选为40％～60％℃，例如40％、45％、50％、60％等。在其他实施方式中，蚀刻液的浓度亦可小于40％，或可大于60％，例如38％、65％、70％、85％等，并不以本实施方式为限。需说明的是，由于本公开采用对第一阻挡层240进行钝化处理的工艺步骤，使得后序制程形成的牺牲层250与第一阻挡层240的蚀刻选择比增大，本公开所采用的蚀刻液的浓度可以小于现有工艺中蚀刻液的浓度，以实现更大的刻蚀选择比。当然，在其他实施方式中，本公开亦可采用与现有工艺类似的蚀刻液的浓度。亦即，本实施方式对蚀刻液的浓度的优选范围，实际上是现有工艺无法实现的，而非数据范围的简单选择。
较佳地，在本实施方式中，对于“清洗去除牺牲层250”的步骤而言，对牺牲层250进行蚀刻清洗可以优选地包含以下具体步骤：
利用稀释过的氢氟酸溶液对牺牲层250的表面进行预清洗，去除牺牲层250表面的氧化层；以及
利用磷酸溶液清洗牺牲层250，去除牺牲层250的除填充部251以外的部分。
承上，在具体工艺制程中，在第一阻挡层240表面形成牺牲层250之后，由于牺牲层250暴露并接触于空气，可能会在牺牲层250表面形成一层原生氧化层。对此，本公开通过在利用蚀刻液清洗牺牲层250之前加入预清洗的步骤，能够有效去除牺牲层250表面形成的原生氧化层，使得利用蚀刻液对牺牲层250的清洗去除更加有效，制程的稳定性和可控性较佳。
再者，对于上述蚀刻清洗牺牲层250的具体步骤，可以优选地利用槽式湿法机台进行。具体而言，可以采用按照200：1稀释过的氢氟酸溶液对牺牲层250的表面进行5s～15s预清洗。然后，将预清洗后的半导体结构放入槽式湿法机台中采用低温低浓度(比如温度为100℃～120℃，浓度为40％～60％)的磷酸溶液进行槽式湿法清洗，然后通过水洗及异丙醇干燥后再将干燥后的半导体结构由槽式湿法机台取出。
承上所述，为了论证本公开提出的位线结构制造方法的功效，申请人进行了大量试验 及模拟运算工作，其试验及运算结果能够毫无疑义地证明本公开相关功效的存在。以下将结合本公开的两个具体实施例与现有工艺的对比，对本公开的相关功效进行说明。
参阅下附表1，对本公开与现有工艺的对比，是以“是否进行预清洗”、“以磷酸为例的蚀刻液浓度”、“以磷酸为例的蚀刻液温度”、“以氮气等离子体处理为例的钝化处理”为工艺条件，并以通过各工艺得到的半导体位线结构的牺牲层与阻挡层(本公开为第一阻挡层)的“蚀刻选择比”为比对结果。在此基础上，现有工艺：未采用对阻挡层进行氮气等离子体处理的工艺，磷酸浓度为较高的75％～88％，磷酸温度为较高的150℃～165℃，且未采用对牺牲层进行预清洗的工艺，据此得到的牺牲层与阻挡层的蚀刻选择比约为5:1。本公开的实施例一：采用对第一阻挡层进行氮气等离子体处理的工艺，磷酸浓度和磷酸温度与现有工艺相同，且同样未采用对牺牲层进行预清洗的工艺，据此得到的牺牲层与阻挡层的蚀刻选择比约为16:1。本公开的实施例二：采用对第一阻挡层进行氮气等离子体处理的工艺，磷酸浓度为较低的40％～60％，磷酸温度为较低的100℃～120℃，且采用超纯水清洗对牺牲层进行预清洗，例如H 2O：HF(49％)＝200:1，时间10s，据此得到的牺牲层与阻挡层的蚀刻选择比约为32:1。因此，可以明确得知，本公开提出的位线结构制造方法所制备的半导体位线结构，确实能够增大牺牲层与第一阻挡层的蚀刻选择比，从而确实能够在第一阻挡层厚度较小时，保证蚀刻液清洗去除牺牲层不会损伤第一阻挡层内的导电层。
  现有工艺 本公开实施例一 本公开实施例二
预清洗 否 否 DHF 200:1；10s
磷酸浓度 75％～88％ 75％～88％ 40％～60％
磷酸温度 150℃～165℃ 150℃～165℃ 100℃～120℃
N 2等离子体处理 否 是 是
蚀刻选择比 5:1 16:1 32:1
表1现有工艺与本公开实施例的蚀刻选择比对照表
在此应注意，附图中示出而且在本说明书中描述的位线结构制造方法仅仅是能够采用本公开原理的许多种制造方法中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的位线结构制造方法的任何细节或任何步骤。
基于上述对本公开提出的位线结构制造方法的一示例性实施方式的详细说明，以下将 对本公开提出的半导体结构制造方法的一示例性实施方式进行说明。
在本实施方式中，本公开提出的半导体结构制造方法包含以下步骤：
提供半导体衬底，半导体衬底的表面具有凹槽；
利用本公开提出的并在上述实施方式中所述的位线结构制造方法，在半导体衬底上形成位线结构。
需说明的是，本公开提出的位线结构制造方法，在各自符合其发明构思的实施方式中，可以在形成位线结构之前和之后，采用各种可能的工艺步骤，进而形成各种半导体结构所需的功能结构或者工艺结构，均不以本实施方式为限。
举例而言，在经由本公开提出的半导体结构制造方法的上述步骤形成位线结构之后，可以去除第一阻挡层，然后依次形成第二阻挡层和第二保护层等功能结构。并且，在形成上述各功能结构的步骤中，仍然可以通过沉积(Dep)和刻蚀(Etch)等工艺实现，且进行上述工艺的过程中，仍然可以通过氧化硅和氮化硅等工艺层状结构实现图案化等工艺，均不以本实施方式为限。通过去除第一阻挡层后再次形成第二阻挡层和第二保护层，能够避免去除牺牲层时在第一阻挡层形成的表面损伤带来对半导体结构的不良影响。
在此应注意，附图中示出而且在本说明书中描述的半导体结构制造方法仅仅是能够采用本公开原理的许多种制造方法中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构制造方法的任何细节或任何步骤。
基于上述对本公开提出的位线结构制造方法和半导体结构制造方法的一示例性实施方式的详细说明，以下将配合参阅图8，对本公开提出的半导体结构的一示例性实施方式进行说明。
在本实施方式中，本公开提出的半导体结构是经由本公开提出的并在上述实施方式中所述的半导体结构制造方法制备而成。
如图8所示，本公开提出的半导体结构包含半导体衬底210、位线导电层220、位线插塞间隔层260。其中，半导体衬底210的表面具有凹槽211。位线导电层220部分位于半导体衬底表面的凹槽211内。位线插塞间隔层260填充于凹槽内，位线插塞间隔层包含第一保护层230、经由钝化处理后的第一阻挡层240以及填充部251。
较佳地，在本实施方式中，第一保护层230的厚度可以优选为1nm～3nm。
较佳地，在本实施方式中，第一阻挡层240的厚度可以优选为2nm～8nm。
较佳地，在本实施方式中，第一保护层230的材质可以优选地包含氮化硅。
较佳地，在本实施方式中，第一阻挡层240的材质可以优选地包含氧化硅。
较佳地，在本实施方式中，填充部251的材质可以优选地包含氮化硅。
较佳地，在本实施方式中，经由钝化处理后的第一阻挡层240包含两层薄膜结构，分别为邻接第一保护层230的第一薄膜层241和远离第一保护层230的第二薄膜层242；其中，填充部251与第二薄膜层242的蚀刻选择比大于填充部251与第一薄膜层241的蚀刻选择比。
较佳地，在本实施方式中，第一薄膜层241的材质包含氧化硅，第二薄膜层242的材质包含氮氧化硅。
在此应注意，附图中示出而且在本说明书中描述的半导体结构仅仅是能够采用本公开原理的许多种半导体结构中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构的任何细节或任何部件。
综上所述，本公开通过对第一阻挡层进行钝化处理，使得蚀刻液对牺牲层与对第一阻挡层蚀刻选择比增大，从而在利用蚀刻液清洗去除牺牲层时，不会损伤第一阻挡层内的导电层。并且，在实现上述功效的基础上，相比于现有工艺，本公开无需在蚀刻液中加入活性剂，因此本公开的清洗工艺的较为简单，也不会影响产品良率。另外，本公开无需增大第一阻挡层的厚度，能够进一步满足半导体产品关键尺寸的微细化、薄型化的设计要求。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (20)

  1. 一种位线结构制造方法，其特征在于，包含以下步骤：
    在半导体衬底的表面形成位线导电层，所述位线导电层部分位于所述半导体衬底表面的凹槽内；
    在所述位线导电层和所述半导体衬底的表面形成第一保护层；
    在所述第一保护层的表面形成第一阻挡层；
    对所述第一阻挡层的表面进行钝化处理；
    在所述第一阻挡层的表面形成牺牲层，所述牺牲层具有填充于所述凹槽内的填充部；以及
    利用蚀刻液清洗去除所述牺牲层的除所述填充部以外的部分。
  2. 根据权利要求1所述的位线结构制造方法，其特征在于，所述钝化处理包含等离子体处理、离子注入或者热氧化处理。
  3. 根据权利要求1所述的位线结构制造方法，其特征在于，经由钝化处理后的所述第一阻挡层包含两层薄膜结构，分别为邻接所述第一保护层的第一薄膜层和远离所述第一保护层的第二薄膜层；其中，所述牺牲层与所述第二薄膜层的蚀刻选择比大于所述牺牲层与所述第一薄膜层的蚀刻选择比。
  4. 根据权利要求3所述的位线结构制造方法，其特征在于，所述第一阻挡层的材质包含氧化硅；其中，所述钝化处理包含氮气等离子体处理，所述第二薄膜层的材质包含氮氧化硅。
  5. 根据权利要求1所述的位线结构制造方法，其特征在于，所述第一保护层的厚度为1nm～3nm，所述第一阻挡层的厚度为2nm～8nm。
  6. 根据权利要求1所述的位线结构制造方法，其特征在于，所述第一保护层的材质包含氮化硅，所述第一阻挡层的材质包含氧化硅，所述牺牲层的材质包含氮化硅。
  7. 根据权利要求1所述的位线结构制造方法，其特征在于，所述蚀刻液包含磷酸溶液；其中，所述蚀刻液的温度为100℃～120℃。
  8. 根据权利要求1所述的位线结构制造方法，其特征在于，所述蚀刻液包含磷酸溶液；其中，所述蚀刻液的浓度为40％～60％。
  9. 根据权利要求1所述的位线结构制造方法，其特征在于，利用所述蚀刻液清洗去除所述牺牲层的除所述填充部以外的部分之后，还包含以下步骤：
    去除暴露的所述第一阻挡层；
    在所述位线导电层和所述半导体衬底的表面形成第二阻挡层；
    在所述第二阻挡层的表面形成第二保护层。
  10. 根据权利要求1所述的位线结构制造方法，其特征在于，利用所述蚀刻液清洗去除所述牺牲层时，包含以下步骤：
    利用稀释过的氢氟酸溶液对所述牺牲层的表面进行预清洗，去除所述牺牲层表面的氧化层；以及
    利用磷酸溶液清洗所述牺牲层，去除所述牺牲层的除所述填充部以外的部分。
  11. 一种半导体结构制造方法，其特征在于，包含以下步骤：
    提供半导体衬底，所述半导体衬底的表面具有凹槽；以及
    利用权利要求1～10任一项所述的位线结构制造方法，在所述半导体衬底上形成位线结构。
  12. 根据权利要求11所述的半导体结构制造方法，其特征在于，所述钝化处理包含等离子体处理；其中，对所述第一阻挡层进行钝化处理时，包含以下步骤：
    对处理设备的处理腔室进行预热；
    将形成有所述第一阻挡层的半导体结构放入处理腔室；
    输入反应介质并对所述第一阻挡层的表面进行等离子体处理；
    对处理腔室进行冷却；以及
    取出半导体结构。
  13. 一种半导体结构，其特征在于，包含：
    半导体衬底，所述半导体衬底的表面具有凹槽；
    位线导电层，位线导电层部分位于所述半导体衬底表面的凹槽内；
    位线插塞间隔层，所述位线插塞间隔层填充于所述凹槽内，所述位线插塞间隔层包含第一保护层、经由钝化处理后的第一阻挡层以及填充部。
  14. 根据权利要求13所述的半导体结构，其特征在于，所述第一保护层的厚度为1nm～3nm。
  15. 根据权利要求13所述的半导体结构，其特征在于，所述第一阻挡层的厚度为2nm～8nm。
  16. 根据权利要求13所述的半导体结构，其特征在于，所述第一保护层的材质包含氮化硅。
  17. 根据权利要求13所述的半导体结构，其特征在于，所述第一阻挡层的材质包含氧化硅。
  18. 根据权利要求13所述的半导体结构，其特征在于，所述填充部的材质包含氮化硅。
  19. 根据权利要求13所述的半导体结构，其特征在于，经由钝化处理后的所述第一阻挡层包含两层薄膜结构，分别为邻接所述第一保护层的第一薄膜层和远离所述第一保护层的第二薄膜层；其中，所述填充部与所述第二薄膜层的蚀刻选择比大于所述填充部与所述第一薄膜层的蚀刻选择比。
  20. 根据权利要求19所述的半导体结构，其特征在于，所述第一薄膜层的材质包含氧化硅，所述第二薄膜层的材质包含氮氧化硅。
PCT/CN2021/100459 2020-08-13 2021-06-16 位线结构制造方法、半导体结构制造方法及半导体结构 WO2022033165A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP21855220.6A EP4027377A4 (en) 2020-08-13 2021-06-16 BITLINE STRUCTURE MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD, AND SEMICONDUCTOR STRUCTURE
KR1020227021263A KR102710233B1 (ko) 2020-08-13 2021-06-16 비트 라인 구조 제조 방법, 반도체 구조 제조 방법 및 반도체 구조
JP2022539177A JP2023509403A (ja) 2020-08-13 2021-06-16 ビット線構造の製造方法、半導体構造の製造方法及び半導体構造
US17/446,445 US11985814B2 (en) 2020-08-13 2021-08-30 Method for manufacturing bit line structure, method for manufacturing semiconductor structure, and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010811435.X 2020-08-13
CN202010811435.XA CN114078775A (zh) 2020-08-13 2020-08-13 位线结构制造方法、半导体结构制造方法及半导体结构

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/446,445 Continuation US11985814B2 (en) 2020-08-13 2021-08-30 Method for manufacturing bit line structure, method for manufacturing semiconductor structure, and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2022033165A1 true WO2022033165A1 (zh) 2022-02-17

Family

ID=80246905

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/100459 WO2022033165A1 (zh) 2020-08-13 2021-06-16 位线结构制造方法、半导体结构制造方法及半导体结构

Country Status (2)

Country Link
CN (1) CN114078775A (zh)
WO (1) WO2022033165A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633080A (zh) * 2014-11-26 2016-06-01 台湾积体电路制造股份有限公司 栅极间隔件和形成方法
US20180342520A1 (en) * 2017-05-26 2018-11-29 SK Hynix Inc. Semiconductor device and method for fabricating the same
CN109003938A (zh) * 2018-07-26 2018-12-14 长鑫存储技术有限公司 半导体接触结构、存储器结构及其制备方法
CN110491876A (zh) * 2019-08-23 2019-11-22 福建省晋华集成电路有限公司 半导体存储元件的制造方法及该元件
CN111326517A (zh) * 2018-12-14 2020-06-23 三星电子株式会社 包括间隔物的半导体器件和制造该半导体器件的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633080A (zh) * 2014-11-26 2016-06-01 台湾积体电路制造股份有限公司 栅极间隔件和形成方法
US20180342520A1 (en) * 2017-05-26 2018-11-29 SK Hynix Inc. Semiconductor device and method for fabricating the same
CN109003938A (zh) * 2018-07-26 2018-12-14 长鑫存储技术有限公司 半导体接触结构、存储器结构及其制备方法
CN111326517A (zh) * 2018-12-14 2020-06-23 三星电子株式会社 包括间隔物的半导体器件和制造该半导体器件的方法
CN110491876A (zh) * 2019-08-23 2019-11-22 福建省晋华集成电路有限公司 半导体存储元件的制造方法及该元件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4027377A4

Also Published As

Publication number Publication date
CN114078775A (zh) 2022-02-22

Similar Documents

Publication Publication Date Title
JP4677177B2 (ja) 半導体素子の製造方法
KR100459724B1 (ko) 저온 원자층증착에 의한 질화막을 식각저지층으로이용하는 반도체 소자 및 그 제조방법
JP4282616B2 (ja) 半導体装置の製造方法
KR100506816B1 (ko) 반도체 장치 커패시터의 하부 전극 및 이를 형성하기 위한방법
US20040115909A1 (en) Cleaning solution and method of cleaning a semiconductor device using the same
TW461025B (en) Method for rounding corner of shallow trench isolation
JP3544622B2 (ja) 二重酸化膜の形成方法
WO2022033165A1 (zh) 位线结构制造方法、半导体结构制造方法及半导体结构
KR100732591B1 (ko) 반도체 장치의 제조 방법
US11985814B2 (en) Method for manufacturing bit line structure, method for manufacturing semiconductor structure, and semiconductor structure
US20080003792A1 (en) Method for forming a gate of a semiconductor device
KR100771535B1 (ko) 금속오염 억제를 위한 반도체웨이퍼의 린스방법
RU2802797C1 (ru) Способ изготовления структуры разрядной шины, способ изготовления полупроводниковой структуры и полупроводниковая структура
JP2004349531A (ja) 半導体装置の製造方法
KR100641916B1 (ko) 반도체소자의 저장전극 형성방법
TWI833380B (zh) 形成半導體結構之方法
KR20060104398A (ko) 반도체 소자의 제조 방법
TW202431945A (zh) 形成半導體結構之方法
KR20050068363A (ko) 하드 마스크를 이용한 미세 패턴 형성 방법
KR100527563B1 (ko) 반도체소자의 캐패시터 형성방법
KR100914290B1 (ko) 반도체 소자의 캐패시터 형성방법
KR20060134323A (ko) 낮은 컨택저항을 갖는 반도체소자의 텅스텐-금속 컨택형성방법
KR20020076563A (ko) 반도체 웨이퍼의 세정 방법
KR20040098488A (ko) 반도체소자의 캐패시터 제조방법
KR20010058648A (ko) 반도체 소자의 게이트 전극 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21855220

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021855220

Country of ref document: EP

Effective date: 20220404

ENP Entry into the national phase

Ref document number: 20227021263

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2022539177

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2022117155

Country of ref document: RU

NENP Non-entry into the national phase

Ref country code: DE