WO2022033147A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022033147A1
WO2022033147A1 PCT/CN2021/098929 CN2021098929W WO2022033147A1 WO 2022033147 A1 WO2022033147 A1 WO 2022033147A1 CN 2021098929 W CN2021098929 W CN 2021098929W WO 2022033147 A1 WO2022033147 A1 WO 2022033147A1
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layer
conductive layer
forming
support
capacitor
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English (en)
French (fr)
Inventor
王凌翔
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/411,108 priority Critical patent/US12356637B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • the size of the formed capacitor is also shrinking. It is necessary to form a capacitor with a high aspect ratio to ensure the capacitance of the capacitor.
  • the main method is to form a double-sided capacitor. In order to improve the capacitance of the capacitor, in the process of forming a double-sided capacitor with a high aspect ratio, it is necessary to etch a capacitor hole with a high aspect ratio to form a hollow capacitor column.
  • the inner layer capacitance of the capacitor is electrically unstable, which affects the yield of the semiconductor structure.
  • Embodiments of the present application provide a method for forming a semiconductor structure and a semiconductor structure.
  • a stable support structure to form a stable columnar capacitor
  • the aspect ratio of the formed capacitor structure is improved, and the formed capacitor structure is stable and not easy to collapse, thereby improving the Yield of semiconductor structures.
  • embodiments of the present application provide a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate at least including discrete conductive layers; forming discretely arranged support structures on the semiconductor substrate, the support structures
  • the bottom includes a bottom conductive layer, and a capacitor opening is included between the supporting structures, and the bottom conductive layer is electrically connected to the conductive layer; a lower electrode is formed on the sidewall of the supporting structure, and the lower electrode is electrically connected to the bottom conductive layer; the top and the lower electrode side of the supporting structure are formed to cover The wall and the capacitor dielectric layer at the bottom of the capacitor opening; the upper electrode covering the capacitor dielectric layer is formed to form a capacitor structure.
  • a stable support structure is first formed on the semiconductor substrate, and a columnar capacitor structure is formed based on the stable support structure;
  • the height of the capacitor is greatly improved, that is, the columnar capacitor has a larger aspect ratio; and in the process of forming the columnar capacitor, there is no need to etch to form a capacitor hole with a high aspect ratio, and the process steps are more Simple and cost-effective; because there is no need to etch to form capacitor holes with high aspect ratio, the stability of the formed capacitor structure is also ensured; in addition, compared with double-sided capacitors, columnar capacitors avoid the existence of inner-layer capacitors in double-sided capacitors Typically unstable conditions, thereby increasing the yield of semiconductor structures.
  • the step of forming discretely arranged supporting structures on the semiconductor substrate includes: forming a bottom conductive layer on the semiconductor substrate; forming a supporting layer on the bottom conductive layer; patterning the supporting layer and the bottom conductive layer to form capacitor openings, and the remaining supporting layers
  • the layers and the bottom conductive layer constitute the support structure.
  • the steps of forming a bottom conductive layer on the semiconductor substrate and forming a support layer on the bottom conductive layer include: forming a bottom conductive film on the semiconductor substrate; patterning the bottom conductive film, forming a through hole penetrating the bottom conductive film, and the remaining bottom conductive film
  • the membrane acts as the bottom conductive layer; a support layer is formed on the bottom conductive layer, and the support layer also fills the vias.
  • the step of forming a plurality of discrete capacitor openings by patterning the support layer includes: sequentially forming a mask layer and a patterned photoresist layer on the support layer; patterning the mask layer based on the photoresist layer; After the mask layer, the support layer and the bottom conductive layer are etched to form capacitor openings.
  • the capacitor openings expose at least a portion of the top surface of each discrete conductive layer.
  • the support layer is stacked in sequence to form a bottom support layer and a filling layer.
  • the step of forming the discretely arranged support structure on the semiconductor base includes: forming a discretely arranged initial support structure on the semiconductor base, the initial support structure including a bottom support layer and a filling layer formed by stacking in sequence; laterally etching the partial width A bottom support layer is formed to form a conductive opening; a bottom conductive layer that fills the conductive opening is formed, and the bottom conductive layer and the remaining initial support structure form a support structure.
  • the width of the formed conductive opening is less than or equal to one third of the width of the bottom conductive layer.
  • the step of forming the bottom conductive layer filling the conductive openings includes: forming a bottom conductive film filling the conductive openings and part of the height capacitor openings, the height of the top surface of the bottom conductive film is higher than the height of the top surface of the bottom support layer; The exposed bottom conductive film is opened to form a bottom conductive layer.
  • the step of forming a lower electrode electrically connected to a conductive layer on the sidewall of the support structure includes: forming a top conductive layer on the top and sidewalls of the support structure and the bottom of the capacitor opening; removing the top conductive layer on the top of the support structure and the bottom of the capacitor opening , forming a lower electrode on the sidewall of the support structure.
  • the manner of removing the top conductive layer on top of the support structure includes chemical mechanical polishing.
  • the step of forming the upper electrode covering the capacitor dielectric layer includes: forming a first conductive layer covering the capacitor dielectric layer; forming a second conductive layer filling the gap between the first conductive layers, the top surface of the second conductive layer being on the support structure
  • the top surface of the first conductive layer on the top surface is parallel, and the height of the top surface of the second conductive layer is higher than the height of the top surface of the first conductive layer on the support structure.
  • forming the second conductive layer filling the gap between the first conductive layers includes the steps of: forming a second conductive film filling the gap between the first conductive layers, the top surface of the second conductive film having a height higher than that on the support structure height of the top surface of the first conductive layer; chemical mechanical polishing is performed on the top surface of the second conductive film to form the second conductive layer.
  • An embodiment of the present application further provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate at least includes a discrete conductive layer; a plurality of discrete support structures located on the semiconductor substrate, the bottom of the support structure at least includes a bottom conductive layer, the bottom conductive layer and a capacitor structure supported by the support structure, the capacitor structure includes: a lower electrode, located on the sidewall of the support structure, and electrically connected to the bottom conductive layer; a capacitor dielectric layer, located on the top of the support structure, the sidewall of the lower electrode and the bottom conductive layer; The bottom of the gap between the support structures; the upper electrode, on the capacitive dielectric layer.
  • the gaps between the support structures expose at least a portion of the top surface of each discrete conductive layer.
  • the lower electrode and the bottom conductive layer have an integral structure.
  • the lower electrode and the bottom conductive layer are integrally formed to further reduce the contact resistance of the lower electrode.
  • the width of the bottom conductive layer is less than or equal to one third of the width of the bottom conductive layer.
  • the capacitance structure of columnar capacitors is formed based on a stable support structure; due to the stable support structure, the height of columnar capacitors is greatly improved compared with double-sided capacitors, that is, columnar capacitors have more Large aspect ratio; and the process steps for forming columnar capacitors are simpler and cost-effective; since there is no need to etch to form capacitor holes with high aspect ratio, the stability of the capacitor structure of the columnar capacitors formed is also guaranteed; in addition, the columnar capacitors Compared with the double-sided capacitor, the typical instability of the inner-layer capacitance of the double-sided capacitor is avoided, thereby improving the yield of the semiconductor structure.
  • 1 to 18 are schematic cross-sectional structural diagrams of a semiconductor structure corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application;
  • 19 to 30 are schematic cross-sectional structural diagrams of the semiconductor structure corresponding to each step of the method for forming a semiconductor structure according to another embodiment of the present application.
  • the capacitor structure is unstable, and the phenomenon of collapse easily occurs.
  • the layer capacitance is electrically unstable, which affects the yield of the semiconductor structure.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, where the semiconductor substrate at least includes discrete conductive layers; forming discretely arranged support structures on the semiconductor substrate, the support structures A capacitor opening is included between; a lower electrode is formed on the sidewall of the support structure, and the lower electrode is electrically connected to the conductive layer; a capacitor dielectric layer covering the top of the support structure, the sidewall of the lower electrode and the bottom of the capacitor opening is formed; an upper electrode covering the capacitor dielectric layer is formed , to form a capacitor structure.
  • FIG. 18 are schematic flowcharts corresponding to each step of the method for forming a semiconductor structure provided in this embodiment, and the method for forming a semiconductor structure in this embodiment will be specifically described below. It should be noted that this embodiment takes a semiconductor structure in a memory as an example for specific description, that is, the semiconductor structure to be protected in this embodiment is formed in a DRAM memory or an SRAM memory.
  • a semiconductor substrate 100 is provided, and discretely arranged support structures 203 are formed on the semiconductor substrate 100 .
  • the bottom of the support structure 203 includes a bottom conductive layer 201 , and between the support structures 203 includes a capacitor opening 103 , and the bottom conductive layer 201
  • the conductive layer 110 is electrically connected.
  • a semiconductor substrate 100 includes at least discrete conductive layers 110 therein.
  • the discrete conductive layers 110 are arranged in the semiconductor substrate 100 as shown in FIG. 2 .
  • the conductive layers 110 are the capacitive contact pads (landing pads) in the DRAM structure, and the conductive layers 110 are arranged in a hexagonal manner for electrically connecting the DRAM array transistor.
  • an initial support layer 101 is formed on the semiconductor substrate 100 , and the initial support layer 101 is used for subsequent etching to form the initial support structure 102 .
  • the initial support layer 101 includes a bottom support layer 111 and a filling layer 121 which are sequentially stacked and formed.
  • the process of stacking the formed initial support layers 101 in sequence avoids the formation of a thick initial support layer 101 by a single deposition, and ensures better compactness of the formed initial support layers 101.
  • the initial support layers 101 are formed by sequentially stacking, This ensures that the initial support structure 102 formed subsequently has a higher height, thereby increasing the aspect ratio of the column capacitor formed subsequently.
  • the bottom support layer 111 and the filling layer 121 are formed of different insulating materials.
  • the initial support layer may also be implemented by a stack structure of three or more layers, and the height of the stack structure formed in this way is higher, that is, the subsequently formed support structure has a higher height the height of.
  • the initial support layer 101 is patterned to form capacitor openings 103 , and the remaining initial support layer 101 constitutes the initial support structure 102 .
  • a mask layer 120 and a patterned photoresist layer 130 are sequentially formed on the initial support layer 101 .
  • the mask layer 120 is patterned based on the photoresist layer 130 .
  • the initial support layer 101 is etched to form the capacitor opening 103 .
  • the capacitor opening 103 exposes at least a portion of the top surface of each discrete conductive layer 110 .
  • the top morphology distribution of the capacitor opening 103 and the conductive layer 110 is shown in FIG. 6 , and the remaining initial support layer 101 after the capacitor opening 103 is etched is used as the initial support structure 102 , that is, in this embodiment, the initial support structures 102 are stacked in sequence
  • the formed bottom support layer 111 fills the layer 121 .
  • the method further includes: sequentially removing the photoresist layer 130 and the mask layer 120 .
  • the photoresist layer 130 is removed by a first dry cleaning process.
  • the first dry cleaning process uses a mixed gas of ammonia, nitrogen and hydrogen, and the mixed gas reacts with the photoresist layer 130 to form a first cured product , and then the first cured product is evaporated by means of high temperature evaporation, that is, the removal of the photoresist layer 130 is completed.
  • the mixed gas does not contain oxygen and prevents the initial support structure 102 is in contact with air to prevent natural oxidation of the sidewalls of the initial support structure 102 while removing the photoresist layer 130 .
  • a portion of the width of the bottom support layer 111 is laterally etched to form conductive openings 200 .
  • a partial width of the bottom support layer 111 is selectively laterally etched. Specifically, a material having an etching selectivity ratio is used, so that the etching rate of the bottom support layer 111 is higher than that of the filling layer 121 .
  • the width of the conductive opening 200 is less than or equal to one third of the width of the bottom conductive layer 201 . It is ensured that the remaining bottom support layer 111 can still support the initial support structure 102 to prevent the initial support structure 102 from collapsing.
  • the initial support structure 102 is cylindrical, that is, the bottom conductive layer 201 formed is a ring-shaped structure at the bottom of the initial support structure 102 .
  • This embodiment does not limit the topography of the bottom conductive layer. In other embodiments, the topography of the bottom conductive layer is related to the initial support structure.
  • a bottom conductive layer 201 filling the conductive opening 200 is formed, and the bottom conductive layer 201 and the remaining initial support structure 102 form a support structure 203 .
  • the bottom conductive layer 201 is formed by etching back, and the bottom electrode 104 electrically connected to the bottom conductive layer 201 is subsequently formed to increase the contact area between the bottom electrode 104 and the conductive layer 110 , thereby reducing the distance between the bottom electrode 104 and the conductive layer 110 contact resistance between.
  • the bottom conductive layer 201 can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the bottom conductive layer 201 is made of nitride. Titanium material.
  • a bottom conductive film (not shown) filling the conductive opening 200 and part of the height capacitor opening 103 is formed, and the height of the top surface of the bottom conductive film (not shown) is higher than the height of the top surface of the bottom support layer 111 . Then, the bottom conductive film (not shown) exposed at the capacitor opening 103 is removed by etching to form a bottom conductive layer 201 .
  • the capacitor opening 103 formed by etching the initial support layer 101 based on the patterned mask layer 120 the capacitor opening 103 does not expose the conductive layer 110 . top surface.
  • the top morphology distribution of the capacitor opening 103 and the conductive layer 110 is shown in FIG. 13 .
  • the capacitor structure 107 is formed based on the support structure 203 .
  • a lower electrode 104 is formed on the sidewall of the support structure 203 , and the lower electrode 104 is electrically connected to the bottom conductive layer 201 and the conductive layer 110 .
  • the lower electrode 104 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc. In this embodiment, the lower electrode 104 is made of titanium nitride material .
  • a top conductive layer 114 is formed on the top and sidewalls of the support structure 203 and the bottom of the capacitor opening 103 .
  • the top conductive layer 114 is formed by an atomic layer deposition process or a chemical vapor deposition method.
  • the top conductive layer 114 is formed by an atomic layer deposition process
  • the top conductive layer 114 is formed by an atomic layer deposition process. It has good coverage; in other embodiments, for example, the top conductive layer can be formed by chemical vapor deposition at 500°C or 600°C.
  • the above description of the specific temperature parameters using chemical vapor deposition is only to facilitate the understanding of those skilled in the art, and does not constitute a limitation to this solution. In practical applications, as long as the parameters within the above range are within within the scope of protection of this application.
  • the top conductive layer 114 at the top of the support structure 203 and the bottom of the capacitor opening 103 is formed on the lower electrode 104 on the sidewall of the support structure 203 .
  • the manner of removing the top conductive layer 114 on top of the support structure 203 includes chemical mechanical polishing.
  • the top conductive layer 114 of the support structure is removed by chemical mechanical polishing, the process is simple and the cost is low, and the manufacturing efficiency of the capacitor structure can be effectively improved.
  • the top conductive layer may also be planarized by etching.
  • the bottom conductive layer 201 and the lower electrode 104 are formed in steps, that is, the bottom conductive layer 201 is formed first, and then the bottom electrode 104 is formed.
  • the bottom conductive layer 201 and the bottom electrode 104 can be formed in a one-step forming process. At this time, the bottom electrode 104 and the bottom conductive layer 201 are formed as a single structure, which can further reduce the difference between the bottom electrode 104 and the bottom conductive layer 201. contact resistance between.
  • a capacitor dielectric layer 105 covering the top of the support structure 203 , the sidewalls of the lower electrode 104 and the bottom of the capacitor opening 103 is formed.
  • the capacitor dielectric layer 105 is made of high dielectric constant materials, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used. Specifically, the capacitor dielectric layer 105 is formed by the atomic layer deposition process or the chemical vapor deposition method. In this embodiment, the capacitor dielectric layer 105 is formed by the atomic layer deposition process, and the capacitor dielectric layer 105 is formed by the atomic layer deposition process It has good coverage; in other embodiments, for example, the capacitor dielectric layer can be formed by chemical vapor deposition at 500°C or 600°C.
  • the upper electrode covering the capacitor dielectric layer 105 is formed, and the lower electrode 104 , the capacitor dielectric layer 105 and the upper electrode together constitute the capacitor structure 107 .
  • the step of forming the upper electrode covering the capacitor dielectric layer includes:
  • a first conductive layer 106 covering the capacitive dielectric layer 105 is formed.
  • the first conductive layer 106 may be made of a single conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the first conductive layer 106 is made of Titanium nitride material.
  • the first conductive layer 106 is formed by an atomic layer deposition process or a chemical vapor deposition method.
  • the first conductive layer 106 is formed by an atomic layer deposition process
  • the first conductive layer 106 is formed by an atomic layer deposition process.
  • the conductive layer 106 has good coverage; in other embodiments, for example, the first conductive layer 106 may be formed by chemical vapor deposition at 500°C or 600°C. It should be noted that the above description of the specific temperature parameters using chemical vapor deposition is only to facilitate the understanding of those skilled in the art, and does not constitute a limitation to this solution. In practical applications, as long as the parameters within the above range are within within the scope of protection of this application.
  • a second conductive layer 108 filling the gap between the first conductive layers 106 is formed.
  • the top surface of the second conductive layer 108 is parallel to the top surface of the first conductive layer 106 on the support structure 203 , and the height of the top surface of the second conductive layer 108 is higher than the top surface of the first conductive layer 106 on the support structure 203 the height of the surface.
  • a second conductive film (not shown) is formed to fill the gap between the first conductive layers 106, and the height of the top surface of the second conductive film is higher than that of the top surface of the first conductive layer 106; for the second conductive film ( Not shown) chemical mechanical polishing is performed on the top surface to form the second conductive layer 108 .
  • the chemical mechanical polishing method is used to form the second conductive layer 108 , the process is simple and the cost is low, and the manufacturing efficiency of the semiconductor structure can be effectively improved. It should be noted that, in other embodiments, the second conductive layer may also be formed by etching the second conductive film. By filling the voids between the first conductive layers 106, the discrete capacitive structures 107 have been integrated into one body.
  • a stable support structure is first formed on the semiconductor substrate, and a columnar capacitor structure is formed based on the stable support structure;
  • the height of the capacitor is greatly improved, that is, the columnar capacitor has a larger aspect ratio; and in the process of forming the columnar capacitor, there is no need to etch to form a capacitor hole with a high aspect ratio, and the process steps are more Simple and cost-effective; because there is no need to etch to form capacitor holes with high aspect ratio, the stability of the formed capacitor structure is also ensured; in addition, compared with double-sided capacitors, columnar capacitors avoid the existence of inner-layer capacitors in double-sided capacitors Typically unstable conditions, thereby increasing the yield of semiconductor structures.
  • Another embodiment of the present application relates to a method for forming a semiconductor structure. Different from the above embodiments, this embodiment provides another method for forming a bottom conductive layer.
  • FIG. 30 are schematic flowcharts corresponding to each step of the method for forming a semiconductor structure provided in this embodiment, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • discretely arranged support structures 302 are formed on a semiconductor substrate 300 .
  • a bottom conductive layer 401 is formed on the semiconductor substrate 300
  • a bottom conductive film 400 is formed on the semiconductor substrate 300.
  • the bottom conductive film 400 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and tungsten.
  • the bottom conductive film 400 is made of titanium nitride material.
  • the bottom conductive film 400 is patterned to form through holes 410 through the bottom conductive film 400 .
  • the bottom conductive film 400 remains as the bottom conductive layer 401 .
  • a support layer 301 is formed on the bottom conductive layer 401 , and the support layer 301 also fills the through holes 410 .
  • the support layer 301 is a bottom support layer 311 and a filling layer 321 formed by stacking in sequence. Through the process of stacking the supporting layers 301 formed in sequence, the formation of a supporting layer 301 with a larger thickness by a single deposition is avoided, and the denseness of the supporting layer 301 formed is ensured.
  • the support structure 302 has a higher height, thereby increasing the aspect ratio of the column capacitors formed subsequently.
  • the bottom support layer 111 and the filling layer are formed of different insulating materials. It should be noted that, in other embodiments, the support layer may also be implemented by a stack structure of three or more layers, and the height of the stack structure formed in this way is higher, that is, the support structure formed subsequently has a higher height high.
  • the patterned support layer 301 forms a plurality of discrete capacitor openings 303 , and the remaining support layer 301 serves as the support layer 302 .
  • a mask layer (not shown) and a patterned photoresist (not shown) are sequentially formed on the support layer 301, based on the photoresist layer, a patterned mask layer (not shown), based on the pattern
  • the support layer 301 and the bottom conductive layer 401 can form the capacitor opening 303 , and the remaining support layer 301 and the bottom conductive layer 401 are used as the support layer 302 .
  • the capacitor opening 303 exposes at least part of the top surface of each discrete conductive layer 310 .
  • capacitor openings 303 are formed on the support layer 301 based on the patterned mask layer, and the capacitor openings 303 do not expose the top surface of the conductive layer 310 .
  • a capacitor structure 307 is formed based on the support structure 302 .
  • a lower electrode 304 is formed on the sidewall of the support structure 302 , and the lower electrode 304 is electrically connected to the bottom conductive layer 401 and the conductive layer 310 .
  • the lower electrode 304 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc. In this embodiment, the lower electrode 304 is made of titanium nitride material .
  • a top conductive layer 314 is formed on the top and sidewalls of the support structure 302 and the bottom of the capacitor opening 303 .
  • the top conductive layer 314 is formed by an atomic layer deposition process or a chemical vapor deposition method.
  • the top conductive layer 314 is formed by an atomic layer deposition process
  • the top conductive layer 314 is formed by an atomic layer deposition process. It has good coverage; in other embodiments, for example, the top conductive layer can be formed by chemical vapor deposition at 500°C or 600°C.
  • the above description of the specific temperature parameters using chemical vapor deposition is only to facilitate the understanding of those skilled in the art, and does not constitute a limitation to this solution. In practical applications, as long as the parameters within the above range are within within the scope of protection of this application.
  • the top conductive layer 314 at the top of the support structure 302 and the bottom of the capacitor opening 303 is formed on the lower electrode 304 on the sidewall of the support structure 302 .
  • the manner in which the top conductive layer 314 on top of the support structure 302 is removed includes chemical mechanical polishing.
  • the top conductive layer 314 of the support structure is removed by chemical mechanical polishing, which has a simple process and low cost, and can effectively improve the manufacturing efficiency of the capacitor structure. It should be noted that, in other embodiments, the top conductive layer may also be planarized by etching.
  • a capacitor dielectric layer 305 is formed covering the top of the support structure 302 , the sidewalls of the lower electrode 304 and the bottom of the capacitor opening 303 .
  • the capacitor dielectric layer 305 is made of high dielectric constant materials, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used. Specifically, the capacitor dielectric layer 305 is formed by an atomic layer deposition process or a chemical vapor deposition method. In this embodiment, the capacitor dielectric layer 305 is formed by an atomic layer deposition process, and the capacitor dielectric layer 305 is formed by an atomic layer deposition process It has good coverage; in other embodiments, for example, the capacitor dielectric layer can be formed by chemical vapor deposition at 500°C or 600°C.
  • an upper electrode covering the capacitor dielectric layer 305 is formed, and the lower electrode 304 , the capacitor dielectric layer 305 and the upper electrode together constitute a capacitor structure 307 .
  • the step of forming the upper electrode covering the capacitor dielectric layer includes:
  • a first conductive layer 306 covering the capacitive dielectric layer 305 is formed.
  • the first conductive layer 306 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the first conductive layer 306 is made of Titanium nitride material.
  • the first conductive layer 306 is formed by the atomic layer deposition process or the chemical vapor deposition method.
  • the first conductive layer 306 is formed by the atomic layer deposition process
  • the first conductive layer 306 is formed by the atomic layer deposition process.
  • the conductive layer 306 has good coverage; in other embodiments, for example, the first conductive layer 306 may be formed by chemical vapor deposition at 500° C. or 600° C. It should be noted that the above description of the specific temperature parameters using chemical vapor deposition is only to facilitate the understanding of those skilled in the art, and does not constitute a limitation to this solution. In practical applications, as long as the parameters within the above range are within within the scope of protection of this application.
  • a second conductive layer 308 filling the gap between the first conductive layers 306 is formed.
  • the top surface of the second conductive layer 308 is parallel to the top surface of the first conductive layer 306 on the support structure 302 , and the height of the top surface of the second conductive layer 308 is higher than the top of the first conductive layer 306 on the support structure 302 the height of the surface.
  • a second conductive film filling the gap between the first conductive layers 306 is formed, and the height of the top surface of the second conductive film is higher than that of the top surface of the first conductive layer 306; for the second conductive film ( Not shown) chemical mechanical polishing is performed on the top surface to form the second conductive layer 308 .
  • the second conductive layer 308 has a simple process and low cost, and can effectively improve the manufacturing efficiency of the semiconductor structure. It should be noted that, in other embodiments, the second conductive layer may also be formed by etching the second conductive film. By filling the voids between the first conductive layers 306, the discrete capacitive structures 307 have been integrated.
  • a stable support structure is first formed on the semiconductor substrate, and a columnar capacitor structure is formed based on the stable support structure;
  • the height of the capacitor is greatly improved, that is, the columnar capacitor has a larger aspect ratio; and in the process of forming the columnar capacitor, there is no need to etch to form a capacitor hole with a high aspect ratio, and the process steps are more Simple and cost-effective; because there is no need to etch to form capacitor holes with high aspect ratio, the stability of the formed capacitor structure is also ensured; in addition, compared with double-sided capacitors, columnar capacitors avoid the existence of inner-layer capacitors in double-sided capacitors Typically unstable conditions, thereby increasing the yield of semiconductor structures.
  • this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other structures in this embodiment.
  • FIG. 18 Yet another embodiment of the present application relates to a semiconductor structure.
  • the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, and the parts that are the same as or corresponding to the above-mentioned embodiment will not be described in detail below.
  • the semiconductor structure includes: a semiconductor substrate 100, the semiconductor substrate 100 at least includes a discrete conductive layer 110, a plurality of discrete support structures 203 located on the semiconductor substrate 100, the bottom of the support structure 203 includes a bottom conductive layer 201, and the bottom conductive layer 201 is electrically connected
  • the discrete conductive layers 110 are arranged in the semiconductor substrate 100 as shown in FIG. 2 .
  • the conductive layers 110 are the capacitive contact pads (landing pads) in the DRAM structure, and the conductive layers 110 are arranged in a hexagonal manner for electrically connecting the DRAM array transistor.
  • the support structure 203 provided in this embodiment may be implemented by a stack structure, and the height of the support structure 203 formed by the stack structure is higher, that is, the capacitor structure 107 formed subsequently has a higher aspect ratio.
  • the gap between the support structures 203 exposes at least a portion of the top surface of each discrete conductive layer 110 ; the lower electrode 104 is used to connect the exposed top surface of the discrete conductive layer 110 .
  • the lower electrode 104 and the bottom conductive layer 201 are integrally formed, and the lower electrode and the bottom conductive layer are integrally formed, thereby further reducing the contact resistance of the lower electrode.
  • the width of the conductive opening 200 is less than or equal to one third of the width of the bottom conductive layer 201 . It is ensured that the remaining bottom support layer 111 can still support the initial support structure 102 to prevent the initial support structure 102 from collapsing.
  • the capacitor structure 107 includes: a lower electrode 104 located on the sidewall of the support structure 102 and electrically connected to the conductive layer 110; a capacitor dielectric layer 105 located at the top of the support structure 102, the sidewall of the lower electrode 104 and the bottom of the gap between the support structure 102; The upper electrode is located on the capacitor dielectric layer 105 .
  • the lower electrode 104 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc. In this embodiment, the lower electrode 104 is made of titanium nitride material .
  • the capacitor dielectric layer 105 is made of high dielectric constant materials, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used.
  • the upper electrode includes a first conductive layer 106 and a second conductive layer 108 .
  • the first conductive layer 106 covers the capacitor dielectric layer 105, and the first conductive layer 106 can be made of a conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the first conductive layer 106 is made of titanium nitride material.
  • the second conductive layer 108 fills the gap between the first conductive layers 106, wherein the top surface of the second conductive layer 108 is parallel to the top surface of the first conductive layer 106 on the support structure 203, and the top surface of the second conductive layer 108 The height is higher than the height of the top surface of the first conductive layer 106 on the support structure 203 .
  • the capacitance structure of columnar capacitors is formed based on a stable support structure; due to the stable support structure, the height of columnar capacitors is greatly improved compared with double-sided capacitors, that is, columnar capacitors have more Large aspect ratio; and the process steps for forming columnar capacitors are simpler and cost-effective; since there is no need to etch to form capacitor holes with high aspect ratio, the stability of the capacitor structure of the columnar capacitors formed is also guaranteed; in addition, the columnar capacitors Compared with the double-sided capacitor, the typical instability of the inner-layer capacitance of the double-sided capacitor is avoided, thereby improving the yield of the semiconductor structure.
  • this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other structures in this embodiment.

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Abstract

一种半导体结构的形成方法及半导体结构，其中，半导体结构的形成方法包括：提供半导体基底(100)，半导体基底(100)中至少包括分立的导电层(110)；在半导体基底(100)上形成分立排布的支撑结构(203)，支撑结构(203)底部包括底部导电层(201)，且支撑结构(203)之间包括电容开口(103)，底部导电层(201)电连接导电层(110)；在支撑结构(203)的侧壁形成下电极(104)，下电极(104)电连接底部导电层(201)；形成覆盖支撑结构(203)顶部、下电极(104)侧壁和电容开口(103)底部的电容介质层(105)；形成覆盖电容介质层(105)的上电极（106），以构成电容结构(107)。

Description

半导体结构的形成方法及半导体结构
交叉引用
本申请引用于2020年8月13日递交的名称为“半导体结构的形成方法及半导体结构”的第202010814732.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构的形成方法及半导体结构。
背景技术
随着动态随机存取存储器(DRAM)特征尺寸持续缩小，形成的电容器的尺寸也在不断缩小，需要通过形成高身宽比电容器的方式以保证电容器的电容，目前主要通过形成双面电容的方式来提高电容器的电容，形成高深宽比的双面电容的过程中，需要刻蚀形成高深宽比的电容孔以形成空心电容柱。
然而申请人发现：形成双面电容的过程中，若形成的双面电容的深宽比较大，在刻蚀形成空心电容柱的过程中，电容结构不稳定，容易出现倒塌的现象，且双面电容的内层电容存在电性不稳定的情况，从而影响半导体结构的良率。
发明内容
本申请实施例提供一种半导体结构的形成方法及半导体结构，通过形成稳定的支撑结构以形成稳定柱状电容，提高了形成的电容结构的深宽比，且形成的电容结构稳定不易倒塌，提高了半导体结构的良率。
为解决上述技术问题，本申请实施例提供了一种半导体结构的形成方法，包括：提供半导体基底，半导体基底中至少包括分立的导电层；在半导体基底上形成分立排布的支撑结构，支撑结构底部包括底部导电层，且支撑结构之间包括电容开口，底部导电层电连接导电层；在支撑结构的侧壁形成下电极，下电极电连接底部导电层；形成覆盖支撑结构顶部、下电极侧壁和电容开口底部的电容介质层；形成覆盖电容介质层的上电极，以构成电容结构。
与相关技术形成双面电容的方式相比，本申请实施例通过在半导体基底上先形成稳定的支撑结构，基于稳定的支撑结构形成柱状结构的电容结构；由于具有稳定的支撑结构，形成的柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且在形成柱状电容的过程中，不需要刻蚀形成高深宽比的电容孔，工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
另外，在半导体基底上形成分立排布的支撑结构的步骤包括：在半导体基底上形成底部导电层；在底部导电层上形成支撑层；图形化支撑层和底部导电层形成电容开口，剩余的支撑层和底部导电层构成支撑结构。
另外，在半导体基底上形成底部导电层和在底部导电层上形成支撑层的步骤包括：在半导体基底上形成底部导电膜；图形化底部导电膜，形成贯穿底部导电膜的通孔，剩余底部导电膜作为底部导电层；在底部导电层上形成支撑层，支撑层还填充通孔。
另外，图形化支撑层形成多个分立的电容开口的步骤包括：在支撑层上 依次形成掩膜层和图形化的光刻胶层；基于光刻胶层，图形化掩膜层；基于图形化后的掩膜层，刻蚀支撑层和底部导电层形成电容开口。
另外，电容开口至少暴露出每个分立的导电层的部分顶部表面。
另外，支撑层为依次堆叠形成底支撑层和填充层。通过依次堆叠形成的薄层的过程，避免了单次沉积形成厚度较大的薄层，保证形成的薄层的致密性更好，且通过依次堆叠形成的薄层，保证了支撑结构的具有较高的高度，从而增加后续形成的柱状电容的深宽比。
另外，在半导体基底上形成分立排布的支撑结构的步骤包括：在半导体基地上形成分立排布的初始支撑结构，初始支撑结构包括依次堆叠形成的底支撑层和填充层；横向刻蚀部分宽度的底支撑层，形成导电开口；形成填充导电开口的底部导电层，底部导电层与剩余初始支撑结构成支撑结构。
另外，平行于半导体基底顶部表面的方向上，形成的导电开口的宽度小于等于底部导电层宽度的三分之一。通过合理设置形成的导电开口的宽度，保证底部导电层的尺寸以增大下电极与导电层的接触面积，减小接触电阻，并保证支撑结构的稳定性。
另外，形成填充导电开口的底部导电层的步骤包括：形成填充导电开口和部分高度电容开口的底部导电膜，底部导电膜顶部表面的高度高于底支撑层顶部表面的高度；刻蚀去除位于电容开口暴露出的底部导电膜，形成底部导电层。
另外，在支撑结构的侧壁形成电连接一导电层的下电极的步骤包括：在支撑结构顶部和侧壁以及电容开口底部形成顶导电层；去除位于支撑结构顶部以及电容开口底部的顶导电层，形成位于支撑结构侧壁的下电极。
另外，去除位于支撑结构顶部的顶导电层的方式包括化学机械研磨。
另外，形成覆盖电容介质层的上电极的步骤包括：形成覆盖电容介质层的第一导电层；形成填充第一导电层之间间隙的第二导电层，第二导电层顶部表面与位于支撑结构上的第一导电层的顶部表面平行，且第二导电层顶部表面的高度高于位于支撑结构上的第一导电层顶部表面的高度。
另外，形成填充第一导电层之间间隙的第二导电层包括以下步骤：形成填充第一导电层之间间隙的第二导电膜，第二导电膜顶部表面的高度高于位于支撑结构上的第一导电层顶部表面的高度；对第二导电膜顶部表面进行化学机械研磨处理，以形成第二导电层。
本申请实施例还提供了一种半导体结构，包括：半导体基底，半导体基底中至少包括分立的导电层；多个分立的支撑结构，位于半导体基底上，支撑结构底部至少包括底部导电层，底部导电层电连接导电层；以及通过支撑结构支撑的电容结构，电容结构包括：下电极，位于支撑结构的侧壁，且电连接底部导电层；电容介质层，位于支撑结构顶部、下电极侧壁和支撑结构之间的间隙底部；上电极，位于电容介质层上。
另外，支撑结构之间的间隙至少暴露出每个分立的导电层的部分顶部表面。
另外，下电极与底部导电层为一体结构。一体形成下电极与底部导电层，进一步减少下电极的接触电阻。
另外，平行于半导体基底顶部表面的方向上，底部导电层的宽度小于等于底部导电层宽度的三分之一。
与双面电容的电容结构相比，柱状电容的电容结构基于稳定的支撑结构 形成；由于具有稳定的支撑结构，柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且形成柱状电容的工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的柱状电容的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
附图说明
图1至图18为本申请一实施例提供的半导体结构的形成方法的各步骤对应的半导体结构的剖面结构示意图；
图19至图30为本申请另一实施例提供的半导体结构的形成方法的各步骤对应的半导体结构的剖面结构示意图。
具体实施方式
目前，形成双面电容的过程中，若形成的双面电容的深宽比较大，在刻蚀形成空心电容柱的过程中，电容结构不稳定，容易出现倒塌的现象，且双面电容的内层电容存在电性不稳定的情况，从而影响半导体结构的良率。
为解决上述问题，本申请一实施例提供了一种半导体结构的形成方法，包括：提供半导体基底，半导体基底中至少包括分立的导电层；在半导体基底上形成分立排布的支撑结构，支撑结构之间包括电容开口；在支撑结构的侧壁形成下电极，下电极电连接导电层；形成覆盖支撑结构顶部、下电极侧壁和电容开口底部的电容介质层；形成覆盖电容介质层的上电极，以构成电容结构。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。 但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图18为本实施例提供的半导体结构的形成方法各步骤对应的流程示意图，下面对本实施例的半导体结构的形成方法进行具体说明。需要说明的是，本实施例以存储器中的半导体结构为例进行具体介绍，即本实施例中所要保护的半导体结构形成在DRAM存储器或SRAM存储器中。
参考图1和图8，提供半导体基底100，在半导体基底100上形成分立排布的支撑结构203，支撑结构203底部包括底部导电层201，支撑结构203之间包括电容开口103，底部导电层201电连接导电层110。
参考图1，半导体基底100中至少包括分立的导电层110。
分立的导电层110在半导体基底100中排布方式如图2所示，导电层110即DRAM结构中的电容接触垫(landing pad),导电层110呈六方排布，用于电连接DRAM的阵列晶体管。
继续参考图1，在半导体基底100上形成初始支撑层101，初始支撑层101用于后续刻蚀形成初始支撑结构102。
初始支撑层101包括依次堆叠形成的底支撑层111和填充层121。通过依次堆叠形成的初始支撑层101的过程，避免了单次沉积形成厚度较大的初始支撑层101，保证形成的初始支撑层101的致密性更好，且通过依次堆叠形成初始支撑层101，保证了后续形成的初始支撑结构102的具有较高的高度，从而增加后续形成的柱状电容的深宽比。在本实施例中底支撑层111和填充层121 采用不同的绝缘材料形成。
需要说明的是，在其他实施例中，初始支撑层也可以采用三层及三层以上的堆叠结构实现，以这种方式形成的堆叠结构的高度更高，即后续形成的支撑结构具有更高的高度。
参考图3～图6，图形化初始支撑层101形成电容开口103，剩余的初始支撑层101构成初始支撑结构102。
参考图3，在初始支撑层101上依次形成掩膜层120和图形化的光刻胶层130。
参考图4，基于光刻胶层130图形化掩膜层120。
参考图5，基于图形化后的掩膜层120，刻蚀初始支撑层101形成电容开口103。
在本实施例中，电容开口103至少暴露出每个分立的导电层110的部分顶部表面。电容开口103与导电层110的顶部形貌分布如图6所示，刻蚀电容开口103后剩余的初始支撑层101作为初始支撑结构102，即在本实施例中，初始支撑结构102为依次堆叠形成的底支撑层111填充层121。
刻蚀形成电容开口103之后还包括：依次去除光刻胶层130和掩膜层120。具体地，采用第一干法清洗工艺去除所述光刻胶层130，第一干法清洗工艺采用氨气、氮气和氢气的混合气体，混合气体与光刻胶层130反应生成第一固化物，然后通过高温蒸发的方式蒸发第一固化物，即完成光刻胶层130的去除。需要说明的是，在本实施例中采用氨气、氮气和氢气的混合气体与光刻胶层130反应生成第一固化物的过程中，由于混合气体中不含有氧气，且阻止了初始支撑结构102与空气相接触，在去除光刻胶层130的同时，防止初始支撑结构102 侧壁的自然氧化。在去除光刻胶层130之后，采用第一湿法清洗工艺去除掩膜层120，第一湿法清洗工艺采用49％HF以及1:1:60APM(H2O2:NH4OH:H2O＝1:1:60)的混合溶液，混合溶液与掩膜层120发生化学反应以去除掩膜层120。需要说明的是，在本实施例中采用49％HF以及1:1:60APM的混合溶液与掩膜层120反应去除掩膜层120的过程中，由于混合液体中含有NH4OH，会电离出OH-，由于OH-的负电荷排斥作用以及H2O2的氧化性，可以去除初始支撑结构102侧壁的颗粒物。
参考图7，横向刻蚀部分宽度的底支撑层111，形成导电开口200。
选择性横向刻蚀部分宽度的底支撑层111。具体地，采用具有刻蚀选择比的材料，使得底支撑层111的被刻蚀速率高于填充层121的被刻蚀速率。
在本实施例中，在平行于半导体基底100顶部表面的方向上，导电开口200的宽度小于等于底部导电层201宽度的三分之一。保证剩余底支撑层111仍然可以支撑初始支撑结构102，防止初始支撑结构102坍塌。
需要说明的是，在本实施例中，初始支撑结构102为圆柱形设置，即形成的底部导电层201为初始支撑结构102底部的环状结构。本实施例并不对底部导电层的形貌进行限定，在其他实施例中底部导电层的形貌与初始支撑结构相关。
参考图8，形成填充导电开口200的底部导电层201，底部导电层201与剩余初始支撑结构102构成支撑结构203。本实施例通过回刻蚀形成底部导电层201，并后续形成电连接底部导电层201的下电极104以增大下电极104与导电层110的接触面积，从而减少下电极104与导电层110之间的接触电阻。
底部导电层201可以为一种导电材料或者由多种导电材料构成，例如掺 杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，底部导电层201采用氮化钛材料。
具体地，形成填充导电开口200和部分高度电容开口103的底部导电膜(未图示)，底部导电膜(未图示)顶部表面的高度高于底支撑层111顶部表面的高度。然后刻蚀去除位于电容开口103暴露出的底部导电膜(未图示)形成底部导电层201。
需要说明的是，在其他实施例中，参考图9～图12，基于图形化后的掩膜层120刻蚀初始支撑层101形成的电容开口103，电容开口103并不暴露出导电层110的顶部表面。电容开口103与导电层110的顶部形貌分布如图13所示。
参考图14～图18，基于支撑结构203形成电容结构107。
具体地，参考图14～图15，在支撑结构203的侧壁形成下电极104，下电极104电连接底部导电层201和导电层110。
下电极104可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极104采用氮化钛材料。
参考图14，在支撑结构203顶部和侧壁以及电容开口103底部形成顶导电层114。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成顶导电层114，在本实施例中，采用原子层沉积工艺的方式形成顶导电层114，采用原子层沉积工艺形成的顶导电层114具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成顶导电层。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的 理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图15，区域位于支撑结构203顶部以及电容开口103底部的顶导电层114，形成于支撑结构203侧壁的下电极104。
具体地，去除位于支撑结构203顶部的顶导电层114的方式包括化学机械研磨。采用化学机械研磨的方式去除支撑结构的顶导电层114，流程简单且成本低廉，可以有效提高电容结构的制造效率。需要说明的是，在其他实施例中，也可以通过刻蚀的方式对顶导电层进行平坦化处理。
需要说明的是，在本实施例中，对底部导电层201和下电极104的形成方式为分步形成，即先形成的底部导电层201，再形成下电极104。在其他实施方式中，底部导电层201和下电极104可以在一步形成工艺中形成，此时形成的下电极104和底部导电层201为一体结构，可以进一步减少下电极104与底部导电层201之间的接触电阻。
参考图16，形成覆盖支撑结构203顶部、下电极104侧壁和电容开口103底部的电容介质层105。
电容介质层105为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。具体地，采用原子层沉积工艺或化学气相沉积的方法形成电容介质层105，在本实施例中，采用原子层沉积工艺的方式形成电容介质层105，采用原子层沉积工艺形成的电容介质层105具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成电容介质层。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本 方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图17～图18，形成覆盖电容介质层105的上电极，下电极104、电容介质层105和上电极共同构成电容结构107。
具体地，形成覆盖电容介质层的上电极的步骤包括：
参考图17，形成覆盖电容介质层105的第一导电层106。
第一导电层106可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，第一导电层106采用氮化钛材料。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成第一导电层106，在本实施例中，采用原子层沉积工艺的方式形成第一导电层106，采用原子层沉积工艺形成的第一导电层106具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成第一导电层106。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图18，形成填充第一导电层106之间间隙的第二导电层108。其中，第二导电层108顶部表面与位于支撑结构203上的第一导电层106的顶部表面平行，且第二导电层108顶部表面的高度高于位于支撑结构203上的第一导电层106顶部表面的高度。
具体地，形成填充第一导电层106之间间隙的第二导电膜(未图示)，第二导电膜顶部表面的高度高于第一导电层106顶部表面的高度；对第二导电膜 (未图示)顶部表面进行化学机械研磨处理，以形成第二导电层108。
采用化学机械研磨的方式形成第二导电层108，流程简单且成本低廉，可以有效提高半导体结构的制造效率。需要说明的是，在其他实施例中，也可以通过刻蚀第二导电膜以形成第二导电层。通过填充第一导电层106之间的空隙，已将分立的电容结构107构成一个整体。
与相关技术形成双面电容的方式相比，本申请实施例通过在半导体基底上先形成稳定的支撑结构，基于稳定的支撑结构形成柱状结构的电容结构；由于具有稳定的支撑结构，形成的柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且在形成柱状电容的过程中，不需要刻蚀形成高深宽比的电容孔，工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种半导体结构的形成方法，与上述实施例不同的是，本实施例给出了另一种底部导电层的形成方法。
图19至图30为本实施例提供的半导体结构的形成方法各步骤对应的流程示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
参考图19～图22，在半导体基底300上形成分立排布的支撑结构302。
参考图19～图20，在半导体基底300上形成底部导电层401
具体地，参考图19，在半导体基底300上形成底部导电膜400，底部导电膜400可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，底部导电膜400采用氮化钛材料。
参考图20，图形化底部导电膜400，形成贯穿底部导电膜400的通孔410。剩余底部导电膜400作为底部导电层401。
参考图21，在底部导电层401上形成支撑层301，支撑层301还填充通孔410。在本实施例中支撑层301为依次堆叠形成的底支撑层311和填充层321。通过依次堆叠形成的支撑层301的过程，避免了单次沉积形成厚度较大的支撑层301，保证形成的支撑层301的致密性更好，且通过依次堆叠形成支撑层301，保证了后续形成的支撑结构302的具有较高的高度，从而增加后续形成的柱状电容的深宽比。在本实施例中底支撑层111和填充层采用不同的绝缘材料形成。需要说明的是，在其他实施例中，支撑层也可以采用三层及三层以上的堆叠结构实现，以这种方式形成的堆叠结构的高度更高，即后续形成的支撑结构具有更高的高度。
参考图22，图形化支撑层301形成多个分立的电容开口303，剩余支撑层301作为支撑层302。
具体地，在支撑层301上依次形成掩膜层(未图示)和图形化的光刻胶(未图示)，基于光刻胶层，图形化掩膜层(未图示)，基于图形化后的掩膜层，可是支撑层301和底部导电层401形成电容开口303，剩余支撑层301和底部导电层401作为支撑层302。
需要说明的是，在本实施例中，电容开口303至少暴露出每个分立的导电层310的部分顶部表面。在其他实施例中，参考图23～图25，基于图形化后的掩膜层可是支撑层301形成电容开口303，电容开口303并不暴露出导电层310的顶部表面。
参考图26～图30，基于支撑结构302形成电容结构307。
具体地，参考图26～图27，在支撑结构302的侧壁形成下电极304，下电极304电连接底部导电层401和导电层310。
下电极304可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极304采用氮化钛材料。
参考图26，在支撑结构302顶部和侧壁以及电容开口303底部形成顶导电层314。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成顶导电层314，在本实施例中，采用原子层沉积工艺的方式形成顶导电层314，采用原子层沉积工艺形成的顶导电层314具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成顶导电层。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图27，区域位于支撑结构302顶部以及电容开口303底部的顶导电层314，形成于支撑结构302侧壁的下电极304。
具体地，去除位于支撑结构302顶部的顶导电层314的方式包括化学机 械研磨。采用化学机械研磨的方式去除支撑结构的顶导电层314，流程简单且成本低廉，可以有效提高电容结构的制造效率。需要说明的是，在其他实施例中，也可以通过刻蚀的方式对顶导电层进行平坦化处理。
参考图28，形成覆盖支撑结构302顶部、下电极304侧壁和电容开口303底部的电容介质层305。
电容介质层305为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。具体地，采用原子层沉积工艺或化学气相沉积的方法形成电容介质层305，在本实施例中，采用原子层沉积工艺的方式形成电容介质层305，采用原子层沉积工艺形成的电容介质层305具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成电容介质层。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图29～图30，形成覆盖电容介质层305的上电极，下电极304、电容介质层305和上电极共同构成电容结构307。
具体地，形成覆盖电容介质层的上电极的步骤包括：
参考图29，形成覆盖电容介质层305的第一导电层306。
第一导电层306可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，第一导电层306采用氮化钛材料。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成第一导电层 306，在本实施例中，采用原子层沉积工艺的方式形成第一导电层306，采用原子层沉积工艺形成的第一导电层306具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成第一导电层306。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图30，形成填充第一导电层306之间间隙的第二导电层308。其中，第二导电层308顶部表面与位于支撑结构302上的第一导电层306的顶部表面平行，且第二导电层308顶部表面的高度高于位于支撑结构302上的第一导电层306顶部表面的高度。
具体地，形成填充第一导电层306之间间隙的第二导电膜(未图示)，第二导电膜顶部表面的高度高于第一导电层306顶部表面的高度；对第二导电膜(未图示)顶部表面进行化学机械研磨处理，以形成第二导电层308。
采用化学机械研磨的方式形成第二导电层308，流程简单且成本低廉，可以有效提高半导体结构的制造效率。需要说明的是，在其他实施例中，也可以通过刻蚀第二导电膜以形成第二导电层。通过填充第一导电层306之间的空隙，已将分立的电容结构307构成一个整体。
与相关技术形成双面电容的方式相比，本申请实施例通过在半导体基底上先形成稳定的支撑结构，基于稳定的支撑结构形成柱状结构的电容结构；由于具有稳定的支撑结构，形成的柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且在形成柱状电容的过程中，不需要刻蚀形成高深宽比的电容孔，工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深 宽比的电容孔，还保证了形成的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的结构。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请又一实施例涉及一种半导体结构。参考图18，以下将结合附图对本实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
半导体结构，包括：半导体基底100，半导体基底100至少包括分立的导电层110，多个分立的支撑结构203，位于半导体基底100上，支撑结构203底部包括底部导电层201，底部导电层201电连接导电层110；以及通过支撑结构203支撑的电容结构107，电容结构107包括：下电极104，位于支撑结 构203的侧壁，且电连接导电层110；电容介质层105，位于支撑结构203顶部、下电极104侧壁和支撑结构203之间的间隙底部；上电极，位于电容介质层105上。
分立的导电层110在半导体基底100中排布方式如图2所示，导电层110即DRAM结构中的电容接触垫(landing pad),导电层110呈六方排布，用于电连接DRAM的阵列晶体管。
本实施例提供的支撑结构203可以通过堆叠结构的方式实现，以堆叠结构形成支撑结构203的高度更高，即后续形成的电容结构107具有更高的深宽比。
在本实施例中，支撑结构203之间的间隙至少暴露出每个分立的导电层110的部分顶部表面；下电极104用于连接暴露出的分立的导电层110的顶部表面。
在一个例子中，下电极104与底部导电层201为一体结构，一体形成下电极与底部导电层，进一步减少下电极的接触电阻。
在本实施例中，在平行于半导体基底100顶部表面的方向上，导电开口200的宽度小于等于底部导电层201宽度的三分之一。保证剩余底支撑层111仍然可以支撑初始支撑结构102，防止初始支撑结构102坍塌。
电容结构107包括：下电极104，位于支撑结构102的侧壁，且电连接导电层110；电容介质层105，位于支撑结构102顶部、下电极104侧壁和支撑结构102之间的间隙底部；上电极，位于电容介质层105上。
下电极104可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极104采用 氮化钛材料。电容介质层105为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。
上电极包括第一导电层106和第二导电层108。第一导电层106覆盖电容介质层105，第一导电层106可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，第一导电层106采用氮化钛材料。第二导电层108填充第一导电层106之间间隙，其中，第二导电层108顶部表面与位于支撑结构203上的第一导电层106的顶部表面平行，且第二导电层108顶部表面的高度高于位于支撑结构203上的第一导电层106顶部表面的高度。
与双面电容的电容结构相比，柱状电容的电容结构基于稳定的支撑结构形成；由于具有稳定的支撑结构，柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且形成柱状电容的工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的柱状电容的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的结构。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述 实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种半导体结构的形成方法，其特征在于，包括如下步骤：
    提供半导体基底，所述半导体基底中至少包括分立的导电层；
    在所述半导体基底上形成分立排布的支撑结构，所述支撑结构底部包括底部导电层，且所述支撑结构之间包括电容开口，所述底部导电层电连接所述导电层；
    在所述支撑结构的侧壁形成下电极，所述下电极电连接所述底部导电层；
    形成覆盖所述支撑结构顶部、所述下电极侧壁和所述电容开口底部的电容介质层；
    形成覆盖所述电容介质层的上电极，以构成电容结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其特征在于，在所述半导体基底上形成分立排布的支撑结构的步骤包括：
    在所述半导体基底上形成所述底部导电层；
    在所述底部导电层上形成支撑层；
    图形化所述支撑层和所述底部导电层形成所述电容开口，剩余的所述支撑层和所述底部导电层构成所述支撑结构。
  3. 根据权利要求2所述的半导体结构的形成方法，其特征在于，在所述半导体基底上形成所述底部导电层和在所述底部导电层上形成支撑层的步骤包括：
    在所述半导体基底上形成底部导电膜；
    图形化所述底部导电膜，形成贯穿所述底部导电膜的通孔，剩余所述底部导电膜作为所述底部导电层；
    在所述底部导电层上形成支撑层，所述支撑层还填充所述通孔。
  4. 根据权利要求2所述的半导体结构的形成方法，其特征在于，图形化所述支撑层形成多个分立的所述电容开口的步骤包括：
    在所述支撑层上依次形成掩膜层和图形化的光刻胶层；
    基于所述光刻胶层，图形化所述掩膜层；
    基于图形化后的所述掩膜层，刻蚀所述支撑层和所述底部导电层形成所述电容开口。
  5. 根据权利要求2所述的半导体结构的形成方法，所述电容开口至少暴露出每个分立的所述导电层的部分顶部表面。
  6. 根据权利要求2所述的半导体结构的形成方法，其特征在于，所述支撑层为依次堆叠形成底支撑层和填充层。
  7. 根据权利要求1所述的半导体结构的形成方法，其特征在于，在所述半导体基底上形成分立排布的支撑结构的步骤包括：
    在所述半导体基地上形成分立排布的初始支撑结构，所述初始支撑结构包括依次堆叠形成的底支撑层和填充层；
    横向刻蚀部分宽度的所述底支撑层，形成导电开口；
    形成填充所述导电开口的底部导电层，所述底部导电层与剩余所述初始支撑结构成所述支撑结构。
  8. 根据权利要求7所述的半导体结构的形成方法，其特征在于，平行于所述半导体基底顶部表面的方向上，所述导电开口的宽度小于等于所述底部导电层宽度的三分之一。
  9. 根据权利要求7所述的半导体结构的形成方法，其特征在于，形成填充所述导电开口的底部导电层的步骤包括：
    形成填充所述导电开口和部分高度所述电容开口的底部导电膜，所述底部导电膜顶部表面的高度高于所述底支撑层顶部表面的高度；
    刻蚀去除位于电容开口暴露出的所述底部导电膜，形成所述底部导电层。
  10. 根据权利要求1所述的半导体结构的形成方法，其特征在于，在所述支撑结构的侧壁形成电连接一所述导电层的下电极的步骤包括：
    在所述支撑结构顶部和侧壁以及所述电容开口底部形成顶导电层；
    去除位于所述支撑结构顶部以及所述电容开口底部的所述顶导电层，形成 位于所述支撑结构侧壁的下电极。
  11. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述去除位于所述支撑结构顶部的所述顶导电层的方式包括化学机械研磨。
  12. 根据权利要求1所述的半导体结构的形成方法，其特征在于，形成覆盖所述电容介质层的上电极的步骤包括：
    形成覆盖所述电容介质层的第一导电层；
    形成填充所述第一导电层之间间隙的第二导电层，所述第二导电层顶部表面与位于所述支撑结构上的所述第一导电层的顶部表面平行，且所述第二导电层顶部表面的高度高于位于所述支撑结构上的所述第一导电层顶部表面的高度。
  13. 根据权利要求12所述的半导体结构的形成方法，其特征在于，形成填充所述第一导电层之间间隙的第二导电层包括以下步骤：
    形成填充所述第一导电层之间间隙的第二导电膜，所述第二导电膜顶部表面的高度高于位于所述支撑结构上的所述第一导电层顶部表面的高度；
    对所述第二导电膜顶部表面进行化学机械研磨处理，以形成所述第二导电层。
  14. 一种半导体结构，其特征在于，包括：
    半导体基底，所述半导体基底中至少包括分立的导电层；
    多个分立的支撑结构，位于所述半导体基底上，所述支撑结构底部至少包括底部导电层，所述底部导电层电连接所述导电层；
    以及通过所述支撑结构支撑的电容结构，所述电容结构包括：
    下电极，位于所述支撑结构的侧壁，且电连接所述底部导电层；
    电容介质层，位于所述支撑结构顶部、所述下电极侧壁和所述支撑结构之间的间隙底部；
    上电极，位于所述电容介质层上。
  15. 根据权利要求14所述的半导体结构，其特征在于，所述支撑结构之间的间 隙至少暴露出每个分立的所述导电层的部分顶部表面。
  16. 根据权利要求14所述的半导体结构，其特征在于，所述下电极与所述底部导电层为一体结构。
  17. 根据权利要求14所述的半导体结构，其特征在于，平行于所述半导体基底顶部表面的方向上，所述底部导电层的宽度小于等于所述底部导电层宽度的三分之一。
PCT/CN2021/098929 2020-08-13 2021-06-08 半导体结构的形成方法及半导体结构 Ceased WO2022033147A1 (zh)

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