WO2022033146A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022033146A1
WO2022033146A1 PCT/CN2021/098928 CN2021098928W WO2022033146A1 WO 2022033146 A1 WO2022033146 A1 WO 2022033146A1 CN 2021098928 W CN2021098928 W CN 2021098928W WO 2022033146 A1 WO2022033146 A1 WO 2022033146A1
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forming
layer
conductive layer
capacitor
support structure
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PCT/CN2021/098928
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English (en)
French (fr)
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王凌翔
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长鑫存储技术有限公司
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Priority to US17/445,993 priority Critical patent/US11961881B2/en
Publication of WO2022033146A1 publication Critical patent/WO2022033146A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • the size of the formed capacitor is also shrinking. It is necessary to form a high aspect ratio capacitor to ensure the capacitance of the capacitor.
  • the main method is to form a double-sided capacitor. In the process of increasing the capacitance of the capacitor and forming a double-sided capacitor with a high aspect ratio, it is necessary to etch a capacitor hole with a high aspect ratio to form a hollow capacitor column.
  • the inner layer capacitance of the capacitor is electrically unstable, which affects the yield of the semiconductor structure.
  • Embodiments of the present application provide a method for forming a semiconductor structure and a semiconductor structure.
  • a stable support structure to form a stable columnar capacitor
  • the aspect ratio of the formed capacitor structure is improved, and the formed capacitor structure is stable and not easy to collapse, thereby improving the Yield of semiconductor structures.
  • embodiments of the present application provide a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate at least including discrete conductive layers; forming discretely arranged support structures on the semiconductor substrate, the support structures A capacitor opening is included between; a lower electrode is formed on the sidewall of the support structure, and the lower electrode is electrically connected to the conductive layer; a capacitor dielectric layer covering the top of the support structure, the sidewall of the lower electrode and the bottom of the capacitor opening is formed; an upper electrode covering the capacitor dielectric layer is formed , to form a capacitor structure.
  • a stable support structure is first formed on the semiconductor substrate, and a columnar capacitor structure is formed based on the stable support structure; due to the stable support structure, the height of the formed columnar capacitor is
  • the double-sided capacitor has been greatly improved, that is, the columnar capacitor has a larger aspect ratio; and in the process of forming the columnar capacitor, there is no need to etch to form a capacitor hole with a high aspect ratio, the process steps are simpler, and the cost is saved; There is no need to etch to form capacitor holes with high aspect ratio, which also ensures the stability of the formed capacitor structure; in addition, compared with double-sided capacitors, columnar capacitors avoid the typical instability of the inner layer capacitors of double-sided capacitors. Thereby, the yield of the semiconductor structure is improved.
  • the step of forming discretely arranged supporting structures on the semiconductor substrate includes: forming a supporting layer on the semiconductor substrate; patterning the supporting layer to form capacitor openings, and the remaining supporting layers forming the supporting structure.
  • the capacitor openings expose at least a portion of the top surface of each discrete conductive layer.
  • the lower electrode formed on the sidewall of the support structure is electrically connected to the conductive layer.
  • the method for forming the semiconductor structure further includes the following steps: before the step of forming the support structure, it further includes: forming a bottom conductive layer on the semiconductor substrate, and the bottom conductive layer is electrically connected to the conductive layer; the step of forming the support structure includes: forming a bottom conductive layer on the bottom conductive layer A discretely arranged support structure is formed on the top; after the lower electrode is formed and before the capacitor dielectric layer is formed, the following steps are further included: etching and removing the bottom conductive layer exposed at the bottom of the capacitor opening. Before forming the support structure, a bottom conductive layer is formed on the top surface of the semiconductor substrate.
  • the conductive layer is also located at the bottom of the support structure, so as to increase the contact area between the lower electrode and the conductive layer formed subsequently, and ensure that the formed lower electrode and the conductive layer are formed. Stability of electrical connections between conductive layers.
  • the supporting structure is a stacked structure formed by stacking in sequence.
  • the stacked structure includes a bottom support layer and a filling layer formed by stacking in sequence.
  • the step of forming a plurality of discrete capacitor openings by patterning the support layer includes: sequentially forming a mask layer and a patterned photoresist layer on the support layer; patterning the mask layer based on the photoresist layer; After the mask layer, the supporting layer is etched to form capacitor openings.
  • the step of forming a lower electrode electrically connected to a conductive layer on the sidewall of the support structure includes: forming a top conductive layer on the top and sidewalls of the support structure and the bottom of the capacitor opening; removing the top conductive layer on the top of the support structure and the bottom of the capacitor opening , forming a lower electrode on the sidewall of the support structure.
  • the manner of removing the top conductive layer on top of the support structure includes chemical mechanical polishing.
  • the method for forming a semiconductor structure is characterized in that it further includes the following steps: the step of forming an upper electrode covering the capacitor dielectric layer includes: forming a first conductive layer covering the capacitor dielectric layer; A second conductive layer, the top surface of the second conductive layer is parallel to the top surface of the first conductive layer on the support structure, and the height of the top surface of the second conductive layer is higher than the height of the top surface of the first conductive layer on the support structure .
  • forming the second conductive layer filling the gap between the first conductive layers includes the steps of: forming a second conductive film filling the gap between the first conductive layers, the top surface of the second conductive film having a height higher than that on the support structure height of the top surface of the first conductive layer; chemical mechanical polishing is performed on the top surface of the second conductive film to form the second conductive layer.
  • Embodiments of the present application further provide a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate at least includes discrete conductive layers; a plurality of discrete support structures located on the semiconductor substrate; and a capacitor structure supported by the support structure, the capacitor structure It includes: a lower electrode located on the sidewall of the support structure and electrically connected to the conductive layer; a capacitive dielectric layer located on the top of the support structure, the bottom electrode sidewall and the bottom of the gap between the support structure; an upper electrode located on the capacitive dielectric layer.
  • the gap between the support structures exposes at least a portion of the top surface of each discrete conductive layer; the lower electrode is used to connect the exposed top surface of the discrete conductive layer.
  • the semiconductor structure further includes: a bottom conductive layer located between the semiconductor substrate and the support structure for electrically connecting the conductive layer and the lower electrode.
  • the capacitance structure of columnar capacitors is formed based on a stable support structure; due to the stable support structure, the height of columnar capacitors is greatly improved compared with double-sided capacitors, that is, columnar capacitors have more Large aspect ratio; and the process steps for forming columnar capacitors are simpler and cost-effective; since there is no need to etch to form capacitor holes with high aspect ratio, the stability of the capacitor structure of the columnar capacitors formed is also guaranteed; in addition, the columnar capacitors Compared with the double-sided capacitor, the typical instability of the inner-layer capacitance of the double-sided capacitor is avoided, thereby improving the yield of the semiconductor structure.
  • FIG. 1 to 11 are schematic cross-sectional structural diagrams of a semiconductor structure corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application;
  • FIGS. 12 to 19 are schematic cross-sectional structural diagrams of the semiconductor structure corresponding to each step of the method for forming a semiconductor structure according to another embodiment of the present application.
  • the capacitor structure is unstable, and the phenomenon of collapse easily occurs.
  • the layer capacitance is electrically unstable, which affects the yield of the semiconductor structure.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, where the semiconductor substrate at least includes discrete conductive layers; forming discretely arranged support structures on the semiconductor substrate, the support structures A capacitor opening is included between; a lower electrode is formed on the sidewall of the support structure, and the lower electrode is electrically connected to the conductive layer; a capacitor dielectric layer covering the top of the support structure, the sidewall of the lower electrode and the bottom of the capacitor opening is formed; an upper electrode covering the capacitor dielectric layer is formed , to form a capacitor structure.
  • FIG. 1 to 11 are schematic flowcharts corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • this embodiment takes a semiconductor structure in a memory as an example for specific description, that is, the semiconductor structure to be protected in this embodiment is formed in a DRAM memory or an SRAM memory.
  • a semiconductor substrate 100 is provided on which discretely arranged support structures 102 are formed.
  • a semiconductor substrate 100 includes at least discrete conductive layers 110 therein.
  • the discrete conductive layers 110 are arranged in the semiconductor substrate 100 as shown in FIG. 2 .
  • the conductive layers 110 are the capacitive contact pads (landing pads) in the DRAM structure, and the conductive layers 110 are arranged in a hexagonal manner for electrically connecting the DRAM array transistor.
  • a support layer 101 is formed on the semiconductor substrate 100 , and the support layer 101 is used for subsequent etching to form a support structure 102 .
  • the support layer 101 includes a bottom support layer 111 and a filling layer 121 which are formed by stacking in sequence.
  • the formation of the supporting layer 101 with a larger thickness in a single deposition is avoided, and the denseness of the formed supporting layer 101 is ensured.
  • the overall structure 102 has a higher height, thereby increasing the aspect ratio of the subsequently formed columnar capacitors.
  • the bottom support layer 111 and the filling layer 121 are formed of different insulating materials.
  • the support layer 101 is realized by the bottom support layer 111 and the filling layer 121, only to reflect that the support layer 101 provided in this embodiment can be realized by a stack structure, and this embodiment does not implement the bottom support layer 111 and the filling layer 121.
  • Layer 121 is thickness-defining.
  • the support layer can also be realized by a single-layer structure, that is, the support structure formed subsequently is a single-layer structure, and the support layer can also be realized by a stack structure of three or more layers. The height of the structure is higher, that is, the subsequently formed support structure 102 has a higher height.
  • the patterned support layer 101 forms capacitor openings 103 , and the remaining support layer 101 forms a support structure 102 .
  • a mask layer 120 and a patterned photoresist layer 130 are sequentially formed on the support layer 101 .
  • the mask layer 120 is patterned based on the patterned photoresist layer 130 .
  • the support layer 101 is etched to form the capacitor opening 103.
  • the capacitor opening 103 exposes at least a portion of the top surface of each discrete conductive layer 110 .
  • the top shape distribution of the capacitor opening 103 and the conductive layer 110 is shown in FIG. 6 , and the remaining support layer 101 after etching the capacitor opening 103 is used as the support structure 102 , that is, in this embodiment, the support structure 102 It is a stacked structure formed by sequentially stacking, and the stacked structure includes a bottom support layer 111 and a filling layer 121 formed by stacking sequentially.
  • the method further includes: sequentially removing the photoresist layer 130 and the mask layer 120 .
  • the photoresist layer 130 is removed by a first dry cleaning process.
  • the first dry cleaning process uses a mixed gas of ammonia, nitrogen and hydrogen, and the mixed gas reacts with the photoresist layer 130 to form a first cured product, and then The first cured product is evaporated by means of high temperature evaporation, that is, the removal of the photoresist layer 130 is completed.
  • the mixed gas of ammonia, nitrogen and hydrogen in the process of using the mixed gas of ammonia, nitrogen and hydrogen to react with the photoresist layer 130 to form the first cured product, since the mixed gas does not contain oxygen, it prevents the support structure 102 Contact with air prevents natural oxidation of the sidewalls of the support structure 102 while removing the photoresist layer 130 .
  • the mixed solution of 49% HF and 1:1:60 APM is used to react with the mask layer 120 to remove the mask layer 120. Since the mixed solution contains NH 4 OH, ionization will occur. OH ⁇ , due to the negative charge repulsion of OH ⁇ and the oxidizing properties of H 2 O 2 , can remove particulate matter from the sidewalls of the support structure 102 .
  • a capacitor structure 107 is formed based on the support structure 102 .
  • a lower electrode 104 is formed on the sidewall of the support structure 102 , and the lower electrode 104 is electrically connected to the conductive layer 110 .
  • the lower electrode 104 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc. In this embodiment, the lower electrode 104 is made of titanium nitride material .
  • a top conductive layer 114 is formed on the top and sidewalls of the support structure 102 and the bottom of the capacitor opening 103 .
  • the top conductive layer 114 is formed by an atomic layer deposition process or a chemical vapor deposition method.
  • the top conductive layer 114 is formed by an atomic layer deposition process, and the top conductive layer 114 is formed by an atomic layer deposition process. It has good coverage; in other embodiments, for example, the top conductive layer can be formed by chemical vapor deposition at 500°C or 600°C.
  • the top conductive layer 114 at the top of the support structure 102 and the bottom of the capacitor opening 103 is formed on the lower electrode 104 on the sidewall of the support structure 102 .
  • the manner of removing the top conductive layer 114 on top of the support structure 102 includes chemical mechanical polishing.
  • the top conductive layer 114 of the support structure is removed by chemical mechanical polishing, the process is simple and the cost is low, and the manufacturing efficiency of the capacitor structure can be effectively improved.
  • the top conductive layer may also be planarized by etching.
  • a capacitor dielectric layer 105 covering the top of the support structure 102 , the sidewalls of the lower electrode 104 and the bottom of the capacitor opening 103 is formed.
  • the capacitor dielectric layer 105 is made of high dielectric constant materials, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used.
  • the capacitor dielectric layer 105 is formed by the atomic layer deposition process or the chemical vapor deposition method.
  • the capacitor dielectric layer 105 is formed by the atomic layer deposition process, and the capacitor dielectric layer 105 is formed by the atomic layer deposition process It has good coverage; in other embodiments, for example, the capacitor dielectric layer can be formed by chemical vapor deposition at 500°C or 600°C.
  • an upper electrode covering the capacitor dielectric layer 105 is formed, and the lower electrode 104 , the capacitor dielectric layer 105 and the upper electrode together constitute a capacitor structure 107 .
  • the step of forming the upper electrode covering the capacitor dielectric layer includes:
  • a first conductive layer 106 covering the capacitive dielectric layer 105 is formed.
  • the first conductive layer 106 may be made of a single conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the first conductive layer 106 is made of Titanium nitride material.
  • the first conductive layer 106 is formed by an atomic layer deposition process or a chemical vapor deposition method.
  • the first conductive layer 106 is formed by an atomic layer deposition process
  • the first conductive layer 106 is formed by an atomic layer deposition process.
  • the conductive layer 106 has good coverage; in other embodiments, for example, the first conductive layer 106 may be formed by chemical vapor deposition at 500°C or 600°C.
  • a second conductive layer 108 filling the gap between the first conductive layers 106 is formed.
  • the top surface of the second conductive layer 108 is parallel to the top surface of the first conductive layer 106 on the support structure 102 , and the height of the top surface of the second conductive layer 108 is higher than the top surface of the first conductive layer 106 on the support structure 102 the height of the surface.
  • a second conductive film (not shown) is formed to fill the gap between the first conductive layers 106, and the height of the top surface of the second conductive film is higher than that of the top surface of the first conductive layer 106; for the second conductive film ( Not shown) chemical mechanical polishing is performed on the top surface to form the second conductive layer 108 .
  • the chemical mechanical polishing method is used to form the second conductive layer 108 , the process is simple and the cost is low, and the manufacturing efficiency of the semiconductor structure can be effectively improved.
  • the second conductive layer can also be formed by etching the second conductive film. By filling the voids between the first conductive layers 106, the discrete capacitive structures 107 have been integrated into one body.
  • a stable support structure is first formed on the semiconductor substrate, and a columnar capacitor structure is formed based on the stable support structure;
  • the height of the capacitor is greatly improved, that is, the columnar capacitor has a larger aspect ratio; and in the process of forming the columnar capacitor, there is no need to etch to form a capacitor hole with a high aspect ratio, and the process steps are more Simple and cost-effective; because there is no need to etch to form capacitor holes with high aspect ratio, the stability of the formed capacitor structure is also ensured; in addition, compared with double-sided capacitors, columnar capacitors avoid the existence of inner-layer capacitors in double-sided capacitors Typically unstable conditions, thereby increasing the yield of semiconductor structures.
  • Another embodiment of the present application relates to a method for forming a semiconductor structure.
  • the bottom conductive layer is provided to increase the size of the lower electrode.
  • the area of electrical connection with the conductive layer, in addition, the contact area is large, so that the contact resistance is small, and the signal delay of the transistor can also be reduced.
  • FIG. 12 to FIG. 19 are schematic flowcharts corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • this embodiment further includes: forming a bottom conductive layer 200 on the semiconductor substrate, and the bottom conductive layer 200 is electrically connected to the conductive layer 110 .
  • the bottom conductive layer 200 is formed on the top surface of the semiconductor substrate 100. After the support structure 102 is formed, the bottom conductive layer 200 is also located at the bottom of the support structure 102, so as to increase the distance between the lower electrode 104 and the conductive layer 110 formed subsequently. The contact area ensures the stability of the electrical connection between the formed lower electrode 104 and the conductive layer 110 .
  • discretely arranged support structures 102 can be formed on the bottom conductive layer 200 .
  • the embodiments of the present application provide the positions of two kinds of support structures 102, which are as follows:
  • Mode 1 Referring to FIG. 13 , the support structure 102 is located on the bottom conductive layer 200 , and the projection of the support structure 102 on the semiconductor substrate 100 completely covers the projection of the conductive layer 110 on the semiconductor substrate 100 .
  • the support structure 102 is located on the bottom conductive layer 200, and the projection of the support structure 102 on the semiconductor substrate 100 and the projection of the conductive layer 110 on the semiconductor substrate 100 have a non-overlapping area, that is, in the previous embodiment The positional relationship between the support structure 102 and the conductive layer 110 .
  • the embodiments of the present application take the position of the support structure 102 in the first mode as an example to perform the subsequent formation process of the capacitor structure.
  • the lower electrode 104 is formed.
  • a lower electrode 104 is formed on the sidewall of the support structure 102 , and the lower electrode 104 is electrically connected to the bottom conductive layer 200 .
  • the method further includes: etching and removing the bottom conductive layer 200 exposed at the bottom of the capacitor opening 103 .
  • a capacitor dielectric layer 105 is formed covering the top of the support structure 102 , the sidewalls of the lower electrode 104 and the bottom of the capacitor opening 103 .
  • an upper electrode covering the capacitor dielectric layer 105 is formed, and the lower electrode 104 , the capacitor dielectric layer 105 and the upper electrode together constitute a capacitor structure 107 .
  • the step of forming the upper electrode covering the capacitor dielectric layer includes:
  • a first conductive layer 106 covering the capacitive dielectric layer 105 is formed.
  • a second conductive layer 108 filling the gap between the first conductive layers 106 is formed.
  • the top surface of the second conductive layer 108 is parallel to the top surface of the first conductive layer 106 on the support structure 102 , and the height of the top surface of the second conductive layer 108 is higher than the top surface of the first conductive layer 106 on the support structure 102 the height of the surface.
  • a bottom conductive layer is formed on the top surface of the semiconductor substrate.
  • the conductive layer is also located at the bottom of the support structure, so as to increase the contact area between the lower electrode and the conductive layer formed subsequently, and to ensure that the formed lower electrode and the conductive layer are formed. Stability of electrical connections between conductive layers.
  • a stable support structure is first formed on the semiconductor substrate, and a columnar capacitor structure is formed based on the stable support structure;
  • the height of the capacitor is greatly improved, that is, the columnar capacitor has a larger aspect ratio; and in the process of forming the columnar capacitor, there is no need to etch to form a capacitor hole with a high aspect ratio, and the process steps are more Simple and cost-effective; because there is no need to etch to form capacitor holes with high aspect ratio, the stability of the formed capacitor structure is also ensured; in addition, compared with double-sided capacitors, columnar capacitors avoid the existence of inner-layer capacitors in double-sided capacitors Typically unstable conditions, thereby increasing the yield of semiconductor structures.
  • this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other structures in this embodiment.
  • Yet another embodiment of the present application relates to a semiconductor structure.
  • the semiconductor structure includes: a semiconductor substrate 100, the semiconductor substrate 100 includes at least discrete conductive layers 110; a plurality of discrete support structures 102 on the semiconductor substrate 100; and a capacitor structure 107 supported by the support structure 102, the capacitor structure 107 includes:
  • the lower electrode 104 is located on the sidewall of the support structure 102 and is electrically connected to the conductive layer 110; the capacitor dielectric layer 105 is located at the top of the support structure 102 and the bottom of the gap between the sidewall of the lower electrode 104 and the support structure 102; the upper electrode is located in the capacitor on the dielectric layer 105 .
  • the discrete conductive layers 110 are arranged in the semiconductor substrate 100 as shown in FIG. 2 .
  • the conductive layers 110 are the capacitive contact pads (landing pads) in the DRAM structure, and the conductive layers 110 are arranged in a hexagonal manner for electrically connecting the DRAM array transistor.
  • the support structure 102 provided in this embodiment may be implemented in a stacked structure, and the height of the support structure 102 formed by the stacked structure is higher, that is, the subsequently formed capacitor structure 107 has a higher aspect ratio. In other embodiments, the support structure 102 may also be implemented with a single-layer structure.
  • the gap between the support structures 102 exposes at least a portion of the top surface of each discrete conductive layer 110 ; the lower electrode 104 is used to connect the exposed top surface of the discrete conductive layer 110 .
  • the capacitor structure 107 includes: a lower electrode 104 located on the sidewall of the support structure 102 and electrically connected to the conductive layer 110; a capacitor dielectric layer 105 located at the top of the support structure 102, the sidewall of the lower electrode 104 and the bottom of the gap between the support structure 102; The upper electrode is located on the capacitor dielectric layer 105 .
  • the lower electrode 104 and the upper electrode can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the lower electrode 104 and the upper electrode The electrode is made of titanium nitride material.
  • the capacitor dielectric layer 105 is made of high dielectric constant materials, such as high dielectric constant elements such as Hf, La, Ti and Zr or their oxides, and Si and N dopants can also be used.
  • the upper electrode includes: a first conductive layer 106 and a second conductive layer 108, the first conductive layer 106 is located on the capacitive dielectric layer 105, the second conductive layer 108 fills the gap between the first conductive layers 106, and The height of the top surface of the second conductive layer 108 is higher than the height of the top surface of the first conductive layer on the support structure 102 .
  • the semiconductor structure further includes: a bottom conductive layer 200 located between the semiconductor substrate 100 and the support structure 102 for electrically connecting the conductive layer 110 and the lower electrode 104 .
  • the bottom conductive layer 200 is provided to increase the area of the electrical connection between the lower electrode 104 and the conductive layer 110 , thereby ensuring the stability of the electrical connection between the formed lower electrode 104 and the conductive layer 110 .
  • the capacitance structure of columnar capacitors is formed based on a stable support structure; due to the stable support structure, the height of columnar capacitors is greatly improved compared with double-sided capacitors, that is, columnar capacitors have more Large aspect ratio; and the process steps for forming columnar capacitors are simpler and cost-effective; since there is no need to etch to form capacitor holes with high aspect ratio, the stability of the capacitor structure of the columnar capacitors formed is also guaranteed; in addition, the columnar capacitors Compared with the double-sided capacitor, the typical instability of the inner-layer capacitance of the double-sided capacitor is avoided, thereby improving the yield of the semiconductor structure.
  • this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other structures in this embodiment.

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Abstract

本申请实施例提供一种半导体结构的形成方法及半导体结构，其中，半导体结构的形成方法包括：提供半导体基底(100)，半导体基底(100)中至少包括分立的导电层(110)；在半导体基底(100)上形成分立排布的支撑结构(102)，支撑结构(102)之间包括电容开口(103)；在支撑结构(102)的侧壁形成下电极(104)，下电极(104)电连接导电层(110)；形成覆盖支撑结构(102)顶部、下电极(104)侧壁和电容开口(103)底部的电容介质层(105)；形成覆盖电容介质层(105)的上电极，以构成电容结构(107)。本申请实施例通过形成稳定的支撑结构以形成稳定柱状电容，提高了形成的电容结构的深宽比，且形成的电容结构稳定不易倒塌，提高了半导体结构的良率。

Description

半导体结构的形成方法及半导体结构
交叉引用
本申请引用于2020年8月13日递交的名称为“半导体结构的形成方法及半导体结构”的第202010813668.3号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构的形成方法及半导体结构。
背景技术
随着动态随机存取存储器(DRAM)特征尺寸持续缩小，形成的电容器的尺寸也在不断缩小，需要通过形成高深宽比电容器的方式以保证电容器的电容，目前主要通过形成双面电容的方式来提高电容器的电容，形成高深宽比的双面电容的过程中，需要刻蚀形成高深宽比的电容孔以形成空心电容柱。
然而申请人发现：形成双面电容的过程中，若形成的双面电容的深宽比较大，在刻蚀形成空心电容柱的过程中，电容结构不稳定，容易出现倒塌的现象，且双面电容的内层电容存在电性不稳定的情况，从而影响半导体结构的良率。
发明内容
本申请实施例提供一种半导体结构的形成方法及半导体结构，通过形成稳定的支撑结构以形成稳定柱状电容，提高了形成的电容结构的深宽比，且形成的电容结构稳定不易倒塌，提高了半导体结构的良率。
为解决上述技术问题，本申请实施例提供了一种半导体结构的形成方法，包括：提供半导体基底，半导体基底中至少包括分立的导电层；在半导体基底上形成分立排布的支撑结构，支撑结构之间包括电容开口；在支撑结构的侧壁形成下电极，下电极电连接导电层；形成覆盖支撑结构顶部、下电极侧壁和电容开口底部的电容介质层；形成覆盖电容介质层的上电极，以构成电容结构。
与相关技术相比，本申请实施例通过在半导体基底上先形成稳定的支撑结构，基于稳定的支撑结构形成柱状结构的电容结构；由于具有稳定的支撑结构，形成的柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且在形成柱状电容的过程中，不需要刻蚀形成高深宽比的电容孔，工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
另外，在半导体基底上形成分立排布的支撑结构的步骤包括：在半导体基底上形成支撑层；图形化支撑层形成电容开口，剩余的支撑层构成支撑结构。
另外，电容开口至少暴露出每个分立的导电层的部分顶部表面。通过电容开口暴露出的导电层顶部表面，实现在支撑结构侧壁形成的下电极电连接导电层。
另外，半导体结构的形成方法还包括如下步骤：在形成支撑结构的步骤之前还包括：在半导体基底上形成底部导电层，底部导电层电连接导电层；形成支撑结构的步骤包括：在底部导电层上形成分立排布的支撑结构；形成下电极后且形成电容介质层前，还包括以下步骤：刻蚀去除电容开口底部暴露出的底部导电层。在形成支撑结构之前，在半导体基底顶部表面形成底部导电层， 形成支撑结构之后，导电层还位于支撑结构底部，以增大后续形成的下电极与导电层的接触面积，保证形成的下电极与导电层之间的电连接的稳定性。
另外，支撑结构为依次堆叠形成的堆叠结构。
另外，堆叠结构包括依次堆叠形成的底支撑层和填充层。通过依次堆叠形成的薄层的过程，避免了单次沉积形成厚度较大的薄层，保证形成的薄层的致密性更好，且通过依次堆叠形成的薄层，保证了支撑结构的具有较高的高度，从而增加后续形成的柱状电容的深宽比。
另外，图形化支撑层形成多个分立的电容开口的步骤包括：在支撑层上依次形成掩膜层和图形化的光刻胶层；基于光刻胶层，图形化掩膜层；基于图形化后的掩膜层，刻蚀支撑层形成电容开口。
另外，在支撑结构的侧壁形成电连接一导电层的下电极的步骤包括：在支撑结构顶部和侧壁以及电容开口底部形成顶导电层；去除位于支撑结构顶部以及电容开口底部的顶导电层，形成位于支撑结构侧壁的下电极。
另外，去除位于支撑结构顶部的顶导电层的方式包括化学机械研磨。
另外，半导体结构的形成方法，其特征在于，还包括以下步骤：形成覆盖电容介质层的上电极的步骤包括：形成覆盖电容介质层的第一导电层；形成填充第一导电层之间间隙的第二导电层，第二导电层顶部表面与位于支撑结构上的第一导电层的顶部表面平行，且第二导电层顶部表面的高度高于位于支撑结构上的第一导电层顶部表面的高度。
另外，形成填充第一导电层之间间隙的第二导电层包括以下步骤：形成填充第一导电层之间间隙的第二导电膜，第二导电膜顶部表面的高度高于位于支撑结构上的第一导电层顶部表面的高度；对第二导电膜顶部表面进行化学机 械研磨处理，以形成第二导电层。
本申请实施例还提供了一种半导体结构，包括：半导体基底，半导体基底中至少包括分立的导电层；多个分立的支撑结构，位于半导体基底上；以及通过支撑结构支撑的电容结构，电容结构包括：下电极，位于支撑结构的侧壁，且电连接导电层；电容介质层，位于支撑结构顶部、下电极侧壁和支撑结构之间的间隙底部；上电极，位于电容介质层上。
另外，支撑结构之间的间隙至少暴露出每个分立的导电层的部分顶部表面；下电极用于连接暴露出的分立的导电层的顶部表面。
另外，半导体结构还包括：底部导电层，位于半导体基底和支撑结构之间，用于电连接导电层和下电极。
与双面电容的电容结构相比，柱状电容的电容结构基于稳定的支撑结构形成；由于具有稳定的支撑结构，柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且形成柱状电容的工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的柱状电容的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
附图说明
图1至图11为本申请一实施例提供的半导体结构的形成方法的各步骤对应的半导体结构的剖面结构示意图；
图12至图19为本申请另一实施例提供的半导体结构的形成方法的各步骤对应的半导体结构的剖面结构示意图。
具体实施方式
目前，形成双面电容的过程中，若形成的双面电容的深宽比较大，在刻蚀形成空心电容柱的过程中，电容结构不稳定，容易出现倒塌的现象，且双面电容的内层电容存在电性不稳定的情况，从而影响半导体结构的良率。
为解决上述问题，本申请一实施例提供了一种半导体结构的形成方法，包括：提供半导体基底，半导体基底中至少包括分立的导电层；在半导体基底上形成分立排布的支撑结构，支撑结构之间包括电容开口；在支撑结构的侧壁形成下电极，下电极电连接导电层；形成覆盖支撑结构顶部、下电极侧壁和电容开口底部的电容介质层；形成覆盖电容介质层的上电极，以构成电容结构。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图11为本申请实施例提供的半导体结构的形成方法各步骤对应的流程示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
需要说明的是，本实施例以存储器中的半导体结构为例进行具体介绍，即本实施例中所要保护的半导体结构形成在DRAM存储器或SRAM存储器中。
参考图1和图6，提供半导体基底100，在半导体基底100上形成分立排布的支撑结构102。
参考图1，半导体基底100中至少包括分立的导电层110。
分立的导电层110在半导体基底100中排布方式如图2所示，导电层110即DRAM结构中的电容接触垫(landing pad),导电层110呈六方排布，用于电连接DRAM的阵列晶体管。
继续参考图1，在半导体基底100上形成支撑层101，支撑层101用于后续刻蚀形成支撑结构102。
在本实施例中，支撑层101包括依次堆叠形成的底支撑层111和填充层121。通过依次堆叠形成的支撑层101，避免了单次沉积形成厚度较大的支撑层101，保证形成的支撑层101的致密性更好，且通过依次堆叠形成支撑层101，保证了后续形成的支撑结构102的总体具有较高的高度，从而增加后续形成的柱状电容的深宽比。另外，在本实施例中，底支撑层111和填充层121采用不同的绝缘材料形成。
需要说明的是，支撑层101通过底支撑层111和填充层121实现，仅是为了体现本实施例提供的支撑层101可以通过堆叠结构的方式实现，本实施例并不对底支撑层111和填充层121进行厚度限定。在其他实施例中，支撑层也可以采用单层结构实现，即后续形成的支撑结构为单层结构，支撑层也可以采用三层及三层以上的堆叠结构实现，以这种方式形成的堆叠结构的高度更高，即后续形成的支撑结构102具有更高的高度。
参考图3～图6，图形化支撑层101形成电容开口103，剩余的支撑层101构成支撑结构102。
参考图3，在支撑层101上依次形成掩膜层120和图形化的光刻胶层130。
参考图4，基于图形化的光刻胶层130图形化掩膜层120。
参考图5，基于图形化后的掩膜层120，刻蚀支撑层101形成电容开口 103。
在本实施例中，电容开口103至少暴露出每个分立的导电层110的部分顶部表面。在本实施例中，电容开口103与导电层110的顶部形貌分布如图6所示，刻蚀电容开口103后剩余的支撑层101作为支撑结构102，即在本实施例中，支撑结构102为依次堆叠形成的堆叠结构，且堆叠结构包括依次堆叠形成的底支撑层111填充层121。
刻蚀形成电容开口103之后还包括：依次去除光刻胶层130和掩膜层120。
具体地，采用第一干法清洗工艺去除光刻胶层130，第一干法清洗工艺采用氨气、氮气和氢气的混合气体，混合气体与光刻胶层130反应生成第一固化物，然后通过高温蒸发的方式蒸发第一固化物，即完成光刻胶层130的去除。
需要说明的是，在本实施例中采用氨气、氮气和氢气的混合气体与光刻胶层130反应生成第一固化物的过程中，由于混合气体中不含有氧气，且阻止了支撑结构102与空气相接触，在去除光刻胶层130的同时，防止支撑结构102侧壁的自然氧化。
在去除光刻胶层130之后，采用第一湿法清洗工艺去除掩膜层120，第一湿法清洗工艺采用49％HF以及1:1:60APM(H 2O 2:NH 4OH:H 2O＝1:1:60)的混合溶液，混合溶液与掩膜层120发生化学反应以去除掩膜层120。
需要说明的是，在本实施例中采用49％HF以及1:1:60APM的混合溶液与掩膜层120反应去除掩膜层120的过程中，由于混合液体中含有NH 4OH，会电离出OH -，由于OH -的负电荷排斥作用以及H 2O 2的氧化性，可以去除支撑结构102侧壁的颗粒物。
参考图7～图11，基于支撑结构102形成电容结构107。
具体地，参考图7～图8，在支撑结构102的侧壁形成下电极104，下电极104电连接导电层110。
下电极104可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极104采用氮化钛材料。
参考图7，在支撑结构102顶部和侧壁以及电容开口103底部形成顶导电层114。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成顶导电层114，在本实施例中，采用原子层沉积工艺的方式形成顶导电层114，采用原子层沉积工艺形成的顶导电层114具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成顶导电层。
需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图8，区域位于支撑结构102顶部以及电容开口103底部的顶导电层114，形成于支撑结构102侧壁的下电极104。
具体地，去除位于支撑结构102顶部的顶导电层114的方式包括化学机械研磨。采用化学机械研磨的方式去除支撑结构的顶导电层114，流程简单且成本低廉，可以有效提高电容结构的制造效率。在其他实施例中，也可以通过刻蚀的方式对顶导电层进行平坦化处理。
参考图9，形成覆盖支撑结构102顶部、下电极104侧壁和电容开口103底部的电容介质层105。
电容介质层105为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成电容介质层105，在本实施例中，采用原子层沉积工艺的方式形成电容介质层105，采用原子层沉积工艺形成的电容介质层105具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成电容介质层。
需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
参考图10～图11，形成覆盖电容介质层105的上电极，下电极104、电容介质层105和上电极共同构成电容结构107。
具体地，形成覆盖电容介质层的上电极的步骤包括：
参考图10，形成覆盖电容介质层105的第一导电层106。
第一导电层106可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，第一导电层106采用氮化钛材料。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成第一导电层106，在本实施例中，采用原子层沉积工艺的方式形成第一导电层106，采用原子层沉积工艺形成的第一导电层106具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成第一导电层106。
需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符 合上述范围中的参数都应落入本申请的保护范围中。
参考图11，形成填充第一导电层106之间间隙的第二导电层108。其中，第二导电层108顶部表面与位于支撑结构102上的第一导电层106的顶部表面平行，且第二导电层108顶部表面的高度高于位于支撑结构102上的第一导电层106顶部表面的高度。
具体地，形成填充第一导电层106之间间隙的第二导电膜(未图示)，第二导电膜顶部表面的高度高于第一导电层106顶部表面的高度；对第二导电膜(未图示)顶部表面进行化学机械研磨处理，以形成第二导电层108。
采用化学机械研磨的方式形成第二导电层108，流程简单且成本低廉，可以有效提高半导体结构的制造效率。在其他实施例中，也可以通过刻蚀第二导电膜以形成第二导电层。通过填充第一导电层106之间的空隙，已将分立的电容结构107构成一个整体。
与相关技术形成双面电容的方式相比，本申请实施例通过在半导体基底上先形成稳定的支撑结构，基于稳定的支撑结构形成柱状结构的电容结构；由于具有稳定的支撑结构，形成的柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且在形成柱状电容的过程中，不需要刻蚀形成高深宽比的电容孔，工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本 专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种半导体结构的形成方法，与上述实施例不同的是，本实施例为了保证下电极与导电层的电连接的稳定性，通过设置底部导电层以增大下电极与导电层电连接的面积，另外，接触面积大，使得接触电阻小，还可以降低晶体管的信号延迟。
图12至图19为本申请实施例提供的半导体结构的形成方法各步骤对应的流程示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
参考图12，与上述实施例相比，本实施例在形成支撑层101之前，还包括：在半导体基底上形成底部导电层200，底部导电层200电连接导电层110。
在形成支撑结构102之前，在半导体基底100顶部表面形成底部导电层200，形成支撑结构102之后，底部导电层200还位于支撑结构102底部，以增大后续形成的下电极104与导电层110的接触面积，保证形成的下电极104与导电层110之间的电连接的稳定性。
参考图13和图14，在底部导电层200上能形成分立排布的支撑结构102。本申请实施例给出了两种支撑结构102的位置，具体如下：
方式一：参考图13，支撑结构102位于底部导电层200上，且支撑结构102在半导体基底100上的投影完全覆盖导电层110在半导体基底100上的投影。
方式二：参考图14，支撑结构102位于底部导电层200上，且支撑结构102在半导体基底100上的投影和导电层110在半导体基底100上的投影存在不重叠区域，即上一实施例中支撑结构102与导电层110的位置关系。
参考图15～18本申请实施例以方式一的支撑结构102的位置为例进行后续电容结构的形成过程。
具体地，参考图15和图16，形成下电极104。在支撑结构102的侧壁形成下电极104，下电极104电连接底部导电层200。形成下电极104之后，且形成电容介质层105前，还包括：刻蚀去除电容开口103底部暴露出的底部导电层200。
参考图17，形成覆盖支撑结构102顶部、下电极104侧壁和电容开口103底部的电容介质层105。
参考图18～图19，形成覆盖电容介质层105的上电极，下电极104、电容介质层105和上电极共同构成电容结构107。
具体地，形成覆盖电容介质层的上电极的步骤包括：
参考图18，形成覆盖电容介质层105的第一导电层106。
参考图19，形成填充第一导电层106之间间隙的第二导电层108。其中，第二导电层108顶部表面与位于支撑结构102上的第一导电层106的顶部表面平行，且第二导电层108顶部表面的高度高于位于支撑结构102上的第一导电层106顶部表面的高度。
在形成支撑结构之前，在半导体基底顶部表面形成底部导电层，形成支撑结构之后，导电层还位于支撑结构底部，以增大后续形成的下电极与导电层的接触面积，保证形成的下电极与导电层之间的电连接的稳定性。
与相关技术形成双面电容的方式相比，本申请实施例通过在半导体基底上先形成稳定的支撑结构，基于稳定的支撑结构形成柱状结构的电容结构；由于具有稳定的支撑结构，形成的柱状电容的高度相比于双面电容有极大的提高， 即柱状电容具有更大的深宽比；且在形成柱状电容的过程中，不需要刻蚀形成高深宽比的电容孔，工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的结构。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请又一实施例涉及一种半导体结构。
参考图11和图19，以下将结合附图对本实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
半导体结构包括：半导体基底100，半导体基底100中至少包括分立的导电层110；多个分立的支撑结构102，位于半导体基底100上；以及通过支撑 结构102支撑的电容结构107，电容结构107包括：下电极104，位于支撑结构102的侧壁，且电连接导电层110；电容介质层105，位于支撑结构102顶部、下电极104侧壁和支撑结构102之间的间隙底部；上电极，位于电容介质层105上。
分立的导电层110在半导体基底100中排布方式如图2所示，导电层110即DRAM结构中的电容接触垫(landing pad),导电层110呈六方排布，用于电连接DRAM的阵列晶体管。
本实施例提供的支撑结构102可以通过堆叠结构的方式实现，以堆叠结构形成支撑结构102的高度更高，即后续形成的电容结构107具有更高的深宽比。在其他实施例中，支撑结构102也可以采用单层结构实现。
具体地，支撑结构102之间的间隙至少暴露出每个分立的导电层110的部分顶部表面；下电极104用于连接暴露出的分立的导电层110的顶部表面。
电容结构107包括：下电极104，位于支撑结构102的侧壁，且电连接导电层110；电容介质层105，位于支撑结构102顶部、下电极104侧壁和支撑结构102之间的间隙底部；上电极，位于电容介质层105上。
下电极104和上电极可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极104和上电极采用氮化钛材料。电容介质层105为高介电常数材料，例如Hf、La、Ti和Zr等高介电常数的元素或其氧化物，也可以采用Si和N的掺杂剂。
在本实施例中，上电极包括：第一导电层106和第二导电层108，第一导电层106位于电容介质层105上，第二导电层108填充第一导电层106之间间隙，且第二导电层108顶部表面的高度高于位于支撑结构102上的第一导电 层顶部表面的高度。
在一个例子中，参考图19，半导体结构还包括：底部导电层200，位于半导体基底100和支撑结构102之间，用于电连接导电层110和下电极104。通过设置底部导电层200以增大下电极104与导电层110电连接的面积，从而，保证形成的下电极104与导电层110之间的电连接的稳定性。
与双面电容的电容结构相比，柱状电容的电容结构基于稳定的支撑结构形成；由于具有稳定的支撑结构，柱状电容的高度相比于双面电容有极大的提高，即柱状电容具有更大的深宽比；且形成柱状电容的工艺步骤更加简单，节约成本；由于不需要刻蚀形成高深宽比的电容孔，还保证了形成的柱状电容的电容结构的稳定性；另外，柱状电容相比于双面电容，避免了双面电容的内层电容存在典型不稳定的情况，从而提高了半导体结构的良率。
为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的结构。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种半导体结构的形成方法，其特征在于，包括如下步骤：
    提供半导体基底，所述半导体基底中至少包括分立的导电层；
    在所述半导体基底上形成分立排布的支撑结构，所述支撑结构之间包括电容开口；
    在所述支撑结构的侧壁形成下电极，所述下电极电连接所述导电层；
    形成覆盖所述支撑结构顶部、所述下电极侧壁和所述电容开口底部的电容介质层；
    形成覆盖所述电容介质层的上电极，以构成电容结构。
  2. 根据权利要求1所述的半导体结构的形成方法，在所述半导体基底上形成分立排布的支撑结构的步骤包括：
    在所述半导体基底上形成支撑层；
    图形化所述支撑层形成所述电容开口，剩余的所述支撑层构成所述支撑结构。
  3. 根据权利要求2所述的半导体结构的形成方法，所述电容开口至少暴露出每个分立的所述导电层的部分顶部表面。
  4. 根据权利要求1所述的半导体结构的形成方法，其特征在于，还包括如下步骤：
    在形成所述支撑结构的步骤之前还包括：在所述半导体基底上形成底部导电层，所述底部导电层电连接所述导电层；
    形成所述支撑结构的步骤包括：在所述底部导电层上形成分立排布的所述支撑结构；
    形成所述下电极后且形成所述电容介质层前，还包括以下步骤：刻蚀去除所述电容开口底部暴露出的所述底部导电层。
  5. 根据权利要求1中所述的半导体结构的形成方法，其特征在于，所述支撑结 构为依次堆叠形成的堆叠结构。
  6. 根据权利要求5所述的半导体结构的形成方法，其特征在于，所述堆叠结构包括依次堆叠形成的底支撑层和填充层。
  7. 根据权利要求2所述的半导体结构的形成方法，其特征在于，图形化所述支撑层形成多个分立的所述电容开口的步骤包括：
    在所述支撑层上依次形成掩膜层和图形化的光刻胶层；
    基于所述光刻胶层，图形化所述掩膜层；
    基于图形化后的所述掩膜层，刻蚀所述支撑层形成所述电容开口。
  8. 根据权利要求1所述的半导体结构的形成方法，其特征在于，在所述支撑结构的侧壁形成电连接一所述导电层的下电极的步骤包括：
    在所述支撑结构顶部和侧壁以及所述电容开口底部形成顶导电层；
    去除位于所述支撑结构顶部以及所述电容开口底部的所述顶导电层，形成位于所述支撑结构侧壁的下电极。
  9. 根据权利要求8所述的半导体结构的形成方法，其特征在于，所述去除位于所述支撑结构顶部的所述顶导电层的方式包括化学机械研磨。
  10. 根据权利要求1所述的半导体结构的形成方法，其特征在于，形成覆盖所述电容介质层的上电极的步骤包括：
    形成覆盖所述电容介质层的第一导电层；
    形成填充所述第一导电层之间间隙的第二导电层，所述第二导电层顶部表面与位于所述支撑结构上的所述第一导电层的顶部表面平行，且所述第二导电层顶部表面的高度高于位于所述支撑结构上的所述第一导电层顶部表面的高度。
  11. 根据权利要求10所述的半导体结构的形成方法，其特征在于，形成填充所述第一导电层之间间隙的第二导电层包括以下步骤：
    形成填充所述第一导电层之间间隙的第二导电膜，所述第二导电膜顶部表面的高度高于位于所述支撑结构上的所述第一导电层顶部表面的高度；
    对所述第二导电膜顶部表面进行化学机械研磨处理，以形成所述第二导电层。
  12. 一种半导体结构，其特征在于，包括：
    半导体基底，所述半导体基底中至少包括分立的导电层；
    多个分立的支撑结构，位于所述半导体基底上；
    以及通过所述支撑结构支撑的电容结构，所述电容结构包括：
    下电极，位于所述支撑结构的侧壁，且电连接所述导电层；
    电容介质层，位于所述支撑结构顶部、所述下电极侧壁和所述支撑结构之间的间隙底部；
    上电极，位于所述电容介质层上。
  13. 根据权利要求12所述的半导体结构，其特征在于，所述支撑结构之间的间隙至少暴露出每个分立的所述导电层的部分顶部表面；所述下电极用于连接暴露出的分立的导电层的顶部表面。
  14. 根据权利要求12所述的半导体结构，其特征在于，所述上电极包括：
    第一导电层，位于所述电容介质层上；
    第二导电层，填充所述第一导电层之间间隙，且所述第二导电层顶部表面的高度高于位于所述支撑结构上的第一导电层顶部表面的高度。
  15. 根据权利要求12所述的半导体结构，其特征在于，还包括：底部导电层，位于所述半导体基底和所述支撑结构之间，用于电连接所述导电层和所述下电极。
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CN110957303A (zh) * 2018-09-26 2020-04-03 长鑫存储技术有限公司 电容器及其形成方法、半导体器件及其形成方法
CN110957317A (zh) * 2018-09-26 2020-04-03 长鑫存储技术有限公司 电容器及其形成方法、半导体器件及其形成方法

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