WO2022022030A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022022030A1
WO2022022030A1 PCT/CN2021/095610 CN2021095610W WO2022022030A1 WO 2022022030 A1 WO2022022030 A1 WO 2022022030A1 CN 2021095610 W CN2021095610 W CN 2021095610W WO 2022022030 A1 WO2022022030 A1 WO 2022022030A1
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layer
support
support layer
forming
stacked structure
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PCT/CN2021/095610
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English (en)
French (fr)
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吴承恩
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长鑫存储技术有限公司
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Priority to US17/444,058 priority Critical patent/US11935917B2/en
Publication of WO2022022030A1 publication Critical patent/WO2022022030A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • the main principle of action is to use the amount of charge stored in a capacitor to represent a binary bit (bit). Therefore, the arrangement of the positions of the formed capacitors and the positional relationship between the capacitors and other structures are very important in the formation process of the DRAM.
  • the capacitor is mainly supported and placed by a stack structure, so as to avoid the dumping problem of the capacitor in the DRAM.
  • the applicant found that the arrangement of the stack structure in the related art is not firm, and the collapse of the stack structure will lead to the scrapping of the entire DRAM, thereby seriously affecting the yield of the DRAM.
  • Embodiments of the present application provide a method for forming a semiconductor structure and a semiconductor structure. By strengthening the stacked structure, the problem of collapse of the stacked structure is prevented, thereby improving the yield of the DRAM.
  • the embodiments of the present application provide a method for forming a semiconductor structure, including: providing a substrate, the substrate at least including a conductive layer; the top surface of the substrate has a bottom support layer and a stack structure on the top surface of the bottom support layer,
  • the stacked structure includes a sacrificial layer and a support part formed by stacking in sequence; part of the stacked structure and the underlying support layer are etched to expose the conductive layer to form a through hole; the part of the width of the support part exposed by the sidewall of the through hole is laterally etched to form a gap forming a protective layer filling the voids; forming a lower electrode electrically connected to the conductive layer on the sidewalls of the through holes and the sidewalls of the protective layer; removing the sacrificial layer.
  • the oxidized support portion is etched in the subsequent step of removing the sacrificial portion, resulting in voids at the edge of the support portion, thereby causing the collapse of the stacked structure.
  • the present application manufactures a protective layer on the edge of the support portion to prevent the edge of the support portion from being oxidized.
  • the subsequent step of removing the sacrificial portion since the edge of the support portion is not oxidized, it will not be etched. Therefore, the stability of the support portion is ensured, and the DRAM yield is improved by forming a stable stack structure.
  • the stacked structure includes a first stacked structure and a second stacked structure formed in sequence; the first stacked structure is located on the top surface of the bottom support layer, the first stacked structure includes a first sacrificial layer and an intermediate support part formed in sequence; the second stacked structure Located on the top surface of the first stack structure, the second stack structure includes a second sacrificial layer and a top support part formed in sequence; laterally etching the part of the width of the support part exposed by the sidewall of the through hole, and forming a gap includes: laterally etching the through hole The exposed part of the width of the middle support part of the side wall forms a gap.
  • the intermediate support part includes: a first support layer, a buffer layer and a second support layer are formed by stacking in sequence.
  • the first support layer is used to support the second support layer and the buffer layer
  • the buffer layer is used to separate the first support layer and the second support layer
  • the buffer layer is also used for anti-oxidation
  • the second support layer is used to prevent the buffer layer. and the first support layer is oxidized.
  • the materials of the second support layer and the first support layer include silicon carbonitride
  • the nitrogen content in the second support layer is greater than that of the first support layer
  • the material of the buffer layer includes silicon nitride.
  • the materials of the second support layer and the first support layer include silicon carbonitride
  • the carbon content of the first support layer is greater than that of the second support layer
  • the material of the buffer layer includes silicon nitride.
  • the thickness relationship of the first support layer, the buffer layer and the second support layer is formed in the range of 2:1:2 ⁇ first support layer:buffer layer:second support layer ⁇ 10:1:2.
  • removing the sacrificial layer includes: forming a plurality of first openings on the remaining top support parts, the first openings expose the second sacrificial layer, and removing the second sacrificial layer; etching the middle support parts along the first openings to support the remaining middle support parts A plurality of second openings are formed on the portion, the second openings expose the first sacrificial layer, and the first sacrificial layer is removed.
  • the entirety of the first opening and the entirety of the second opening are arranged radially.
  • the entirety of the first opening and the second opening is arranged in a radial shape, which can reduce the overall arrangement quantity of the first opening and the second opening, and further ensure the stability of the stacked structure.
  • the width of the formed protective layer corresponds to the width of the void.
  • forming the protective layer to fill the gap includes: forming a protective film on the sidewall of the through hole, and the formed protective film also fills the gap; removing the protective film on the sidewall of the through hole and retaining the protective film in the gap to form the protective layer.
  • Embodiments of the present application further provide a semiconductor structure, comprising: a substrate, the substrate includes at least a conductive layer; a bottom support layer, located on the top surface of the substrate; a layer and a supporting part; a through hole, located in the stacked structure, and exposing the conductive layer; a lower electrode, located on the sidewall of the through hole and electrically connected to the conductive layer; a protective layer, located between the lower electrode and the supporting part.
  • the stacked structure includes a first stacked structure and a second stacked structure; the first stacked structure is located on the top surface of the bottom support layer, the first stacked structure includes a first sacrificial layer and an intermediate support part formed in sequence; the second stacked structure is located on the first On the top surface of the stack structure, the second stack structure includes a second sacrificial layer and a top support part formed in sequence; the protection layer is located between the lower electrode and the middle support part.
  • the intermediate support part includes: a first support layer, a buffer layer and a second support layer; wherein, the first support layer and the second support layer are located on surfaces of opposite sides of the buffer layer, and the first support layer is close to the substrate, and the first support layer is The surfaces of the support layer and the second support layer away from the buffer layer are connected to the sacrificial layer.
  • the thickness relationship between the first support layer, the buffer layer and the second support layer is in the range of 2:1:2 ⁇ first support layer:buffer layer:second support layer ⁇ 10:1:2.
  • the thickness of the first support layer is 4 nm to 20 nm
  • the thickness of the buffer layer is 1 nm to 6 nm
  • the thickness of the second support layer is 2 nm to 12 nm.
  • the materials of the second support layer and the first support layer include silicon carbonitride, and the nitrogen content in the second support layer is greater than that of the first support layer; the material of the buffer layer includes silicon nitride.
  • the materials of the second support layer and the first support layer include silicon carbonitride, and the carbon content of the first support layer is greater than that of the second support layer; the material of the buffer layer includes silicon nitride.
  • the present application uses a protective layer to prevent the edge of the support portion from being oxidized. Since the edge of the support portion is not oxidized and will not be removed by etching, the stability of the support portion is ensured. A solid stack structure is formed, which improves the DRAM yield.
  • FIG. 1 to 11 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application;
  • FIG. 12 is a schematic cross-sectional structure diagram corresponding to a method for forming a semiconductor structure provided by another embodiment of the present application.
  • the capacitors are mainly supported and placed by the stack structure, so as to avoid the dumping problem of the capacitors in the DRAM.
  • the setting of the stack structure in the related art is not firm. The collapse of the stack structure will lead to the scrapping of the entire DRAM, which will seriously affect the DRAM performance Yield.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate at least including a conductive layer; the top surface of the substrate has a bottom support layer and a stack structure on the top surface of the bottom support layer,
  • the stacked structure includes a sacrificial layer and a support part formed by stacking in sequence; part of the stacked structure and the underlying support layer are etched to expose the conductive layer to form a through hole; the part of the width of the support part exposed by the sidewall of the through hole is laterally etched to form a gap forming a protective layer filling the voids; forming a lower electrode electrically connected to the conductive layer on the sidewalls of the through holes and the sidewalls of the protective layer; removing the sacrificial layer.
  • FIGS. 1 to 11 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • a substrate 101 is provided, and the substrate 101 includes at least a conductive layer 111 therein.
  • the material of the substrate 101 may include silicon, silicon carbide, silicon nitride, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.; in this embodiment, the substrate 101 is made of silicon material, and it is clear to those skilled in the art that the use of silicon material as the substrate 101 in this embodiment is to facilitate those skilled in the art to understand the subsequent formation method, and It does not constitute a limitation, and in the actual application process, a suitable substrate material can be selected according to the requirements.
  • the conductive layer 111 may be made of a single conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a tungsten compound.
  • the layer 111 is used to electrically connect the lower electrode to be formed later, so as to realize the electrical connection between the capacitor structure and the substrate 101 to be formed later.
  • the substrate 101 also includes other semiconductor structures other than the conductive layer 111, such as shallow trench isolation structures, word line structures, active regions, etc. Since other semiconductor structures do not involve the core technology of the present application, It will not be repeated here; those skilled in the art can understand that the substrate 101 further includes other semiconductor structures except the conductive layer 111 to ensure the normal operation of the semiconductor structures.
  • the top surface of the substrate 101 has a bottom support layer 102 and a stack structure 103 located on the top surface of the bottom support layer 102 .
  • the stack structure 103 includes a sacrificial layer and a support portion formed by stacking in sequence.
  • the stacked structure 103 includes a first stacked structure 1031 and a second stacked structure 1032 formed in sequence; wherein, the first stacked structure 1031 is located on the top surface of the underlying support layer 102, and the first stacked structure 1031 includes a sequentially formed first stacked structure 1031.
  • the bottom support layer 102 is located on the top surface of the substrate 101 to prevent the subsequently formed stack structure 103 from being electrically connected to the substrate 101 , and the bottom support layer 102 serves as the bottom structure of the stack structure 103 to reinforce the subsequently formed stack structure 103 .
  • the material of the underlying support layer 102 includes silicon nitride or silicon oxynitride. In this embodiment, the material of the underlying support layer 102 is silicon nitride.
  • a first opening needs to be formed on the top support portion to etch the sacrificial layer 113 .
  • the material of the intermediate support portion 123 is exposed to the air and is easily oxidized to form an oxide layer.
  • the oxide layer is sandwiched between the intermediate support portion 123 and the lower electrode.
  • the sacrificial layer 113 is used for the subsequent formation of the air gap, and the space gap is used for the subsequent formation of the dielectric layer and the upper electrode. After the sacrificial layer 113 is removed and before the dielectric layer and the upper electrode are formed, the stack structure 103 is hollowed out, so it is necessary to ensure the stacking Stability of structure 103.
  • a sacrificial layer 113 is formed on the top surface of the bottom support layer 102, and the material of the sacrificial layer 113 is boron and phosphorus doped silicon dioxide (BPSG) or an oxygen-containing material, and subsequently, in the process of removing the sacrificial layer 113 to form an air gap , the sacrificial layer can be removed by targeted etching using a wet etching process. Due to the pertinence of the wet etching process, the top support portion 163, the middle support portion 123 and the bottom support layer 102 will not be etched during the process of removing the sacrificial layer 113; thus, the process of forming an air gap is avoided. , the collapse phenomenon of the stack structure 103 occurs.
  • BPSG boron and phosphorus doped silicon dioxide
  • the intermediate support portion 123 includes a first support layer 133 , a buffer layer 143 and a second support layer 153 that are sequentially stacked.
  • a first support layer 133 is formed on the top surface of the first sacrificial layer, and the first support layer 133 is mainly used to support the capacitor structure formed later; in one example, the materials of the first support layer 133 and the second support layer 153 It includes silicon carbonitride, and the carbon content in the first support layer 133 is greater than the carbon content in the second support layer 153. Due to the high carbon content, the first support layer 133 has a strong hardness to support the capacitance structure in the later stage. . In another example, the nitrogen content of the second support layer 153 may be greater than the nitrogen content of the first support layer 133 to ensure that the carbon content of the first support layer 133 is greater than that of the second support layer 153 .
  • the above-mentioned first support layer 133 is formed by the first chemical vapor deposition (CVD) method.
  • the mixed gas used in the first chemical vapor deposition includes: carbon-containing gas TMS, SIH 4 , NH 3 and N 2 .
  • the flow rate of carbon gas TMS is used to control the level of carbon content in the deposited SiCN.
  • a buffer layer 143 is formed on the top surface of the first support layer 143, the buffer layer 143 is used to separate the first support layer 133 and the second support layer 153, and the buffer layer 143 is also used for anti-oxidation; in one example, the buffer layer 143 Materials include silicon nitride.
  • a second support layer 153 is formed on the top surface of the buffer layer 143, and the second support layer 153 is used to prevent the intermediate support portion 123 from being oxidized; in one example, the materials of the first support layer 133 and the second support layer 153 include carbonitride silicon, and the nitrogen content of the second support layer 153 is greater than that of the first support layer 133. Due to the high nitrogen content, the second support layer 153 has strong oxidation resistance to prevent the second support layer 153 from being oxidized . In another example, the nitrogen content of the second support layer 153 may be greater than that of the first support layer 133 by ensuring that the carbon content of the first support layer 133 is greater than that of the second support layer 153 .
  • the above-mentioned second support layer 153 is formed by the second chemical vapor deposition method.
  • the mixed gas used in the second chemical vapor deposition includes: carbon-containing gas TMS, SIH 4 , NH 3 and N 2 .
  • the flow rate is used to control the nitrogen content in the deposited SiCN.
  • the stability of the intermediate support portion 123 is improved by setting the first support layer 133 as a silicon carbonitride layer with a higher carbon content; the second support layer 153 is set as a silicon carbonitride layer with a higher nitrogen content to The intermediate support portion 123 is prevented from being oxidized after the capacitor hole is etched, so as to prevent the oxidized portion of the intermediate support portion 123 from being etched by DHF when the sacrificial layer is etched. Meanwhile, the buffer layer 143 can further improve the oxidation resistance of the intermediate support portion 123 .
  • the thickness relationship between the first support layer 133, the buffer layer 143 and the second support layer 153 is formed in the range of 2:1:2 ⁇ first support layer 133:buffer layer 143:second support layer 153 ⁇ 10:1:2.
  • the thickness of the first support layer 133 is 4 nm ⁇ 30 nm, eg, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm or 30 nm; the thickness of the buffer layer 143 is 1 nm ⁇ 6 nm, eg, 1 nm, 2 nm, 3 nm, 4 nm , 5 nm or 6 nm; the thickness of the second support layer 153 is 2 nm ⁇ 12 nm, for example, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm or 12 nm.
  • the above examples of the thicknesses of the first support layer 133 , the buffer layer 143 and the second support layer 153 are only schematic representations of the thicknesses of the first support layer 133 , the buffer layer 143 and the second support layer 153 in this embodiment.
  • the description does not constitute a limitation to the embodiments of the present application.
  • the intermediate support portion can also be formed in a double-layer structure, and the material of the intermediate support portion includes a combination of silicon carbonitride and silicon nitride, that is, the silicon nitride is disposed above the silicon carbonitride, and the carbonitride
  • the silicon can be set to gradually increase in nitrogen content from bottom to top surface, or gradually decrease in carbon content.
  • this embodiment takes the first stack structure 1031 and the second stack structure 1032 as examples to introduce the method for forming the semiconductor structure. one or more than three.
  • the orthographic projection of the conductive layer 111 and the middle support portion 123 on the substrate 101 has an overlapping area, so as to ensure that the subsequent process can easily form through holes in the middle support portion 123 to expose the conductive layer 111 , thereby forming a lower layer electrically connected to the conductive layer 111 . electrode.
  • FIG. 2 is a schematic cross-sectional view of the through holes 104 formed by etching
  • FIG. 3 is a top view of the through holes 104 formed by etching, to show the arrangement of the through holes 104
  • FIG. 4 is a three-dimensional perspective view of the formed through holes 104; It should be noted that this embodiment takes the circular through hole 104 as an example for illustration.
  • the through hole may be in the shape of a triangle, a quadrilateral or a pentagon, and the shape of the through hole 104 is not specified in this embodiment Specifically, the shape of the through hole 104 can be set according to actual requirements.
  • a portion of the width of the middle support portion 123 exposed from the sidewall of the through hole 104 is laterally etched along the sidewall of the through hole 104 to form a void 105 .
  • the intermediate support portion 123 with a preset thickness is removed by etching.
  • wet etching can be used to remove the intermediate support portion 123 with a preset thickness.
  • DSP and IPA are used to remove the intermediate support portion 123 with a preset thickness.
  • Intermediate support portion 123 .
  • chemical dry etching may also be used to remove the intermediate support portion 123 with a predetermined thickness.
  • the etched middle support portion 123 includes the oxidized middle support portion 123, and the remaining middle support portion 123 does not include the oxidized portion.
  • the specific etching width needs to be set according to the degree of oxidation of the middle support portion 123. Certainly.
  • a protective layer 106 filling the voids is formed.
  • a protective film 116 is formed on the sidewall of the through hole 104 , and the formed protective film 116 fills the void 105 .
  • the secondary oxidation of the middle support portion 123 is avoided by adopting N 2 protection.
  • the material of the protective film 116 and the protective layer 106 is silicon nitride.
  • the protective film 116 is formed by atomic layer deposition (ALD).
  • the protective film 116 formed by the atomic layer deposition process has good coverage.
  • the protective layer 106 is fabricated on the edge of the intermediate support portion 123 to prevent the edge of the intermediate support portion 123 from being oxidized. In the subsequent step of removing the sacrificial portion 113, since the edge of the intermediate support portion 123 is not oxidized, it will not be etched Therefore, the stability of the intermediate support portion 123 is ensured, and a stable stack structure 103 is formed, thereby improving the yield of the DRAM.
  • the protective film 116 on the sidewall of the through hole 104 is removed to form the protective layer 106 .
  • the protective film 116 on the sidewall of the through hole 104 is removed by a second dry etching process, and the mixed gas used in the second dry etching process includes SF 6 , CF x , CL 2 and argon.
  • a wet cleaning process may also be used to remove the protective film on the sidewalls of the through holes.
  • the thickness of the protective layer 106 given in the drawings of this embodiment is consistent with the thickness of the gap 105 . In other embodiments, the thickness of the remaining protective layer may be larger than the thickness of the gap.
  • a lower electrode 107 electrically connected to the conductive layer 111 is formed on the sidewall of the through hole 104 and the sidewall of the protective layer 106.
  • the lower electrode 107 further includes a top surface covering the conductive layer 111.
  • the lower electrode 107 may be a conductive material or It is composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the lower electrode 107 is made of titanium nitride material.
  • the sacrificial layer 113 is removed.
  • a plurality of first openings 109 are formed on the remaining top support portion 163 , the first openings expose the second sacrificial layer 113 , and the second sacrificial layer is removed; along the first openings 109
  • the middle support portion 123 is etched, a plurality of second openings are formed on the remaining middle support portion 123 , the second openings expose the first sacrificial layer 113 , and the first sacrificial layer in the middle support portion is removed.
  • the projection of the second opening and the first opening 109 on the substrate 101 completely overlaps or partially overlaps.
  • the first openings are formed on the top support portion 163 between the through holes 104 , and the plurality of first openings 109 are arranged in a radial shape as a whole.
  • the entire first opening is arranged in a radial shape, which can reduce the overall arrangement quantity of the opening, and at the same time ensure that the etching damage to the intermediate support portion 123 is reduced when the sacrificial layer is etched, thereby further ensuring the stacked structure.
  • this embodiment takes the square first circle 109 as an example for illustration.
  • the first opening may be in the shape of a triangle, a square, a pentagon, etc.
  • the shape of the opening 109 is specifically limited, and the shape of the first opening 109 can be set according to actual requirements.
  • a dielectric layer and an upper electrode are deposited to form a capacitor structure.
  • nitrogen gas is continuously supplied during the interval time between each step of the method for forming the semiconductor structure.
  • the semiconductor structure is isolated from contact with oxygen, thereby preventing the semiconductor structure from being oxidized.
  • the interval time between each step is shortened.
  • the semiconductor structure is not oxidized.
  • the oxidized support portion is etched in the subsequent step of removing the sacrificial portion, resulting in voids at the edge of the support portion, thereby causing the collapse of the stacked structure.
  • the present application manufactures a protective layer on the edge of the support portion to prevent the edge of the support portion from being oxidized.
  • the subsequent step of removing the sacrificial portion since the edge of the support portion is not oxidized, it will not be etched. Therefore, the stability of the support portion is ensured, and the DRAM yield is improved by forming a stable stack structure.
  • the stack structure in this embodiment includes at least two, and the stack structure in this embodiment includes a first stack structure, a second stack structure
  • the stack structure and the third stack structure are taken as examples for illustration.
  • a stack structure can also be formed on top of the second stack structure, that is, there is a single stack structure similar to this embodiment.
  • the stacked structure should all fall within the protection scope of the present application.
  • FIG. 12 is a schematic cross-sectional structure diagram corresponding to a method for forming a semiconductor structure provided by another embodiment of the present application, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • the stack structure 203 includes a first stack structure 2031, a second stack structure 2032 and a third stack structure 2033;
  • the first stacked structure 2031 includes a first sacrificial layer and a first intermediate support portion 223 sequentially stacked on the underlying support layer 102 .
  • the first sacrificial layer is etched in a subsequent process to form an air gap 208 .
  • the first intermediate support portion 223 includes a first support layer 233 , a first buffer layer 243 and a second support layer 253 which are sequentially stacked.
  • the materials of the first support layer 233 and the second support layer 253 include silicon carbonitride, and the carbon content of the first support layer 233 is greater than that of the second support layer 253. Due to the higher carbon content, The first support layer 233 has a strong hardness to support the subsequent capacitor structure; the first buffer layer 243 is used to separate the first support layer 233 and the second support layer 253, and the material of the first buffer layer 243 includes silicon nitride
  • the nitrogen content of the second support layer 253 is greater than that of the first support layer 233. Due to the higher nitrogen content, the second support layer 253 has strong oxidation resistance to prevent the first intermediate support portion 223 from being oxidized.
  • the second stack includes a second sacrificial layer and a second intermediate support 323 sequentially stacked on the first stack structure 2031 .
  • the second sacrificial layer is etched in a subsequent process to form an air gap 208 .
  • the second intermediate support portion 323 includes a third support layer 333 , a second buffer layer 343 and a fourth support layer 353 that are sequentially stacked.
  • the materials of the third support layer 333 and the fourth support layer 353 include silicon carbonitride, and the carbon content of the third support layer 333 is greater than that of the fourth support layer 353. Due to the higher carbon content, The third support layer 333 has a strong hardness to support the subsequent capacitor structure; the second buffer layer 343 is used to separate the third support layer 333 and the fourth support layer 353, and the material of the second buffer layer 343 includes silicon nitride; The nitrogen content of the fourth support layer 353 is greater than that of the third support layer 333 . Due to the higher nitrogen content, the fourth support layer 353 has strong oxidation resistance to prevent the second intermediate support portion 323 from being oxidized.
  • the third stacked structure 2033 includes a third sacrificial layer and a top layer support 423 sequentially stacked on the second stacked structure 2032 .
  • the third sacrificial layer is etched in a subsequent process to form an air gap 208 .
  • the top support part 423 includes a fifth support layer 433 , a third buffer layer 443 and a sixth support layer 453 which are sequentially stacked.
  • the materials of the fifth support layer 433 and the sixth support layer 453 include silicon carbonitride, and the carbon content of the fifth support layer 433 is greater than that of the sixth support layer 453. Due to the higher carbon content, The fifth support layer 433 has strong hardness to support the subsequent capacitor structure; the third buffer layer 443 is used to separate the fifth support layer 433 and the sixth support layer 453, and the material of the third buffer layer 443 includes silicon nitride; The nitrogen content of the sixth support layer 453 is greater than that of the fifth support layer 433 . Due to the higher nitrogen content, the sixth support layer 453 has strong oxidation resistance to prevent the top support layer 423 from being oxidized.
  • the middle support part is a three-layer laminated structure
  • the top support part 423 is also manufactured with a three-layer laminated structure, and the formed laminated structure 203 is further strengthened, and the protective layer 206 is also located in the top support part.
  • the edge of 423 is used to protect the edge of the top support portion 423 from being oxidized.
  • the stack structure 203 includes three sub-stack structures 203 as an example for illustration, and in other embodiments, the stack structure may be more than three stack structures.
  • the oxidized support portion is etched in the subsequent step of removing the sacrificial portion, resulting in voids at the edge of the support portion, thereby causing the collapse of the stacked structure.
  • the present application manufactures a protective layer on the edge of the support portion to prevent the edge of the support portion from being oxidized.
  • the subsequent step of removing the sacrificial portion since the edge of the support portion is not oxidized, it will not be etched. Therefore, the stability of the support portion is ensured, and the DRAM yield is improved by forming a stable stack structure.
  • Yet another embodiment of the present application relates to a semiconductor structure.
  • the semiconductor structure includes: a substrate 101, the substrate 101 includes at least a conductive layer 111; a bottom support layer 102, located on the top surface of the substrate 101; a stack structure 103, located on the top surface of the bottom support layer 102, the stack structure 103 includes sacrificial layers formed by stacking in sequence and the supporting part; the through hole 104 is located in the stack structure 103 and exposes the conductive layer 111; the lower electrode 107 is located on the sidewall of the through hole 104 and is electrically connected to the conductive layer 111; the protective layer 106 is located between the lower electrode 107 and the supporting part between. In other embodiments, the protective layer 106 is also located at the edge of the top support portion 163 for preventing the top support portion 163 from being oxidized.
  • the stack structure 103 includes two sub-stack structures 103 as an example for illustration, and in other embodiments, the stack structure may be three or more than three stack structures.
  • the material of the substrate 101 may include silicon, silicon carbide, silicon nitride, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.; in this embodiment, the substrate 101 is made of silicon material, and it is clear to those skilled in the art that the use of silicon material as the substrate 101 in this embodiment is to facilitate those skilled in the art to understand the subsequent formation method, and It does not constitute a limitation, and in the actual application process, a suitable substrate material can be selected according to the requirements.
  • the conductive layer 111 may be made of a single conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a tungsten compound.
  • the layer 111 is used to electrically connect the lower electrode to be formed later, so as to realize the electrical connection between the capacitor structure and the substrate 101 to be formed later.
  • the substrate 101 also includes other semiconductor structures other than the conductive layer 111, such as shallow trench isolation structures, word line structures, active regions, etc. Since other semiconductor structures do not involve the core technology of the present application, It will not be repeated here; those skilled in the art can understand that the substrate 101 further includes other semiconductor structures except the conductive layer 111 to ensure the normal operation of the semiconductor structures.
  • the bottom support layer 102 is located on the top surface of the substrate 101 to prevent the subsequently formed stack structure 103 from being electrically connected to the substrate 101 , and the bottom support layer 102 serves as the bottom layer of the stack structure 103 to reinforce the subsequently formed stack structure 103 .
  • the material of the underlying support layer 102 includes silicon nitride or silicon oxynitride. In this embodiment, the material of the underlying support layer 102 is silicon nitride.
  • the stacked structure 103 includes a sacrificial layer and a support portion that are sequentially stacked.
  • the stacked structure 103 includes a first stacked structure 1031 and a second stacked structure 1032 formed in sequence; wherein, the first stacked structure 1031 is located on the top surface of the underlying support layer 102 , and the first stacked structure 1031 includes a sequentially formed first stacked structure 1031 A sacrificial layer (the sacrificial layer 113 located below the intermediate support portion 123 ) and the intermediate support portion 123 , the second stack structure 1032 includes a second sacrificial layer (the sacrificial layer 113 located above the intermediate support portion 123 ) and the top support portion formed in sequence 163.
  • the sacrificial layer 113 is used for the subsequent formation of the air gap, and the space gap is used for the subsequent formation of the dielectric layer and the upper electrode. After the sacrificial layer 113 is removed and before the dielectric layer and the upper electrode are formed, the stack structure 103 is hollowed out, so it is necessary to ensure the stacking Stability of structure 103.
  • the intermediate support portion 123 includes a first support layer 133 , a buffer layer 143 and a second support layer 153 that are stacked in sequence.
  • the first support layer 133 is located on the top surface of the first sacrificial layer, and the first support layer 133 is mainly used to support the capacitor structure formed later; in one example, the materials of the first support layer 133 and the second support layer 153 include Silicon carbonitride, and the carbon content in the first support layer 133 is greater than the carbon content in the second support layer 153. Due to the high carbon content, the first support layer 133 has a strong hardness to support the buffer layer 143 and the second support layer 153. Two supporting layers 153 . In another example, the nitrogen content of the second support layer 153 may be greater than the nitrogen content of the first support layer 133 to ensure that the carbon content of the first support layer 133 is greater than that of the second support layer 153 .
  • the buffer layer 143 is located on the top surface of the first support layer 143 for separating the first support layer 133 and the second support layer 153, and the buffer layer 143 is also used for anti-oxidation; in one example, the material of the buffer layer 143 includes nitride silicon.
  • the second support layer 153 is located on the top surface of the buffer layer 143, and the second support layer 153 is used to prevent the intermediate support portion 123 from being oxidized; in one example, the materials of the first support layer 133 and the second support layer 153 include silicon carbonitride , and the nitrogen content of the second support layer 153 is greater than that of the first support layer 133 . Due to the high nitrogen content, the second support layer 153 has strong oxidation resistance to prevent the second support layer 153 from being oxidized. In another example, the nitrogen content of the second support layer 153 may be greater than that of the first support layer 133 by ensuring that the carbon content of the first support layer 133 is greater than that of the second support layer 153 .
  • the stability of the intermediate support portion 123 is improved by setting the first support layer 133 as a silicon carbonitride layer with a higher carbon content; the second support layer 153 is set as a silicon carbonitride layer with a higher nitrogen content to The oxidation of the intermediate support portion 123 is prevented after the capacitor hole is etched, so as to prevent the oxidized portion of the intermediate support portion 123 from being etched by DHF when the sacrificial layer is etched. Meanwhile, the buffer layer 143 can further improve the oxidation resistance of the intermediate support portion 123 .
  • the thickness relationship between the first support layer 133, the buffer layer 143 and the second support layer 153 is in the range of 2:1:2 ⁇ first support layer 133:buffer layer 143:second support layer 153 ⁇ 10:1:2.
  • the thickness of the first support layer 133 is 4 nm ⁇ 30 nm, eg, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm or 30 nm; the thickness of the buffer layer 143 is 1 nm ⁇ 6 nm, eg, 1 nm, 2 nm, 3 nm, 4 nm , 5 nm or 6 nm; the thickness of the second support layer 153 is 2 nm ⁇ 12 nm, for example, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm or 12 nm.
  • the above examples of the thicknesses of the first support layer 133 , the buffer layer 143 and the second support layer 153 are only schematic representations of the thicknesses of the first support layer 133 , the buffer layer 143 and the second support layer 153 in this embodiment.
  • the description does not constitute a limitation to the embodiments of the present application.
  • the intermediate support portion can also be formed in a double-layer structure, and the material of the intermediate support portion includes a combination of silicon carbonitride and silicon nitride, that is, the silicon nitride is disposed above the silicon carbonitride, and the carbonitride
  • the silicon can be set to gradually increase in nitrogen content from bottom to top surface, or gradually decrease in carbon content. It should be noted that this embodiment takes the first stack structure 1031 and the second stack structure 1032 as examples to introduce the method for forming the semiconductor structure. In other embodiments, the stack structures on the top surface of the underlying support layer may be three or three more than one.
  • the orthographic projection of the conductive layer 111 and the middle support portion 123 on the substrate 101 has an overlapping area, so as to ensure that the subsequent process can easily form through holes in the middle support portion 123 to expose the conductive layer 111 , thereby forming a lower layer electrically connected to the conductive layer 111 . electrode.
  • the protective layer 106 is used to prevent the edge of the middle support portion 123 from being oxidized. Since the edge of the middle support portion 123 is not oxidized and will not be removed by etching, the stability of the middle support portion 123 is ensured.
  • the stacked structure 103 improves the yield of the DRAM.
  • the semiconductor structure further includes: a first opening 109 located on the top support part 163 and a second opening located on the middle support part 123 , wherein the projection of the second opening and the first opening on the substrate 101 is completely complete overlapping or partially overlapping.
  • the first opening and the second opening expose the sacrificial layer for subsequent etching of the sacrificial layer to form an air gap.
  • the entirety of the first opening and the second opening is radially arranged. Compared with the arrangement of openings in the related art, the entirety of the first opening and the second opening is arranged in a radial shape, which can reduce the overall arrangement quantity of the first opening and the second opening, and further ensure the stability of the stacked structure.
  • the present application uses a protective layer to prevent the edge of the support portion from being oxidized. Since the edge of the support portion is not oxidized and will not be removed by etching, the stability of the support portion is ensured. A solid stack structure is formed, which improves the DRAM yield.

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Abstract

一种半导体结构的形成方法及半导体结构，半导体结构的形成方法包括：提供基底(101)，基底(101)中至少包括导电层(111)；基底(101)顶部表面具有底层支撑层(102)以及位于底层支撑层(102)顶部表面的堆叠结构(103)，堆叠结构(103)包括依次堆叠形成的牺牲层(113)和支撑部；刻蚀部分堆叠结构(103)以及底层支撑层(102)，暴露出导电层(111)，形成通孔(104)；横向刻蚀通孔(104)侧壁暴露出的部分宽度的支撑部，形成空隙(105)；形成填充空隙(105)的保护层(106)；在通孔(104)侧壁以及保护层(106)侧壁形成电连接导电层(111)的下电极(107)；去除牺牲层(113)。通过形成稳固的堆叠结构，提高了DRAM的良率。

Description

半导体结构的形成方法及半导体结构
交叉引用
本申请引用于2020年7月27日递交的名称为“半导体结构的形成方法及半导体结构”的第202010730710.5号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构的形成方法及半导体结构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种广泛应用于计算机系统的半导体存储器，主要的作用原理是利用电容内存储电荷的多少来代表一个二进制比特(bit)。因此，形成的电容位置的排布以及电容与其它结构的位置关系在DRAM的形成过程中显得十分重要。
目前主要通过堆叠结构来支撑并放置电容，从而避免DRAM中电容的倾倒问题。然而，申请人发现，相关技术中的堆叠结构的设置并不牢固，堆叠结构的倒塌会导致整个DRAM的报废，进而严重影响了DRAM的良率。
发明内容
本申请实施例提供一种半导体结构的形成方法及半导体结构，通过加固堆叠结构，防止堆叠结构出现倒塌的问题，从而提高了DRAM的良率。
为解决上述技术问题，本申请实施例提供了一种半导体结构的形成方法，包括：提供基底，基底中至少包括导电层；基底顶部表面具有底层支撑层以及 位于底层支撑层顶部表面的堆叠结构，堆叠结构包括依次堆叠形成的牺牲层和支撑部；刻蚀部分堆叠结构以及底层支撑层，暴露出导电层，形成通孔；横向刻蚀通孔侧壁暴露出的部分宽度的支撑部，形成空隙；形成填充空隙的保护层；在通孔侧壁以及保护层侧壁形成电连接导电层的下电极；去除牺牲层。
由于支撑部边缘易被氧化，被氧化的支撑部在后续去除牺牲部的步骤中被刻蚀，导致支撑部的边缘存在空隙，从而造成堆叠结构的坍塌。与相关技术相比，本申请在支撑部的边缘制造保护层以防止支撑部的边缘被氧化，后续在去除牺牲部的步骤中，由于支撑部的边缘并没有被氧化，并不会被刻蚀去除，从而保证了支撑部的稳定性，通过形成了稳固的堆叠结构，提高了DRAM的良率。
另外，堆叠结构包括依次形成的第一堆叠结构和第二堆叠结构；第一堆叠结构位于底层支撑层顶部表面，第一堆叠结构包括依次形成的第一牺牲层和中间支撑部；第二堆叠结构位于第一堆叠结构顶部表面，第二堆叠结构包括依次形成的第二牺牲层和顶层支撑部；横向刻蚀通孔侧壁暴露出的部分宽度的支撑部，形成空隙包括：横向刻蚀通孔侧壁暴露出的部分宽度的中间支撑部，形成空隙。
另外，中间支撑部包括：依次堆叠形成第一支撑层、缓冲层和第二支撑层。其中，第一支撑层用于支撑第二支撑层和缓冲层，缓冲层用于分离第一支撑层和第二支撑层，且缓冲层还用于抗氧化，第二支撑层用于防止缓冲层和第一支撑层被氧化。
另外，第二支撑层和第一支撑层的材料包括碳氮化硅，且第二支撑层中的氮含量大于第一支撑层的氮含量，缓冲层的材料包括氮化硅。通过保证第二 支撑层中的氮含量大于第一支撑层，以保证第二支撑层的抗氧化效果；同时保证第一支撑层的碳含量大于第二支撑层，以保证第一支撑层的支撑效果。
另外，第二支撑层和第一支撑层的材料包括碳氮化硅，且第一支撑层中的碳含量大于第二支撑层的碳含量，缓冲层的材料包括氮化硅。通过保证第一支撑层的碳含量大于第二支撑层，以保证第一支撑层的支撑效果，同时保证第二支撑层中的氮含量大于第一支撑层，以保证第二支撑层的抗氧化效果。
另外，形成的第一支撑层、缓冲层和第二支撑层的厚度关系范围为2：1：2＜第一支撑层：缓冲层：第二支撑层＜10：1：2。通过合理设置第一支撑层、缓冲层和第二支撑层之间的厚度关系，以保证中间支撑部的稳定性。
另外，去除牺牲层包括：在剩余顶层支撑部上形成多个第一开口，第一开口暴露出第二牺牲层，去除第二牺牲层；沿第一开口刻蚀中间支撑部，在剩余中间支撑部上形成多个第二开口，第二开口暴露出第一牺牲层，去除第一牺牲层。
另外，第一开口的整体和第二开口的整体呈放射形设置。相比于相关技术的开口设置，将第一开口和第二开口的整体按照放射形设置，可以减少第一开口和第二开口整体的设置数量，进一步保证堆叠结构的稳定性。
另外，形成的保护层的宽度与空隙的宽度一致。
另外，形成填充空隙的保护层，包括：在通孔侧壁形成保护膜，形成的保护膜还填充空隙；去除通孔侧壁的保护膜，保留空隙中的保护膜，以形成保护层。
本申请实施例还提供了一种半导体结构，包括：基底，基底中至少包括导电层；底层支撑层，位于基底顶部表面；堆叠结构，位于底层支撑层顶部表 面，堆叠结构包括依次堆叠形成的牺牲层和支撑部；通孔，位于堆叠结构中，且暴露出导电层；下电极，位于通孔侧壁且电连接导电层；保护层，位于下电极与支撑部之间。
另外，堆叠结构包括第一堆叠结构和第二堆叠结构；第一堆叠结构位于底层支撑层顶部表面，第一堆叠结构包括依次形成的第一牺牲层和中间支撑部；第二堆叠结构位于第一堆叠结构顶部表面，第二堆叠结构包括依次形成的第二牺牲层和顶层支撑部；保护层位于下电极与中间支撑部之间。
另外，中间支撑部包括：第一支撑层、缓冲层和第二支撑层；其中，第一支撑层和第二支撑层位于缓冲层相对两侧的表面，且第一支撑层靠近基底，第一支撑层和第二支撑层远离缓冲层的表面连接牺牲层。
另外，第一支撑层、缓冲层和第二支撑层的厚度关系范围为2：1：2＜第一支撑层：缓冲层：第二支撑层＜10：1：2。
另外，第一支撑层的厚度为4nm～20nm，缓冲层的厚度为1nm～6nm，第二支撑层的厚度二为2nm～12nm。
另外，第二支撑层和第一支撑层的材料包括碳氮化硅，且第二支撑层中的氮含量大于第一支撑层的氮含量；缓冲层的材料包括氮化硅。
另外，第二支撑层和第一支撑层的材料包括碳氮化硅，且第一支撑层中的碳含量大于第二支撑层的碳含量；缓冲层的材料包括氮化硅。
相比于相关技术而言，本申请通过保护层以防止支撑部的边缘被氧化，由于支撑部的边缘并没有被氧化，并不会被刻蚀去除，从而保证了支撑部的稳定性，通过形成了稳固的堆叠结构，提高了DRAM的良率。
附图说明
图1至图11为本申请一实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图；
图12为本申请另一实施例提供的半导体结构的形成方法对应的剖面结构示意图。
具体实施方式
目前，主要通过堆叠结构来支撑并放置电容，从而避免DRAM中电容的倾倒问题，但相关技术中堆叠结构的设置并不牢固，堆叠结构的倒塌会导致整个DRAM的报废，进而严重影响了DRAM的良率。
为解决上述问题，本申请一实施例提供了一种半导体结构的形成方法，包括：提供基底，基底中至少包括导电层；基底顶部表面具有底层支撑层以及位于底层支撑层顶部表面的堆叠结构，堆叠结构包括依次堆叠形成的牺牲层和支撑部；刻蚀部分堆叠结构以及底层支撑层，暴露出导电层，形成通孔；横向刻蚀通孔侧壁暴露出的部分宽度的支撑部，形成空隙；形成填充空隙的保护层；在通孔侧壁以及保护层侧壁形成电连接导电层的下电极；去除牺牲层。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图11为本申请一实施例提供的半导体结构的形成方法各步骤对应 的剖面结构示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
参考图1，提供基底101，基底101中至少包括导电层111。
基底101的材料可以包括硅、碳化硅、氮化硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上层锗化硅(SiGeOI)以及绝缘体上层锗(GeOI)等；在本实施例中基底101采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底101是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
导电层111可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，导电层111采用钨材料，导电层111用于电连接后续形成下电极，以实现后续形成电容结构与基底101之间的电连接。
需要说明的是，基底101中还包括除导电层111外的其他半导体结构，例如浅沟槽隔离结构、字线结构、有源区等，由于其他半导体结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底101中还包括除导电层111外的其他半导体结构，以保证半导体结构的正常运行。
继续参考图1，基底101顶部表面具有底层支撑层102以及位于底层支撑层102顶部表面的堆叠结构103，堆叠结构103包括依次堆叠形成的牺牲层以及支撑部。在本实施例中，堆叠结构103包括依次形成的第一堆叠结构1031和第二堆叠结构1032；其中，第一堆叠结构1031位于底层支撑层102顶部表面，第一堆叠结构1031包括依次形成的第一牺牲层(位于中间支撑部123以下的牺牲层113)和中间支撑部123，第二堆叠结构1032包括依次形成的第二牺 牲层(位于中间支撑部123以上的牺牲层113)和顶层支撑部163。
底层支撑层102位于基底101顶部表面，用于防止后续形成的堆叠结构103与基底101形成电连接，且底层支撑层102作为堆叠结构103的底层结构，用于加固后续形成的堆叠结构103。具体地，底层支撑层102的材料包括氮化硅或氮氧化硅，在本实施例中，底层支撑层102的材料为氮化硅。
具体地，在堆叠结构103中形成电容孔，并沉积下电极后，需要在顶层支撑部上形成第一开口去刻蚀牺牲层113。由于在刻蚀形成电容孔后，中间支撑部123材料暴露在空气中，且极容易被氧化形成一层氧化层，沉积下电极后，氧化层夹在中间支撑部123和下电极之间。在后续通过第一开口刻蚀去除第二牺牲层时，中间支撑部123和下电极间的氧化层极易刻蚀，从而中间支撑部123和下电极之间形成以空隙，导致支撑部起不到支撑电极作用，从而后续形成的电极不稳固，同时刻蚀液体从空隙灌到第一牺牲层，导致在刻蚀第一牺牲层时形成不良形貌。
牺牲层113用于后续形成空气间隙，空间间隙用于后续形成介电层和上电极，去除牺牲层113之后且在形成介电层和上电极之前，堆叠结构103为镂空设置，因此需要保证堆叠结构103的稳定性。
具体地，在底层支撑层102顶部表面形成牺牲层113，牺牲层113的材料为掺杂硼和磷的二氧化硅(BPSG)或者含氧材料，后续在去除牺牲层113形成空气间隙的过程中，可采用湿法刻蚀工艺进行针对性刻蚀的方式去除牺牲层。由于湿法刻蚀工艺的具有针对性，在除去牺牲层113的过程中并不会对顶层支撑部163、中间支撑部123和底层支撑层102进行刻蚀；从而避免了在形成空气间隙的过程中，堆叠结构103出现的坍塌现象。
在本实施例中，中间支撑部123包括依次堆叠形成的第一支撑层133、缓冲层143和第二支撑层153。
具体地，在第一牺牲层顶部表面形成第一支撑层133，第一支撑层133主要用于支撑后期形成的电容结构；在一个例子中，第一支撑层133和第二支撑层153的材料包括碳氮化硅，且第一支撑层133中的碳含量大于第二支撑层153的碳含量，由于碳含量较高，使第一支撑层133具有较强的硬度，以支撑后期的电容结构。在另一个例子中，可以通过第二支撑层153的氮含量大于第一支撑层133氮含量，来确保第一支撑层133中的碳含量大于第二支撑层153的碳含量。
具体地，采用第一化学气相沉积(CVD)的方式形成上述第一支撑层133，第一化学气相沉积采用的混合气体包括：含碳气体TMS、SIH 4、NH 3和N 2，通过调节含碳气体TMS的流量来控制沉积的SiCN中碳含量的高低。
在第一支撑层143顶部表面形成缓冲层143，缓冲层143用于分离第一支撑层133和第二支撑层153，且缓冲层143还用于抗氧化；在一个例子中，缓冲层143的材料包括氮化硅。
在缓冲层143顶部表面形成第二支撑层153，第二支撑层153用于防止中间支撑部123被氧化；在一个例子中，第一支撑层133和第二支撑层153的材料包括碳氮化硅，且第二支撑层153的氮含量大于第一支撑层133的氮含量，由于氮含量较高，使第二支撑层153具有较强的抗氧化性，以防止第二支撑层153被氧化。在另一个例子中，可以通过第一支撑层133的碳含量大于第二支撑层153的碳含量，来确保第二支撑层153的氮含量大于第一支撑层133的氮含量。
具体地，采用第二化学气相沉积的方式形成上述第二支撑层153，第二化学气相沉积采用的混合气体包括：含碳气体TMS、SIH 4、NH 3和N 2，通过调节含NH 3的流量来控制沉积的SiCN中氮含量的高低。
通过将第一支撑层133设置为碳含量较高的碳氮化硅层，来提高中间支撑部123的稳固性；将第二支撑层153设置为氮含量较高的碳氮化硅层，以防止刻蚀电容孔后中间支撑部123被氧化，从而避免刻蚀牺牲层时DHF会刻蚀中间支撑部123被氧化的部分。同时，缓冲层143可以进一步提高中间支撑部123的抗氧化性。
另外，在本实施例中，形成的第一支撑层133、缓冲层143和第二支撑层153的厚度关系范围为2：1：2＜第一支撑层133：缓冲层143：第二支撑层153＜10：1：2。通过合理设置第一支撑层133、缓冲层143和第二支撑层153之间的厚度关系，以保证中间支撑部123的稳固性。
在一个例子中，第一支撑层133的厚度为4nm～30nm，例如，5nm、10nm、15nm、20nm、25nm或30nm；缓冲层143的厚度为1nm～6nm，例如，1nm、2nm、3nm、4nm、5nm或6nm；第二支撑层153的厚度为2nm～12nm，例如，2nm、4nm、6nm、8nm、10nm或12nm。
需要说明的是，上述对第一支撑层133、缓冲层143、第二支撑层153厚度的举例仅为本实施例对第一支撑层133、缓冲层143、第二支撑层153厚度的示意性说明，并不构成对本申请实施例的限定。
在其他实施例中，中间支撑部也可以双层结构形成，此时中间支撑部的材料包括碳氮化硅和氮化硅的组合，即氮化硅设置在碳氮化硅上方，碳氮化硅可以设置为从底面到顶面氮含量逐渐增加，或碳含量逐渐减少。
需要说明的是，本实施例以第一堆叠结构1031和第二堆叠结构1032为例介绍半导体结构的形成方法，在其他实施例中，位于底层支撑层顶部表面的堆叠结构103可以为一个、三个或者三个以上。
导电层111与中间支撑部123在基底101上的正投影具有重叠区域，以保证后续工艺容易在中间支撑部123中形成通孔以暴露出导电层111，从而形成与导电层111电连接的下电极。
参考图2至图4，刻蚀部分堆叠结构103以及底层支撑层102，直至暴露出导电层111，形成通孔104。图2为刻蚀形成的通孔104的剖面示意图，图3为刻蚀形成的通孔104的俯视图，以呈现通孔104的排布方式，图4为形成的通孔104的三维立体图；需要说明的是，本实施例以圆形通孔104为例进行举例说明，在其他实施例中，通孔可以采用三角形、四边形或五边形等形状，本实施例并不对通孔104的形状进行具体限定，可以根据实际需求设置通孔104的形状。
参考图5，横向沿通孔104侧壁并横向刻蚀通孔104的侧壁暴露出的部分宽度的中间支撑部123，形成空隙105。
参考图5，刻蚀去除预设厚度的中间支撑部123，在一个例子中，可以采用湿法刻蚀去除预设厚度的中间支撑部123，具体地，采用DSP和IPA来去除预设厚度的中间支撑部123。在其它实施例中，也可以采用化学干法刻蚀去除预设厚度的中间支撑部123。具体地，刻蚀的中间支撑部123包括被氧化的中间支撑部123，剩余的中间支撑部123并不包括被氧化的部分，具体刻蚀宽度需根据中间支撑部123被氧化的程度进行具体设定。
参考图6和图7，形成填充空隙的保护层106。
具体地，参考图6，在通孔104侧壁形成保护膜116，形成的保护膜116填充空隙105。在刻蚀部分宽度中间支撑部123后到形成保护膜过程中，通过采用N 2保护的方法避免中间支撑部123二次氧化。在本实施例中，保护膜116和保护层106的材料为氮化硅。
在一个例子中，通过原子层淀积(ALD)的方式形成上述保护膜116。采用原子层沉积工艺形成的保护膜116具有良好的覆盖性。在中间支撑部123的边缘制造保护层106以防止中间支撑部123的边缘被氧化，后续在去除牺牲部113的步骤中，由于中间支撑部123的边缘并没有被氧化，并不会被刻蚀去除，从而保证了中间支撑部123的稳定性，通过形成了稳固的堆叠结构103，提高了DRAM的良率。
参考图7，去除通孔104侧壁的保护膜116，形成保护层106。
具体地，采用第二干法刻蚀工艺去除通孔104侧壁的保护膜116，第二干法刻蚀工艺采用的混合气体包括SF 6、CF x、CL 2和氩气。在其他实施例中，也可以采用湿法清洗工艺去除通孔侧壁的保护膜。
需要说明的是，本实施例附图中给出的保护层106的厚度与空隙105的厚度一致，在其他实施例中，剩余的保护层的厚度可以比空隙的厚度大。
参考图8，在通孔104侧壁以及保护层106侧壁形成电连接导电层111的下电极107，下电极107还包括覆盖导电层111的顶部表面，下电极107可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，下电极107采用氮化钛材料。
参考图9至图11，去除牺牲层113。
具体地，参考图9，在剩余顶层支撑部163上形成多个第一开口109(图 中虚线部分)，第一开口暴露出第二牺牲层113，去除第二牺牲层；沿第一开口109刻蚀中间支撑部123，在剩余中间支撑部123上形成多个第二开口，第二开口暴露出第一牺牲层113，去除中间支撑部第一牺牲层。其中，第二开口与第一开口109在基底101上的投影完全重叠或者部分重叠。
在一个例子中，参考图10和图11，形成的第一开口位于通孔104之间的顶层支撑部163上，且多个第一开口109的整体呈放射形设置。相比于相关技术的开口设置，将第一开口的整体按照放射形设置，可以减少开口整体的设置数量，同时保证刻蚀牺牲层时减少对中间支撑部123的刻蚀破坏，进一步保证堆叠结构103的稳定性。需要说明的是，本实施例以方形的第一圆形109为例进行举例说明，在其他实施例中，第一开口可以采用三角形、方形、五边形等形状，本实施例并不对第一开口109的形状进行具体限定，可以根据实际需求设置第一开口109的形状。
在另一个实施例中，刻蚀完牺牲层113后沉积介电层和上电极，形成电容结构。
在本实施例中，在执行半导体结构的形成方法的各步骤的间隔时间中持续通入氮气。通过持续通入氮气，以隔绝半导体结构与氧气的接触，从而防止半导体结构被氧化。
在本实施例中，在执行半导体结构的形成方法时，缩短各步骤之间的间隔时间。通过减少制程中各步骤之间的等待时间，以保证半导体结构不被氧化。
由于支撑部边缘易被氧化，被氧化的支撑部在后续去除牺牲部的步骤中被刻蚀，导致支撑部的边缘存在空隙，从而造成堆叠结构的坍塌。与相关技术相比，本申请在支撑部的边缘制造保护层以防止支撑部的边缘被氧化，后续在 去除牺牲部的步骤中，由于支撑部的边缘并没有被氧化，并不会被刻蚀去除，从而保证了支撑部的稳定性，通过形成了稳固的堆叠结构，提高了DRAM的良率。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例提供了一种半导体结构的形成方法，与上述一实施例不同是，本实施例中的堆叠结构至少包括两个，本实施例以堆叠结构包括第一堆叠结构、第二堆叠结构和第三堆叠结构为例进行举例说明，本领域技术人员应该理解，在本实施例的基础上，还可以在第二堆叠结构的顶部形成堆叠结构，即存在与本实施例相似的单个堆叠结构都应属于本申请的保护范围之内。
图12为本申请另一实施例提供的半导体结构的形成方法对应的剖面结构示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
具体地，堆叠结构203包括第一堆叠结构2031、第二堆叠结构2032和第三堆叠结构2033；
第一堆叠结构2031包括依次堆叠在底层支撑层102上的第一牺牲层和第一中间支撑部223。其中，第一牺牲层在后续工艺中被刻蚀形成空气间隙208。
具体地，第一中间支撑部223包括依次堆叠形成的第一支撑层233、第一缓冲层243和第二支撑层253。在一个例子中，第一支撑层233和第二支撑层253的材料包括碳氮化硅，且第一支撑层233中的碳含量大于第二支撑层253的碳含量，由于碳含量较高，使第一支撑层233具有较强的硬度，以支撑后续 的电容结构；第一缓冲层243用于分离第一支撑层233和第二支撑层253，第一缓冲层243的材料包括氮化硅；第二支撑层253的氮含量大于第一支撑层233的氮含量，由于氮含量较高，使第二支撑层253具有较强的抗氧化性，以防止第一中间支撑部223被氧化。
第二堆叠包括依次堆叠在第一堆叠结构2031上的第二牺牲层和第二中间支撑部323。其中，第二牺牲层在后续工艺中被刻蚀形成空气间隙208。
具体地，第二中间支撑部323包括依次堆叠形成的第三支撑层333、第二缓冲层343和第四支撑层353。在一个例子中，第三支撑层333和第四支撑层353的材料包括碳氮化硅，且第三支撑层333中的碳含量大于第四支撑层353的碳含量，由于碳含量较高，使第三支撑层333具有较强的硬度，以支撑后续电容结构；第二缓冲层343用于分离第三支撑层333和第四支撑层353，第二缓冲层343的材料包括氮化硅；第四支撑层353的氮含量大于第三支撑层333的氮含量，由于氮含量较高，使第四支撑层353具有较强的抗氧化性，以防止第二中间支撑部323被氧化。
第三堆叠结构2033包括依次堆叠在第二堆叠结构2032上的第三牺牲层和顶层支撑部423。其中，第三牺牲层在后续工艺中被刻蚀形成空气间隙208。
具体地，顶层支撑部423包括依次堆叠形成的第五支撑层433、第三缓冲层443和第六支撑层453。在一个例子中，第五支撑层433和第六支撑层453的材料包括碳氮化硅，且第五支撑层433中的碳含量大于第六支撑层453的碳含量，由于碳含量较高，使第五支撑层433具有较强的硬度，以支撑后续电容结构；第三缓冲层443用于分离第五支撑层433和第六支撑层453，第三缓冲层443的材料包括氮化硅；第六支撑层453的氮含量大于第五支撑层433的氮 含量，由于氮含量较高，使第六支撑层453具有较强的抗氧化性，以防止顶层支撑层423被氧化。
形成堆叠结构203后其他形成方法同上述一实施例，在本实施例中不再赘述，最终以形成如图12所示的半导体结构。
在本实施例中不仅中间支撑部为三层的叠层结构，顶层支撑部423也才用三层的叠层结构进行制造，进一步加固形成的堆叠结构203，且保护层206还位于顶层支撑部423的边缘，用于保护顶层支撑部423的边缘被氧化。
需要说明的是，在本实施例中，以堆叠结构203包括三个子堆叠结构203为例进行举例说明，在其他实施例中，堆叠结构可以为三个以上的堆叠结构。
由于支撑部边缘易被氧化，被氧化的支撑部在后续去除牺牲部的步骤中被刻蚀，导致支撑部的边缘存在空隙，从而造成堆叠结构的坍塌。与相关技术相比，本申请在支撑部的边缘制造保护层以防止支撑部的边缘被氧化，后续在去除牺牲部的步骤中，由于支撑部的边缘并没有被氧化，并不会被刻蚀去除，从而保证了支撑部的稳定性，通过形成了稳固的堆叠结构，提高了DRAM的良率。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于上述一实施例与本实施例相互对应，因此本实施例可与上述一实施例互相配合实施。上述一实施例中提到的相关技术细节在本实施例中依然有效，在上述一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减 少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述一实施例中。
本申请又一实施例涉及一种半导体结构。
参考图9，以下将结合附图对本实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
半导体结构，包括：基底101，基底101中至少包括导电层111；底层支撑层102，位于基底101顶部表面；堆叠结构103，位于底层支撑层102顶部表面，堆叠结构103包括依次堆叠形成的牺牲层和支撑部；通孔104，位于堆叠结构103中，且暴露出导电层111；下电极107，位于通孔104侧壁且电连接导电层111；保护层106，位于下电极107与支撑部之间。在其他实施例中，保护层106还位于顶层支撑部163的边缘，用于防止顶层支撑部163被氧化。
需要说明的是，在本实施例中，以堆叠结构103包括两个个子堆叠结构103为例进行举例说明，在其他实施例中，堆叠结构可以为三个或三个以上的堆叠结构。
基底101的材料可以包括硅、碳化硅、氮化硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上层锗化硅(SiGeOI)以及绝缘体上层锗(GeOI)等；在本实施例中基底101采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底101是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
导电层111可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，导电层111采用钨 材料，导电层111用于电连接后续形成下电极，以实现后续形成电容结构与基底101之间的电连接。
需要说明的是，基底101中还包括除导电层111外的其他半导体结构，例如浅沟槽隔离结构、字线结构、有源区等，由于其他半导体结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底101中还包括除导电层111外的其他半导体结构，以保证半导体结构的正常运行。
底层支撑层102位于基底101顶部表面，用于防止后续形成的堆叠结构103与基底101形成电连接，且底层支撑层102作为堆叠结构103的底层结构，用于加固后续形成的堆叠结构103。具体地，底层支撑层102的材料包括氮化硅或氮氧化硅，在本实施例中，底层支撑层102的材料为氮化硅。
在本实施例中，堆叠结构103包括依次堆叠形成的牺牲层以及支撑部。在本实施例中，堆叠结构103包括依次形成的第一堆叠结构1031和第二堆叠结构1032；其中，第一堆叠结构1031位于底层支撑层102顶部表面，第一堆叠结构1031包括依次形成的第一牺牲层(位于中间支撑部123以下的牺牲层113)和中间支撑部123，第二堆叠结构1032包括依次形成的第二牺牲层(位于中间支撑部123以上的牺牲层113)和顶层支撑部163。牺牲层113用于后续形成空气间隙，空间间隙用于后续形成介电层和上电极，去除牺牲层113之后且在形成介电层和上电极之前，堆叠结构103为镂空设置，因此需要保证堆叠结构103的稳定性。
在本实施例中，中间支撑部123包括依次堆叠形成的第一支撑层133、缓冲层143和第二支撑层153。
具体地，第一支撑层133位于第一牺牲层顶部表面，第一支撑层133主 要用于支撑后期形成的电容结构；在一个例子中，第一支撑层133和第二支撑层153的材料包括碳氮化硅，且第一支撑层133中的碳含量大于第二支撑层153的碳含量，由于碳含量较高，使第一支撑层133具有较强的硬度，以支撑缓冲层143和第二支撑层153。在另一个例子中，可以通过第二支撑层153的氮含量大于第一支撑层133氮含量，来确保第一支撑层133中的碳含量大于第二支撑层153的碳含量。
缓冲层143位于第一支撑层143顶部表面，用于分离第一支撑层133和第二支撑层153，且缓冲层143还用于抗氧化；在一个例子中，缓冲层143的材料包括氮化硅。
第二支撑层153位于缓冲层143顶部表面，第二支撑层153用于防止中间支撑部123被氧化；在一个例子中，第一支撑层133和第二支撑层153的材料包括碳氮化硅，且第二支撑层153的氮含量大于第一支撑层133的氮含量，由于氮含量较高，使第二支撑层153具有较强的抗氧化性，以防止第二支撑层153被氧化。在另一个例子中，可以通过第一支撑层133的碳含量大于第二支撑层153的碳含量，来确保第二支撑层153的氮含量大于第一支撑层133的氮含量。
通过将第一支撑层133设置为碳含量较高的碳氮化硅层，来提高中间支撑部123的稳固性；将第二支撑层153设置为氮含量较高的碳氮化硅层，以防止刻蚀电容孔后中间支撑部123被氧化，从而避免刻蚀牺牲层时DHF会刻蚀中间支撑部123被氧化的部分。同时，缓冲层143可以进一步提高中间支撑部123的抗氧化性。
另外，在本实施例中，第一支撑层133、缓冲层143和第二支撑层153 的厚度关系范围为2：1：2＜第一支撑层133：缓冲层143：第二支撑层153＜10：1：2。通过合理设置第一支撑层133、缓冲层143和第二支撑层153之间的厚度关系，以保证中间支撑部123的稳固性。
在一个例子中，第一支撑层133的厚度为4nm～30nm，例如，5nm、10nm、15nm、20nm、25nm或30nm；缓冲层143的厚度为1nm～6nm，例如，1nm、2nm、3nm、4nm、5nm或6nm；第二支撑层153的厚度为2nm～12nm，例如，2nm、4nm、6nm、8nm、10nm或12nm。需要说明的是，上述对第一支撑层133、缓冲层143、第二支撑层153厚度的举例仅为本实施例对第一支撑层133、缓冲层143、第二支撑层153厚度的示意性说明，并不构成对本申请实施例的限定。
在其他实施例中，中间支撑部也可以双层结构形成，此时中间支撑部的材料包括碳氮化硅和氮化硅的组合，即氮化硅设置在碳氮化硅上方，碳氮化硅可以设置为从底面到顶面氮含量逐渐增加，或碳含量逐渐减少。需要说明的是，本实施例以第一堆叠结构1031和第二堆叠结构1032为例介绍半导体结构的形成方法，在其他实施例中，位于底层支撑层顶部表面的堆叠结构可以为三个或者三个以上。
导电层111与中间支撑部123在基底101上的正投影具有重叠区域，以保证后续工艺容易在中间支撑部123中形成通孔以暴露出导电层111，从而形成与导电层111电连接的下电极。
保护层106用于防止中间支撑部123的边缘被氧化，由于中间支撑部123的边缘并没有被氧化，并不会被刻蚀去除，从而保证了中间支撑部123的稳定性，通过形成了稳固的堆叠结构103，提高了DRAM的良率。
在本实施例中，半导体结构还包括：位于顶层支撑部163上的第一开口109和位于中间支撑部123上的第二开口，其中，第二开口与第一开口在基底101上的投影完全重叠或者部分重叠。第一开口和第二开口暴露出牺牲层，用于后续刻蚀牺牲层形成空气间隙。第一开口和第二开口的整体呈放射形设置。相比于相关技术的开口设置，将第一开口和第二开口的整体按照放射形设置，可以减少第一开口和第二开口整体的设置数量，进一步保证堆叠结构的稳定性。
相比于相关技术而言，本申请通过保护层以防止支撑部的边缘被氧化，由于支撑部的边缘并没有被氧化，并不会被刻蚀去除，从而保证了支撑部的稳定性，通过形成了稳固的堆叠结构，提高了DRAM的良率。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供基底，所述基底中至少包括导电层；
    所述基底顶部表面具有底层支撑层以及位于所述底层支撑层顶部表面的堆叠结构，所述堆叠结构包括依次堆叠形成的牺牲层和支撑部；
    刻蚀部分所述堆叠结构以及所述底层支撑层，暴露出所述导电层，形成通孔；
    横向刻蚀所述通孔侧壁暴露出的部分宽度的所述支撑部，形成空隙；
    形成填充所述空隙的保护层；
    在所述通孔侧壁以及所述保护层侧壁形成电连接所述导电层的下电极；
    去除所述牺牲层。
  2. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述堆叠结构包括依次形成的第一堆叠结构和第二堆叠结构；
    所述第一堆叠结构位于所述底层支撑层顶部表面，所述第一堆叠结构包括依次形成的第一牺牲层和中间支撑部；
    所述第二堆叠结构位于所述第一堆叠结构顶部表面，所述第二堆叠结构包括依次形成的第二牺牲层和顶层支撑部；
    所述横向刻蚀所述通孔侧壁暴露出的部分宽度的所述支撑部，形成空隙包括：
    横向刻蚀所述通孔侧壁暴露出的部分宽度的所述中间支撑部，形成空隙。
  3. 根据权利要求2所述的半导体结构的形成方法，其特征在于，所述中间支撑部包括：依次堆叠形成第一支撑层、缓冲层和第二支撑层。
  4. 根据权利要求3所述的半导体结构的形成方法，其特征在于，所述第二支撑层和所述第一支撑层的材料包括碳氮化硅，且所述第二支撑层中的氮含量大于所述第一支撑层的氮含量；所述缓冲层的材料包括氮化硅。
  5. 根据权利要求3所述的半导体结构的形成方法，其特征在于，所述第二支撑层和所述第一支撑层的材料包括碳氮化硅，且所述第一支撑层中的碳含量大于所述第二支撑层的碳含量；所述缓冲层的材料包括氮化硅。
  6. 根据权利要求3所述的半导体结构的形成方法，其特征在于，形成的所述第一支撑层、所述缓冲层和所述第二支撑层的厚度关系范围为2：1：2＜所述第一支撑层：所述缓冲层：所述第二支撑层＜10：1：2。
  7. 根据权利要求2所述的半导体结构的形成方法，其特征在于，所述去除所述牺牲层包括：
    在剩余所述顶层支撑部上形成多个第一开口，所述第一开口暴露出所述第二牺牲层，去除所述第二牺牲层；
    沿所述第一开口刻蚀所述中间支撑部，在剩余所述中间支撑部上形成多个第二开口，所述第二开口暴露出所述第一牺牲层，去除所述第一牺牲层。
  8. 根据权利要求7所述的半导体结构的形成方法，其特征在于，所述第一开口的整体和所述第二开口的整体呈放射形设置。
  9. 根据权利要求1所述的半导体结构的形成方法，其特征在于，形成的所述保护层的宽度与所述空隙的宽度一致。
  10. 根据权利要求9所述的半导体结构的形成方法，其特征在于，所述形成填充所述空隙的保护层，包括：
    在所述通孔侧壁形成保护膜，形成的所述保护膜还填充所述空隙；
    去除所述通孔侧壁的所述保护膜，保留所述空隙中的保护膜，以形成所述保护层。
  11. 一种半导体结构，其特征在于，包括：
    基底，所述基底中至少包括导电层；
    底层支撑层，位于所述基底顶部表面；
    堆叠结构，位于所述底层支撑层顶部表面，所述堆叠结构包括依次堆叠形成的牺牲层和支撑部；
    通孔，位于所述堆叠结构中，且暴露出所述导电层；
    下电极，位于所述通孔侧壁且电连接所述导电层；
    保护层，位于所述下电极与所述支撑部之间。
  12. 根据权利要求11所述的半导体结构的形成方法，其特征在于，所述堆叠结构包括第一堆叠结构和第二堆叠结构；
    所述第一堆叠结构位于所述底层支撑层顶部表面，所述第一堆叠结构包括依次形成的第一牺牲层和中间支撑部；
    所述第二堆叠结构位于所述第一堆叠结构顶部表面，所述第二堆叠结构包括依次形成的第二牺牲层和顶层支撑部；
    所述保护层位于所述下电极与所述中间支撑部之间。
  13. 根据权利要求12所述的半导体结构，其特征在于，所述中间支撑部包括：
    第一支撑层、缓冲层和第二支撑层；
    其中，所述第一支撑层和所述第二支撑层位于所述缓冲层相对两侧的表面，且所述第一支撑层靠近所述基底，所述第一支撑层和所述第二支撑层远离所述缓冲层的表面连接所述牺牲层。
  14. 根据权利要求13所述的半导体结构，其特征在于，所述第一支撑层、所述缓冲层和所述第二支撑层的厚度关系范围为2：1：2＜所述第一支撑层：所述缓冲层：所述第二支撑层＜10：1：2。
  15. 根据权利要求14所述的半导体结构，其特征在于，所述第一支撑层的厚度为4nm～20nm，所述缓冲层的厚度为1nm～6nm，所述第二支撑层的厚度二为2nm～12nm。
  16. 根据权利要求13所述的半导体结构，其特征在于，所述第二支撑层和所述第一支撑层的材料包括碳氮化硅，且所述第二支撑层中的氮含量大于所述第一支撑层的氮含量；所述缓冲层的材料包括氮化硅。
  17. 根据权利要求13所述的半导体结构，其特征在于，所述第二支撑层和所述第一支撑层的材料包括碳氮化硅，且所述第一支撑层中的碳含量大于所述第二支撑层的碳含量；所述缓冲层的材料包括氮化硅。
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