US20030127679A1 - Semiconductor storage device and method of manufacturing the same - Google Patents
Semiconductor storage device and method of manufacturing the same Download PDFInfo
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- US20030127679A1 US20030127679A1 US10/373,693 US37369303A US2003127679A1 US 20030127679 A1 US20030127679 A1 US 20030127679A1 US 37369303 A US37369303 A US 37369303A US 2003127679 A1 US2003127679 A1 US 2003127679A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Definitions
- the present invention belongs to the technical field of a semiconductor device, and particularly relates to a semiconductor storage device having a memory cell area containing a capacitor and a transistor, and a method of manufacturing the semiconductor storage device.
- FIG. 9 is a schematic cross-sectional view showing the conventional DRAM thus constructed.
- reference symbol A represents a memory cell area and reference symbol B represents a peripheral circuit area.
- Reference numeral 10 represents a semiconductor substrate
- reference numeral 12 represents an element separation oxide film
- reference numeral 14 represents a MOS transistor for a memory cell constituting the memory cell area A
- reference numeral 16 represents a MOS transistor constituting the peripheral circuit area B.
- reference numeral 14 a represents the source/drain of the MOS transistor 14
- reference numeral 14 b represents the gate of the MOS transistor 14
- Reference numeral 16 a represents the source/drain of the MOS transistor 16
- reference numeral 16 b represents the gate of the MOS transistor 16 .
- Reference numeral 18 represents an insulating layer
- reference numeral 20 represents a connection opening formed in the insulating layer 18 and a conductive member 22 is filled in the connection opening 20 .
- a cylindrical capacitance stack electrode 24 is formed at the position corresponding to the conductive member 22 on the insulating layer 18 , a capacitance insulating film 26 is formed on the side surface and top surface of the capacitance stack electrode 24 , and a capacitance plate electrode 28 is formed on the capacitance insulting film 26 .
- These members construct a capacitor 30 .
- An insulating film (interlayer insulating film) 32 is formed on the insulating layer 18 so as to cover the capacitor 30 . Since desired wires are formed on the insulating film 32 , the upper surface of the insulating film 32 is flattened to prevent the wires from being broken during the wire forming process.
- the element separation oxide film 12 is formed on the semiconductor substrate 10 , and the MOS transistors 14 , 16 and the insulating layer 18 is formed.
- connection opening 20 is formed in the insulting layer 18 , and the conductive member 22 is filled into the connection opening 20 .
- the capacitance stack electrode 24 is formed at the position corresponding to the conductive member 22 , the capacitance insulating film 26 is formed on the capacitance stack electrode 24 , and a capacitance plate electrode 28 is formed on the capacitance insulating film 26 , thereby forming the capacitor 30 .
- the interlayer insulating film 32 is formed on the insulating layer 18 as shown in FIG. 13.
- the upper surface of the interlayer insulating film 32 in the memory cell area A is higher than the upper surface of the interlayer insulating film 32 in the peripheral circuit area B by the amount corresponding to the height of the capacitor 30 . Therefore, the interlayer insulating film 32 of the memory cell area A is subjected to an etching treatment so that the upper surface of the interlayer insulting film 32 in the memory cell area A is located at substantially the same height as the upper surface of the interlayer insulating film 32 in the peripheral circuit area B.
- a photoresist mask 34 is formed on the interlayer insulating film 32 in the peripheral circuit area B.
- the etching treatment is conducted on the interlayer insulating film 32 of the memory cell area A to substantially equalize the height of the interlayer insulating film 32 in the memory cell area A with the height of the interlayer insulating film 32 of the peripheral circuit area B.
- the photoresist mask 34 is removed, and if necessary, an insulating film is further deposited to thereby form the interlayer insulating film 32 having the flat upper face (surface), thereby forming DRAM as shown in FIG. 9.
- the capacitance stack electrode of the capacitor constituting the memory cell is formed of a pillar-shaped conductor, and thus there occurs a large difference in height (step) between the memory cell area and the peripheral circuit area when the interlayer insulating film is formed.
- step since it is necessary to secure the flatness of the surface of the interlayer insulating film (particularly between the memory cell area and the peripheral circuit area) in order to smoothly form wires on the interlayer insulating film in the subsequent step, a photolithography step is further needed to selectively remove the interlayer insulating film only in the memory cell area after the interlayer insulating film is deposited as described above, and thus the number of steps is increased.
- the present invention has been implemented to solve the foregoing problems of the prior art, and has an object to provide a semiconductor device in which an insulating film such as an interlayer insulating film having a flat surface can be formed without any specific step of flattening the insulating film after the insulating film is deposited, that is, without increasing the number of steps, and a method of manufacturing the semiconductor device.
- an insulating film such as an interlayer insulating film having a flat surface
- a semiconductor storage device having plural memory cells each containing a capacitor and a transistor is characterized in that a first insulating layer is formed so as to cover the transistor, the capacitor is formed on the first insulating layer, the capacitor contains a pillar-shaped insulating member formed on the first insulating layer, a first capacitance electrode formed on the side surface of the pillar-shaped insulating member, a capacitance insulating film formed on the first capacitance electrode and a second capacitance electrode formed on the capacitance insulating film, the first insulating layer has a connection opening formed therein, and the connection opening is filled with a conductive member for connecting the first capacitance electrode and the transistor to each other.
- a second insulating layer formed of the same insulating material as the pillar-shaped insulating member of the capacitor is preferably formed at the same height as the pillar-shaped insulating member of the capacitor on the first insulating layer in at least a part of an area other than the memory cell area containing the plural memory cells.
- the transistor is preferably a MOS transistor, and the source or drain of the MOS transistor is connected to the conductive member.
- a method of manufacturing a semiconductor storage device having plural memory cells each containing a capacitor and a transistor is characterized by comprising the steps of: forming the transistor on a semiconductor substrate; forming a first insulating layer so that the transistor is covered by the first insulating layer; forming connection openings in the first insulating layer at the positions corresponding to the respective memory cells; filling a conductive member in each of the connection openings; forming an insulating material layer on the first insulating layer; subjecting the insulating material layer to a patterning treatment to form a pillar-shaped insulating member so that a part of the surface of the conductive member filled in each of the connection openings is covered by the pillar-shaped insulating member; forming a first capacitance electrode on the side surface of the pillar-shaped insulating member, connecting the first capacitance electrode and the conductive member to each other, forming a capacitance insulating film on the first capacitance electrode,
- the patterning treatment of the insulating material layer is preferably performed by using anisotropic etching.
- the formation of the first capacitance electrode is preferably performed by forming a conductive material layer and patterning the conductive material layer with anisotropic etching.
- the transistor is preferably a MOS transistor, and each connection opening is formed at the position corresponding to the source or drain of the MOS transistor.
- the insulating material layer is also formed in an area other than the memory cell area containing the plural memory cells on the semiconductor substrate, and the insulating material layer is subjected to a patterning treatment so that a second insulating layer having the same height as the pillar-shaped insulating member of the capacitor remains in the area other than the memory cell area.
- the capacitor of the memory cell area is constructed while containing the pillar-shaped insulating member, and the pillar-shaped insulating member is formed simultaneously with formation of the interlayer insulating film in the area other than the memory cell area. Therefore, the surface flattening between the memory cell area and the other area can be easily performed without increasing the number of steps.
- FIG. 1 is a schematic cross-sectional view showing DRAM according to an embodiment of a semiconductor storage device of the present invention
- FIG. 2 is a schematic cross-sectional view showing a manufacturing step of DRAM of FIG. 1;
- FIG. 3 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 4 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 5 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 6 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 7 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 8 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 9 is a schematic diagram of conventional DRAM
- FIG. 10 is a schematic cross-sectional view showing a manufacturing step of the conventional DRAM
- FIG. 11 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM.
- FIG. 12 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM.
- FIG. 13 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM
- FIG. 14 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM.
- FIG. 15 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM.
- FIG. 1 is a schematic cross-sectional view of DRAM according to an embodiment of a semiconductor storage device of the present invention.
- reference symbol A represents a memory cell area
- reference symbol B represents a peripheral circuit area located so as to be adjacent to the memory cell area A.
- Reference numeral 1 represents a semiconductor substrate
- reference numeral 2 represents an element separation oxide film
- reference numeral 3 represents a MOS transistor of one memory cell constituting the memory cell area A
- reference numeral 4 represents a MOS transistor constituting the peripheral circuit area B.
- Reference numeral 3 a represents the source/drain of the MOS transistor 3
- reference numeral 3 b represents the gate of the MOS transistor 3
- Reference numeral 4 a represents the source/drain of the MOS transistor 4
- reference numeral represents the gate of the MOS transistor 4 .
- Reference numeral 5 represents a first insulating layer
- reference numeral 6 represents a connection opening formed in the insulating layer 5
- a conductive member 7 is filled in the connection opening 6 .
- the lower end portion of the conductive member 7 is connected to one of the source/drain 3 a of the MOS transistor 3 .
- the capacitor 8 constituting the memory cell is formed on the insulating layer 5 .
- the capacitor 8 has a pillar-shaped insulating member 8 a, a first capacitance electrode 8 b formed on the side surface of the pillar-shaped insulating member 8 a, a capacitance insulating film 8 c which is formed so as to cover the pillar-shaped insulating member 8 a and the first capacitance electrode 8 b, and a second capacitance electrode 8 d which is formed so as to cover the capacitance insulating film 8 c.
- the pillar-shaped insulating member 8 a is disposed so that a part of the lower end portion of the pillar-shaped insulating member 8 a is connected to the upper end portion of the conductive member 7 , and the lower end portion of the first capacitance electrode 8 b is connected to the upper end portion of the conductive member 7 .
- a second insulating layer 9 is formed on the insulating layer 5 .
- the second insulating layer 9 is formed at the same height as the pillar-shaped insulating member 8 a of the capacitor 8 , and formed of the same insulating material as the pillar-shaped insulating member 8 a of the capacitor 8 .
- the second insulating layer 9 serves as an interlayer insulating film.
- an insulating film or a wiring layer may be formed on the structure shown in FIG. 1.
- the element separation oxide film 2 is formed on the semiconductor substrate 1 , and the MOS transistors 3 , 4 and the first insulating layer 5 are formed.
- connection opening 6 is formed at the position corresponding to one of the source/drain 3 a of the MOS transistor 3 in the insulating layer 5 , and the conductive member 7 is filled in the connection opening 6 thus formed, whereby the conductive member 7 is connected to the source/drain 3 a.
- an insulating material layer 9 ′ is formed on the insulating layer 5 in the memory cell area A and the peripheral circuit area B.
- a mask pattern is formed by photolithography, and anisotropic etching is conducted to subject the insulating material layer 9 ′ to a patterning treatment, thereby forming the pillar-shaped insulting member 8 a such as cylindrical insulating member in the memory cell area A and the second insulating layer 9 in the peripheral circuit area B. Accordingly, the pillar-shaped insulating member 8 a and the second insulating layer 9 are formed of the same material and the same height. A part of the upper portion of the conductive member 7 is covered by the pillar-shaped insulating member 8 a, but the other part is exposed.
- a conductive film 8 b ′ is deposited on the overall surface of the intermediate product shown in FIG. 5 by a method such as CVD method or the like which is excellent in step coverage performance.
- the conductive film is left only at the side surface of the pillar-shaped insulating member 8 a in the memory cell area A to form the first capacitance electrode 8 b.
- the lower end portion of the first capacitance electrode 8 b is connected to the conductive member 7 .
- an insulating film 8 c ′ is deposited and formed on the overall surface of the intermediate product shown in FIG. 7 by the method such as CVD method which is excellent in step coverage performance, and a conductive film 8 d ′ is deposited and formed on the insulating film 8 c ′. Thereafter, the conductive film 8 d ′ and the insulating film 8 c ′ are subjected to patterning, thereby obtaining the semiconductor storage device shown in FIG. 1.
- the pillar-shaped insulating member 8 a and the second insulating layer 9 are formed by the patterning of the insulating material layer 9 ′, and thus they are formed of the same insulating material and are formed at the same height. Accordingly, without increasing the number of steps, there can be easily prevented occurrence of the difference in height between the surfaces of the memory cell area A and the other area.
Abstract
In a memory cell area (A) of a semiconductor storage device, a capacitor (8) formed on a first insulating layer (5) formed so as to cover MOS transistors (3, 4) includes a pillar-shaped insulating member (8 a), a first capacitance electrode (8 b) formed on the side surface of the pillar-shaped insulating member (8 a), a capacitance insulating film (8 c) formed on the first capacitance electrode (8 b) and a second capacitance electrode (8 d) formed on the capacitance insulating film (8 c). A conductive member (7) for connecting the source or drain (3 a) of the MOS transistor (3) to the first capacitance electrode (8 b) is filled in a connection opening (6) formed in the first insulating layer (5). In a peripheral circuit area (B) other than the memory cell area (A) containing plural memory cells each having the MOS transistor (3) and the capacitor (8), a second insulating layer (9) which is formed simultaneously with the formation of the pillar-shaped insulating member (8 a) of the capacitor (8) and has the same height as the pillar-shaped insulating member (8 a) is formed on the first insulating layer (5).
Description
- 1. Field of the Invention
- The present invention belongs to the technical field of a semiconductor device, and particularly relates to a semiconductor storage device having a memory cell area containing a capacitor and a transistor, and a method of manufacturing the semiconductor storage device.
- 2. Description of the Related Art
- In order to implement high storage capacity, a so-called stack structure in which the electrode of a capacitor constituting a memory cell is three-dimensionally formed and it is disposed while superposed on a transistor has been applied to DRAM as a representative of semiconductor storage devices.
- FIG. 9 is a schematic cross-sectional view showing the conventional DRAM thus constructed.
- In FIG. 9, reference symbol A represents a memory cell area and reference symbol B represents a peripheral circuit area.
Reference numeral 10 represents a semiconductor substrate,reference numeral 12 represents an element separation oxide film,reference numeral 14 represents a MOS transistor for a memory cell constituting the memory cell area A, andreference numeral 16 represents a MOS transistor constituting the peripheral circuit area B. Further,reference numeral 14 a represents the source/drain of theMOS transistor 14, andreference numeral 14 b represents the gate of theMOS transistor 14.Reference numeral 16 a represents the source/drain of theMOS transistor 16, andreference numeral 16 b represents the gate of theMOS transistor 16.Reference numeral 18 represents an insulating layer, andreference numeral 20 represents a connection opening formed in theinsulating layer 18 and aconductive member 22 is filled in theconnection opening 20. - A cylindrical
capacitance stack electrode 24 is formed at the position corresponding to theconductive member 22 on theinsulating layer 18, acapacitance insulating film 26 is formed on the side surface and top surface of thecapacitance stack electrode 24, and acapacitance plate electrode 28 is formed on the capacitance insultingfilm 26. These members construct acapacitor 30. - An insulating film (interlayer insulating film)32 is formed on the
insulating layer 18 so as to cover thecapacitor 30. Since desired wires are formed on theinsulating film 32, the upper surface of theinsulating film 32 is flattened to prevent the wires from being broken during the wire forming process. - The process of manufacturing DRAM as described above will be described with reference to FIGS.10 to 15.
- First, as shown in FIG. 10, the element
separation oxide film 12 is formed on thesemiconductor substrate 10, and theMOS transistors insulating layer 18 is formed. - Subsequently, as shown in FIG. 11, the
connection opening 20 is formed in theinsulting layer 18, and theconductive member 22 is filled into the connection opening 20. - Subsequently, as shown in FIG. 12, the
capacitance stack electrode 24 is formed at the position corresponding to theconductive member 22, thecapacitance insulating film 26 is formed on thecapacitance stack electrode 24, and acapacitance plate electrode 28 is formed on thecapacitance insulating film 26, thereby forming thecapacitor 30. - Subsequently, the
interlayer insulating film 32 is formed on theinsulating layer 18 as shown in FIG. 13. At this time, the upper surface of theinterlayer insulating film 32 in the memory cell area A is higher than the upper surface of theinterlayer insulating film 32 in the peripheral circuit area B by the amount corresponding to the height of thecapacitor 30. Therefore, theinterlayer insulating film 32 of the memory cell area A is subjected to an etching treatment so that the upper surface of theinterlayer insulting film 32 in the memory cell area A is located at substantially the same height as the upper surface of theinterlayer insulating film 32 in the peripheral circuit area B. In order to perform the etching treatment, aphotoresist mask 34 is formed on theinterlayer insulating film 32 in the peripheral circuit area B. - Subsequently, as shown in FIG. 14, the etching treatment is conducted on the
interlayer insulating film 32 of the memory cell area A to substantially equalize the height of theinterlayer insulating film 32 in the memory cell area A with the height of theinterlayer insulating film 32 of the peripheral circuit area B. - Subsequently, as shown in FIG. 15, the
photoresist mask 34 is removed, and if necessary, an insulating film is further deposited to thereby form theinterlayer insulating film 32 having the flat upper face (surface), thereby forming DRAM as shown in FIG. 9. - The above DRAM is described in NIKKEI MICRODEVICES, November (1993), p.31.
- As described above, in the conventional DRAM, the capacitance stack electrode of the capacitor constituting the memory cell is formed of a pillar-shaped conductor, and thus there occurs a large difference in height (step) between the memory cell area and the peripheral circuit area when the interlayer insulating film is formed. As a result, since it is necessary to secure the flatness of the surface of the interlayer insulating film (particularly between the memory cell area and the peripheral circuit area) in order to smoothly form wires on the interlayer insulating film in the subsequent step, a photolithography step is further needed to selectively remove the interlayer insulating film only in the memory cell area after the interlayer insulating film is deposited as described above, and thus the number of steps is increased.
- Therefore, the present invention has been implemented to solve the foregoing problems of the prior art, and has an object to provide a semiconductor device in which an insulating film such as an interlayer insulating film having a flat surface can be formed without any specific step of flattening the insulating film after the insulating film is deposited, that is, without increasing the number of steps, and a method of manufacturing the semiconductor device.
- In order to attain the above object, according to a first aspect of the present invention, a semiconductor storage device having plural memory cells each containing a capacitor and a transistor is characterized in that a first insulating layer is formed so as to cover the transistor, the capacitor is formed on the first insulating layer, the capacitor contains a pillar-shaped insulating member formed on the first insulating layer, a first capacitance electrode formed on the side surface of the pillar-shaped insulating member, a capacitance insulating film formed on the first capacitance electrode and a second capacitance electrode formed on the capacitance insulating film, the first insulating layer has a connection opening formed therein, and the connection opening is filled with a conductive member for connecting the first capacitance electrode and the transistor to each other.
- In the semiconductor storage device described above, a second insulating layer formed of the same insulating material as the pillar-shaped insulating member of the capacitor is preferably formed at the same height as the pillar-shaped insulating member of the capacitor on the first insulating layer in at least a part of an area other than the memory cell area containing the plural memory cells.
- In the semiconductor storage device described above, the transistor is preferably a MOS transistor, and the source or drain of the MOS transistor is connected to the conductive member.
- According to a second aspect of the present invention, a method of manufacturing a semiconductor storage device having plural memory cells each containing a capacitor and a transistor is characterized by comprising the steps of: forming the transistor on a semiconductor substrate; forming a first insulating layer so that the transistor is covered by the first insulating layer; forming connection openings in the first insulating layer at the positions corresponding to the respective memory cells; filling a conductive member in each of the connection openings; forming an insulating material layer on the first insulating layer; subjecting the insulating material layer to a patterning treatment to form a pillar-shaped insulating member so that a part of the surface of the conductive member filled in each of the connection openings is covered by the pillar-shaped insulating member; forming a first capacitance electrode on the side surface of the pillar-shaped insulating member, connecting the first capacitance electrode and the conductive member to each other, forming a capacitance insulating film on the first capacitance electrode, and forming a second capacitance electrode on the capacitance insulating film.
- In the semiconductor storage device manufacturing method described above, the patterning treatment of the insulating material layer is preferably performed by using anisotropic etching.
- In the above semiconductor storage device manufacturing method, the formation of the first capacitance electrode is preferably performed by forming a conductive material layer and patterning the conductive material layer with anisotropic etching.
- In the above semiconductor storage device manufacturing method, the transistor is preferably a MOS transistor, and each connection opening is formed at the position corresponding to the source or drain of the MOS transistor.
- In the above semiconductor storage device manufacturing method, it is preferable that the insulating material layer is also formed in an area other than the memory cell area containing the plural memory cells on the semiconductor substrate, and the insulating material layer is subjected to a patterning treatment so that a second insulating layer having the same height as the pillar-shaped insulating member of the capacitor remains in the area other than the memory cell area.
- According to the present invention, the capacitor of the memory cell area is constructed while containing the pillar-shaped insulating member, and the pillar-shaped insulating member is formed simultaneously with formation of the interlayer insulating film in the area other than the memory cell area. Therefore, the surface flattening between the memory cell area and the other area can be easily performed without increasing the number of steps.
- FIG. 1 is a schematic cross-sectional view showing DRAM according to an embodiment of a semiconductor storage device of the present invention;
- FIG. 2 is a schematic cross-sectional view showing a manufacturing step of DRAM of FIG. 1;
- FIG. 3 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 4 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 5 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 6 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 7 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 8 is a schematic cross-sectional view showing another manufacturing step of DRAM of FIG. 1;
- FIG. 9 is a schematic diagram of conventional DRAM;
- FIG. 10 is a schematic cross-sectional view showing a manufacturing step of the conventional DRAM;
- FIG. 11 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM;
- FIG. 12 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM;
- FIG. 13 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM;
- FIG. 14 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM; and
- FIG. 15 is a schematic cross-sectional view showing another manufacturing step of the conventional DRAM.
- Preferred embodiments according to the present invention will be described hereunder with reference to the accompanying drawings.
- FIG. 1 is a schematic cross-sectional view of DRAM according to an embodiment of a semiconductor storage device of the present invention.
- In FIG. 1, reference symbol A represents a memory cell area, and reference symbol B represents a peripheral circuit area located so as to be adjacent to the memory cell area
A. Reference numeral 1 represents a semiconductor substrate,reference numeral 2 represents an element separation oxide film,reference numeral 3 represents a MOS transistor of one memory cell constituting the memory cell area A, andreference numeral 4 represents a MOS transistor constituting the peripheral circuit areaB. Reference numeral 3 a represents the source/drain of theMOS transistor 3, andreference numeral 3 b represents the gate of theMOS transistor 3.Reference numeral 4 a represents the source/drain of theMOS transistor 4, and reference numeral represents the gate of theMOS transistor 4. -
Reference numeral 5 represents a first insulating layer,reference numeral 6 represents a connection opening formed in theinsulating layer 5, and aconductive member 7 is filled in theconnection opening 6. The lower end portion of theconductive member 7 is connected to one of the source/drain 3 a of theMOS transistor 3. - In the memory cell area A, the
capacitor 8 constituting the memory cell is formed on theinsulating layer 5. Thecapacitor 8 has a pillar-shaped insulating member 8 a, afirst capacitance electrode 8 b formed on the side surface of the pillar-shapedinsulating member 8 a, acapacitance insulating film 8 c which is formed so as to cover the pillar-shapedinsulating member 8 a and thefirst capacitance electrode 8 b, and asecond capacitance electrode 8d which is formed so as to cover thecapacitance insulating film 8 c. The pillar-shaped insulatingmember 8 a is disposed so that a part of the lower end portion of the pillar-shaped insulatingmember 8 a is connected to the upper end portion of theconductive member 7, and the lower end portion of thefirst capacitance electrode 8 b is connected to the upper end portion of theconductive member 7. - In the peripheral circuit area B, a second
insulating layer 9 is formed on the insulatinglayer 5. The secondinsulating layer 9 is formed at the same height as the pillar-shaped insulatingmember 8 a of thecapacitor 8, and formed of the same insulating material as the pillar-shaped insulatingmember 8 a of thecapacitor 8. The secondinsulating layer 9 serves as an interlayer insulating film. - As not shown, an insulating film or a wiring layer may be formed on the structure shown in FIG. 1.
- The manufacturing process of the above DRAM will be described with reference to FIGS.1 to 8.
- First, as shown in FIG. 2, the element
separation oxide film 2 is formed on thesemiconductor substrate 1, and theMOS transistors layer 5 are formed. - Subsequently, as shown in FIG. 3, the
connection opening 6 is formed at the position corresponding to one of the source/drain 3 a of theMOS transistor 3 in the insulatinglayer 5, and theconductive member 7 is filled in theconnection opening 6 thus formed, whereby theconductive member 7 is connected to the source/drain 3 a. - Subsequently, as shown in FIG. 4, an insulating
material layer 9′ is formed on the insulatinglayer 5 in the memory cell area A and the peripheral circuit area B. - Subsequently, as shown in FIG. 5, a mask pattern is formed by photolithography, and anisotropic etching is conducted to subject the insulating
material layer 9′ to a patterning treatment, thereby forming the pillar-shapedinsulting member 8 a such as cylindrical insulating member in the memory cell area A and the second insulatinglayer 9 in the peripheral circuit area B. Accordingly, the pillar-shaped insulatingmember 8 a and the second insulatinglayer 9 are formed of the same material and the same height. A part of the upper portion of theconductive member 7 is covered by the pillar-shaped insulatingmember 8 a, but the other part is exposed. - Subsequently, as shown in FIG. 6, a
conductive film 8 b′ is deposited on the overall surface of the intermediate product shown in FIG. 5 by a method such as CVD method or the like which is excellent in step coverage performance. - Subsequently, as shown in FIG. 7, by conducting the anisotropic etching, the conductive film is left only at the side surface of the pillar-shaped insulating
member 8 a in the memory cell area A to form thefirst capacitance electrode 8 b. At this time, the lower end portion of thefirst capacitance electrode 8 b is connected to theconductive member 7. - Subsequently, as shown in FIG. 8, an insulating
film 8 c′ is deposited and formed on the overall surface of the intermediate product shown in FIG. 7 by the method such as CVD method which is excellent in step coverage performance, and aconductive film 8 d′ is deposited and formed on the insulatingfilm 8 c′. Thereafter, theconductive film 8 d′ and the insulatingfilm 8 c′ are subjected to patterning, thereby obtaining the semiconductor storage device shown in FIG. 1. - As described above, according to this embodiment, the pillar-shaped insulating
member 8 a and the second insulatinglayer 9 are formed by the patterning of the insulatingmaterial layer 9′, and thus they are formed of the same insulating material and are formed at the same height. Accordingly, without increasing the number of steps, there can be easily prevented occurrence of the difference in height between the surfaces of the memory cell area A and the other area.
Claims (8)
1. A semiconductor storage device having plural memory cells each containing a capacitor and a transistor, characterized in that a first insulating layer is formed so as to cover said transistor, said capacitor is formed on said first insulating layer, said capacitor contains a pillar-shaped insulating member formed on said first insulating layer, a first capacitance electrode formed on the side surface of said pillar-shaped insulating member, a capacitance insulating film formed on said first capacitance electrode and a second capacitance electrode formed on said capacitance insulating film, said first insulating layer has a connection opening formed therein, and said connection opening is filled with a conductive member for connecting said first capacitance electrode and said transistor to each other.
2. The semiconductor storage device as claimed in claim 1 , wherein a second insulating layer formed of the same insulating material as said pillar-shaped insulating member of said capacitor is formed at the same height as said pillar-shaped insulating member of said capacitor on said first insulating layer in at least a part of an area other than the memory cell area containing the plural memory cells.
3. The semiconductor storage device as claimed in any one of claims 1 and 2, wherein said transistor is a MOS transistor, and the source or drain of said MOS transistor is connected to said conductive member.
4. A method of manufacturing a semiconductor storage device having plural memory cells each containing a capacitor and a transistor, characterized by comprising the steps of:
forming the transistor on a semiconductor substrate;
forming a first insulating layer so that the transistor is covered by the first insulating layer;
forming connection openings in the first insulating layer at the positions corresponding to the respective memory cells;
filling a conductive member in each of the connection openings;
forming an insulating material layer on the first insulating layer;
subjecting the insulating material layer to a patterning treatment to form a pillar-shaped insulating member so that a part of the surface of the conductive member filled in each of the connection openings is covered by the pillar-shaped insulating member;
forming a first capacitance electrode on the side surface of the pillar-shaped insulating member;
connecting the first capacitance electrode and the conductive member to each other, forming a capacitance insulating film on the first capacitance electrode; and
forming a second capacitance electrode on the capacitance insulating film.
5. The semiconductor storage device manufacturing method as claimed in claim 4 , wherein the patterning treatment of the insulating material layer is performed by using anisotropic etching.
6. The semiconductor storage device manufacturing method as claimed in claim 4 , wherein the formation of the first capacitance electrode is performed by forming a conductive material layer and patterning the conductive material layer with anisotropic etching.
7. The above semiconductor storage device manufacturing method as claimed in claim 4 , wherein the transistor is a MOS transistor, and each connection opening is formed at the position corresponding to the source or drain of the MOS transistor.
8. The semiconductor storage device manufacturing method as claimed in any one of claims 4 to 7 , wherein the insulating material layer is also formed in an area other than the memory cell area containing the plural memory cells on the semiconductor substrate, and the insulating material layer is subjected to a patterning treatment so that a second insulating layer having the same height as the pillar-shaped insulating member of the capacitor remains in the area other than the memory cell area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/373,693 US20030127679A1 (en) | 1999-10-01 | 2003-02-27 | Semiconductor storage device and method of manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP281550/1999 | 1999-10-01 | ||
JP28155099A JP2001102546A (en) | 1999-10-01 | 1999-10-01 | Semiconductor memory and manufacturing method therefor |
US09/667,695 US6559495B1 (en) | 1999-10-01 | 2000-09-22 | Semiconductor memory cell device |
US10/373,693 US20030127679A1 (en) | 1999-10-01 | 2003-02-27 | Semiconductor storage device and method of manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/667,695 Division US6559495B1 (en) | 1999-10-01 | 2000-09-22 | Semiconductor memory cell device |
Publications (1)
Publication Number | Publication Date |
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US20030127679A1 true US20030127679A1 (en) | 2003-07-10 |
Family
ID=17640754
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/667,695 Expired - Fee Related US6559495B1 (en) | 1999-10-01 | 2000-09-22 | Semiconductor memory cell device |
US10/373,693 Abandoned US20030127679A1 (en) | 1999-10-01 | 2003-02-27 | Semiconductor storage device and method of manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/667,695 Expired - Fee Related US6559495B1 (en) | 1999-10-01 | 2000-09-22 | Semiconductor memory cell device |
Country Status (2)
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US (2) | US6559495B1 (en) |
JP (1) | JP2001102546A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022033147A1 (en) * | 2020-08-13 | 2022-02-17 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
Families Citing this family (3)
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JP4282245B2 (en) * | 2001-01-31 | 2009-06-17 | 富士通株式会社 | Capacitor element, manufacturing method thereof, and semiconductor device |
JP5588123B2 (en) * | 2009-05-22 | 2014-09-10 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and manufacturing method thereof |
CN116133385A (en) * | 2021-08-30 | 2023-05-16 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Family Cites Families (2)
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JP2956482B2 (en) * | 1994-07-29 | 1999-10-04 | 日本電気株式会社 | Semiconductor memory device and method of manufacturing the same |
US6025624A (en) * | 1998-06-19 | 2000-02-15 | Micron Technology, Inc. | Shared length cell for improved capacitance |
-
1999
- 1999-10-01 JP JP28155099A patent/JP2001102546A/en active Pending
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2000
- 2000-09-22 US US09/667,695 patent/US6559495B1/en not_active Expired - Fee Related
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2003
- 2003-02-27 US US10/373,693 patent/US20030127679A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022033147A1 (en) * | 2020-08-13 | 2022-02-17 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
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US6559495B1 (en) | 2003-05-06 |
JP2001102546A (en) | 2001-04-13 |
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