WO2022022008A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022022008A1
WO2022022008A1 PCT/CN2021/093894 CN2021093894W WO2022022008A1 WO 2022022008 A1 WO2022022008 A1 WO 2022022008A1 CN 2021093894 W CN2021093894 W CN 2021093894W WO 2022022008 A1 WO2022022008 A1 WO 2022022008A1
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isolation
layer
isolation trench
semiconductor substrate
forming
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PCT/CN2021/093894
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English (en)
French (fr)
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冯伟
洪海涵
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长鑫存储技术有限公司
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Priority to US17/386,501 priority Critical patent/US11869802B2/en
Publication of WO2022022008A1 publication Critical patent/WO2022022008A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • the isolation trench is prone to generate thicker silicon pads at the bottom of the high aspect ratio area during polysilicon deposition.
  • the subsequent oxidation process cannot be completely oxidized, so that the isolation effect of the formed isolation structure is weakened, resulting in electrical abnormality of the semiconductor device.
  • Embodiments of the present application provide a method for forming a semiconductor structure and a semiconductor structure, in which the feature size of the bottom of the isolation trench is enlarged under the condition that the feature size of the active region between the isolation trenches is kept unchanged, thereby improving the isolation of the formed isolation structure. Effect.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, and the semiconductor substrate has a plurality of isolation trenches distributed at intervals; the isolation trenches include a top region isolation trench and a bottom region isolation trench, Wherein, the top region isolation trench is higher than the bottom region isolation trench; a first protective layer covering the sidewall of the top region isolation trench and the top of the semiconductor substrate is formed; the bottom region isolation trench is oxidized to remove part of the semiconductor near the bottom region isolation trench The substrate is oxidized to form a second substrate isolation layer; a dielectric layer filling the isolation trench is formed, and the first protective layer and the dielectric layer above the top of the semiconductor substrate are etched to form an isolation structure.
  • the semiconductor substrate between the isolation trenches is prevented from being oxidized during the manufacturing process, thereby causing the feature size of the active area between the isolation trenches.
  • the bottom area isolation trench is oxidized, and the semiconductor substrate near the bottom area isolation trench is converted into the second base isolation layer.
  • part of the ingrowth and part of the Outgrowth so that in the direction parallel to the top surface of the semiconductor substrate, the feature size of the bottom of the isolation structure formed by subsequent filling is larger than the feature size of the bottom region isolation trench formed, thereby improving the isolation effect of the formed isolation structure.
  • forming a first protective layer covering the sidewalls of the isolation trenches in the top region and the top of the semiconductor substrate includes: forming a first protective film covering the top of the semiconductor substrate and the sidewalls of the isolation trenches; forming a sacrificial layer filling the isolation trenches in the bottom region; The top of the substrate and the first protective film on the sidewall of the isolation trench in the top region are processed to form a first protective layer; the sacrificial layer and the untreated first protective film are removed, wherein the etching rate of the first protective layer is lower than that of the first protective layer. The etch rate of the protective film.
  • forming a sacrificial layer filling the isolation trenches in the bottom region includes: forming a sacrificial film filling the isolation trenches, the sacrificial film also covering the top surface of the semiconductor substrate; removing the sacrificial film higher than the surface of the first protective film; removing the sacrificial film located in the isolation trenches in the top region the sacrificial film to form a sacrificial layer.
  • the processing includes ion implantation, and the implanted ions include at least one of phosphorus, arsenic, boron, boron fluoride and carbon.
  • the ion implantation is carried out by means of oblique implantation, and the inclination angle ranges from 15° to 20°.
  • the first protective film includes a monocrystalline silicon layer, a polycrystalline silicon layer or a germanium layer; before forming the dielectric layer filling the isolation trench, the method further includes: oxidizing the first protective layer to convert the first protective layer into a first protective layer. Base isolation layer.
  • the process temperature used for the oxidation treatment is in the range of 750°C to 1000°C.
  • the oxidation treatment expands the feature size of the bottom of the isolation trench, the first base isolation layer and the second base isolation layer formed by the oxidation treatment have good compactness and fewer defects, and the isolation structure formed subsequently has better isolation effect.
  • the method further includes: forming a second protective layer on the top of the semiconductor substrate; and the first protective layer covers the top and sidewalls of the second protective layer.
  • the method further includes: forming a barrier layer on the sidewall of the isolation trench, and the material of the barrier layer is different from the material of the first protective layer and the material of the semiconductor substrate.
  • the barrier layer is formed to prevent the semiconductor substrate on the sidewall of the isolation trench from being oxidized, and also for preventing the etching of the semiconductor substrate on the sidewall of the isolation trench during the manufacturing process.
  • the thickness of the formed barrier layer ranges from 30 angstroms to 70 angstroms.
  • the thickness of the isolation trenches in the top region is less than the thickness of the isolation trenches in the bottom region, and the thickness of the isolation trenches in the top region is greater than two times the thickness of the isolation trenches in the bottom region. one part.
  • the embodiments of the present application further provide a semiconductor structure, including: a semiconductor substrate, and a plurality of isolation trenches distributed at intervals on the semiconductor substrate; the isolation trenches include a top region isolation trench and a bottom region isolation trench, and the top region isolation trench is higher than the bottom region isolation trench A trench; a top isolation structure for filling the top region isolation trench, the top isolation structure including a first base isolation layer on the sidewall of the top region isolation trench and a dielectric layer for filling the top region isolation trench; a bottom isolation structure for filling the bottom Area isolation trench, the bottom isolation structure includes a second base isolation layer located on the sidewall of the bottom area isolation trench and a dielectric layer filling the bottom area isolation trench; in any direction parallel to the surface of the semiconductor substrate, the size of the bottom isolation structure is larger than that of the bottom The size of the zone isolation slot.
  • the height of the top isolation structure is smaller than that of the bottom isolation structure, and the height of the top isolation structure is greater than half of the height of the bottom isolation structure.
  • the semiconductor structure further includes: a barrier layer, the barrier layer is located on the sidewall of the isolation trench; the first base isolation layer is located on the sidewall of the barrier layer in the isolation trench in the top region, and a part of the second base isolation layer is located between the semiconductor substrate and the barrier layer , and part of the second base isolation layer is located between the barrier layer and the dielectric layer.
  • the thickness of the barrier layer is 30 angstroms to 70 angstroms.
  • the first protective layer prevents the semiconductor substrate between the isolation trenches from being oxidized during the manufacturing process, thereby preventing the feature size of the active region between the isolation trenches from being reduced.
  • the second base isolation layer partially occupies the position of the original semiconductor substrate and partially occupies the position of the isolation trench, so that the feature size of the bottom of the isolation structure formed by filling is larger than that of the isolation trench formed in the bottom region, thereby improving the isolation of the isolation structure formed. Effect.
  • 1 to 15 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, and the semiconductor substrate has a plurality of isolation trenches distributed at intervals; the isolation trenches include a top region isolation trench and a bottom region isolation trench, Wherein, the top region isolation trench is higher than the bottom region isolation trench; a first protective layer covering the sidewall of the top region isolation trench and the top of the semiconductor substrate is formed; the bottom region isolation trench is oxidized to remove part of the semiconductor near the bottom region isolation trench The substrate is oxidized to form a second substrate isolation layer; a dielectric layer filling the isolation trench is formed, and the first protective layer and the dielectric layer above the top of the semiconductor substrate are etched to form an isolation structure.
  • FIG. 15 are schematic cross-sectional structural diagrams corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • a semiconductor substrate 101 is provided.
  • the semiconductor substrate 101 has a plurality of isolation trenches 105 distributed at intervals.
  • a second protective layer 102 is provided on the top of the semiconductor substrate 101 between the isolation trenches 105 .
  • the isolation trenches 105 include: top area isolation The trench 115 and the bottom region isolation trench 125 ; wherein the top region isolation trench 115 is higher than the bottom region isolation trench 125 .
  • a semiconductor substrate 101 is formed on the semiconductor substrate 101 in sequence with a second protective layer 102 , a mask layer 103 and a photoresist layer 104 .
  • the second protective layer 102 is made of silicon nitride material.
  • the silicon nitride material is used as an insulating material and is not easily oxidized.
  • the top of the semiconductor substrate 101 between the isolation trenches 105 is oxidized.
  • the second protective layer can also be made of insulating materials such as silicon oxide and silicon oxynitride.
  • the method for forming the semiconductor structure includes a scheme of forming a second protective layer, the second protective layer is used to further prevent the top surface of the semiconductor substrate from being oxidized, and the coverage area of the first protective layer includes The contact surface of the second protective layer and the semiconductor substrate is used to prevent the contact surface of the semiconductor substrate and the second protective layer from being oxidized, thereby resulting in morphology defects.
  • the second protective layer may not be formed.
  • the patterned photoresist layer 104 etches the mask layer 103 , the second protective layer 102 and the semiconductor substrate 101 to form a plurality of isolation trenches 105 distributed at intervals, and the isolation trenches 105 are used for subsequent formation of isolation structures.
  • the feature size of the top of the semiconductor substrate 101 between the isolation trenches 105 is CD1
  • the feature size of the isolation trench 125 in the bottom region on the preset plane is CD2
  • the top of the etched semiconductor substrate 101 has a mask layer 103
  • a mask Layer 103 has a patterned photoresist layer 104 on top.
  • the photoresist layer 104 and the mask layer 103 are sequentially removed.
  • the photoresist layer 104 is removed by a first dry cleaning process.
  • the first dry cleaning process uses a mixed gas of ammonia, nitrogen and hydrogen, and the mixed gas reacts with the photoresist layer 104 to form a first cured product , and then the first cured product is evaporated by means of high temperature evaporation, that is, the removal of the photoresist layer 104 is completed.
  • the isolation groove 105 is prevented. In contact with the air, while removing the photoresist layer 104, natural oxidation of the semiconductor substrate 101 on the sidewalls of the isolation trench 104 is prevented.
  • only the mixed gas for removing the photoresist layer may be used to perform the above-mentioned first dry cleaning process.
  • the mixed solution of 49% HF and 1:1:60 APM is used to react with the mask layer 103 to remove the mask layer 103. Since the mixed solution contains NH 4 OH, ionization will occur. OH-, due to the negative charge repulsion of OH- and the oxidizing property of H 2 O 2 , the particulate matter on the sidewall of the isolation trench 105 can be removed. In other embodiments, only the mixed liquid for removing the mask layer may be used to perform the above-mentioned first wet cleaning process.
  • This embodiment also includes a method for forming a barrier layer.
  • a barrier layer 106 is formed on the sidewall of the isolation trench 105 , and the material of the barrier layer 106 is different from the material of the subsequently formed first protective layer and the material of the semiconductor substrate 101 . .
  • the barrier layer 106 is formed in the isolation trench 105, in order to ensure the isolation effect of the isolation structure formed by the isolation trench 105, a material with better insulating properties needs to be used as the material of the barrier layer 106, that is, in this embodiment, the barrier layer 106 is formed using a silicon oxide material. Specifically, in this embodiment, the thickness of the barrier layer 106 ranges from 30 angstroms to 70 angstroms, for example, 35 angstroms, 40 angstroms, 45 angstroms, 50 angstroms, 55 angstroms, 60 angstroms or 65 angstroms.
  • the method for forming the barrier layer 106 includes forming the barrier layer 106 on the sidewall of the isolation trench 105 by means of atomic layer deposition (ALD), chemical vapor deposition (CVD) or epitaxial growth.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the barrier layer 106 can be grown faster by using ALD, CVD or epitaxial growth to prevent natural oxidation of the semiconductor substrate 101 on the sidewalls of the isolation trench 105 .
  • the method for forming the barrier layer 106 in this embodiment does not constitute a limitation to this embodiment; in other embodiments, the method for forming the semiconductor structure in this embodiment may also be performed by a method without forming a barrier layer.
  • a first protective layer 117 covering the sidewalls of the isolation trenches 115 in the top region is formed.
  • a first protective film 107 is formed covering the sidewalls of the isolation trenches 105 , and the first protective film 107 is used for the subsequent formation of the first protective layer 117 to protect the sidewalls of the isolation trenches 115 in the top region.
  • a sacrificial layer 108 is formed to fill the bottom region isolation trench 125 .
  • a sacrificial film 118 filling the isolation trench 105 is formed; further, the sacrificial film 118 covers the first protective film 107 above the semiconductor substrate 101 .
  • the sacrificial film 118 above the top of the first protective film 107 is removed by chemical mechanical polishing, so that the height of the remaining sacrificial film 118 is the same as that of the first protective film 107 .
  • the remaining sacrificial film 118 is etched downward along the isolation trench 105 to form a sacrificial layer 108 filling the isolation trench 125 in the bottom region, and the etching exposes the first protective film 107 on the sidewall of the isolation trench 115 in the top region.
  • the material of the sacrificial layer 108 is the same as the material of the photoresist layer 104, and the sacrificial layer 108 can be removed by a first dry cleaning process; in another example, the material of the sacrificial layer 108 can be a carbon-containing material , which can be removed by an ashing process later.
  • the first protective film 107 located on the sidewalls and the top surface of the second protective layer 102 is not removed, that is, the subsequent formation of the first protective layer 117 also covers part of the sidewalls and the top surface of the second protective layer 102 . That is, the area covered by the first protective layer 117 includes the contact surface between the second protective layer 102 and the semiconductor substrate 101 , which can prevent the “bird’s beak effect” (“bird’s beak”) caused by oxidation of the contact surface between the second protective layer 102 and the semiconductor substrate 101 .
  • the generated oxide layer will grow in part and grow out, so that the original top surface of the semiconductor substrate 101 becomes uneven, resulting in the semiconductor substrate 101 and the second protective layer 102.
  • the contact surface is raised to produce a "bird's beak"-like angle).
  • the first protective film located on the sidewalls and the top of the second protective layer may also be removed, and the first protective layer formed at this time is only located on the sidewalls of the top region.
  • the height difference between the height of the formed sacrificial layer 108 and the height of the top of the isolation trench 105 accounts for about 1/3 to 1/2 of the depth of the isolation trench 105 , that is, in the vertical direction of the semiconductor substrate 101 In the direction, the height of the top region isolation trench 115 is less than the height of the bottom region isolation trench 125 , and the height of the top region isolation trench 115 is greater than half the height of the bottom region isolation trench 125 .
  • the exposed first protective film 107 is processed to form a first protective layer 117 .
  • the treatment includes ion implantation, so that the hardness of the first protective layer 117 is greater than that of the first protective film 107, so that the etching rate is lower during subsequent etching (the etching rate of the first protective layer 117 is lower than that of the first protective film 107). etch rate), the first protective layer 117 and the first protective film 107 have a larger etching selectivity ratio, so that the first protective layer 117 is more difficult to etch.
  • the implanted ions include at least one of phosphorus, arsenic, boron, boron fluoride and carbon; the ion implantation is performed by means of oblique implantation, and the inclination angle ranges from 15° to 20°, for example, 16° °, 17°, 18° or 19°.
  • the sacrificial layer 108 and the first protective film 107 without ion implantation are removed, and the first protective layer 117 is formed on the sidewall of the isolation trench 115 in the top region.
  • the sacrificial layer 108 is removed.
  • the sacrificial layer 108 is removed using a second dry cleaning process.
  • the mixed gas used in the second dry cleaning includes at least oxygen, which can remove the sacrificial layer 108 as quickly as possible.
  • the barrier layer 106 since the barrier layer 106 is formed, the semiconductor substrate 101 on the sidewall of the trench 105 can be prevented from being isolated at this time. Oxidized.
  • the first protective film 107 without ion implantation is removed, and a first protective layer 117 is formed on the sidewall of the isolation trench 115 in the top region.
  • the first protective layer 117 is used to prevent the semiconductor substrate 101 between the isolation trenches 105 from being oxidized, thereby preventing the CD1 from being reduced, and ensuring that the area of the active region is not reduced. That is, the main purpose of the subsequently formed first protective layer 117 is to prevent the sidewalls of the isolation trenches 115 in the top region from being oxidized.
  • the second wet cleaning process is used to remove the first protective film 107 without ion implantation.
  • the second wet cleaning process is etched using a material with an etch selectivity ratio (the etch rate of the first protective film 107 without ion implantation is greater than the etch rate of the first protective layer 117 ); in one example , and a second wet cleaning process is performed using NH 4 OH or KOH solution to remove the first protective film 107 without ion implantation.
  • the first protective film 107 includes a monocrystalline silicon layer, a polycrystalline silicon layer or a germanium layer, that is, the material of the first protective film 107 is monocrystalline silicon, polycrystalline silicon or germanium.
  • the first protective film 107 without ion implantation can be easily removed by etching.
  • an etching selectivity ratio is formed, which is used to prevent the semiconductor substrate 101 of the sidewall of the isolation trench 105 from being etched.
  • the bottom region isolation trench 125 is oxidized to convert the semiconductor substrate 101 close to the bottom region isolation trench 125 into the second base isolation layer 201 .
  • the second base isolation layer 201 formed by the oxidation treatment is partially grown on the surface of the barrier layer 106 , that is, part of the second base isolation layer 201 is located between the semiconductor substrate 101 and the barrier layer 106 , and part of the second base isolation layer is isolated from the surface of the barrier layer 106 .
  • the layer 201 is located on the side of the barrier layer 106 away from the semiconductor substrate 101 .
  • the process temperature used in the oxidation treatment is in the range of 750°C to 1000°C.
  • 800°C, 850°C, 900°C or 950°C can be used.
  • the first base isolation layer 202 and the second base isolation layer 201 formed by oxidation treatment have good compactness and fewer defects, and the isolation structure formed subsequently has good isolation effect.
  • the material of the barrier layer 106 is the same as the material of the second base isolation layer 201 .
  • the first protective layer 117 needs to be oxidized to convert the first protective layer 117 into the first base isolation layer 202 .
  • the first base isolation layer 202 and the second base isolation layer 201 are formed by simultaneous oxidation in one step of oxidation treatment; the first protective layer 117 is converted into the first base isolation layer 202 to ensure the barrier layer in the isolation trench 105 106.
  • the first base isolation layer 202, the second base isolation layer 201, and the dielectric layer formed subsequently are all formed of the same material, so as to ensure the uniformity of the isolation material, and the isolation effect is better.
  • the base material for ion implantation is monocrystalline silicon, polycrystalline silicon or germanium, which is easily oxidized to form the first base isolation layer 202 .
  • a dielectric layer 109 filling the isolation trenches 105 is formed.
  • the dielectric layer 109 , the first base isolation layer 202 and the second protective layer 102 above the top of the semiconductor substrate 101 are etched to form an isolation structure.
  • the isolation structures include a top isolation structure 135 located in the top region isolation trench 115 and a bottom isolation structure 145 located in the bottom region isolation trench 125 .
  • the ALD process or CVD process is used to fill the isolation trench 105 to form the dielectric layer 109.
  • the ALD process or the CVD process has the characteristics of slow deposition rate, high density of the deposited film and good step coverage.
  • the electrical layer 109 can completely fill the remaining isolation trenches 105 to form a dense insulating structure.
  • the material of the dielectric layer 109 is the same as the material of the first base isolation layer 202, and both are silicon oxide to ensure isolation.
  • the isolation materials in the grooves 105 are all of the same material and have continuity.
  • the dielectric layer 109, the first base isolation layer 202 and the second protective layer 102 higher than the surface of the semiconductor substrate 101 are subsequently etched away, that is, an isolation structure is formed.
  • the feature size on the top of the semiconductor substrate 101 between the isolation structures is different. change, that is, the feature size CD1 of the active region remains unchanged, which ensures that a sufficient area is left for subsequent capacitive contact or bit line contact, so that the contact performance of the semiconductor device is improved.
  • the feature size of the formed isolation structure becomes larger, that is, the feature size of the bottom of the isolation structure formed in the above-mentioned manner on the preset plane is larger than the feature size of the isolation trench in the bottom region (that is, CD3 is larger than CD2), thereby improving the isolation effect of the isolation structure. .
  • the semiconductor substrate between the isolation trenches is prevented from being oxidized during the manufacturing process of the isolation trenches, thereby causing the characteristics of the active area between the isolation trenches.
  • the size becomes smaller; then the bottom area isolation trench is oxidized to convert the semiconductor substrate close to the bottom area isolation trench into the second base isolation layer.
  • part of the ingrowth and part of the isolation layer are formed. Outward growth, in a direction parallel to the top surface of the semiconductor substrate, the feature size of the bottom of the isolation structure formed by subsequent filling is larger than that of the bottom region isolation trench formed, thereby improving the isolation effect of the formed isolation structure.
  • Another embodiment of the present application relates to a semiconductor structure.
  • FIGS. 12 to 15 the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, and the same or corresponding parts as those of the above-mentioned embodiment will not be described in detail below.
  • the semiconductor structure includes: a semiconductor substrate 101 with a plurality of isolation trenches 105 distributed at intervals on the semiconductor substrate 101; the isolation trenches 105 include a top region isolation trench 115 and a bottom region isolation trench 125, wherein the top region isolation trench 115 is higher than the bottom region isolation trench The trench 125; the top isolation structure 135 is used to fill the top region isolation trench 115, and the top isolation structure 135 includes the first base isolation layer 202 located on the sidewall of the top region isolation trench 115 and the dielectric layer 109 filling the top region isolation trench 115; The bottom isolation structure 145 is used to fill the bottom region isolation trench 125, and the bottom isolation structure 145 includes a second base isolation layer 201 located on the sidewall of the bottom region isolation trench 145 and a dielectric layer 109 filling the bottom region isolation trench; parallel to the semiconductor In any direction on the surface of the substrate 101 , the size of the bottom isolation structure 145 is larger than the size of the bottom region isolation trench 115 .
  • the size of the bottom isolation structure 145 is larger than the size of the bottom region isolation trench 125 .
  • the isolation trench 105 is used for subsequent formation of the isolation structure.
  • the feature size of the top of the semiconductor substrate 101 between the isolation trenches 105 is CD1
  • the feature size of the isolation trench 125 in the bottom region on the predetermined plane is CD2.
  • the height of the isolation trenches 115 in the top region is smaller than the height of the isolation trenches in the bottom region, and the height of the isolation trenches in the top region is greater than two times the height of the isolation trenches in the bottom region. one part. That is, the height of the top isolation structure 135 is smaller than the height of the bottom isolation structure 145 , and the height of the top isolation structure 135 is greater than half of the height of the bottom isolation structure 145 .
  • the semiconductor structure further includes: a barrier layer 106 located on the sidewall of the isolation trench 105 , at this time, the first base isolation layer 202 is located on the sidewall of the barrier layer 106 of the isolation trench 115 in the top region, and the barrier layer 106 is located on the semiconductor between the substrate 101 and the first substrate isolation layer 202 .
  • the material of the barrier layer 106 is different from the material of the semiconductor substrate 101 because the barrier layer 106 is formed to prevent the semiconductor substrate 101 on the sidewall of the isolation trench 105 from being oxidized; the etching selectivity ratio is formed due to the material difference to prevent the process process In the process, the semiconductor substrate 101 on the sidewall of the isolation trench 105 is etched.
  • the top isolation structure 135 is used to fill the top area isolation trench 115 , and the top isolation structure 135 includes the first base isolation layer 202 located on the sidewall of the top area isolation trench 115 and the dielectric for filling the top area isolation trench 115 Layer 109; bottom isolation structure 145 for filling bottom area isolation trench 125, bottom isolation structure 145 including second base isolation layer 201 on the sidewall of bottom area isolation trench 125 and dielectric layer 109 filling bottom area isolation trench.
  • the barrier layer 106 is formed of a silicon oxide material. Specifically, in this embodiment, the thickness of the barrier layer 106 ranges from 30 angstroms to 70 angstroms, for example, 35 angstroms, 40 angstroms, 45 angstroms, 50 angstroms, 55 angstroms, 60 angstroms or 65 angstroms.
  • the second base isolation layer 201 is converted from the semiconductor base 101 , and partially occupies the position of the original semiconductor base 101 and partially occupies the position of the original isolation trench 105 . Since the second base isolation layer 201 partially occupies the position of the semiconductor base 101 , the feature size at the bottom of the formed isolation structure is larger than that at the bottom of the isolation trench 105 , that is, in any direction parallel to the surface of the semiconductor base 101 , the bottom isolation structure 145 The size of the bottom isolation structure 145 is larger than the size of the bottom region isolation trench 125 in the direction perpendicular to the surface of the semiconductor substrate 101 .
  • the material of the dielectric layer 109 and the material of the second base isolation layer 201 are both silicon oxide to ensure the isolation trench
  • the isolation materials in 105 are all the same material and have continuity.
  • the first protective layer prevents the semiconductor substrate between the isolation trenches from being oxidized during the manufacturing process, thereby preventing the feature size of the active region between the isolation trenches from being reduced.
  • the second base isolation layer partially occupies the position of the original semiconductor substrate and partially occupies the position of the isolation trench, so that the feature size of the bottom of the isolation structure formed by filling is larger than the feature size of the isolation trench formed in the bottom region, thereby increasing the isolation structure formed. isolation effect.

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Abstract

本申请实施例提供一种半导体结构的形成方法及半导体结构，半导体结构的形成方法，包括：提供半导体基底(101)，半导体基底(101)上具有间隔分布的若干隔离槽(105)；隔离槽(105)包括顶部区域隔离槽(115)和底部区域隔离槽(125)；形成覆盖顶部区域隔离槽(115)侧壁和半导体基底(101)顶部的第一保护层(117)；对底部区域隔离槽(125)进行氧化处理，以将靠近底部区域隔离槽(115)的部分半导体基底(101)氧化形成第二基底隔离层(201)；形成填充隔离槽(105)的介电层(109)，并刻蚀高于半导体基底(101)顶部的第一保护层(117)和介电层(109)，以形成隔离结构；本申请实施例旨在提高形成的隔离结构的隔离效果。

Description

半导体结构的形成方法及半导体结构
交叉引用
本申请引用于2020年7月29日递交的名称为“半导体结构的形成方法及半导体结构”的第202010745804.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构的形成方法及半导体结构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种广泛应用于计算机系统的半导体存储器。随着半导体集成电路器件的特征尺寸不断缩小，DRAM的关键尺寸也越来越小，制作难度越来越大。
随着DRAM制程技术来到17nm左右，由于多晶硅薄层补偿技术的引入，隔离槽在进行多晶硅沉积时易在高深宽比的区域底部产生较厚的硅衬垫，底部较厚的硅衬垫在后续氧化制程中不能被氧化完全，从而使得形成的隔离结构的隔离效果减弱，导致半导体器件的电性异常。
发明内容
本申请实施例提供一种半导体结构的形成方法及半导体结构，在保证隔离槽之间有源区的特征尺寸不变的情况下，扩大隔离槽底部的特征尺寸，从而提高形成的隔离结构的隔离效果。
为解决上述技术问题，本申请实施例提供了一种半导体结构的形成方法， 包括：提供半导体基底，半导体基底上具有间隔分布的若干隔离槽；隔离槽包括顶部区域隔离槽和底部区域隔离槽，其中，顶部区域隔离槽高于底部区域隔离槽；形成覆盖顶部区域隔离槽侧壁和半导体基底顶部的第一保护层；对底部区域隔离槽进行氧化处理，以将靠近底部区域隔离槽的部分半导体基底氧化形成第二基底隔离层；形成填充隔离槽的介电层，并刻蚀高于半导体基底顶部的第一保护层和介电层，以形成隔离结构。
与相关技术相比，通过在顶部区域隔离槽侧壁形成第一保护层，防止隔离槽在制程过程中，隔离槽之间的半导体基底被氧化，从而造成隔离槽之间有源区的特征尺寸变小；然后对底部区域隔离槽进行氧化处理，将靠近底部区域隔离槽的半导体基底转化为第二基底隔离层，半导体基底转化为第二基底隔离层的过程中，部分向内生长、部分向外生长，使得在平行于半导体基底顶部表面的方向上，后续填充形成的隔离结构底部的特征尺寸大于形成的底部区域隔离槽的特征尺寸，从而提高形成的隔离结构的隔离效果。
另外，形成覆盖顶部区域隔离槽侧壁和半导体基底顶部的第一保护层，包括：形成覆盖半导体基底顶部和隔离槽侧壁的第一保护膜；形成填充底部区域隔离槽的牺牲层；对半导体基底顶部和顶部区域隔离槽侧壁的第一保护膜进行处理，形成第一保护层；去除牺牲层以及未进行处理的第一保护膜，其中，第一保护层的被刻蚀速率小于第一保护膜的被刻蚀速率。
另外，形成填充底部区域隔离槽的牺牲层，包括：形成填充隔离槽的牺牲膜，牺牲膜还覆盖半导体基底顶部表面；去除高于第一保护膜表面的牺牲膜；去除位于顶部区域隔离槽中的牺牲膜，形成牺牲层。
另外，处理包括离子注入，所注入的离子至少包括：磷、砷、硼、氟化 硼和碳中的其中一种。离子注入采用倾斜注入的方式进行注入，倾斜角度范围为15°～20°。
另外，第一保护膜包括单晶硅层、多晶硅层或者锗层；形成填充隔离槽的介电层之前，还包括：对第一保护层进行氧化处理，以将第一保护层转化为第一基底隔离层。
另外，氧化处理采用的工艺温度的范围为750℃～1000℃。氧化处理扩大隔离槽底部的特征尺寸时，采用氧化处理形成的第一基底隔离层和第二基底隔离层的致密性好，且缺陷较少，后续形成的隔离结构的隔离效果较好。
另外，形成第一保护层之前，还包括：在半导体基底顶部形成第二保护层；第一保护层覆盖第二保护层的顶部和侧壁。
另外，形成第一保护层之前，还包括：在隔离槽的侧壁形成阻挡层，阻挡层的材料与第一保护层的材料以及半导体基底的材料不同。形成阻挡层以防止隔离槽侧壁的半导体基底被氧化，还用于防止制程过程中，对隔离槽侧壁的半导体基底的刻蚀。
另外，形成的阻挡层的厚度范围为30埃～70埃。
在垂直于所述半导体基底表面的方向上，所述顶部区域隔离槽的厚度小于所述底部区域隔离槽的厚度，且所述顶部区域隔离槽的厚度大于所述底部区域隔离槽的厚度的二分之一。
本申请实施例还提供了一种半导体结构，包括：半导体基底，半导体基底上具有间隔分布的若干隔离槽；隔离槽包括顶部区域隔离槽和底部区域隔离槽，顶部区域隔离槽高于底部区域隔离槽；顶部隔离结构，用于填充顶部区域隔离槽，顶部隔离结构包括位于顶部区域隔离槽侧壁的第一基底隔离层以及填 充顶部区域隔离槽的介电层；底部隔离结构，用于填充底部区域隔离槽，底部隔离结构包括位于底部区域隔离槽侧壁的第二基底隔离层以及填充底部区域隔离槽的介电层；在平行于半导体基底表面的任意方向上，底部隔离结构的尺寸大于底部区域隔离槽的尺寸。
另外，在垂直于半导体基底表面的方向上，顶部隔离结构的高度小于底部隔离结构的高度，且顶部隔离结构的高度大于底部隔离结构的高度的二分之一。
另外，半导体结构还包括：阻挡层，阻挡层位于隔离槽侧壁；第一基底隔离层位于顶部区域隔离槽中的阻挡层的侧壁，部分第二基底隔离层位于半导体基底以及阻挡层之间，部分第二基底隔离层位于阻挡层与介电层之间。
另外，阻挡层的厚度为30埃～70埃。
相比于相关技术而言，通过第一保护层，防止在制程过程中隔离槽之间的半导体基底被氧化，从而防止隔离槽之间有源区的特征尺寸变小。同时第二基底隔离层部分占据原半导体基底的位置，部分占据隔离槽的位置，使得填充形成的隔离结构底部的特征尺寸大于形成的底部区域隔离槽的特征尺寸，从而提高形成的隔离结构的隔离效果。
附图说明
图1至图15为本申请一实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图。
具体实施方式
目前，由于多晶硅薄层补偿技术的引入，隔离槽在进行多晶硅沉积时易在高深宽比的区域底部产生较厚的硅衬垫，底部较厚的硅衬垫在后续氧化制程 中不能被氧化完全，从而使得形成的隔离结构的隔离效果减弱，导致半导体器件的电性异常。
为解决上述问题，本申请一实施例提供了一种半导体结构的形成方法，包括：提供半导体基底，半导体基底上具有间隔分布的若干隔离槽；隔离槽包括顶部区域隔离槽和底部区域隔离槽，其中，顶部区域隔离槽高于底部区域隔离槽；形成覆盖顶部区域隔离槽侧壁和半导体基底顶部的第一保护层；对底部区域隔离槽进行氧化处理，以将靠近底部区域隔离槽的部分半导体基底氧化形成第二基底隔离层；形成填充隔离槽的介电层，并刻蚀高于半导体基底顶部的第一保护层和介电层，以形成隔离结构。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图15为本申请实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
参考图1至图3，提供半导体基底101，半导体基底101上具有间隔分布的若干隔离槽105，隔离槽105之间的半导体基底101顶部具有第二保护层102，隔离槽105包括：顶部区域隔离槽115和底部区域隔离槽125；其中，顶部区域隔离槽115高于底部区域隔离槽125。
具体地，参考图1，半导体基底101，半导体基底101上依次形成有第二保护层102、掩膜层103和光刻胶层104。
在本实施例中，第二保护层102采用氮化硅材料，氮化硅材料作为绝缘材料且不易被氧化，既可以用于保护隔离槽105之间的半导体基底101，也可以防止后续制程中隔离槽105之间半导体基底101的顶部被氧化。在其他实施例中，第二保护层也可以采用氧化硅、氮氧化硅等绝缘材料。
需要说明的是，在本实施例中，半导体结构的形成方法中包括形成第二保护层的方案，第二保护层用于进一步防止半导体基底的顶部表面被氧化，且第一保护层覆盖区域包括第二保护层与半导体基底的接触面，用于防止半导体基底与第二保护层的接触面被氧化，从而产生的形貌缺陷。在其他实施例中，也可以不形成第二保护层。
参考图2，图形化光刻胶层104刻蚀所述掩膜层103、第二保护层102以及半导体基底101，形成间隔分布的若干隔离槽105，隔离槽105用于后续形成隔离结构。其中，隔离槽105之间的半导体基底101顶部的特征尺寸为CD1，底部区域隔离槽125在预设平面上的特征尺寸为CD2，刻蚀后的半导体基底101顶部具有掩膜层103、掩膜层103顶部具有图形化的光刻胶层104。
参考图3，依次去除光刻胶层104以及掩膜层103。
具体地，采用第一干法清洗工艺去除所述光刻胶层104，第一干法清洗工艺采用氨气、氮气和氢气的混合气体，混合气体与光刻胶层104反应生成第一固化物，然后通过高温蒸发的方式蒸发第一固化物，即完成光刻胶层104的去除。
需要说明的是，在本实施例中采用氨气、氮气和氢气的混合气体与光刻 胶层104反应生成第一固化物的过程中，由于混合气体中不含有氧气，且阻止了隔离槽105与空气相接触，在去除光刻胶层104的同时，防止隔离槽104侧壁的半导体基底101的自然氧化。在其他实施例中，也可以仅采用去除光刻胶层的混合气体进行上述第一干法清洗工艺。
在去除光刻胶层104之后，采用第一湿法清洗工艺去除掩膜层103，第一湿法清洗工艺采用49％HF以及1:1:60APM(H 2O 2:NH 4OH:H 2O＝1:1:60)的混合溶液，混合溶液与掩膜层103发生化学反应以去除掩膜层103。
需要说明的是，在本实施例中采用49％HF以及1:1:60APM的混合溶液与掩膜层103反应去除掩膜层103的过程中，由于混合液体中含有NH 4OH，会电离出OH-，由于OH-的负电荷排斥作用以及H 2O 2的氧化性，可以去除隔离槽105侧壁的颗粒物。在其他实施例中，也可以仅采用去除掩膜层的混合液体进行上述第一湿法清洗工艺。
本实施例还包括形成阻挡层的形成方法，参考图4，在隔离槽105的侧壁形成阻挡层106，阻挡层106的材料与后续形成的第一保护层的材料以及半导体基底101的材料不同。
由于阻挡层106是形成在隔离槽105中，为了保证隔离槽105后续形成的隔离结构的隔离效果，需采用绝缘性较好的材料作为阻挡层106的材料，即在本实施例中，阻挡层106采用氧化硅材料形成。具体地，本实施例中，阻挡层106的厚度范围为30埃～70埃，例如，35埃、40埃、45埃、50埃、55埃、60埃或65埃。
具体地，形成阻挡层106的方法包括为通过原子层淀积(ALD)、化学气相淀积(CVD)或外延生长的方式在隔离槽105的侧壁形成阻挡层106。采用 ALD、CVD或外延生长的方式能较快的生长阻挡层106，防止隔离槽105侧壁的半导体基底101的自然氧化。
需要说明的是，本实施例中阻挡层106的形成方法并不构成对本实施例的限定；在其他实施例中，也可以采用不形成阻挡层的方法执行本实施例半导体结构的形成方法。
参考图5～图11，形成覆盖顶部区域隔离槽115侧壁的第一保护层117。
具体地，参考图5，形成覆盖隔离槽105侧壁的第一保护膜107，第一保护膜107用于后续形成第一保护层117，以保护顶部区域隔离槽115的侧壁。
参考图6～图8，形成填充底部区域隔离槽125的牺牲层108。
具体地，参考图6，形成填充隔离槽105的牺牲膜118；进一步地，牺牲膜118覆盖所述半导体基底101上方的所述第一保护膜107。
参考图7，利用化学机械研磨法去除第一保护膜107顶部以上的牺牲膜118，使剩余的牺牲膜118的高度与所述第一保护膜107的高度平齐。
参考图8，沿隔离槽105向下刻蚀剩余的牺牲膜118形成填充底部区域隔离槽125的牺牲层108，刻蚀使得位于顶部区域隔离槽115侧壁的第一保护膜107得以显露。
在一个例子中，牺牲层108的材料与光刻胶层104的材料一致，后续可以采用第一干法清洗工艺去除牺牲层108；在另一个例子中，牺牲层108的材料可以采用含碳材料，后续可以采用灰化工艺进行清除。
在本实施例中，并不去除位于第二保护层102侧壁以及顶部表面的第一保护膜107，即后续形成第一保护层117还覆盖部分第二保护层102的侧壁和顶部表面。即第一保护层117覆盖区域包括第二保护层102与半导体基底101 的接触面，可以防止第二保护层102与半导体基底101的接触面被氧化而导致的“鸟嘴效应”(“鸟嘴效应”是由于半导体基底101被氧化，生成的氧化层会部分向内生长，部分向外生长，使得原本顶部表面平整的半导体基底101变得不平整，从而导致半导体基底101与第二保护层102的接触面翘起产生一个类似“鸟嘴”的角度)。在一个例子中，也可以去除位于第二保护层侧壁以及顶部的第一保护膜，此时形成的第一保护层仅位于顶部区域的侧壁。
需要说明的是，在本实施例中，形成的牺牲层108的高度与隔离槽105顶部的高度差，约占隔离槽105深度的1/3～1/2，即在垂直于半导体基底101的方向上，顶部区域隔离槽115的高度小于底部区域隔离槽125的高度，且顶部区域隔离槽115的高度大于底部区域隔离槽125的高度的二分之一。
参考图9，对显露出的第一保护膜107进行处理形成第一保护层117。
所述处理包括离子注入，使得第一保护层117的硬度大于第一保护膜107，使得在后续刻蚀时刻蚀速率较低(第一保护层117的被刻蚀速率小于第一保护膜107的被刻蚀速率)，第一保护层117与第一保护膜107具有较大的刻蚀选择比，从而使得第一保护层117更难刻蚀。
具体地，所注入的离子至少包括：磷、砷、硼、氟化硼和碳中的其中一种；离子注入采用倾斜注入的方式进行注入，倾斜角度范围为15°～20°，例如，16°、17°、18°或者19°。
参考图10以及图11，去除牺牲层108以及未进行离子注入的第一保护膜107，在顶部区域隔离槽115的侧壁形成第一保护层117。
具体地，参考图10，去除牺牲层108。
在一个例子中，采用第二干法清洗工艺去除牺牲层108。第二干法清洗 采用的混合气体中至少包括氧气，可以尽可能较快的去除牺牲层108，且本实施例中由于形成了阻挡层106，此时可以防止隔离槽105侧壁的半导体基底101被氧化。
参考图11，去除未进行离子注入的第一保护膜107，在顶部区域隔离槽115的侧壁形成第一保护层117。
第一保护层117用于防止隔离槽105之间的半导体基底101被氧化，从而防止CD1减小，保证有源区的面积不会减小。即后续形成的第一保护层117的主要目的在于防止顶部区域隔离槽115的侧壁被氧化。
在一个例子中，采用第二湿法清洗工艺去除未进行离子注入的第一保护膜107。第二湿法清洗工艺采用具有刻蚀选择比的材料进行刻蚀(未进行离子注入的第一保护膜107的被刻蚀速率大于第一保护层117的被刻蚀速率)；在一个例子中，采用NH 4OH或KOH溶液进行第二湿法清洗工艺，以去除未进行离子注入的第一保护膜107。
在一个例子中，第一保护膜107包括单晶硅层、多晶硅层或者锗层，即第一保护膜107的材料为单晶硅、多晶硅或锗。这样通过牺牲层108的覆盖，以及离子注入造成的刻蚀选择比差异，可以较为容易的刻蚀去除掉未进行离子注入的第一保护膜107。同时由于阻挡层106和第一保护膜107的材料差异形成刻蚀选择比，用于防止隔离槽105侧壁的半导体基底101被刻蚀。
参考图12，对底部区域隔离槽125进行氧化处理，以将靠近底部区域隔离槽125的半导体基底101转化为第二基底隔离层201。
在本实施例中，通过氧化处理形成的第二基底隔离层201部分生长在阻挡层106的表面，即部分第二基底隔离层201位于半导体基底101以及阻挡层 106之间，部分第二基底隔离层201位于阻挡层106远离半导体基底101的一侧。
其中，氧化处理采用的工艺温度的范围为750℃～1000℃。例如，可采用800℃、850℃、900℃或950℃。采用氧化处理形成的第一基底隔离层202和第二基底隔离层201的致密性好，且缺陷较少，后续形成的隔离结构的隔离效果好。
需要说明的是，在本实施例中，阻挡层106的材料与第二基底隔离层201的材料一致。且在本实施例中，参考图13，还需要对第一保护层117进行氧化处理，以将第一保护层117转化为第一基底隔离层202。需要说明的是，第一基底隔离层202和第二基底隔离层201通过一步氧化处理同时氧化形成；将第一保护层117转化为第一基底隔离层202，以保证隔离槽105中的阻挡层106、第一基底隔离层202、第二基底隔离层201以及后续形成的介电层都采用同一材料形成，保证隔离材料的均一性，隔离效果更好。且离子注入的基材为单晶硅、多晶硅或锗，较容易被氧化生成第一基底隔离层202。
参考图14，形成填充隔离槽105的介电层109。
参考图15，刻蚀高于所述半导体基底101顶部的介电层109、第一基底隔离层202和第二保护层102，以形成隔离结构。其中，隔离结构包括位于顶部区域隔离槽115中的顶部隔离结构135和位于底部区域隔离槽125中的底部隔离结构145。
具体地，采用ALD工艺或CVD工艺填充隔离槽105形成介电层109，ALD工艺或CVD工艺具有沉积速率慢，沉积形成的膜层致密性高和阶梯覆盖率好等特点，如此，能够使得介电层109能够在完全填充剩余的隔离槽105以 形成致密的绝缘结构，在本实施例中，介电层109的材料与第一基底隔离层202的材料一致，都为氧化硅，以保证隔离槽105中的隔离材料都是同一材料，具有连续性。
后续刻蚀掉高于半导体基底101表面的介电层109、第一基底隔离层202和第二保护层102，即形成了隔离结构，此时隔离结构之间的半导体基底101顶部的特征尺寸不变，即有源区特征尺寸CD1不变，保证后续做电容接触或位线接触时留有足够的面积，使得半导体器件的接触性能变好。形成的隔离结构的特征尺寸变大，即按照上述方式形成的隔离结构底部在预设平面上的特征尺寸大于底部区域隔离槽的特征尺寸(即CD3大于CD2)，从而提高了隔离结构的隔离效果。
相对于相关技术而言，通过在顶部区域隔离槽侧壁形成第一保护层，防止隔离槽在制程过程中，隔离槽之间的半导体基底被氧化，从而造成隔离槽之间有源区的特征尺寸变小；然后对底部区域隔离槽进行氧化处理，将靠近底部区域隔离槽的半导体基底转化为第二基底隔离层，半导体基底转化为第二基底隔离层的过程中，部分向内生长、部分向外生长，使得在平行于半导体基底顶部表面的方向上，后续填充形成的隔离结构底部的特征尺寸大于形成的底部区域隔离槽的特征尺寸，从而提高形成的隔离结构的隔离效果。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种半导体结构。
参考图12～图15，以下将结合附图对本实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
半导体结构，包括：半导体基底101，半导体基底101上具有间隔分布的若干隔离槽105；隔离槽105包括顶部区域隔离槽115和底部区域隔离槽125，其中，顶部区域隔离槽115高于底部区域隔离槽125；顶部隔离结构135，用于填充顶部区域隔离槽115，顶部隔离结构135包括位于顶部区域隔离槽115侧壁的第一基底隔离层202以及填充顶部区域隔离槽115的介电层109；底部隔离结构145，用于填充底部区域隔离槽125，底部隔离结构145包括位于底部区域隔离槽145侧壁的第二基底隔离层201以及填充底部区域隔离槽的介电层109；在平行于半导体基底101表面的任意方向上，底部隔离结构145的尺寸大于底部区域隔离槽115的尺寸。
需要说明的是，在本实施例中，在垂直于半导体基底101表面的方向上，底部隔离结构145的尺寸大于底部区域隔离槽125的尺寸。
隔离槽105用于后续形成隔离结构。其中，隔离槽105之间的半导体基底101顶部的特征尺寸为CD1，底部区域隔离槽125在预设平面上的特征尺寸为CD2。
在本实施例中，在垂直于半导体基底101的方向上，顶部区域隔离槽115的高度小于底部区域隔离槽125的高度，且顶部区域隔离槽115的高度大于底部区域隔离槽125的高度的二分之一。即顶部隔离结构135的高度小于底部隔离结构145的高度，且顶部隔离结构135的高度大于底部隔离结构145的高度的二分之一。
在本实施例中，半导体结构还包括：位于隔离槽105侧壁的阻挡层106， 此时，第一基底隔离层202位于顶部区域隔离槽115的阻挡层106的侧壁，阻挡层106位于半导体基底101以及第一基底隔离层202之间。阻挡层106的材料与半导体基底101的材料不同，其原因在于：形成阻挡层106，以防止隔离槽105侧壁的半导体基底101被氧化；由于材料差异形成刻蚀选择比，用于防止制程过程中，隔离槽105侧壁的半导体基底101被刻蚀。
在本实施例中，顶部隔离结构135，用于填充顶部区域隔离槽115，顶部隔离结构135包括位于顶部区域隔离槽115侧壁的第一基底隔离层202以及填充顶部区域隔离槽115的介电层109；底部隔离结构145，用于填充底部区域隔离槽125，底部隔离结构145包括位于底部区域隔离槽125侧壁的第二基底隔离层201以及填充底部区域隔离槽的介电层109。
具体地，阻挡层106采用氧化硅材料形成。具体地，本实施例中，阻挡层106的厚度范围为30埃～70埃，例如，35埃、40埃、45埃、50埃、55埃、60埃或65埃。
第二基底隔离层201即半导体基底101转化而成，部分占据原半导体基底101的位置，部分占据原隔离槽105的位置。由于第二基底隔离层201部分占据半导体基底101的位置，导致形成的隔离结构底部的特征尺寸大于隔离槽105底部的特征尺寸，即在平行于半导体基底101表面的任意方向上，底部隔离结构145的尺寸大于底部区域隔离槽的尺寸，且在垂直于半导体基底101表面的方向上，底部隔离结构145的尺寸大于底部区域隔离槽125的尺寸。
为了保证介电层109的材料与第二基底隔离层201的材料一致性，在本实施里中，介电层109的材料与第二基底隔离层201的材料都采用氧化硅，以保证隔离槽105中的隔离材料都是同一材料，具有连续性。
与相关技术相比，通过第一保护层，防止隔离槽在制程过程中，隔离槽之间的半导体基底被氧化，从而防止隔离槽之间有源区的特征尺寸变小。同时第二基底隔离层部分占据原半导体基底的位置，部分占据隔离槽的位置，使得填充形成的隔离结构底部的特征尺寸大于形成的底部区域隔离槽的特征尺寸增大，从而提高形成的隔离结构的隔离效果。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供半导体基底，所述半导体基底上具有间隔分布的若干隔离槽；
    所述隔离槽包括顶部区域隔离槽和底部区域隔离槽，其中，所述顶部区域隔离槽高于所述底部区域隔离槽；
    形成覆盖所述顶部区域隔离槽侧壁和所述半导体基底顶部的第一保护层；
    对所述底部区域隔离槽进行氧化处理，以将靠近所述底部区域隔离槽的部分所述半导体基底氧化形成第二基底隔离层；
    形成填充所述隔离槽的介电层，并刻蚀高于所述半导体基底顶部的所述第一保护层和所述介电层，以形成隔离结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述形成覆盖所述顶部区域隔离槽侧壁和所述半导体基底顶部的第一保护层，包括：
    形成覆盖所述半导体基底顶部和所述隔离槽侧壁的第一保护膜；
    形成填充所述底部区域隔离槽的牺牲层；
    对所述半导体基底顶部和所述顶部区域隔离槽侧壁的第一保护膜进行处理，形成所述第一保护层；
    去除所述牺牲层以及未进行所述处理的所述第一保护膜，其中，所述第一保护层的被刻蚀速率小于所述第一保护膜的被刻蚀速率。
  3. 根据权利要求2所述的半导体结构的形成方法，其特征在于，所述形成填充所述底部区域隔离槽的牺牲层，包括：
    形成填充所述隔离槽的牺牲膜，所述牺牲膜还覆盖所述半导体基底顶部表面；
    去除高于所述第一保护膜顶部表面的所述牺牲膜；
    去除位于所述顶部区域隔离槽中的所述牺牲膜，形成所述牺牲层。
  4. 根据权利要求2所述的半导体结构的形成方法，其特征在于，所述处理包括离子注入，所注入的离子至少包括：磷、砷、硼、氟化硼和碳中的其中一种。
  5. 根据权利要求4所述的半导体结构的形成方法，其特征在于，所述离子注入采用倾斜注入的方式进行注入，倾斜角度范围为15°～20°。
  6. 根据权利要求2所述的半导体结构的形成方法，其特征在于，所述第一保护膜包括单晶硅层、多晶硅层或者锗层；
    所述形成填充所述隔离槽的介电层之前，还包括：
    对所述第一保护层进行所述氧化处理，以将所述第一保护层转化为第一基底隔离层。
  7. 根据权利要求6所述的半导体结构的形成方法，其特征在于，所述氧化处理采用的工艺温度的范围为750℃～1000℃。
  8. 根据权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第一保护层之前，还包括：
    在所述半导体基底顶部形成第二保护层；
    所述第一保护层覆盖所述第二保护层的顶部和侧壁。
  9. 根据权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第一保护层之前，还包括：
    在所述隔离槽的侧壁形成阻挡层，所述阻挡层的材料与所述第一保护层的材料以及所述半导体基底的材料不同。
  10. 根据权利要求9所述的半导体结构的形成方法，其特征在于，形成的所述阻 挡层的厚度范围为30埃～70埃。
  11. 根据权利要求1所述的半导体结构的形成方法，其特征在于，在垂直于所述半导体基底表面的方向上，所述顶部区域隔离槽的厚度小于所述底部区域隔离槽的厚度，且所述顶部区域隔离槽的厚度大于所述底部区域隔离槽的厚度的二分之一。
  12. 一种半导体结构，其特征在于，包括：
    半导体基底，所述半导体基底上具有间隔分布的若干隔离槽；
    所述隔离槽包括顶部区域隔离槽和底部区域隔离槽，所述顶部区域隔离槽高于所述底部区域隔离槽；
    顶部隔离结构，用于填充所述顶部区域隔离槽，所述顶部隔离结构包括位于所述顶部区域隔离槽侧壁的第一基底隔离层以及填充所述顶部区域隔离槽的介电层；
    底部隔离结构，用于填充所述底部区域隔离槽，所述底部隔离结构包括位于所述底部区域隔离槽侧壁的第二基底隔离层以及填充所述底部区域隔离槽的介电层；
    在平行于所述半导体基底表面的任意方向上，所述底部隔离结构的尺寸大于所述底部区域隔离槽的尺寸。
  13. 根据权利要求12所述的半导体结构，其特征在于，在垂直于所述半导体基底表面的方向上，所述顶部隔离结构的高度小于所述底部隔离结构的高度，且所述顶部隔离结构的高度大于所述底部隔离结构的高度的二分之一。
  14. 根据权利要求12所述的半导体结构，其特征在于，还包括：
    阻挡层，所述阻挡层位于所述隔离槽侧壁；
    所述第一基底隔离层位于所述顶部区域隔离槽中的所述阻挡层的侧壁，
    部分所述第二基底隔离层位于所述半导体基底以及所述阻挡层之间，部分所述第二基底隔离层位于所述阻挡层与所述介电层之间。
  15. 根据权利要求14所述的半导体结构，其特征在于，所述阻挡层的厚度为30埃～70埃。
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