WO2022018561A1 - 撮像装置および電子機器 - Google Patents

撮像装置および電子機器 Download PDF

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Publication number
WO2022018561A1
WO2022018561A1 PCT/IB2021/056222 IB2021056222W WO2022018561A1 WO 2022018561 A1 WO2022018561 A1 WO 2022018561A1 IB 2021056222 W IB2021056222 W IB 2021056222W WO 2022018561 A1 WO2022018561 A1 WO 2022018561A1
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WO
WIPO (PCT)
Prior art keywords
layer
circuit
transistor
pixel
image pickup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2021/056222
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English (en)
French (fr)
Japanese (ja)
Inventor
佐藤駿介
米田誠一
根来雄介
廣瀬丈也
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2022538486A priority Critical patent/JP7686648B2/ja
Priority to DE112021003951.2T priority patent/DE112021003951T5/de
Priority to KR1020227045104A priority patent/KR20230047331A/ko
Priority to US18/008,302 priority patent/US12120446B2/en
Priority to CN202180043372.0A priority patent/CN116018818A/zh
Publication of WO2022018561A1 publication Critical patent/WO2022018561A1/ja
Anticipated expiration legal-status Critical
Priority to US18/910,318 priority patent/US20250088769A1/en
Priority to JP2025084797A priority patent/JP2025113384A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/191—Photoconductor image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors

Definitions

  • One aspect of the present invention relates to an image pickup apparatus.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, image pickup devices, and the like.
  • the operation method or the manufacturing method thereof can be given as an example.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • Transistors and semiconductor circuits are one aspect of semiconductor devices.
  • the storage device, the display device, the image pickup device, and the electronic device may have a semiconductor device.
  • Patent Document 1 discloses an image pickup apparatus having an oxide semiconductor and using a transistor having an extremely low off-current in a pixel circuit.
  • Patent Document 2 discloses a technique for adding a calculation function to an image pickup apparatus.
  • Imaging devices installed in mobile devices and the like have a general function of acquiring high-resolution images. In the next generation, it is required that the image pickup device be equipped with more intelligent functions.
  • the image data (analog data) acquired by the image pickup apparatus is converted into digital data, and after being taken out to the outside, image processing is performed as necessary. If the processing can be performed in the image pickup apparatus, the cooperation with an external device becomes faster and the convenience of the user is improved. In addition, the load and power consumption of peripheral devices can be reduced.
  • the image pickup device in order to give the image pickup device a function, it is preferable to stack elements such as an increasing number of circuits. For example, by providing a plurality of circuits so as to overlap with the pixel circuit, it is possible to suppress an increase in the area, and it is possible to form a high-performance and small-sized image pickup device. Further, the wiring length can be shortened between the stacked circuits, and high-speed and low power consumption operation can be realized.
  • one of the objects of the present invention is to provide an image pickup apparatus capable of performing image processing.
  • one of the purposes is to provide a high-performance and small-sized image pickup device.
  • one of the purposes is to provide an image pickup apparatus capable of high-speed operation.
  • one of the purposes is to provide an image pickup device with low power consumption.
  • one of the purposes is to provide a highly reliable image pickup apparatus.
  • one of the purposes is to provide a new image pickup device or the like.
  • one of the purposes is to provide a driving method for the image pickup apparatus.
  • one of the purposes is to provide a new semiconductor device or the like.
  • One aspect of the present invention relates to an image pickup apparatus having an image processing function and capable of high-speed operation.
  • One aspect of the present invention is an image pickup apparatus having a plurality of pixel blocks, wherein the pixel block has a first layer and a second layer, and the first layer is a second layer.
  • the pixel block has an overlapping region, and the pixel block has a plurality of pixel circuits and a plurality of first storage circuits in the first layer, and a plurality of product-sum calculation circuits and a plurality of layers in the second layer.
  • a first binarization circuit, a plurality of second binarization circuits, and a pixel circuit and a first storage circuit are image pickup devices having a transistor having a metal oxide in a channel forming region. be.
  • Another aspect of the present invention is an image pickup apparatus having a plurality of pixel blocks, wherein the pixel block has a first layer, a second layer, and a third layer, and the first layer.
  • the layers are located between the second layer and the third layer, or the third layer is between the first layer and the second layer, and the first to third layers are located on each other.
  • the pixel block has a plurality of overlapping regions, and the pixel block has a plurality of pixel circuits in the first layer, and a plurality of product-sum calculation circuits, a plurality of first binarization circuits, and a plurality of pixels in the second layer.
  • the second binarization circuit of the above, the third layer has a plurality of first storage circuits, and the pixel circuit and the first storage circuit have a metal oxide in the channel forming region. It is an image pickup device having a transistor.
  • the product-sum calculation circuit, the first binarization circuit and the second binarization circuit preferably have a transistor having silicon in the channel formation region.
  • the pixel circuit and the first binarization circuit have the same number, and the pixel circuit can be electrically connected to one first binarization circuit.
  • One first binarization circuit can be electrically connected to a plurality of product-sum operation circuits.
  • One first storage circuit can be electrically connected to a plurality of product-sum operation circuits.
  • the product-sum calculation circuit and the second binarization circuit have the same number, and one product-sum calculation circuit can be electrically connected to one second binarization circuit.
  • the drive circuit of the pixel circuit and the drive circuit of the first storage circuit can be provided in the second layer.
  • the input terminal of the second storage circuit is electrically connected to a plurality of second binarization circuits, and the output terminal of the second storage circuit is a plurality of products. It may be electrically connected to the sum calculation circuit.
  • the third storage circuit has a third storage circuit and a third binarization circuit, and the third storage circuit is electrically connected to a plurality of product-sum operation circuits via the third binarization circuit. It may have been done.
  • the second storage circuit, the third storage circuit, and the third binarization circuit can be provided in the second layer.
  • the metal oxide preferably contains In, Zn, and M (where M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).
  • an image pickup apparatus capable of performing image processing.
  • a low power consumption imaging device can be provided.
  • a highly reliable image pickup device can be provided.
  • a new image pickup device or the like can be provided.
  • a new semiconductor device or the like can be provided.
  • FIG. 1 is a diagram illustrating an image pickup apparatus.
  • 2A to 2C are diagrams for explaining the pixel portion.
  • FIG. 3 is a diagram illustrating a pixel block.
  • FIG. 4 is a diagram illustrating a pixel block.
  • FIG. 5 is a diagram illustrating a pixel block.
  • FIG. 6A is a diagram illustrating a product-sum calculation circuit.
  • FIG. 6B is a diagram illustrating a binarization circuit.
  • FIG. 7 is a diagram illustrating a pixel block.
  • FIG. 8 is a diagram illustrating a pixel block and a readout circuit.
  • FIG. 9 is a timing chart illustrating the operation of the read circuit.
  • 10A to 10C are diagrams illustrating a pixel circuit.
  • FIG. 1 is a diagram illustrating an image pickup apparatus.
  • FIG. 3 is a diagram illustrating a pixel block.
  • FIG. 4 is a diagram illustrating a pixel block.
  • FIG. 5 is
  • 11A is a diagram illustrating a storage circuit.
  • 11B and 11C are diagrams illustrating memory cells.
  • 12A and 12B are diagrams illustrating the layout of the pixel circuit.
  • FIG. 13 is a diagram illustrating an operation of reading data from a pixel block.
  • FIG. 14 is a diagram illustrating a data distribution operation to pixel blocks.
  • FIG. 15A is a diagram illustrating an operation of reading data from a pixel block.
  • FIG. 15B is a diagram illustrating the circuit 25.
  • FIG. 16A is a diagram illustrating a readout circuit.
  • FIG. 16B is a timing chart illustrating the operation of the readout circuit.
  • 17A to 17D are diagrams illustrating the configuration of pixels of the image pickup apparatus.
  • FIG. 18A to 18C are diagrams illustrating the configuration of the photoelectric conversion device.
  • FIG. 19 is a cross-sectional view illustrating the pixels.
  • 20A to 20C are diagrams illustrating Si transistors.
  • FIG. 21 is a cross-sectional view illustrating the pixels.
  • FIG. 22 is a cross-sectional view illustrating the pixels.
  • FIG. 23 is a cross-sectional view illustrating the pixels.
  • 24A to 24D are diagrams illustrating an OS transistor.
  • FIG. 25 is a cross-sectional view illustrating the pixels.
  • FIG. 26 is a cross-sectional view illustrating the pixels.
  • FIG. 27 is a cross-sectional view illustrating the pixels.
  • 28A to 28C are perspective views (cross-sectional views) illustrating the pixels.
  • FIG. 19 is a cross-sectional view illustrating the pixels.
  • 20A to 20C are diagrams illustrating Si transistors.
  • FIG. 21 is a cross-sectional view illustrating the pixels.
  • 29A is a diagram illustrating a package containing an imaging device.
  • FIG. 29B is a diagram illustrating a module containing an image pickup device.
  • 30A to 30F are diagrams illustrating an electronic device.
  • 31A and 31B are diagrams illustrating a moving body.
  • the element may be composed of a plurality of elements if there is no functional inconvenience.
  • a plurality of transistors operating as switches may be connected in series or in parallel.
  • the capacitor may be divided and arranged at a plurality of positions.
  • one conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in the present specification, a plurality of names may be used for the same element. Further, even if the elements are shown to be directly connected on the circuit diagram, the elements may actually be connected via one or a plurality of conductors. , In the present specification, such a configuration is also included in the category of direct connection.
  • One aspect of the present invention is an image pickup apparatus having additional functions such as image processing.
  • the imaging device binarizes the analog data (image data) acquired in the imaging operation at the pixel unit, and performs a product-sum calculation using the binarized data.
  • a storage circuit is provided in the pixel unit to hold a weighting coefficient (also called weight data or filter) used in the product-sum operation. Therefore, the calculation can be performed without reading the weighting coefficient from the outside each time, and the power consumption can be reduced.
  • the wiring length between the circuits can be shortened by forming the pixel circuit, the storage circuit, and the like by stacking the product-sum calculation circuit and the like, and the power consumption is low. Can perform operation and high-speed operation. Further, it is possible to provide a high-performance and small-sized image pickup device.
  • FIG. 1 is a perspective view illustrating an image pickup apparatus according to an aspect of the present invention.
  • the image pickup apparatus has a layer 10 and a layer 20.
  • the layer 10 can be provided on the layer 20.
  • the image pickup apparatus has a pixel unit 11 provided with a pixel circuit, a storage circuit, and the like.
  • the pixel unit 11 has an element provided in the layer 10 and an element provided in the layer 20.
  • a pixel circuit and a storage circuit can be provided on the layer 10.
  • the layer 20 may be provided with a drive circuit for the circuit included in the layer 10, an arithmetic circuit for data acquired by the circuit included in the layer 10, a data conversion circuit, a storage circuit, and the like.
  • the layer 20 may be provided with a calculation unit 21, a low driver 31 and a column driver 32 for driving a pixel circuit, a low driver 33 and a column driver 34 for driving a storage circuit, and the like.
  • the layer 20 may be provided with a circuit 35, a circuit 36, or the like having a data selection function, a holding function, a conversion function, a reading function, and the like, if necessary.
  • the circuit included in the layer 10 and the circuit included in the layer 20 can be electrically connected by electrodes or wirings penetrating the layer 10. It should be noted that some of the above-mentioned circuits may be provided in a layer opposite to that described above or outside the image pickup apparatus.
  • FIG. 2A is a diagram illustrating details of the pixel unit 11.
  • the pixel unit 11 has a plurality of pixel blocks 12 arranged in a matrix. Further, the pixel block 12 has pixel blocks 13 arranged in 3 ⁇ 3. Further, the pixel block 13 has 3 ⁇ 3 pixels 14. That is, the pixel block 12 has 9 ⁇ 9 pixels 14.
  • the pixel 14 has a pixel circuit 15 and a storage circuit 16.
  • the pixel block 13 has 3 ⁇ 3 pixels 14, but the number of pixels is not limited to the above-mentioned number of pixels, for example, 2 ⁇ 2, 4 ⁇ 4. It can be 5 ⁇ 5, 25 ⁇ 25, or the like.
  • the number of pixels 14 in the horizontal direction and the number of pixels 14 in the vertical direction may be different.
  • a part of the pixel blocks 13 can be shared by the adjacent pixel blocks 12.
  • a part of the pixels 14 can be shared by the adjacent pixel blocks 13.
  • the number of pixel blocks 13 included in the pixel block 12 can also be changed as appropriate.
  • the pixel 14 shown in FIG. 2A is an example in which the pixel circuit 15 and the storage circuit 16 are provided side by side in the layer 10, but as shown in FIG. 2B, the pixel circuit 15 may be provided on the storage circuit 16 in an overlapping manner. .. Alternatively, as shown in FIG. 2C, the storage circuit 16 may be provided on the pixel circuit 15 in an overlapping manner.
  • FIG. 3 is a diagram illustrating components of the pixel block 13.
  • the pixel block 13 has 3 ⁇ 3 pixels 14. Therefore, the pixel block 13 has nine pixel circuits 15 and nine storage circuits 16 on the layer 10. Further, in the region (layer 20) overlapping with the pixel circuit 15 or the storage circuit 16, a plurality of binarization circuits 22, a plurality of product-sum calculation circuits 23, and a plurality of binarization circuits 24 are provided as the calculation unit 21. ..
  • the binarization circuit 22 is provided in the same number as the pixel circuit 15, that is, nine.
  • the binarization circuit 22 is provided at a position having a region overlapping with the pixel circuit 15.
  • FIG. 4 is a diagram showing the connection relationship between the pixel circuit 15 and the binarization circuit 22, and one pixel circuit 15 is electrically connected to one binarization circuit 22 having an overlapping region.
  • the binarization circuit 22 is a circuit that determines the image data (analog data) acquired by the pixel circuit 15 with a preset threshold value and binarizes the image data, and for example, a comparator can be used.
  • a plurality of product-sum calculation circuits 23 are provided in one pixel block 13, and in the present embodiment, an example in which six product-sum calculation circuits 23 are provided is shown. The number of the product-sum calculation circuit 23 can be appropriately increased or decreased depending on the purpose.
  • the input terminal of the product-sum calculation circuit 23 is electrically connected to the storage circuit 16 and the binarization circuit 22.
  • FIG. 5 is a diagram showing a connection relationship between the product-sum calculation circuit 23, the storage circuit 16, and the binarization circuit 22. In order to clearly show the connection relationship, nine binarization circuits 22 are extracted and shown.
  • the pixel block 13 has nine storage circuits 16, each of which has a plurality of memory cells. A 1-bit weighting coefficient can be written in advance in each of the plurality of memory cells. Each of the nine storage circuits 16 is electrically connected to each of the six multiply-accumulate circuits 23. Therefore, a weighting coefficient for 9 bits can be supplied to each of the product-sum calculation circuits 23. Since the weighting coefficient can be supplied from one storage circuit 16 to the six product-sum calculation circuits 23, here, if the weighting coefficient for at least 1 bit is written in one storage circuit 16, the operation is performed. be able to.
  • Each of the binarization circuits 22 can output image data converted into 1 bit.
  • Each of the nine binarization circuits 22 is electrically connected to each of the six multiply-accumulate circuits 23. Since the image data can be supplied from one binarization circuit 22 to the six product-sum calculation circuits 23, 9 bits of image data are supplied to each of the product-sum calculation circuits 23.
  • FIG. 6A is a diagram for briefly explaining the configuration and operation of the product-sum calculation circuit 23.
  • the product-sum calculation circuit 23 can be configured to have, for example, nine multipliers 23a and one adder 23b.
  • Image data (X1 to X9) converted into 1 bit by the binarization circuit 22 and 1 bit weight coefficient (W1 to W9) read from the storage circuit 16 are input to each multiplier 23a, and a multiplication operation is performed. And outputs 1 bit of data to the adder 23b.
  • the adder 23b the data input from each multiplier 23a is added and output to the binarization circuit 24.
  • the data output from the adder 23b (multiply-accumulate calculation circuit 23) takes a value of 0 to 9, so that it is 4-bit data.
  • the number of binarization circuits 24 is the same as that of the product-sum calculation circuit 23, that is, six. As shown in FIGS. 6A, 6B and 7, one binarization circuit 24 is electrically connected to one product-sum calculation circuit 23. As shown in FIGS. 6A and 6B, the data input to the binarization circuit 24 is 4-bit digital data corresponding to 0 to 9. The binarization circuit 24 outputs 1 when it is determined that the input data is 5 or more, and outputs 0 when it is determined that the input data is 4 or less. That is, the binarization circuit 24 is a circuit having a function of converting 4-bit data into 1-bit data.
  • FIG. 8 is a diagram illustrating reading of arithmetic data from the pixel block 12 (pixel block 13 [1,1] to pixel block 13 [3,3]).
  • the six binarization circuits 24 included in the pixel block 13 each have a selection transistor 24S that controls the output.
  • the gates of the six selection transistors 24S are electrically connected to the wiring RSEL (wiring RSEL [0], wiring RSEL [1], wiring RSEL [2]).
  • the wiring RSEL is shared by the pixel blocks 13 provided in the row direction.
  • the six output lines OUT (OUT [0] to OUT [5]) to which the six binarization circuits 24 are electrically connected are shared by the pixel block 13 provided in the column direction.
  • a readout circuit 40 is electrically connected to the six output lines OUT.
  • the readout circuit 40 has a switch 40S, a switch 41S, and a switch 42S that are electrically connected to the six output lines OUT of each row, respectively.
  • the switch 40S to the switch 42S have a plurality of transistors.
  • the gate of the transistor included in the switch 40S is electrically connected to the wiring CSEL [0].
  • the gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL [1].
  • the gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL [2].
  • the wiring on the output side of the switch 40S to the switch 42S is electrically connected to one output line OUT for every three wires. With this configuration, data for each pixel block 13 can be output.
  • the readout circuit 40 can be provided on the layer 20 as an element of the circuit 35 or the circuit 36 shown in FIG.
  • FIG. 9 is a timing chart illustrating reading of arithmetic data from the pixel block 12 (pixel block 13 [1,1] to pixel block 13 [3,3]). Before the time T1, all the operations are completed in each pixel block 13, and the operation data is held in the binarization circuit 24. Further, in the following description, the potential (high potential) that makes the transistor in the conductive state is expressed as “H”, and the potential that makes the transistor in the non-conducting state (low potential) is expressed as “L”.
  • the switch 40S in which the gate is electrically connected to the wiring CSEL [0] is electrically connected, and the output line OUT [0] to the output line OUT [0] is conducted.
  • the calculation data of the pixel block 13 [1,1] is output to 5].
  • the switch 40S When the potential of the wiring CSEL [0] is set to “L” and the potential of the wiring CSEL [1] is set to "H” at time T2, the switch 40S becomes non-conducting and the gate is electrically connected to the wiring CSEL [1]. The switch 41S conducts, and the arithmetic data of the pixel blocks 13 [1, 2] is output to the output line OUT [0] to the output line OUT [5].
  • the switch 41S becomes non-conducting and the gate is electrically connected to the wiring CSEL [2].
  • the switch 42S conducts, and the arithmetic data of the pixel block 13 [1,3] is output to the output line OUT [0] to the output line OUT [5].
  • the potential of the wiring RSEL [0] is set to "L”
  • the potential of the wiring CSEL [2] is set to "L”
  • the pixel block 13 (pixel block 13 [1,1] to the pixel block 13 [1] on the 0th line is set.
  • 3] ends the output of the calculation data.
  • the potential of the wiring RSEL [1] is set to “H”, and the same operation as described above is performed to perform the pixel block 13 (pixel block 13 [2, 1] to pixel block 13) on the first row. [2,3]) Outputs the operation data.
  • the potential of the wiring RSEL [2] is set to “H”, and the same operation as described above is performed to perform the pixel block 13 (pixel block 13 [3, 1] to pixels) in the second row.
  • the operation data of the block 13 [3,3]) is output.
  • one pixel block 12 can be read in a total of 10 clocks.
  • the pixel blocks 12 for one row can be read in parallel.
  • the pixel circuit 15 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 106.
  • One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102.
  • the other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104.
  • One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105.
  • the other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 111.
  • the gate of the transistor 102 is electrically connected to the wiring 114.
  • the other of the source or drain of the transistor 103 is electrically connected to the wiring 112.
  • the gate of the transistor 103 is electrically connected to the wiring 115.
  • the other of the source or drain of the transistor 104 is electrically connected to the wiring 113.
  • the other of the source or drain of the transistor 105 is electrically connected to the wiring 117.
  • the gate of the transistor 105 is electrically connected to the wiring 116.
  • a node N is an electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104. ..
  • Wiring 111, 112, 113 can have a function as a power line.
  • the wiring 111 can function as a low-potential power line
  • the wiring 112 and 113 can function as a high-potential power line.
  • the wiring 112 and the wiring 113 may be electrically connected.
  • the wirings 114, 115, and 116 can function as signal lines for controlling the continuity of each transistor.
  • the wiring 117 can function as wiring that electrically connects the pixel circuit 15 and the binarization circuit 22.
  • a photodiode can be used as the photoelectric conversion device 101.
  • the transistor 102 can have a function of controlling the potential of the node N.
  • the transistor 103 can have a function of initializing the potential of the node N.
  • the transistor 104 can have a function of passing a current according to the potential of the node N.
  • the transistor 105 can have a function of selecting pixels.
  • the direction of connection of the pair of electrodes of the photoelectric conversion device 101 may be reversed.
  • the wiring 111 may function as a high-potential power supply line
  • the wiring 112 and 113 may function as a low-potential power supply line.
  • the transistors 102 and 103 it is preferable to use a transistor (OS transistor) in which a metal oxide is used in the channel forming region.
  • the OS transistor has a characteristic that the off current is extremely low.
  • the period during which the electric charge can be held at the node N can be made extremely long. Further, it is possible to apply a global shutter method in which charge storage operation is simultaneously performed on all pixels without complicating the circuit configuration and operation method.
  • the transistor 104 has excellent amplification characteristics.
  • the transistor 105 it may be preferable to use a transistor having high mobility capable of high-speed operation. Therefore, a transistor (Si transistor) using silicon in the channel forming region may be applied to the transistors 104 and 105.
  • an OS transistor and a Si transistor may be arbitrarily combined and applied. Further, all the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (microcrystalline silicon, low temperature polysilicon, single crystal silicon), and the like.
  • the transistor may be provided with a back gate (second gate). By electrically connecting the back gate to the front gate, the on-current of the transistor can be increased. Further, the threshold voltage of the transistor can be controlled by supplying an appropriate constant potential to the back gate.
  • the configuration in which the back gate is provided in the transistor can also be applied to other circuits of the present specification. Further, the circuit may be configured by mixing the transistors with and without the back gate.
  • a transistor 107 and a transistor 108 may be added to the configuration of FIG. 10A.
  • the gate of the transistor 107 is electrically connected to the gate of the transistor 104.
  • One of the source or drain of the transistor 107 is electrically connected to one of the source or drain of the transistor 108.
  • the other of the source or drain of the transistor 107 is electrically connected to the wiring 113.
  • the gate of the transistor 108 is electrically connected to the wiring 118.
  • the other of the source or drain of the transistor 108 is electrically connected to wiring 119.
  • the wiring 118 can function as a signal line for controlling the continuity of the transistor 108.
  • the wiring 119 can be electrically connected to the circuit 60.
  • the circuit 60 is an image readout circuit, and for example, a CDS circuit (correlated double sampling circuit) or the like can be used.
  • image data can be output to the wiring 117 and the wiring 119.
  • the image data output to the wiring 117 is input to the binarization circuit 22, and then the product-sum operation is performed.
  • the image data output to the wiring 119 is read out to the outside via the circuit 60. These operations can be performed in parallel. Further, only calculation (image processing) or only reading of image data can be performed.
  • the circuit 60 can be provided on the layer 20 as an element of the circuit 35 or the circuit 36 shown in FIG.
  • the storage circuit 16 is provided in the pixel 14. Further, the storage circuit 16 has a plurality of memory cells, and 1 bit of data corresponding to a weighting coefficient is stored in the memory cells.
  • FIG. 11A is a diagram showing the connection relationship between the memory cell 150, the low driver 33, and the column driver 34. It is preferable to use an OS transistor as the transistor constituting the memory cell 150.
  • the plurality of memory cells 150 are provided on the layer 10 as storage circuits 16.
  • the low driver 33 and the column driver 34 are drive circuits of the memory cell 150 and can be provided on the layer 20.
  • the storage circuit 16 has m (m is an integer of 1 or more) in one column, n (n is an integer of 1 or more) in one row, and a total of m ⁇ n memory cells 150, and the memory cells 150 have a matrix shape. Is located in.
  • 11B and 11C are diagrams illustrating memory cells 150a and memory cells 150b that can be applied to memory cells 150.
  • the bit wires can be connected to the column driver 34. Further, the word line can be connected to the low driver 33. The bit wires are also electrically connected to the product-sum calculation circuit 23, but are not shown here.
  • low driver 33 and the column driver 34 for example, a decoder or a shift register can be used.
  • a plurality of low drivers 33 and column drivers 34 may be provided.
  • FIG. 11B shows a circuit configuration example of a gain cell type (also referred to as “2Tr1C type”) memory cell 150a having two transistors and one capacitor.
  • the memory cell 150a has a transistor 273, a transistor 272, and a capacitor 274.
  • One of the source or drain of the transistor 273 is connected to one electrode of the capacitor 274, the other of the source or drain of the transistor 273 is connected to the wiring WBL, the gate of the transistor 273 is connected to the wiring WL, and the transistor 273.
  • the back gate of is connected to the wiring BGL.
  • the other electrode of the capacitor 274 is connected to the wiring RL.
  • One of the source or drain of the transistor 272 is connected to the wiring RBL, the other of the source or drain of the transistor 272 is connected to the wiring SL, and the gate of the transistor 272 is connected to one electrode of the capacitor 274.
  • the wiring WBL functions as a write bit line.
  • the wiring RBL functions as a read bit line.
  • the wiring WL functions as a word line.
  • the wiring RL functions as wiring for applying a predetermined potential to the other electrode of the capacitor 274. It is preferable to apply a reference potential to the wiring RL during data writing and data retention.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor 273.
  • the threshold voltage of the transistor 273 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • Data writing is performed by applying a high level potential to the wiring WL, making the transistor 273 conductive, and electrically connecting one electrode of the wiring WBL and the capacitor 274. Specifically, when the transistor 273 is in a conductive state, a potential corresponding to the information recorded in the wiring WBL is applied, and the potential is written to one electrode of the capacitor 274 and the gate of the transistor 272. After that, a low level potential is applied to the wiring WL to make the transistor 273 non-conducting, thereby holding the potential of one electrode of the capacitor 274 and the potential of the gate of the transistor 272.
  • Data is read out by applying a predetermined potential to the wiring RL and the wiring SL.
  • the source of transistor 272 and the potential of one of the source or drain of transistor 273 are determined by the potential of the gate of transistor 272 and the potential of the other of source or drain of transistor 273, so that the current flowing between the source and drain of transistor 272 and the potential of one of the source or drain of transistor 273 are the source of transistor 272.
  • the potential held by one electrode of the capacitor 274 (or the gate of the transistor 272) can be read out. That is, the information written in this memory cell can be read out from the potential held in one electrode of the capacitor 274 (or the gate of the transistor 272).
  • the wiring WBL and the wiring RBL may be combined into one wiring BIL.
  • the wiring WBL and the wiring RBL of the memory cell 150a are used as one wiring BIL, and the source or drain of the transistor 273 and one of the source or drain of the transistor 272 are connected to the wiring BIL. It has become a configuration. That is, the memory cell 150b has a configuration in which the write bit line and the read bit line operate as one wiring BIL.
  • an OS transistor for the transistor 273 A storage device using an OS transistor for the transistor 273 and using a 2Tr1C type memory cell such as a memory cell 150a and a memory cell 150b is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).
  • NOSRAM Non-volatile Oxide Semiconductor Random Access Memory
  • FIG. 12A shows the back gate wiring 170, the metal oxide layer 175, and the source-drain wiring 180.
  • the metal oxide layer 175 is a layer provided with a channel forming region of the OS transistor.
  • FIG. 12B shows a configuration in which a gate wiring 185 and a wiring 190 electrically connected to the gate wiring 185 are added to FIG. 12A.
  • the transistor 102, the transistor 103, the transistor 104, and the transistor 105 shown in FIG. 10B are formed.
  • a plurality of transistors 109 are formed.
  • the transistor 109 is a dummy transistor that is not involved in the circuit operation, but with such a configuration, the uniformity of the wiring width and the like can be improved, and variations in the transistor characteristics can be suppressed.
  • an image pickup apparatus having an image processing function and capable of high-speed operation.
  • the image pickup device described in the first embodiment has a configuration in which a product-sum operation is performed once on the image data and the calculation data is taken out, but the image pickup device described in the present embodiment has a configuration on the image data. It has a configuration in which the product-sum operation is performed a plurality of times and the operation data is taken out.
  • FIG. 13 is a diagram illustrating a connection relationship between the pixel block 12 and the register 51, which is one of two registers (register 51, register 52).
  • a selection circuit may be provided between the pixel block 13 and the register 51 to reduce the number of wires.
  • the pixel block 12 shown in FIG. 13 is a simplified diagram of the pixel block 12 shown in FIG. 8, and the calculation data output from each pixel block 13 after the first product-sum calculation is 6 bits (1 bit ⁇ 6). It shows that there is.
  • the 6-bit operation data output from each pixel block 13 is input to and stored in the register 51.
  • the arithmetic data for 6 bits output from the nine pixel blocks 13 is input to the register 51, the arithmetic data for a total of 54 bits (6 bits ⁇ 9) is stored.
  • each pixel block 13 is provided with six product-sum calculation circuits 23 capable of processing 9-bit data shown in FIG. 6A, and 9-bit calculation data is distributed to each product-sum calculation circuit 23. Further, a weighting coefficient for 9 bits is supplied to each product-sum calculation circuit 23 from the nine storage circuits 16 of the pixel block 13. Therefore, each product-sum calculation circuit 23 can perform a second product-sum calculation.
  • the 4-bit calculation data output by each product-sum calculation circuit 23 is input to the same number of circuits 25 as the pixel block 13.
  • the calculation data input to the circuit 25 is for 24 bits (4 bits ⁇ 6).
  • FIG. 15B is a diagram illustrating the circuit 25.
  • the circuit 25 has an adder circuit 26a and a binarization circuit 26b. Since 4 bits (corresponding to 0 to 9) of arithmetic data are input from the 6 product-sum calculation circuits 23 to the addition circuit 26a, the output of the addition circuit 26a is 6 bits (equivalent to 0 to 54). The 6-bit data is input to the binarization circuit 26b. The binarization circuit 26b can convert the input data into 1 bit, and outputs 1 when the data is 28 or more and 0 when the data is 27 or less.
  • the circuit 25 is shown inside the pixel block 12 in FIG. 15, it may be provided outside the pixel block 12.
  • the 1-bit arithmetic data (data for a total of 9 bits) output by each circuit 25 is input to and stored in the register 52.
  • 9 bits of arithmetic data can be read out as needed.
  • a selection circuit may be provided between the circuit 25 and the register 52 to reduce the number of wires.
  • the product-sum calculation circuit 23 of the pixel block 13 holds the calculation data for 54 bits redistributed from the register 51, and the product is re-stacked by changing the weighting coefficient supplied from the storage circuit 16. It is possible to perform a sum operation and obtain different operation data. Then, the calculated data is stored in the register 52 in the same manner as the calculated data obtained in the previous product-sum operation. Therefore, a total of 18 bits of arithmetic data is stored in the register 52.
  • FIG. 16A is a diagram illustrating a read circuit 41 connected to the output side of the register 52.
  • a plurality of six output lines are provided on the output side of the register 52 so that arithmetic data can be read out every 6 bits.
  • a readout circuit 41 is electrically connected to the six output lines.
  • the readout circuit 41 has a switch 43S, a switch 44S, and a switch 45S that are electrically connected to the six output lines, respectively.
  • the switch 43S to the switch 45S have a plurality of transistors.
  • the gate of the transistor included in the switch 43S is electrically connected to the wiring CSEL [0].
  • the gate of the transistor included in the switch 44S is electrically connected to the wiring CSEL [1].
  • the gate of the transistor included in the switch 45S is electrically connected to the wiring CSEL [2].
  • the wiring on the output side of the switches 43S to 45S is electrically connected to one output line OUT (OUT [0] to OUT [5]) for every three wires. With this configuration, it is possible to output arithmetic data every 6 bits.
  • the register 51, the register 52, and the read circuit 41 can be provided on the layer 20 as elements of the circuit 35 or the circuit 36 shown in FIG.
  • FIG. 16B is a timing chart illustrating reading of arithmetic data stored in the register 52. It is assumed that all the arithmetic data (18 bits) are held in the register 52 before the time T1. Further, in the following description, the potential (high potential) that makes the transistor in the conductive state is expressed as “H”, and the potential that makes the transistor in the non-conducting state (low potential) is expressed as “L”.
  • the switch 43S When the potential of the wiring CSEL [0] is set to “L” and the potential of the wiring CSEL [1] is set to "H” at time T2, the switch 43S becomes non-conducting and the gate is electrically connected to the wiring CSEL [1]. The switch 44S conducts, and the second 6-bit operation data different from the first data is output to the output line OUT [0] to the output line OUT [5].
  • the process of storing the operation data for 54 bits in the register 51 is performed in the first clock, the operation data for the first 9 bits is stored in the register 52 in the second clock, and the operation data is stored in the register 52 for the second time. It is assumed that the process of storing the operation data for 9 bits is performed in the third clock. Then, the first 6-bit operation data is read from the register 52 in the 4th clock, the second 6-bit operation data is read in the 5th clock, and the third 6-bit operation data is read. If it is performed at the 6th clock, all operations can be completed at the 6th clock.
  • the operations of the 1st to 3rd clocks and the operations of the 4th to 6th clocks can be operated in parallel, and the time T1 to the time T2 period of the timing chart shown in FIG. 16B is the 4th clock, and the period of the time T2 to the time T3 is 5.
  • the arithmetic data for the next 18 bits can be read out at the time T4 to the time T7. Further, at time T7 to time T10, the next 18 bits of arithmetic data can be read out.
  • the operation of reading the calculated data from the pixel block 12 in the first embodiment and the present embodiment corresponds to the operation of the stride 3, and the pooling process is omitted. However, the pooling process is performed to obtain the calculated data. It may be further compressed.
  • an image pickup apparatus having an image processing function and capable of high-speed operation.
  • FIG. 17A is a diagram showing an example of the pixel structure of the image pickup apparatus, and may be a laminated structure of layers 561 and 563.
  • Layer 561 has a photoelectric conversion device 101.
  • the photoelectric conversion device 101 can have a layer 565a and a layer 565b as shown in FIG. 18A. In some cases, the layer may be referred to as a region.
  • the photoelectric conversion device 101 shown in FIG. 18A is a pn junction type photodiode.
  • a p-type semiconductor can be used for the layer 565a and an n-type semiconductor can be used for the layer 565b.
  • an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.
  • the pn junction type photodiode can be typically formed by using single crystal silicon.
  • a photodiode having a single crystal silicon as a photoelectric conversion layer has a relatively wide spectral sensitivity characteristic from ultraviolet light to near-infrared light, and can detect light of various wavelengths by combining with an optical conversion layer described later. Can be done.
  • a compound semiconductor may be used as the photoelectric conversion layer of the pn junction type photodiode.
  • the compound semiconductor include gallium-arsenic-phosphorus compound (GaAsP), gallium-phosphorus compound (GaP), indium-gallium-arsenic compound (InGaAs), lead-sulfur compound (PbS), and lead-selenium compound (PbSe). ), Indium-arsenic compound (InAs), indium-antimonide compound (InSb), mercury-cadmium-tellulu compound (HgCdTe) and the like can be used.
  • the compound semiconductor includes a compound semiconductor having a group 13 element (aluminum, gallium, indium, etc.) and a group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.) (also referred to as a group 3-5 compound semiconductor), or a group 12 element. It is preferably a compound semiconductor (also referred to as a group 2-6 compound semiconductor) having a group 16 element (oxygen, sulfur, selenium, tellurium, etc.) (magnesium, zinc, cadmium, mercury, etc.) and a group 16 element (oxygen, sulfur, selenium, tellurium, etc.).
  • the band gap of the compound semiconductor can be changed according to the combination of constituent elements and the atomic number ratio thereof, it is possible to form a photodiode having sensitivity in various wavelength ranges from ultraviolet light to infrared light. ..
  • the wavelength of ultraviolet light is around 0.01 ⁇ m to 0.38 ⁇ m
  • the wavelength of visible light is around 0.38 ⁇ m to 0.75 ⁇ m
  • the wavelength of near infrared light is around 0.75 ⁇ m to 2.5 ⁇ m. It can be generally defined that the wavelength of near-infrared light is near 2.5 ⁇ m to around 4 ⁇ m, and the wavelength of far-infrared light is near 4 ⁇ m to around 1000 ⁇ m.
  • GaP or the like can be used for the photoelectric conversion layer.
  • silicon, GaAsP or the like can be used for the photoelectric conversion layer.
  • InGaAs or the like can be used for the photoelectric conversion layer.
  • PbS, InAs or the like can be used for the photoelectric conversion layer.
  • PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.
  • the photodiode using the compound semiconductor may be a pin junction as well as a pn junction. Further, the pn junction and the pin junction are not limited to the homozygous structure, but may be a heterojunction structure.
  • a first compound semiconductor can be used for one layer of the pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used for the other layer.
  • a first compound semiconductor can be used for any one or two layers of the pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used for the other layer.
  • One of the first compound semiconductor and the second compound semiconductor may be a single semiconductor such as silicon.
  • the photoelectric conversion layer of the photodiode may be formed by using a different material for each pixel.
  • an image pickup device having any two types of pixels such as a pixel for detecting ultraviolet light, a pixel for detecting visible light, and a pixel for detecting infrared light, or three types of pixels can be formed. Can be done.
  • the photoelectric conversion device 101 included in the layer 561 may be a stack of the layer 566a, the layer 566b, the layer 566c, and the layer 566d.
  • the photoelectric conversion device 101 shown in FIG. 18B is an example of an avalanche photodiode, in which layers 566a and 566d correspond to electrodes, and layers 566b and 566c correspond to photoelectric conversion units.
  • the layer 566a is preferably a low resistance metal layer or the like.
  • a low resistance metal layer or the like aluminum, titanium, tungsten, tantalum, silver or a laminate thereof can be used.
  • the layer 566d it is preferable to use a conductive layer having high translucency with respect to visible light.
  • a conductive layer having high translucency with respect to visible light For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene and the like can be used. It should be noted that the layer 566d may be omitted.
  • the layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction type photodiode having a selenium-based material as a photoelectric conversion layer, for example. It is preferable to use a selenium-based material which is a p-type semiconductor as the layer 566b and a gallium oxide which is an n-type semiconductor as the layer 566c.
  • a photoelectric conversion device using a selenium-based material has a characteristic of high external quantum efficiency with respect to visible light.
  • the amplification of electrons with respect to the amount of incident light can be increased by utilizing the avalanche multiplication.
  • the selenium-based material has a high light absorption coefficient, it has a production advantage that the photoelectric conversion layer can be formed of a thin film.
  • the thin film of the selenium-based material can be formed by a vacuum vapor deposition method, a sputtering method, or the like.
  • selenium-based material crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium can be used. These have light sensitivity from ultraviolet light to visible light. Further, a compound of copper, indium and selenium (CIS), a compound of copper, indium, gallium and selenium (CIGS) and the like can be used. These have photosensitivity from ultraviolet light to near infrared light.
  • CIS copper, indium and selenium
  • CGS indium, gallium and selenium
  • the n-type semiconductor is preferably made of a material having a wide bandgap and translucency with respect to visible light.
  • a material having a wide bandgap and translucency with respect to visible light For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used.
  • these materials also have a function as a hole injection blocking layer, and can reduce the dark current.
  • the photoelectric conversion device 101 included in the layer 561 may be a stack of the layer 567a, the layer 567b, the layer 567c, the layer 567d, and the layer 567e.
  • the photoelectric conversion device 101 shown in FIG. 18C is an example of an organic photoconductive film
  • the layer 567a is a lower electrode
  • the layer 567e is a translucent upper electrode
  • the layers 567b, 567c, and 567d correspond to a photoelectric conversion unit. ..
  • One of the layers 567b and 567d of the photoelectric conversion unit can be a hole transport layer and the other can be an electron transport layer. Further, the layer 567c can be a photoelectric conversion layer.
  • the hole transport layer for example, molybdenum oxide or the like can be used.
  • the electron transport layer for example, fullerenes such as C 60 and C 70 , or derivatives thereof and the like can be used.
  • the photoelectric conversion layer a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.
  • a mixed layer bulk heterojunction structure
  • organic semiconductors There are various types of organic semiconductors, and a material having photosensitivity to a target wavelength may be selected for the photoelectric conversion layer.
  • a silicon substrate can be used as the layer 563 shown in FIG. 17A.
  • the silicon substrate has a Si transistor or the like.
  • the Si transistor can be used to form a circuit for driving the pixel circuit, an image signal readout circuit, an image processing circuit, a neural network, a communication circuit, and the like.
  • a storage circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (MicroControl Unit), or the like may be formed.
  • the above circuit excluding the pixel circuit is referred to as a functional circuit.
  • the transistor provided in the functional circuit (calculation unit 21, low driver 31, column driver 32, low driver 33, column driver 34, circuit 35, circuit 36, etc.) provided in the layer 20 described in the first embodiment, one of them. Part or all can be provided in layer 563.
  • the layer 563 may be a stack of a plurality of layers as shown in FIG. 17B.
  • FIG. 17B three layers of layers 563a, 563b, and 563c are illustrated, but two layers may be used.
  • the layer 563 may be a stack of four or more layers. These layers can be laminated by using, for example, a bonding step. With this configuration, the pixel circuit and the functional circuit can be dispersed in a plurality of layers, and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a compact and highly functional image pickup device can be manufactured.
  • the pixel may have a laminated structure of layers 561, 562, and 563.
  • the layer 562 corresponds to the layer 10 described in the first embodiment and may have an OS transistor.
  • One or more of the above-mentioned functional circuits may be formed by an OS transistor.
  • one or more functional circuits may be formed by using the Si transistor included in the layer 563 and the OS transistor included in the layer 562.
  • the layer 563 may be used as a support substrate such as a glass substrate, and the pixel circuit and the functional circuit may be formed by the OS transistor included in the layer 562.
  • a normally-off CPU (also referred to as “NoffCPU (registered trademark)" can be realized by using an OS transistor and a Si transistor.
  • the NonfCPU is an integrated circuit including a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.
  • the NoffCPU can stop the power supply to the circuit that does not need to be operated in the NoffCPU and put the circuit in the standby state. No power is consumed in the circuit where the power supply is stopped and the circuit is in the standby state. Therefore, the Noff CPU can minimize the amount of power used. Further, the Noff CPU can retain information necessary for operation such as setting conditions for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to restart the power supply to the circuit, and it is not necessary to rewrite the setting conditions and the like. That is, high-speed recovery from the standby state is possible. In this way, the Nonf CPU can reduce the power consumption without significantly reducing the operating speed.
  • the layer 562 may be a stack of a plurality of layers as shown in FIG. 17D.
  • FIG. 17D two layers of layers 562a and 562b are illustrated, but three or more layers may be laminated. These layers can be formed, for example, to be stacked on layer 563. Alternatively, the layer formed on the layer 563 and the layer formed on the layer 561 may be bonded and formed.
  • a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
  • a typical example is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS, which will be described later, can be used.
  • CAAC-OS is suitable for transistors and the like in which the atoms constituting the crystal are stable and reliability is important. Further, since the CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like that is driven at high speed.
  • the OS transistor Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits an extremely low off-current characteristic of several yA / ⁇ m (current value per 1 ⁇ m of channel width). Further, the OS transistor has features different from those of the Si transistor such as impact ionization, avalanche breakdown, and short channel effect, and can form a circuit having high withstand voltage and high reliability. In addition, variations in electrical characteristics due to crystallinity non-uniformity, which is a problem with Si transistors, are unlikely to occur with OS transistors.
  • the semiconductor layer of the OS transistor includes, for example, indium, zinc and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, ittrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It can be a film represented by an In—M—Zn-based oxide containing.
  • the In-M-Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by using an ALD (Atomic layer deposition) method.
  • the atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn-based oxide by the sputtering method preferably satisfies In ⁇ M and Zn ⁇ M.
  • the atomic number ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target.
  • the semiconductor layer an oxide semiconductor having a low carrier density is used.
  • the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, and more preferably 1 ⁇ 10 11 / cm. 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3, it is possible to use an oxide semiconductor of 1 ⁇ 10 -9 / cm 3 or more carrier density.
  • Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It can be said that the oxide semiconductor is an oxide semiconductor having a low defect level density and stable characteristics.
  • a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the semiconductor, it is preferable that the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer are appropriate. ..
  • the concentration of silicon or carbon in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of the alkali metal or alkaline earth metal in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the oxide semiconductor constituting the semiconductor layer when the oxide semiconductor constituting the semiconductor layer contains hydrogen, it reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen deficiency, the transistor may have normally-on characteristics. In addition, a defect containing hydrogen in an oxygen deficiency may function as a donor and generate electrons as carriers. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.
  • Defects containing hydrogen in oxygen deficiencies can function as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, the carrier concentration may be used for evaluation instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the oxide semiconductor, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as a "donor concentration".
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3, more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor layer may have, for example, a non-single crystal structure.
  • the non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented on the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • the amorphous structure has the highest defect level density
  • CAAC-OS has the lowest defect level density.
  • the oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and has no crystal component.
  • the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal portion.
  • the semiconductor layer is a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystal structure region, a CAAC-OS region, and a single crystal structure region.
  • the mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.
  • CAC Cloud-Aligned Complex
  • the CAC-OS is, for example, a composition of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof.
  • the oxide semiconductor one or more metal elements are unevenly distributed, and the region having the metal elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
  • the state of being mixed in is also called a mosaic shape or a patch shape.
  • the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, ittrium, copper, vanadium, berylium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.
  • CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter, InO).
  • InO indium oxide
  • X1 X1 is a real number larger than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers larger than 0
  • gallium With an oxide (hereinafter, GaO X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)).
  • the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter, also referred to as a cloud-like.) in be.
  • the CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component are mixed.
  • the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region 2.
  • IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.
  • CAC-OS relates to the material composition of oxide semiconductors.
  • CAC-OS is a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.
  • CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component.
  • the regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.
  • the CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated.
  • a sputtering method one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good.
  • the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
  • CAC-OS is characterized by the fact that no clear peak is observed when measured using the ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c axis direction is not observed.
  • XRD X-ray diffraction
  • the CAC-OS has a ring-shaped high-brightness region (ring region) and the ring in the electron diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm. Multiple bright spots are observed in the area. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • nc nano-crystal
  • GaO X3 is the main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component have a structure in which they are unevenly distributed and mixed.
  • EDX energy dispersive X-ray spectroscopy
  • CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.
  • the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is a region having higher conductivity than the region in which GaO X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component. Therefore, a high field effect mobility ( ⁇ ) can be realized by distributing the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component in the oxide semiconductor in a cloud shape.
  • the region in which GaO X3 or the like is the main component is a region having higher insulating properties than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, since the region containing GaO X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, so that the insulation is high. On current ( Ion ) and high field effect mobility ( ⁇ ) can be achieved.
  • CAC-OS is suitable as a constituent material of various semiconductor devices.
  • ⁇ Laminate structure 1> Next, the laminated structure of the image pickup apparatus will be described with reference to a cross-sectional view.
  • the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted. Further, the laminated structure shown below can be formed by using a bonding step, a polishing step, or the like, if necessary.
  • FIG. 19 is an example of a cross-sectional view of a laminated body having a layer 560, a layer 561, and a layer 563 and having a bonded surface between the layers 563a and the layer 563b constituting the layer 563.
  • the layer 563b can have a functional circuit provided on the silicon substrate 611.
  • a transistor 223, a transistor 224, and a transistor 225 are shown as a part of the transistors included in the functional circuit.
  • the transistor 225 is exemplified as a transistor included in the binarization circuit 22.
  • the layer 563b is provided with a silicon substrate 611 and insulating layers 612, 613, 614, 616, 617, and 618.
  • the insulating layer 612 has a function as a protective film.
  • the insulating layers 613, 614, 616, and 617 have a function as an interlayer insulating film and a flattening film.
  • the insulating layer 618 and the conductive layer 619 have a function as a bonded layer.
  • the conductive layer 619 is electrically connected to the gate of the transistor 225.
  • a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used as the protective film.
  • an inorganic insulating film such as a silicon oxide film or an organic insulating film such as an acrylic resin or a polyimide resin can be used.
  • a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used as the dielectric layer of the capacitor. The bonding layer will be described later.
  • Conductors that can be used as wiring, electrodes, and plugs for electrical connections between devices include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, and hafnium. , Vanadium, Niob, Manganese, Magnesium, Zirconium, Berylium, Indium, Luthenium, Iridium, Strontium, Lantern, etc., or alloys containing the above-mentioned metal elements as components, or alloys containing the above-mentioned metal elements. Etc. may be appropriately selected and used.
  • the conductor is not limited to a single layer, and may be a plurality of layers made of different materials.
  • Layer 563a has the elements of pixel 14. Further, it may have an element of a functional circuit.
  • the transistor 102 and the transistor 105 included in the pixel circuit 15 are shown as a part of the elements of the pixel 14. In the cross-sectional view shown in FIG. 19, the electrical connection between the two is not shown.
  • the layer 563a is provided with a silicon substrate 632 and insulating layers 631, 633, 634, 635, 637, 638. Further, conductive layers 636 and 639 are provided.
  • the insulating layer 631 and the conductive layer 639 have a function as a bonded layer.
  • the insulating layers 634, 635, and 637 have a function as an interlayer insulating film and a flattening film.
  • the insulating layer 633 has a function as a protective film.
  • the insulating layer 638 has a function of insulating the silicon substrate 632 and the conductive layer 639.
  • the insulating layer 638 can be formed of the same material as other insulating layers. Further, the insulating layer 638 may be made of the same material as the insulating layer 631.
  • the conductive layer 639 is electrically connected to the other of the source or drain of the transistor 105 and to the conductive layer 619. Further, the conductive layer 636 is electrically connected to the wiring 111 (see FIG. 10A).
  • the Si transistor shown in FIG. 19 is a fin type having a channel forming region on a silicon substrate (silicon substrates 611, 632). A cross section in the channel width direction (cross section of A1-A2 shown in layer 563a of FIG. 19) is shown in FIG. 20A.
  • the Si transistor may be a planar type as shown in FIG. 20B.
  • the semiconductor layer 545 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 546 on the silicon substrate 632.
  • SOI Silicon on Insulator
  • Layer 561 has a photoelectric conversion device 101.
  • the photoelectric conversion device 101 can be formed on the layer 563a.
  • FIG. 19 shows a configuration in which the organic photoconductive film shown in FIG. 18C is used for the photoelectric conversion layer as the photoelectric conversion device 101.
  • the layer 567a is used as a cathode and the layer 567e is used as an anode.
  • the layer 561 is provided with insulating layers 651, 652, 653, 654, and a conductive layer 655.
  • the insulating layers 651, 653, and 654 have a function as an interlayer insulating film and a flattening film. Further, the insulating layer 654 is provided so as to cover the end portion of the photoelectric conversion device 101, and has a function of preventing a short circuit between the layer 567e and the layer 567a.
  • the insulating layer 652 has a function as an element separation layer. It is preferable to use an organic insulating film or the like as the element separation layer.
  • the layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to either the source or the drain of the transistor 102 included in the layer 563a.
  • the layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 of the layer 563a via the conductive layer 655.
  • Layer 560 is formed on layer 561.
  • the layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.
  • the light-shielding layer 671 can suppress the inflow of light to adjacent pixels.
  • a metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.
  • a color filter can be used for the optical conversion layer 672.
  • a color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.
  • the color filter 672R (red), the color filter 672G (green), and the color filter 672B (blue) can be assigned to different pixels.
  • an image pickup device that can obtain images in various wavelength regions can be obtained.
  • the infrared image pickup device can be obtained.
  • a filter that blocks light having a wavelength of near infrared rays or less is used in the optical conversion layer 672, a far infrared ray imaging device can be obtained.
  • the optical conversion layer 672 uses an ultraviolet filter that blocks light having a wavelength equal to or higher than that of visible light, the optical conversion layer 672 can be used as an ultraviolet image pickup device.
  • a plurality of different optical conversion layers may be arranged in one image pickup apparatus.
  • the color filter 672R red
  • the color filter 672G green
  • the color filter 672B blue
  • the infrared filter 672IR can be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired at the same time.
  • the color filter 672R red
  • the color filter 672G green
  • the color filter 672B blue
  • the ultraviolet filter 672UV can be assigned to different pixels.
  • a visible light image and an ultraviolet light image can be acquired at the same time.
  • the image pickup device can obtain an image that visualizes the intensity of radiation used in an X-ray image pickup device or the like.
  • radiation such as X-rays transmitted through a subject
  • a scintillator it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon.
  • the image data is acquired by detecting the light with the photoelectric conversion device 101.
  • an image pickup device having the above configuration may be used for a radiation detector or the like.
  • a scintillator contains a substance that absorbs its energy and emits visible or ultraviolet light when irradiated with radiation such as X-rays or gamma rays.
  • Gd 2 O 2 S Tb
  • Gd 2 O 2 S Pr
  • Gd 2 O 2 S Eu
  • BaFCl Eu
  • NaI, CsI, CaF 2 , BaF 2 , CeF 3 LiF, LiI, ZnO and the like.
  • Those dispersed in resin or ceramics can be used.
  • imaging with infrared light or ultraviolet light it is possible to impart an inspection function, a security function, a sensor function, and the like to the imaging device. For example, by performing imaging with infrared light, non-destructive inspection of products, selection of agricultural products (sugar content meter function, etc.), vein recognition, medical inspection, etc. can be performed. Further, by performing imaging with ultraviolet light, it is possible to detect ultraviolet light emitted from a light source or a flame, and it is possible to manage a light source, a heat source, a production device, and the like.
  • a microlens array 673 is provided on the optical conversion layer 672.
  • the light passing through the individual lenses of the microlens array 673 passes through the optical conversion layer 672 directly below and irradiates the photoelectric conversion device 101.
  • the microlens array 673 is preferably formed of a resin or glass having high translucency with respect to light of a target wavelength.
  • the layer 563b is provided with an insulating layer 618 and a conductive layer 619.
  • the conductive layer 619 has a region embedded in the insulating layer 618. Further, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights match.
  • the layer 563a is provided with an insulating layer 631 and a conductive layer 639.
  • the conductive layer 639 has a region embedded in the insulating layer 631. Further, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match.
  • the conductive layer 619 and the conductive layer 639 are metal elements having the same main component. Further, it is preferable that the insulating layer 618 and the insulating layer 631 are composed of the same components.
  • Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 619 and 639.
  • Cu, Al, W, or Au is preferably used because of the ease of joining.
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used for the insulating layers 618 and 631.
  • the conductive layer 619 and the conductive layer 639 may have a multi-layer structure of a plurality of layers, in which case the surface layer (bonding surface) may be the same metal material. Further, the insulating layer 618 and the insulating layer 631 may also have a multi-layered structure of a plurality of layers, in which case the insulating materials having the same surface layer (bonding surface) may be used.
  • a surface-activated bonding method can be used in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering treatment or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. ..
  • a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonds occur at the atomic level, so excellent bonding can be obtained not only electrically but also mechanically.
  • the surfaces treated with hydrophilicity such as oxygen plasma are brought into contact with each other for temporary bonding, and then main bonding is performed by dehydration by heat treatment.
  • a joining method or the like can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.
  • an insulating layer and a metal layer coexist on the respective bonding surfaces. Therefore, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.
  • a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer.
  • the surface of the metal layer may be made of a refractory metal such as Au and subjected to hydrophilic treatment.
  • a joining method other than the above-mentioned method may be used.
  • the circuit of the layer 563b and the element of the pixel 14 of the layer 563a can be electrically connected.
  • FIG. 21 is a modification of the laminated structure shown in FIG. 19, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and the partial configuration of the layer 563a are different, and the bonded surface is also formed between the layer 561 and the layer 563a. It is a configuration having.
  • the layer 561 has a photoelectric conversion device 101, insulating layers 661, 662, 664, 665 and conductive layers 685, 686.
  • the photoelectric conversion device 101 is a pn junction type photodiode, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region.
  • a pn junction type photodiode is formed on a silicon substrate.
  • the photoelectric conversion device 101 is an embedded photodiode, and a thin p-type region (a part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a can suppress dark current and reduce noise. can.
  • the insulating layer 661 and the conductive layers 685 and 686 have a function as a bonded layer.
  • the insulating layer 662 has a function as an interlayer insulating film and a flattening film.
  • the insulating layer 664 has a function as an element separation layer.
  • the silicon substrate is provided with a groove for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and the groove.
  • the insulating layer 665 By providing the insulating layer 665, it is possible to prevent the carriers generated in the photoelectric conversion device 101 from flowing out to the adjacent pixels.
  • the insulating layer 665 also has a function of suppressing the intrusion of stray light. Therefore, the insulating layer 665 can suppress color mixing.
  • An antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.
  • the insulating layer 664 can be formed by using the LOCOS (LOCOxidation of Silicon) method. Alternatively, it may be formed by using an STI (Shallow Trench Isolation) method or the like.
  • LOCOS LOCxidation of Silicon
  • STI Shallow Trench Isolation
  • an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a polyimide resin or an acrylic resin can be used.
  • the insulating layer 665 may have a multi-layer structure. Further, a space may be provided in a part of the insulating layer 665. The space may have a gas such as air or an inert gas. Further, the space may be in a decompressed state.
  • the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685.
  • the layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686.
  • the conductive layers 685 and 686 have a region embedded in the insulating layer 661. Further, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that their heights match.
  • an insulating layer 638 is formed on the insulating layer 637. Further, a conductive layer 683 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 684 electrically connected to the conductive layer 636 are formed.
  • the insulating layer 638 and the conductive layers 683 and 684 have a function as a bonded layer.
  • the conductive layers 683 and 684 have a region embedded in the insulating layer 638. Further, the surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that their heights match.
  • the conductive layers 683, 684, 685, and 686 are the same bonded layers as the above-mentioned conductive layers 619 and 639.
  • the insulating layers 638 and 661 are the same bonded layers as the above-mentioned insulating layers 618 and 631.
  • the conductive layer 683 and the conductive layer 685 one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101. Further, by laminating the conductive layer 684 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 and the wiring 111 (see FIG. 10A) can be electrically connected. Further, by laminating the insulating layer 638 and the insulating layer 661, the layer 561 and the layer 563a can be electrically and mechanically bonded.
  • FIG. 22 is a modification different from the above, and has a configuration in which the transistor 102 is provided on the layer 561.
  • one of the source or drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source or drain acts as a node N.
  • the charge accumulated in the photoelectric conversion device 101 can be completely transferred, and an image pickup device with less noise can be obtained.
  • the other of the source or drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692.
  • the gate of the transistor 104 included in the layer 563 is electrically connected to the conductive layer 691.
  • the conductive layers 691 and 692 are the same bonded layers as the above-mentioned conductive layers 619 and 639.
  • FIG. 23 is an example of a cross-sectional view of a laminated body having layers 560, 561, 562, and 563 and having no bonding surface.
  • a Si transistor is provided on the layer 563.
  • An OS transistor is provided on the layer 562. Since the configurations of the layers 563, 561 and 560 are the same as those shown in FIG. 19, the description thereof will be omitted here.
  • Layer 562 is formed on the layer 563.
  • Layer 562 has an OS transistor.
  • the transistor 102 and the transistor 105 are shown. In the cross-sectional view shown in FIG. 23, the electrical connection between the two is not shown.
  • the layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, 628. Further, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 111 (see FIG. 10A).
  • the insulating layer 621 has a function as a blocking layer.
  • the insulating layers 622, 623, 625, 626, and 628 have functions as an interlayer insulating film and a flattening film.
  • the insulating layer 624 has a function as a protective film.
  • the blocking layer it is preferable to use a film having a function of preventing the diffusion of hydrogen.
  • hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of the OS transistor is one of the factors that generate carriers in the oxide semiconductor layer, which reduces reliability. .. Therefore, it is preferable to provide a hydrogen blocking film between the layer on which the Si device is formed and the layer on which the OS transistor is formed.
  • the blocking film for example, aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.
  • aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.
  • the other of the source or drain of the transistor 105 is electrically connected to the gate of the transistor 225 via a plug. Further, the conductive layer 627 is electrically connected to the wiring 111 (see FIG. 10A).
  • One of the source and drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561.
  • the conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561.
  • FIG. 24A shows the details of the OS transistor.
  • the OS transistor shown in FIG. 24A is a self-aligned type in which an insulating layer is provided on a laminate of an oxide semiconductor layer and a conductive layer, and an opening reaching the oxide semiconductor layer is provided to form a source electrode 705 and a drain electrode 706. It is the composition of.
  • the OS transistor may have a channel forming region 708, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.
  • the OS transistor may have a self-aligned configuration in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.
  • FIG. 24C it may be a non-self-aligned top gate type transistor having a region where the source electrode 705 or the drain electrode 706 and the gate electrode 701 overlap.
  • the OS transistor shows a structure having a back gate 735, it may have a structure having no back gate.
  • the back gate 735 may be electrically connected to the front gate of the transistor provided opposite to each other as shown in the cross-sectional view in the channel width direction of the transistor shown in FIG. 24D.
  • FIG. 24D shows a cross section of the transistor B1-B2 of FIG. 24A as an example, but the same applies to transistors having other structures.
  • the back gate 735 may be configured to be able to supply a fixed potential different from that of the front gate.
  • FIG. 25 is a modification of the laminated structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and the partial configuration of the layer 562 are different, and a bonded surface is formed between the layer 561 and the layer 562. It is a structure to have.
  • the photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode, and has the same configuration as shown in FIG. 21.
  • an insulating layer 648 is formed on the insulating layer 628. Further, a conductive layer 688 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 689 electrically connected to the conductive layer 627 are formed.
  • the insulating layer 648 and the conductive layers 688 and 689 have a function as a bonded layer.
  • the conductive layers 688 and 689 have a region embedded in the insulating layer 648. Further, the surfaces of the insulating layer 648 and the conductive layers 688 and 689 are flattened so that their heights match.
  • the conductive layers 688 and 689 are the same bonded layers as the above-mentioned conductive layers 619 and 639.
  • the insulating layer 648 is the same bonded layer as the above-mentioned insulating layers 618 and 631.
  • the conductive layer 688 and the conductive layer 685 one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101. Further, by laminating the conductive layer 689 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 and the wiring 111 (see FIG. 10A) can be electrically connected. Further, by laminating the insulating layer 648 and the insulating layer 661, it is possible to perform electrical bonding and mechanical bonding between the layer 561 and the layer 562.
  • a configuration in which the transistor 102 is provided on the layer 561 shown in FIG. 22 may be applied to the configuration.
  • FIG. 26 has a configuration in which transistors 102, 105, etc., which are elements of a pixel circuit, and transistors 273, etc., which are elements of a memory cell 150, are provided on the same surface of layer 562.
  • FIG. 27 is a configuration in which the transistors 102, 104, 105, etc., which are elements of the pixel circuit, and the transistors 272, 273, etc., which are elements of the memory cell 150, are laminated so as to have an overlapping region in the layer 562. ..
  • the circuit area can be reduced, and a highly functional and compact image pickup device can be formed.
  • the wiring length of the wiring for electrically connecting the stacked elements can be shortened, the operation can be performed at high speed and low power consumption.
  • the configuration in which the transistor 102 is provided in the layer 561 shown in FIG. 22 may be applied to the configuration shown in FIGS. 26 and 27. Further, the configuration of the photoelectric conversion device 101 shown in FIG. 23 may be applied.
  • FIG. 29A is an external perspective view of the package containing the image sensor chip.
  • the package is a CSP (Chip Size Package) and has a bare chip 450 of an image sensor, a cover glass 440, an adhesive 430 for adhering both, and the like.
  • CSP Chip Size Package
  • the electrode pad 425 provided on the outside of the pixel array 455 is electrically connected to the back surface electrode 415 via the through electrode 420.
  • the electrode pad 425 is electrically connected to the circuit constituting the image sensor by wiring or wire.
  • the bare chip 450 may be a laminated chip laminated with a circuit having various functions.
  • FIG. 29 exemplifies a BGA (Ball Grid Array) having a configuration in which a bump 410 is formed from a solder ball on the back surface electrode 415.
  • BGA Bit Grid Array
  • it is not limited to BGA, and may be LGA (Land Grid Array) or PGA (Pin Grid Array).
  • a package in which the bare chip 450 is mounted on a QFN (Quad Flat No-lead package) or a QFP (Quad Flat Package) may be used.
  • FIG. 29B is an external perspective view of the upper surface side of the camera module in which the image sensor chip and the lens are combined.
  • the camera module has a lens cover 460, a plurality of lenses 470, and the like on the configuration of FIG. 29A.
  • an optical filter 480 that absorbs light having a specific wavelength is provided between the lens 470 and the cover glass 440, if necessary.
  • the optical filter 480 for example, in the case of an image sensor that mainly captures visible light, an infrared cut filter or the like can be used.
  • the image sensor chip By housing the image sensor chip in a package having the above-mentioned form, it can be easily mounted on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.
  • a display device As electronic devices that can use the image pickup device according to one aspect of the present invention, a display device, a personal computer, an image storage device or image reproduction device provided with a recording medium, a mobile phone, a game machine including a portable type, and a portable data terminal.
  • Electronic book terminals video cameras, cameras such as digital still cameras, goggle type displays (head mount displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers , Automatic cash deposit / payment machine (ATM), vending machine, etc. Specific examples of these electronic devices are shown in FIGS. 30A to 30F.
  • FIG. 30A is an example of a mobile phone, which includes a housing 981, a display unit 982, an operation button 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like.
  • the mobile phone includes a touch sensor on the display unit 982. All operations such as making a phone call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus.
  • An image pickup device according to an aspect of the present invention and an operation method thereof can be applied to the mobile phone.
  • FIG. 30B is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like.
  • Information can be input / output by the touch panel function of the display unit 912.
  • characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as voice by the speaker 913.
  • An image pickup device according to an aspect of the present invention and an operation method thereof can be applied to the portable data terminal.
  • FIG. 30C is a surveillance camera, which has a support base 951, a camera unit 952, a protective cover 953, and the like.
  • the camera unit 952 is provided with a rotation mechanism or the like, and by installing it on the ceiling, it is possible to take an image of the entire surroundings.
  • An image pickup device according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the camera unit.
  • the surveillance camera is an idiomatic name and does not limit its use.
  • a device having a function as a surveillance camera is also called a camera or a video camera.
  • FIG. 30D is a drive recorder, which includes a frame 941, a camera 942, an operation button 943, a mounting component 944, and the like. By installing it on the front window of an automobile or the like via the mounting component 944, it is possible to record the scenery in front of the vehicle while driving. A display panel for displaying the recorded image is provided on the back surface (not shown). An image pickup apparatus of one aspect of the present invention and an operation method thereof can be applied to the camera 942.
  • FIG. 30E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, and the like.
  • An image pickup device according to an aspect of the present invention and an operation method thereof can be applied to the digital camera.
  • FIG. 30F is a wristwatch-type information terminal, which has a display unit 932, a housing / wristband 933, a camera 939, and the like.
  • the display unit 932 includes a touch panel for operating the information terminal.
  • the display unit 932 and the housing / wristband 933 have flexibility and are excellent in wearability to the body.
  • An image pickup device according to an aspect of the present invention and an operation method thereof can be applied to the information terminal.
  • FIG. 31A is a drone which is an example of a mobile body, has a frame 921, an arm 922, a rotor 923, a blade 924, a camera 925, a battery 926, and the like, and has a function of autonomously flying, a function of resting in the air, and the like.
  • An image pickup apparatus of one aspect of the present invention and an operation method thereof can be applied to the camera 925.
  • FIG. 31B illustrates an external view of an automobile as an example of a moving body.
  • the automobile 890 has a plurality of cameras 891 and the like, and can acquire information on the front, rear, left, right, and above of the automobile 890.
  • An image pickup apparatus according to an aspect of the present invention and an operation method thereof can be applied to the camera 891.
  • the automobile 890 is equipped with various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.
  • the automobile 890 can analyze the image acquired by the camera 891 for a plurality of imaging directions 892, determine the surrounding traffic conditions such as the presence or absence of a guardrail or a pedestrian, and perform automatic driving. It can also be used in systems for road guidance, danger prediction, and the like.
  • the obtained image data is subjected to arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (for security purposes, etc.), and object recognition. It can perform processing such as (purpose of automatic operation, etc.), image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, and reduction of reflection reflection.
  • arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (for security purposes, etc.), and object recognition. It can perform processing such as (purpose of automatic operation, etc.), image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, and reduction of reflection reflection.
  • the automobile may be an automobile having an internal combustion engine, an electric vehicle, a hydrogen vehicle, or the like.
  • the moving body is not limited to the automobile.
  • examples of moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets), etc., and artificial intelligence is applied to these moving objects by applying a computer of one aspect of the present invention. It is possible to add a system that utilizes intelligence.

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JP2022538486A JP7686648B2 (ja) 2020-07-24 2021-07-12 撮像装置および電子機器
DE112021003951.2T DE112021003951T5 (de) 2020-07-24 2021-07-12 Abbildungsvorrichtung und elektronische Vorrichtung
KR1020227045104A KR20230047331A (ko) 2020-07-24 2021-07-12 촬상 장치 및 전자 기기
US18/008,302 US12120446B2 (en) 2020-07-24 2021-07-12 Imaging device and electronic device
CN202180043372.0A CN116018818A (zh) 2020-07-24 2021-07-12 摄像装置及电子设备
US18/910,318 US20250088769A1 (en) 2020-07-24 2024-10-09 Imaging device and electronic device
JP2025084797A JP2025113384A (ja) 2020-07-24 2025-05-21 撮像装置

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