WO2022017044A9 - 一种显示装置及其驱动方法 - Google Patents

一种显示装置及其驱动方法 Download PDF

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Publication number
WO2022017044A9
WO2022017044A9 PCT/CN2021/099187 CN2021099187W WO2022017044A9 WO 2022017044 A9 WO2022017044 A9 WO 2022017044A9 CN 2021099187 W CN2021099187 W CN 2021099187W WO 2022017044 A9 WO2022017044 A9 WO 2022017044A9
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Prior art keywords
transistor
electrode
line
node
control
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PCT/CN2021/099187
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English (en)
French (fr)
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WO2022017044A1 (zh
Inventor
青海刚
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/771,499 priority Critical patent/US11908414B2/en
Publication of WO2022017044A1 publication Critical patent/WO2022017044A1/zh
Publication of WO2022017044A9 publication Critical patent/WO2022017044A9/zh
Priority to US18/404,923 priority patent/US20240153461A1/en

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular, to a display device and a driving method thereof.
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • OLED has the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response speed, and has been widely used in mobile phones, tablet computers, digital cameras, etc. displayed in the field.
  • OLED is current-driven, and OLED is controlled by a stable current to emit light.
  • the pixel circuit is set to output a driving circuit to the OLED to drive the OLED to emit light.
  • the present disclosure provides a display device, comprising: light-emitting elements arranged in a matrix, pixel circuits arranged in a matrix, scan signal lines, data signal lines, initial signal lines, light-emitting control lines, first power lines, a first reset line, a second reset line and a third reset line;
  • the pixel circuit is in one-to-one correspondence with the light-emitting element; the pixel circuit is configured to drive the corresponding light-emitting element to emit light; the pixel circuit includes: a first reset sub-circuit, a node control sub-circuit, a light-emitting control sub-circuit and a second reset subcircuit;
  • the first reset subcircuit is respectively connected to the first reset line, the scan signal line, the initial signal line and the first node, and is configured to provide the initial signal to the first node under the control of the first reset line and the scan signal line line signal;
  • the node control subcircuit is respectively connected to the scan signal line, the second reset line, the data signal line, the first node, the second node, the third node and the first power supply line, and is set to be connected to the scan signal line, the second reset line, and the first power supply line.
  • the signal of the data signal line is provided to the second node, and the first node is compensated through the second node and the third node until the voltage of the first node meets the threshold condition;
  • the signal of the second node is provided to the third node;
  • the light-emitting control sub-circuit is respectively connected with the light-emitting control line, the first power line, the second node, the third node and the light-emitting element, and is configured to provide the second node with the first power line under the control of the light-emitting control line. a signal, providing a signal of the third node to the light-emitting element;
  • the second reset subcircuit is respectively connected to the third reset line, the initial signal line and the light-emitting element, and is configured to provide the light-emitting element with the signal of the initial signal line under the control of the third reset line;
  • the third reset line connected to the pixel circuit at row i is electrically connected to the first reset line connected to the pixel circuit at row i+1, where 1 ⁇ i ⁇ M, where M is the total number of rows of pixel circuits.
  • the display device includes: a substrate, and a driving structure layer and a light-emitting structure layer sequentially disposed on the substrate;
  • the driving structure layer includes: pixel circuits, scan signal lines, data signal lines, initial signal lines, light-emitting control lines, first power lines, first reset lines, second reset lines and third reset lines.
  • the light-emitting structure includes: a light-emitting element;
  • the scan signal line, the initial signal line, the light emission control line, the first reset line, the second reset line, and the third reset line extend in a first direction, and the data signal line and the the first power line extends along the second direction;
  • the first direction intersects the second direction.
  • each pixel circuit includes: a storage capacitor, and the storage capacitor includes: a first electrode plate and a second electrode plate; the first electrode plate is connected to a first power line, and the second electrode plate is connected to a first power line. the pole plate is connected to the first node;
  • the orthographic projection of the first pole plate on the substrate partially overlaps with the orthographic projection of the second pole plate on the substrate;
  • the first pole plate is provided with a via hole, and the via hole of the first pole plate exposes the second polar plate;
  • the scan signal line, the first reset line and the second reset line are located on one side of the second pole plate, and the light emission control line and the third reset line are located away from the second pole plate one side of the first reset line;
  • the first reset line is located on the side of the scan signal line away from the second pole plate, and the second reset line is located on the side of the scan signal line close to the second pole plate; the third reset line be located on the side of the light-emitting control line away from the second pole plate;
  • the initial signal line includes: a first initial signal line and a second initial signal line; the first initial signal line and the first reset line are located on the same side of the second plate, and are located on the first reset line A side away from the second pole plate; the second initial signal line and the third reset line are located on the same side of the second pole plate, and are located on the side of the third reset line away from the second pole plate .
  • the driving structure layer further includes: a power supply connection line and a connection electrode;
  • the power supply connecting wire and the first power supply line are arranged in different layers, and are connected with the first power supply line, and the first electrode plate is connected with the first power supply line through the power supply connecting line;
  • the orthographic projection of the power connection line on the substrate at least partially overlaps with the orthographic projection of the first pole plate on the substrate, and at least partially overlaps with the orthographic projection of the first power cord on the substrate;
  • connection electrode is arranged to connect the pixel circuit and the light-emitting element.
  • the node control subcircuit includes: a writing subcircuit, a driving subcircuit, a compensation subcircuit and an energy storage subcircuit;
  • the writing sub-circuit is respectively connected with the scan signal line, the second reset line, the data signal line and the second node, and is configured to provide the second node with a data signal line under the control of the scan signal line and the second reset line signal, or discharge to the second node;
  • the driving subcircuit is connected to the first node, the second node and the third node respectively, and is set to provide the signal of the second node to the third node under the control of the first node;
  • the compensation sub-circuit is respectively connected to the first node, the second reset line and the third node, and is set to provide the potential of the third node to the first node under the control of the second reset line, so as to perform the compensation on the first node. Compensation until the voltage of the first node satisfies the threshold condition;
  • the energy storage sub-circuit is connected to the first power line and the first node respectively, and is configured to store the voltage difference between the first power line and the first node.
  • the first reset sub-circuit includes: a first transistor and a second transistor;
  • the control electrode of the first transistor is connected to the first reset line, the first electrode of the first transistor is connected to the initial signal line, and the second electrode of the first transistor is connected to the first electrode of the second transistor ;
  • the control electrode of the second transistor is connected to the scan signal terminal, and the second electrode of the second transistor is connected to the first node.
  • the writing sub-circuit includes: a third transistor and a fourth transistor;
  • the control electrode of the third transistor is connected to the scan signal line, the first electrode of the third transistor is connected to the data signal line, and the second electrode of the third transistor is connected to the first electrode of the fourth transistor;
  • the control electrode of the fourth transistor is connected to the second reset line, and the second electrode of the fourth transistor is connected to the second node;
  • the length of the channel region of the fourth transistor is greater than the threshold length, and the width of the channel region of the fourth transistor is greater than the threshold width.
  • the driving sub-circuit includes: a fifth transistor, and the fifth transistor is a driving transistor;
  • the energy storage sub-circuit includes: a storage capacitor;
  • the control electrode of the fifth transistor is connected to the first node, the first electrode of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the third node;
  • the first end of the storage capacitor is connected to the first power line, and the second end of the storage capacitor is connected to the first node.
  • the compensation sub-circuit includes: a sixth transistor
  • the control electrode of the sixth transistor is connected to the second reset line, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the third node.
  • the light-emitting control sub-circuit includes: a seventh transistor and an eighth transistor;
  • the control electrode of the seventh transistor is connected to the light-emitting control line, the first electrode of the seventh transistor is connected to the first power supply line, and the second electrode of the seventh transistor is connected to the second node;
  • the control electrode of the eighth transistor is connected to the light-emitting control line, the first electrode of the eighth transistor is connected to the third node, and the second electrode of the eighth transistor is connected to the light-emitting element.
  • the second reset sub-circuit includes: a ninth transistor
  • the control electrode of the ninth transistor is connected to the third reset line, the first electrode of the ninth transistor is connected to the initial signal line, and the second electrode of the ninth transistor is connected to the light-emitting element.
  • the first reset sub-circuit includes: a first transistor and a second transistor;
  • the node control sub-circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a storage capacitor, the fifth transistor is a driving transistor;
  • the light-emitting control sub-circuit includes: a seventh transistor and an eighth transistor;
  • the second reset sub-circuit includes: a ninth transistor;
  • the control electrode of the first transistor is connected to the first reset line, the first electrode of the first transistor is connected to the initial signal line, and the second electrode of the first transistor is connected to the first electrode of the second transistor ;
  • the control electrode of the second transistor is connected to the scanning signal terminal, and the second electrode of the second transistor is connected to the first node;
  • the control electrode of the third transistor is connected to the scan signal line, the first electrode of the third transistor is connected to the data signal line, and the second electrode of the third transistor is connected to the first electrode of the fourth transistor;
  • the control electrode of the fourth transistor is connected to the second reset line, and the second electrode of the fourth transistor is connected to the second node;
  • the control electrode of the fifth transistor is connected to the first node, the first electrode of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the third node;
  • the control electrode of the sixth transistor is connected to the second reset line, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the third node;
  • the first end of the storage capacitor is connected to the first power line, and the second end of the storage capacitor is connected to the first node;
  • the control electrode of the seventh transistor is connected to the light-emitting control line, the first electrode of the seventh transistor is connected to the first power supply line, and the second electrode of the seventh transistor is connected to the second node;
  • the control electrode of the eighth transistor is connected to the light-emitting control line, the first electrode of the eighth transistor is connected to the third node, and the second electrode of the eighth transistor is connected to the light-emitting element;
  • the control electrode of the ninth transistor is connected to the third reset line, the first electrode of the ninth transistor is connected to the initial signal line, and the second electrode of the ninth transistor is connected to the light-emitting element.
  • the light-emitting element includes: an organic light-emitting diode
  • the anode of the organic light emitting diode is respectively connected with the second electrode of the eighth transistor and the second electrode of the ninth transistor, and the cathode of the organic light emitting diode is connected with the second power line.
  • the threshold condition is that the voltage of the first node is equal to the difference between the voltage of the signal of the data signal line and the absolute value of the threshold voltage of the fifth transistor.
  • the scan signal line and the third reset line are electrically connected.
  • each transistor includes: an active layer, a control electrode, a first electrode and a second electrode;
  • the driving structure layer includes: an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer arranged in sequence along a direction perpendicular to the substrate , a fourth insulating layer, a first flat layer, a fourth metal layer and a second flat layer;
  • the active layer includes: an initial signal line and active layers of all transistors;
  • the first metal layer includes: a scan signal line, a first reset line, a second reset line, a second electrode plate, a light-emitting control line, a first Three reset lines and control electrodes of all transistors;
  • the second metal layer includes: a first plate;
  • the third metal layer includes: a power supply connection line and the first or second electrodes of some transistors;
  • the fourth The metal layer includes: a first power supply line, a data signal line and a pixel electrode.
  • control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, the control electrode of the fourth transistor, and the control electrode of the sixth transistor The control electrode is located on the first side of the second electrode plate, the control electrode of the seventh transistor, the control electrode of the eighth transistor and the control electrode of the ninth transistor are located on the second side of the second electrode plate, the the first side and the second side are oppositely arranged;
  • the control electrode of the second transistor is located on the side of the control electrode of the first transistor close to the second plate; the control electrode of the second transistor and the control electrode of the third transistor are integrally formed;
  • the control electrode of the four transistors is located on the side of the control electrode of the second transistor close to the second electrode plate; the control electrode of the fourth transistor and the control electrode of the sixth transistor are integrally formed; the second electrode plate and the The control electrode of the fifth transistor is an integral molding structure; the control electrode of the seventh transistor and the control electrode of the eighth transistor are integral molding structure, and the control electrode of the ninth transistor is located away from the control electrode of the seventh transistor. one side of the second plate.
  • a first via hole, a second via hole, a third via hole and a fourth via hole are provided on the first insulating layer, the second insulating layer and the third insulating layer ; the second insulating layer and the third insulating layer are provided with a fifth via hole; the third insulating layer is provided with a sixth via hole; the fourth insulating layer and the first flat layer are provided A seventh via hole, an eighth via hole and a ninth via hole are provided; the second flat layer includes: a tenth via hole;
  • the first via hole exposes the active layer of the third transistor, and the first electrode of the third transistor is connected to the active layer of the third transistor through the first via hole;
  • the second via hole exposes the active layer of the third transistor The active layer of the second transistor, the second electrode of the second transistor is connected to the active layer of the second transistor through a second via hole;
  • the third via hole exposes the active layer of the eighth transistor, the The second electrode of the eighth transistor is connected to the active layer of the eighth transistor through a third via hole;
  • the fourth via hole exposes the active layer of the seventh transistor, and the first electrode of the seventh transistor passes through the fourth
  • the via hole is connected with the active layer of the seventh transistor;
  • the fifth via hole exposes the second electrode plate, and the second electrode of the second transistor is connected with the second electrode plate through the fifth via hole;
  • the The sixth via hole exposes the first electrode plate, and the power connection line is connected to the first electrode plate through the sixth via hole;
  • the seventh via hole exposes the first electrode of the third transistor, and the
  • the light-emitting element includes: a first electrode, a second electrode, and an organic light-emitting layer; the first electrode is located on the side of the organic light-emitting layer close to the substrate, and the second electrode is located on the side of the organic light-emitting layer close to the substrate. the side of the organic light-emitting layer away from the substrate;
  • the light-emitting structure layer includes: a pixel definition layer, a transparent conductive layer, an organic material layer and a conductive layer, the transparent conductive layer includes: a first electrode, the organic material layer includes: an organic light-emitting layer; The conductive layer includes: second electrode.
  • the present disclosure also provides a method for driving a display device, which is configured to drive the above-mentioned display device, and the method includes:
  • the first reset subcircuit Under the control of the first reset line and the scan signal line, the first reset subcircuit provides the first node with a signal of the initial signal line;
  • the second reset subcircuit Under the control of the third reset line, the second reset subcircuit provides the signal of the initial signal line to the light-emitting element, and under the control of the scan signal line, the second reset line and the first node, the node control subcircuit provides data to the second node The signal of the signal line is compensated to the first node through the second node and the third node, until the voltage of the first node meets the threshold condition;
  • the light-emitting control sub-circuit Under the control of the light-emitting control line, the light-emitting control sub-circuit provides the signal of the first power line to the second node, and the signal of the third node to the light-emitting element; under the control of the first node, the node control sub-circuit sends the signal of the third node to the third node Provides a signal from the second node.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an exemplary embodiment
  • FIG. 3 is an equivalent circuit diagram of a first reset sub-circuit provided by an exemplary embodiment
  • FIG. 4 is an equivalent circuit diagram of a node control sub-circuit provided by an exemplary embodiment
  • FIG. 5 is an equivalent circuit diagram of a lighting control sub-circuit provided by an exemplary embodiment
  • FIG. 6 is an equivalent circuit diagram of a second reset sub-circuit provided by an exemplary embodiment
  • FIG. 7 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment
  • FIG. 8 is a working timing diagram of a pixel circuit provided by an exemplary embodiment
  • 9A is an equivalent circuit diagram of a pixel circuit in a first stage provided by an exemplary embodiment
  • FIG. 9B is an equivalent circuit diagram of a pixel circuit in a second stage provided by an exemplary embodiment
  • 9C is an equivalent circuit diagram of a pixel circuit in a third stage provided by an exemplary embodiment
  • 9D is an equivalent circuit diagram of a pixel circuit in a fourth stage provided by an exemplary embodiment
  • 9E is an equivalent circuit diagram of a pixel circuit in a fifth stage provided by an exemplary embodiment
  • 9F is an equivalent circuit diagram of a pixel circuit in a sixth stage provided by an exemplary embodiment
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 11 is a partial top view of a display device provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of forming an active layer
  • FIG. 13 is a schematic diagram of forming a first metal layer
  • FIG. 14 is a schematic diagram of forming a second metal layer
  • 15 is a schematic diagram of forming a third insulating layer
  • 16 is a schematic diagram of forming a third metal layer
  • FIG. 17 is a schematic diagram of forming a first flat layer
  • FIG. 19 is a schematic diagram of forming a second planarization layer.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the "drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation.
  • transistors include: P-type transistors or N-type transistors, wherein the P-type transistor is turned on when the gate is low, and is turned off when the gate is high, and the N-type transistor is turned on when the gate is high. It is turned off when the gate is low.
  • a pixel circuit includes a drive transistor and a storage capacitor. Since the scan signal in the pixel circuit maintains an effective level for a short time, the amount of charge stored in the storage capacitor is insufficient, which affects the threshold voltage of the drive transistor. Insufficient compensation results in uneven display of the OLED display product, which reduces the display effect of the OLED display product.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit provided by the embodiment of the present disclosure is configured to drive the light-emitting element to emit light, and the pixel circuit includes: a first reset subcircuit, a node control subcircuit, a light emission control subcircuit and a second reset subcircuit.
  • the first reset sub-circuit is respectively connected to the first reset line RST1, the scan signal line Gate, the initial signal line Vinit and the first node N1, and is set to be controlled by the first reset line RST1 and the scan signal line Gate, to the first reset line RST1 and the scan signal line Gate.
  • Node N1 provides the signal of the initial signal line Vinit.
  • the node control sub-circuit is respectively connected with the scanning signal line Gate, the second reset line RST2, the data signal line Data, the first node N1, the second node N2, the third node N3 and the first power supply line VDD, and is set to be in the scanning signal Under the control of the line Gate, the second reset line RST2 and the first node N1, the signal of the data signal line Data is provided to the second node N2, and the compensation is performed to the first node N1 through the second node N2 and the third node N3 until the first node N1.
  • the voltage of a node N1 satisfies the threshold condition, and under the control of the first node N1, a signal of the second node N2 is provided to the third node N3.
  • the light-emitting control sub-circuit is respectively connected with the light-emitting control line EM, the first power line VDD, the second node N2, the third node N3 and the light-emitting element, and is arranged to provide the second node N2 with the first light-emitting element under the control of the light-emitting control line EM.
  • a signal of a power supply line VDD provides a signal of the third node N3 to the light-emitting element.
  • the second reset subcircuit is respectively connected to the third reset line RST3, the initial signal line Vinit and the light-emitting element, and is configured to provide the light-emitting element with a signal of the initial signal line Vinit under the control of the third reset line RST3.
  • the light-emitting element is connected to the second power supply line VSS.
  • the signals of the first reset line RST1 , the second reset line RST2 , the third reset line RST3 , the scan signal line Gate and the light emission control line EM may be pulse signals.
  • the first power supply terminal VDD may continuously provide a high-level signal.
  • the second power line VSS and the initial signal line Vinit may continuously provide a low-level signal.
  • the signal of the initial signal line Vinit may be a signal with a voltage value of 0V.
  • the voltage value of the signal of the second power supply line VSS and the voltage value of the signal of the initial signal line Vinit may be the same, or may be different.
  • the signal of the initial signal line Vinit may reset the light-emitting element and the first node.
  • the light emitting element may be an organic light emitting diode OLED.
  • the anode of the organic light emitting diode OLED is connected to the light-emitting control sub-circuit, and the cathode is connected to the second power supply terminal VSS.
  • the pixel circuit configured to drive the light-emitting element to emit light
  • the pixel circuit includes: a first reset sub-circuit, a node control sub-circuit, a light-emitting control sub-circuit and a second reset sub-circuit; a reset line, a scan signal line, an initial signal line and the first node are connected, and are set to provide a signal of the initial signal line to the first node under the control of the first reset line and the scan signal line;
  • the node control subcircuit is respectively connected with The scan signal line, the second reset line, the data signal line, the first node, the second node, the third node and the first power supply line are connected and set to be connected to the scan signal line, the second reset line and the first node under the control of the scan signal line, the second reset line and the first node.
  • the second node provides the signal of the data signal line, and compensates the first node through the second node and the third node until the voltage of the first node satisfies the threshold condition; under the control of the first node, the third node is provided with the first node
  • the signal of the two nodes; the light-emitting control sub-circuit which is respectively connected with the light-emitting control line, the first power line, the second node, the third node and the light-emitting element, and is set to provide the second node with the first signal under the control of the light-emitting control line.
  • the signal of the power line provides the signal of the third node to the light-emitting element; the second reset sub-circuit is respectively connected with the third reset line, the initial signal line and the light-emitting element, and is set to be controlled by the third reset line to the light-emitting element.
  • the signal of the initial signal line is provided; the light-emitting element is connected to the second power line.
  • the node control subcircuit in the present disclosure compensates the first node by controlling the scan signal line and the second reset line at the same time, so that after the signal at the data signal end is written and before the light-emitting element emits light, the first node is continuously compensated. Until the first node satisfies the threshold condition, the compensation effect is enhanced, and the display effect of the displayed product is improved.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an exemplary embodiment.
  • a node control subcircuit in a pixel circuit provided by an exemplary embodiment includes: a writing subcircuit, a driving subcircuit, a compensation subcircuit, and an energy storage subcircuit.
  • the writing sub-circuit is connected to the scanning signal line Gate, the second reset line RST2, the data signal line Data and the second node N2 respectively, and is set to be controlled by the scanning signal line Gate and the second reset line RST2, to the second node N2 provides the signal of the data signal line Data, and discharges to the second node N2 under the control of the second reset line RST2.
  • the driving sub-circuit is respectively connected to the first node N1, the second node N2 and the third node N3, and is configured to provide the signal of the second node N2 to the third node N3 under the control of the first node N1.
  • the compensation sub-circuit is connected to the first node N1, the second reset line RST2 and the third node N3 respectively, and is set to provide the potential of the third node N3 to the first node N1 under the control of the second reset line RST2, so as to The first node N1 performs compensation until the voltage of the first node N1 satisfies the threshold condition.
  • the energy storage sub-circuit is connected to the first power supply line VDD and the first node N1 respectively, and is configured to store the voltage difference between the first power supply line VDD and the first node N1.
  • FIG. 2 shows an exemplary structure of the node control sub-circuit, and the implementation of the sub-circuit is not limited thereto.
  • FIG. 3 is an equivalent circuit diagram of a first reset sub-circuit provided by an exemplary embodiment.
  • the first reset sub-circuit includes: a first transistor T1 and a second transistor T2.
  • the first transistor T1 and the second transistor T2 are switching transistors.
  • the control electrode of the first transistor T1 is connected to the first reset line RST1, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2.
  • the control electrode of the second transistor T2 is connected to the scanning signal terminal Gate, and the second electrode of the second transistor T2 is connected to the first node N1
  • FIG. 3 shows an exemplary structure of the first reset sub-circuit, and the implementation of the sub-circuit is not limited thereto.
  • FIG. 4 is an equivalent circuit diagram of a node control subcircuit provided by an exemplary embodiment.
  • the write sub-circuit in the node control sub-circuit includes: a third transistor T3 and a fourth transistor T4.
  • the driving sub-circuit includes: a fifth transistor T5, which is a driving transistor.
  • the energy storage sub-circuit includes: a storage capacitor Cst.
  • the compensation sub-circuit includes: a sixth transistor T6.
  • the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are switching transistors.
  • the control electrode of the third transistor T3 is connected to the scanning signal line Gate, the first electrode of the third transistor T3 is connected to the data signal line Data, and the second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4.
  • the control electrode of the fourth transistor T4 is connected to the second reset line RST2, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the control electrode of the fifth transistor T5 is connected to the first node N1, the first electrode of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the third node N3.
  • the control electrode of the sixth transistor T6 is connected to the second reset line RST2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the third node N3.
  • the first end of the storage capacitor Cst is connected to the first power line VDD, and the second end of the storage capacitor Cst is connected to the first node N1.
  • the length of the channel region of the fourth transistor T4 is greater than the threshold length, and the width of the channel region of the fourth transistor T4 is greater than the threshold width.
  • the channel region of the fourth transistor T4 is conductive, and a capacitance is formed between the channel region of the fourth transistor T4 and the control electrode, because the length of the channel region of the fourth transistor T4 is greater than the threshold length , the width of the channel region of the fourth transistor T4 is greater than the threshold width, so that the capacitance value of the capacitor formed between the channel region of the fourth transistor T4 and the control electrode is larger.
  • the fourth transistor T4 when the fourth transistor T4 is turned on, it is equivalent to a capacitor and can be charged or discharged.
  • the threshold length is the maximum value of the conductive channel lengths of the second transistor, the fourth transistor and the fifth transistor
  • the threshold width is the conductive channel length of the second transistor, the fourth transistor and the fifth transistor maximum width
  • the drive transistor may be an enhancement mode transistor, or may be a depletion mode transistor.
  • the signals of the first power supply line VDD and the second power supply line VSS are set so that the driving transistor is in a saturated state when turned on.
  • FIG. 4 specifically shows an exemplary structure of the node control sub-circuit, and the implementation of the sub-circuit is not limited thereto.
  • FIG. 5 is an equivalent circuit diagram of a lighting control sub-circuit provided by an exemplary embodiment. As shown in FIG. 5, in an exemplary embodiment, the lighting control sub-circuit includes: a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 are switching transistors.
  • the control electrode of the seventh transistor T7 is connected to the light-emitting control line EM, the first electrode of the seventh transistor T7 is connected to the first power line VDD, and the second electrode of the seventh transistor T7 is connected to the second node N2.
  • the control electrode of the eighth transistor T8 is connected to the light-emitting control line EM, the first electrode of the eighth transistor T8 is connected to the third node N3, and the second electrode of the eighth transistor T8 is connected to the light-emitting element.
  • FIG. 5 shows an exemplary structure of the lighting control sub-circuit, and the implementation of the sub-circuit is not limited thereto.
  • FIG. 6 is an equivalent circuit diagram of a second reset sub-circuit provided by an exemplary embodiment.
  • the second reset sub-circuit includes: a ninth transistor T9.
  • the ninth transistor T9 is a switching transistor.
  • the control electrode of the ninth transistor T9 is connected to the third reset line RST3, the first electrode of the ninth transistor T9 is connected to the initial signal line Vinit, and the second electrode of the ninth transistor T9 is connected to the light emitting element.
  • the setting of the second reset sub-circuit can eliminate the interface charge in the light-emitting element, and can improve the display effect of the display product.
  • FIG. 6 shows an exemplary structure of the second reset sub-circuit, and the implementation of the sub-circuit is not limited thereto.
  • FIG. 7 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment.
  • the first reset sub-circuit includes: a first transistor T1 and a second transistor T2;
  • the node control sub-circuit includes: a third transistor T3, a fourth transistor T4, a fifth transistor
  • the transistor T5, the sixth transistor T6 and the storage capacitor Cst, the fifth transistor T5 is a driving transistor;
  • the lighting control sub-circuit includes: a seventh transistor T7 and an eighth transistor T8;
  • the second reset sub-circuit includes: a ninth transistor T9.
  • the control electrode of the first transistor T1 is connected to the first reset line RST1, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2.
  • the control electrode of the second transistor T2 is connected to the scanning signal terminal Gate, and the second electrode of the second transistor T2 is connected to the first node N1.
  • the control electrode of the third transistor T3 is connected to the scanning signal line Gate, the first electrode of the third transistor T3 is connected to the data signal line Data, and the second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4.
  • the control electrode of the fourth transistor T4 is connected to the second reset line RST2, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the control electrode of the fifth transistor T5 is connected to the first node N1, the first electrode of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the third node N3.
  • the control electrode of the sixth transistor T6 is connected to the second reset line RST2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the third node N3.
  • the first end of the storage capacitor Cst is connected to the first power line VDD, and the second end of the storage capacitor Cst is connected to the first node N1.
  • the control electrode of the seventh transistor T7 is connected to the light-emitting control line EM, the first electrode of the seventh transistor T7 is connected to the first power line VDD, and the second electrode of the seventh transistor T7 is connected to the second node N2.
  • the control electrode of the eighth transistor T8 is connected to the light-emitting control line EM, the first electrode of the eighth transistor T8 is connected to the third node N3, and the second electrode of the eighth transistor T8 is connected to the light-emitting element.
  • the control electrode of the ninth transistor T9 is connected to the third reset line RST3, the first electrode of the ninth transistor T9 is connected to the initial signal line Vinit, and the second electrode of the ninth transistor T9 is connected to the light emitting element.
  • the anode of the organic light emitting diode OLED is connected to the second electrode of the eighth transistor T8 and the second electrode of the ninth transistor T9, respectively, and the cathode of the organic light emitting diode OLED is connected to the second power line VSS.
  • the transistors T1 to T9 may all be N-type thin film transistors or P-type thin film transistors.
  • the transistors T1 to T9 may be of the same type, or may be different.
  • the process flow can be unified, the process process can be reduced, and the yield of the product can be improved.
  • the transistors T1 to T9 may be low temperature polysilicon thin film transistors.
  • the low temperature polysilicon thin film transistor can reduce the drain electrode in the pixel circuit and improve the performance of the pixel circuit.
  • the transistors T1 to T9 may be of bottom gate structure, or may be of top gate structure.
  • the threshold condition is that the voltage of the first node N1 is equal to the difference between the voltage of the signal of the data signal line Data and the absolute value of the threshold voltage of the fifth transistor T5, which can make the driving current flowing to the light-emitting element equal to
  • the threshold voltage of the driving transistor is irrelevant, ensuring the uniformity of the display product.
  • the scan signal line Gate and the third reset line RST may be different signal lines, or may be the same signal line.
  • the scanning signal line and the third reset line are the same signal line, the number of signal lines in the pixel circuit can be reduced, and the area occupied by the pixel circuit can be reduced.
  • the pixel circuit provided by an exemplary embodiment is described below through the working process of the pixel circuit.
  • FIG. 8 is a working timing diagram of the pixel circuit provided by an exemplary embodiment
  • FIG. 9A is a pixel circuit provided by an exemplary embodiment in the first embodiment.
  • FIG. 9B is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment in a second stage
  • FIG. 9C is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment in a third stage
  • 9D is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment in the fourth stage
  • FIG. 9E is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment in the fifth stage
  • a pixel circuit involved in an exemplary embodiment includes: 8 switching transistors (T1, T2, T3, T4, T6, T7, T8 and T9), 1 driving transistor (T5) , 1 capacitor unit (Cst), 6 input signal lines (Gate, RST1, RST2, RST3, EM and Data) and 3 power terminals (VDD, VSS and Vinit).
  • the first power line VDD continues to provide a high-level signal
  • the second power supply terminal VSS and the initial signal line Vinit continue to provide a low-level signal.
  • a pixel circuit provided by an exemplary embodiment includes: a first stage S1 to a sixth stage S6.
  • the preparation stage as shown in FIG. 9A, the input signal of the first reset line RST1 is at a low level, and the first transistor T1 is turned on.
  • the input signal of the scanning signal line Gate is at a high level, and the second transistor T2 and the third transistor T3 are turned off.
  • the input signal of the second reset line RST2 is at a high level, and the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the input signal of the light-emitting control line EM is at a high level, and the seventh transistor T7 and the eighth transistor T8 are turned off.
  • the input signal of the third reset line RST3 is at a high level, and the ninth transistor T9 is turned off. Since the first transistor T1 is turned on and the second transistor T2 is turned off, the first node N1 cannot be reset.
  • the first stage S1 is a preparation stage for the second stage S2.
  • the second stage S2 is the reset stage. As shown in FIG. 9B , the input signal of the first reset line RST1 is at a low level, and the first transistor T1 is turned on. When the input signal of the scanning signal line Gate is at a low level, the second transistor T2 and the third transistor T3 are turned on. Since the first transistor T1 and the second transistor T2 are turned on, the initial signal line Vinit provides an initial signal to the first node N1 to start charging the first node N1, and at this time, the storage capacitor Cst starts to charge for the data of the third stage Prepare for the writing of the signal.
  • the fifth transistor T5 Since the difference between the voltage value of the first node N1 and the voltage value of the second node N2 is greater than the threshold voltage of the fifth transistor, the fifth transistor T5 is turned on.
  • the input signal of the third reset line RST3 is at low level, the ninth transistor T9 is turned on, and the initial signal line Vinit provides the initial signal to the anode of the organic light emitting diode OLED to initialize the anode of the organic light emitting diode OLED.
  • the input signal of the second reset line RST2 is at a high level, and the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the input signal of the light-emitting control line EM is at a high level, and the seventh transistor T7 and the eighth transistor T8 are turned off.
  • the third stage S3 is the writing compensation stage. As shown in FIG. 9C , the input signal of the scanning signal line Gate is at a low level, and the second transistor T2 and the third transistor T3 are turned on. The input signal of the second reset line RST2 is at a low level, and the fourth transistor T4 and the sixth transistor T6 are turned on. Since the third transistor T3 and the fourth transistor T4 are turned on, the input signal of the data signal line Data is written into the second node N2.
  • the fourth transistor T4 When the fourth transistor T4 is turned on, the fourth transistor T4 is equivalent to the capacitor Cm, the input signal of the data signal line Data charges the capacitor Cm through the third transistor T3, and the input signal of the data signal line Data passes through the third transistor T3, the fourth The transistor T4, the fifth transistor T5 and the sixth transistor T6 charge the storage capacitor Cst to compensate the first node N1. With the extension of the charging time, the voltage value of the second node N2 will soon be equal to the voltage value Vdata of the input signal of the data signal line Data. At this time, the voltage difference between the two ends of the capacitor Cm is V2-Vdata, where V2 is the second The voltage value of the reset line RST2 in the third stage.
  • the input signal of the data signal line Data charges the storage capacitor Cst through the fifth transistor T5, as the voltage value of the first node N1 increases, the current flowing through the fifth transistor T5 becomes smaller and smaller, and the voltage of the first node N1 becomes smaller and smaller. The rise in value is also getting slower and slower.
  • each line of high-frequency display products has less turn-on time, that is, the time when the input signal of the scanning signal line Gate is at a low level is short, therefore, at the end of the third stage S3, the voltage value of the first node N1 is less than Vdata-
  • the input signal of the third reset line RST3 is at low level, the ninth transistor T9 is turned on, and the input signal of the initial signal line Vinit is provided to the anode of the organic light emitting diode OLED to initialize the anode of the organic light emitting diode OLED.
  • the input signal of the first reset line RST1 is at a high level, the first transistor T1 is turned off, the input signal of the light emission control line EM is at a high level, and the seventh transistor T7 and the eighth transistor T8 are turned off.
  • the compensation stage as shown in FIG. 9D, the input signal of the scanning signal line Gate is at a high level, the second transistor T2 and the third transistor T3 are turned off, and the input signal of the second reset line RST3 is at a low level, The fourth transistor T4 and the sixth transistor T6 are turned on.
  • the third transistor T3 is turned off, there is no signal to continue to write the signal to the storage capacitor Cst, but the input signal of the data signal line Data is written to one end of the capacitor Cm in the third stage.
  • the transistor T5 and the sixth transistor T6 continue to charge the storage capacitor Cst to compensate the first node N1, and the voltage value of the first node N1 continues to rise until the fifth transistor T5 is turned off.
  • the voltage of the first node N1 The value satisfies the threshold condition, that is, the voltage value of the first node N1 is equal to Vdata-
  • the voltage value of the first node N1 has a small rise, and the electric charge of the capacitor Cm is limited. Therefore, the capacitor Cm can be approximated as a constant voltage source.
  • the input signal of the first reset line RST1 is at a high level, and the first transistor T1 is turned off.
  • the input signal of the light-emitting control line EM is at a high level, and the seventh transistor T7 and the eighth transistor T8 are turned off.
  • the input signal of the third reset line RST4 is at a high level, and the ninth transistor T9 is turned off.
  • the fifth stage S5 is the buffer stage. As shown in FIG. 9E , the input signal of the first reset line RST1 is at a high level, and the first transistor T1 is turned off.
  • the input signal of the scanning signal line Gate is at a high level, and the second transistor T2 and the third transistor T3 are turned off.
  • the input signal of the second reset line RST2 is at a high level, and the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the input signal of the light-emitting control line EM is at a high level, and the seventh transistor T7 and the eighth transistor T8 are turned off.
  • the input signal of the third reset line RST3 is at a high level, and the ninth transistor T9 is turned off. In this stage, the voltage value of the first node N1 remains unchanged.
  • the length of the fifth stage S5 depends on the moment when the falling edge of the input signal of the lighting control line EM occurs.
  • the input signal of the light-emitting control line EM is at a low level
  • the seventh transistor T7 and the eighth transistor T8 are turned on
  • the storage capacitor Cst begins to discharge
  • the fifth transistor T5 is turned on
  • the fifth transistor T5 outputs a driving current to drive the organic light emitting diode OLED to emit light.
  • the input signal of the first reset line RST1 is at a high level
  • the first transistor T1 is turned off.
  • the input signal of the scanning signal line Gate is at a high level
  • the second transistor T2 and the third transistor T3 are turned off.
  • the input signal of the second reset line RST2 is at a high level
  • the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the input signal of the third reset line RST3 is at a high level
  • the ninth transistor T9 is turned off.
  • the driving current I OLED satisfies the following formula:
  • Vsg is the voltage difference between the source electrode and the gate electrode of the fifth transistor
  • Vdd is the voltage value of the signal of the first power supply line
  • K is a fixed constant related to process parameters and geometric dimensions of the fifth transistor T5.
  • the driving current output by the fifth transistor T5 is not affected by the threshold voltage of the fifth transistor T5, but is only related to the signal of the data signal line, thereby eliminating the fifth transistor T5.
  • the influence of the threshold voltage of the transistor T5 on the driving current can ensure that the display brightness of the display product is uniform, and the display effect of the entire display product is improved.
  • FIG. 10 is a schematic structural diagram of the display device provided by the embodiment of the present disclosure
  • FIG. 11 is a partial top view of the display device provided by the embodiment of the present disclosure.
  • a display device provided by an embodiment of the present disclosure includes: light-emitting elements 10 arranged in a matrix, pixel circuits 20 arranged in a matrix, a scanning signal line Gate, a data signal line Data, an initial signal line Vinit, a light-emitting element A control line EM, a first power supply line VDD, a first reset line RST1, a second reset line RST2 and a third reset line RST3.
  • the third reset line connected to the pixel circuit at row i is electrically connected to the first reset line connected to the pixel circuit at row i+1, where 1 ⁇ i ⁇ M, where M is the total number of rows of pixel circuits.
  • the pixel circuit 20 is the pixel circuit provided by any of the foregoing embodiments.
  • the pixel circuits are in one-to-one correspondence with the light-emitting elements; the pixel circuits are configured to drive the corresponding light-emitting elements to emit light.
  • the pixel circuit includes: a first reset sub-circuit, a node control sub-circuit, a light-emitting control sub-circuit and a second reset sub-circuit.
  • the first reset subcircuit is connected to the first reset line, the scan signal line, the initial signal line and the first node respectively, and is set to provide the first node with the initial signal line under the control of the first reset line and the scan signal line.
  • node control sub-circuit respectively connected with the scanning signal line, the second reset line, the data signal line, the first node, the second node, the third node and the first power supply line, and is set to be in the scanning signal line, the second reset line
  • the signal of the data signal line is provided to the second node, and the first node is compensated through the second node and the third node until the voltage of the first node meets the threshold condition
  • the light-emitting control sub-circuit is respectively connected with the light-emitting control line, the first power line, the second node, the third node and the light-emitting element, and is set to be controlled by the light-emitting control line
  • the signal of the first power supply line is provided to the second node
  • the signal of the third node is provided to the light-emitting element
  • the second reset sub-circuit is respectively connected to the third
  • the display device includes: a plurality of sub-pixels.
  • Each sub-pixel includes: a light-emitting element and a pixel circuit.
  • the light-emitting element in each sub-pixel is connected to the pixel circuit.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display device may include: a substrate, and a driving structure layer and a light emitting structure layer sequentially disposed on the substrate.
  • the driving structure layer includes: pixel circuits, scan signal lines, data signal lines, initial signal lines, light emission control lines, first power supply lines, first reset lines, second reset lines and third reset lines.
  • the light-emitting structure layer includes: a light-emitting element.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal foil; the flexible substrate may be, but not limited to, polyparaphenylene ethylene dicarboxylate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene , one or more of textile fibers.
  • the scan signal line Gate, the initial signal line Vinit, the light emission control line EM, the first reset line RST1 , the second reset line RST2 and the third reset line RST3 are along the first direction
  • the data signal line Data and the first power line VDD extend along the second direction.
  • the first direction intersects the second direction.
  • intersection of the first direction and the second direction means that the included angle between the first direction and the second direction may be about 70 degrees to 90 degrees.
  • the angle between the first direction and the second direction may be 90 degrees.
  • each pixel circuit includes: a storage capacitor.
  • the storage capacitor includes: a first plate C1 and a second plate C2.
  • the first plate C1 is connected to the first power line VDD, and the second plate C2 is connected to the first node N1.
  • the orthographic projection of the first pole plate C1 on the substrate partially overlaps with the orthographic projection of the second pole plate on the substrate; the first pole plate C1 is provided with a via hole, and the first pole plate C1 The via hole exposes the second electrode plate C2.
  • the scanning signal line Gate, the first reset line RST1 and the second reset line RST2 are located on one side of the second electrode plate C2, the light emission control line EM and the third reset line RST3 is located on the side of the second pole plate C2 away from the first reset line RST1.
  • the first reset line RST1 is located on the side of the scan signal line Gate away from the second electrode plate C2 .
  • the second reset line RST2 is located on the side of the scan signal line Gate close to the second electrode plate C2.
  • the third reset line RST3 is located on the side of the light emitting control line EM away from the second electrode plate C2.
  • the initial signal line Vinit includes: a first initial signal line and a second initial signal line.
  • the first initial signal line and the first reset line are located on the same side of the second pole plate, and on the side of the first reset line away from the second pole plate.
  • the second initial signal line and the third reset line are located on the same side of the second electrode plate, and are located on the side of the third reset line away from the second electrode plate.
  • the first initial signal line connected by the pixel circuits is multiplexed as the second initial signal line connected by the pixel circuit in the previous row, and the second initial signal line connected by the pixel circuit is multiplexed as the pixel circuit connection in the next row. the first initial signal line.
  • the driving structure layer further includes: a power supply connection line VL and a connection electrode 101.
  • the power connection line VL is disposed in a different layer from the first power supply line, and is connected to the first power supply line VDD.
  • the first plate C1 is connected to the first power line VDD through the power connection line VL.
  • the orthographic projection of the power connection line VL on the substrate at least partially overlaps with the orthographic projection of the first plate C1 on the substrate, and at least partially overlaps the orthographic projection of the first power supply line VDD on the substrate overlapping.
  • connection electrode 101 is provided to connect the pixel circuit and the light emitting element.
  • each transistor includes: an active layer, a control electrode, a first electrode and a second electrode.
  • the driving structure layer includes: an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, and a fourth insulating layer arranged in sequence along the direction perpendicular to the substrate layer, a first planarization layer, a fourth metal layer and a second planarization layer.
  • the active layer includes an initial signal line Vinit and active layers of all transistors.
  • the initial signal line Vinit and the active layers of all transistors are arranged in the same layer and formed through the same patterning process.
  • the active layers of all transistors include: the active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, the active layer of the fourth transistor, the active layer of the fifth transistor, the active layer of the sixth transistor.
  • the first metal layer includes: a scan signal line Gate, a first reset line RST1, a second reset line RST2, a second electrode plate C2, a light-emitting control line EM, a second reset line RST2 Three reset lines RST3 and gates of all transistors.
  • the scan signal line Gate, the first reset line RST1, the second reset line RST2, the second plate C2, the light-emitting control line EM, the third reset line RST3 and the control electrodes of all transistors are in the same layer set and formed through the same patterning process.
  • the control electrodes of all transistors include: the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, the control electrode of the fourth transistor, the control electrode of the fifth transistor, the control electrode of the sixth transistor, the control electrode of the sixth transistor, and the control electrode of the fourth transistor.
  • control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, the control electrode of the fourth transistor and the control electrode of the sixth transistor are located on the first electrode of the second electrode plate.
  • control electrode of the seventh transistor, the control electrode of the eighth transistor and the control electrode of the ninth transistor are located on the second side of the second plate, and the first side and the second side are oppositely arranged;
  • control electrode of the second transistor is located on the side of the control electrode of the first transistor close to the second plate; the control electrode of the second transistor and the control electrode of the third transistor are integrally formed; The control electrode of the transistor is located on the side of the control electrode of the second transistor close to the second electrode plate; the control electrode of the fourth transistor and the control electrode of the sixth transistor are integrally formed; the control electrode of the second electrode and the control electrode of the fifth transistor are integrally formed Structure; the control electrode of the seventh transistor and the control electrode of the eighth transistor are integrally formed, and the control electrode of the ninth transistor is located on the side of the control electrode of the seventh transistor away from the second plate.
  • the second metal layer includes: a first electrode plate C1 .
  • the third metal layer includes: a power connection line VL and a first electrode or a second electrode of a part of the transistor.
  • the third metal layer includes: a power connection line VL, a second pole of the second transistor, a first pole of the third transistor, a first pole of the sixth transistor, and a first pole of the seventh transistor pole, the second pole of the eighth transistor and the second pole of the ninth transistor.
  • the power connection line VL, the second pole of the second transistor, the first pole of the third transistor, the first pole of the sixth transistor, the first pole of the seventh transistor, the The second electrode and the second electrode of the ninth transistor are disposed in the same layer and formed by the same patterning process.
  • the second electrode of the eighth transistor and the second electrode of the ninth transistor are the same electrode, and the second electrode of the second transistor and the first electrode of the sixth transistor are the same electrode.
  • the active layer is also multiplexed as the first electrode or the second electrode of the transistor other than the first electrode or the second electrode of the part of the transistor included in the third metal layer. That is, the active layer is multiplexed into the first pole of the first transistor, the second pole of the first transistor, the first pole of the second transistor, the second pole of the third transistor, the first pole of the fourth transistor, and the fourth transistor.
  • the second pole of the fifth transistor, the first pole of the fifth transistor, the second pole of the fifth transistor, the second pole of the sixth transistor, the second pole of the seventh transistor, the first pole of the eighth transistor, and the first pole of the ninth transistor one pole.
  • the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are the same electrode.
  • the second electrode 34 of the third transistor and the first electrode 43 of the fourth transistor are the same electrode.
  • the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, and the second electrode 74 of the seventh transistor are the same electrode.
  • the second electrode 54 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 83 of the eighth transistor are the same electrode.
  • the fourth metal layer includes: a first power supply line VDD, a data signal line Data and a pixel electrode 101 .
  • the first power supply line VDD, the data signal line Data and the pixel electrode 101 are disposed in the same layer and formed through the same patterning process.
  • a first via hole, a second via hole, a third via hole and a fourth via hole are provided on the first insulating layer, the second insulating layer and the third insulating layer; the second insulating layer and the third insulating layer are provided with a fifth via hole; the third insulating layer is provided with a sixth via hole; the fourth insulating layer and the first flat layer are provided with a seventh via hole, an eighth via hole and a ninth via hole a hole; the second flat layer includes: a tenth via hole.
  • the first via hole exposes the active layer of the third transistor, and the first electrode of the third transistor is connected to the active layer of the third transistor through the first via hole;
  • the second via hole exposes the active layer of the second transistor, The second electrode of the second transistor is connected to the active layer of the second transistor through the second via hole;
  • the third via hole exposes the active layer of the eighth transistor, and the second electrode of the eighth transistor is connected to the first transistor through the third via hole.
  • the active layers of the eight transistors are connected; the fourth via hole exposes the active layer of the seventh transistor, and the first electrode of the seventh transistor is connected to the active layer of the seventh transistor through the fourth via hole; the fifth via hole exposes the active layer of the seventh transistor.
  • the second electrode plate, the second electrode of the second transistor is connected with the second electrode plate through the fifth via hole; the sixth through hole exposes the first electrode plate, and the power connection line is connected with the first electrode plate through the sixth through hole;
  • the seventh via hole exposes the first pole of the third transistor, and the data signal line is connected to the first pole of the third transistor through the seventh via hole; the power supply connection line is exposed through the eighth via hole, and the first power supply line passes through the eighth via hole.
  • the hole is connected with the power connection line; the ninth via hole exposes the second pole of the eighth transistor, and the connection electrode is connected with the second pole of the eighth transistor through the ninth via hole; the tenth via hole exposes the connection electrode, and the light-emitting element passes through The tenth via hole is connected to the connection electrode.
  • the number of vias in the third insulating layer is small, which can reduce the space occupied by the pixel circuit, which is beneficial to realize the high resolution of the display device.
  • the light-emitting element includes: a first electrode, a second electrode and an organic light-emitting layer; the first electrode is located on the side of the organic light-emitting layer close to the substrate, and the second electrode is located on the side of the organic light-emitting layer away from the substrate .
  • the light-emitting structure layer includes: a pixel defining layer, a transparent conductive layer, an organic material layer and a conductive layer
  • the transparent conductive layer includes: a first electrode
  • the organic material layer includes: an organic light-emitting layer
  • the conductive layer includes : Second electrode.
  • the transistors used in the pixel circuit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the channel region uses semiconductor materials, such as polysilicon (such as low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the control electrode, the first electrode, the second electrode, etc.
  • semiconductor materials such as polysilicon (such as low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc.
  • IGZO indium gallium tin oxide
  • metal materials For example metal aluminum or aluminum alloy.
  • the first pole and the second pole of the transistor used here may be symmetrical in structure, so the first pole and the second pole of the transistor may be indistinguishable in structure.
  • the structure of the display device provided by an exemplary embodiment is described below through a manufacturing process of the display device.
  • the "patterning process” includes deposition of film layers, photoresist coating, mask exposure, development, etching and photoresist stripping processes.
  • Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can use any one or more of spray coating and spin coating
  • etching can use any one or more of dry etching and wet etching. one or more.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the “film” may also be referred to as a "layer”. If the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • each sub-pixel includes: a pixel circuit.
  • the pixel circuit includes first to ninth transistors T1 to T9 and a storage capacitor.
  • the storage capacitor includes: a first plate C1 and a second plate C2.
  • Forming an active layer on a substrate includes: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form an active layer.
  • the active layer includes the initial signal line Vinit, the active layer 11 of the first transistor, the active layer 21 of the second transistor, the active layer 31 of the third transistor, the active layer 41 of the fourth transistor, and the active layer of the fifth transistor.
  • the active layer 51 , the active layer 61 of the sixth transistor, the active layer 71 of the seventh transistor, the active layer 81 of the eighth transistor, and the active layer 91 of the ninth transistor are shown in FIG. 12 .
  • Forming the first metal layer includes: depositing a first insulating film on the substrate on which the active layer is formed, and patterning the first insulating film through a patterning process to form the first insulating layer.
  • a first metal film is deposited on the first insulating layer, and the first metal film is patterned through a patterning process to form a first metal layer.
  • the first metal layer includes: a scanning signal line Gate, a first reset line RST1, a second reset line RST3, a second electrode plate C2, a light-emitting control line EM, a third reset line RST4, the control electrode 12 of the first transistor, the second The gate 22 of the transistor, the gate 32 of the third transistor, the gate 42 of the fourth transistor, the gate 52 of the fifth transistor, the gate 62 of the sixth transistor, the gate 72 of the seventh transistor, the gate of the eighth transistor The gate 82 and the gate 92 of the ninth transistor are shown in FIG. 13 .
  • the first reset line RST1 , the scan signal line Gate, the first reset line RST1 , the light emission control line EM and the third reset line RST3 are arranged in parallel and extend in the first direction.
  • the first reset line RST1, the scanning signal line Gate and the first reset line RST1 are located on the first side of the second pole plate C2
  • the light-emitting control line EM and the third reset line RST3 are located on the second side of the second pole plate C2, the first The side and the second side are oppositely arranged.
  • the control electrode 12 of the first transistor is an integral structure connected to the first reset line RST1, and is disposed across the active layer 11 of the first transistor.
  • the control electrode 22 of the second transistor is an integral structure connected to the scanning signal line Gate, and is arranged across the active layer 21 of the second transistor.
  • the control electrode 32 of the third transistor is an integral structure connected to the scanning signal line Gate, and is arranged across the active layer 31 of the third transistor.
  • the control electrode 42 of the fourth transistor is an integral structure connected to the second reset line RST2, and is arranged across the active layer 41 of the fourth transistor.
  • the control electrode 52 of the fifth transistor is an integral structure connected to the second electrode plate C2, and is arranged across the active layer 51 of the fifth transistor.
  • the control electrode 62 of the sixth transistor is an integral structure connected to the second reset line RST2, and is arranged across the active layer 61 of the sixth transistor.
  • the control electrode 72 of the seventh transistor is an integral structure connected to the light-emitting control line EM, and is arranged across the active layer 71 of the seventh transistor.
  • the control electrode 82 of the eighth transistor is an integral structure connected to the light-emitting control line EM, and is arranged across the active layer 81 of the eighth transistor.
  • the control electrode 92 of the ninth transistor is an integral structure connected to the third reset line RST3, and is arranged across the active layer 91 of the ninth transistor.
  • this process further includes a conductorization process.
  • Conduction processing is to control the gate 12 of the first transistor, the gate 22 of the second transistor, the gate 32 of the third transistor, the gate 42 of the fourth transistor, and the fifth transistor after the formation of the first metal layer.
  • the electrode 52, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, the control electrode 82 of the eighth transistor, and the control electrode 92 of the ninth transistor are used as shielding to perform plasma treatment on the active layer, which is blocked by the first transistor.
  • the active layer in the region blocked by the control electrode 82 of the eighth transistor and the control electrode 92 of the ninth transistor is used as the channel region of the transistor, and the active layer in the region not blocked by the first metal layer is processed into a conductive layer to form Conductive source-drain regions and initial signal lines.
  • Forming the second metal layer includes: depositing a second insulating film on the substrate on which the first metal layer is formed, and patterning the second insulating film through a patterning process to form a second insulating layer.
  • a second metal thin film is deposited on the substrate on which the second insulating layer is formed, and the second metal thin film is patterned through a patterning process to form a second metal layer.
  • the second metal layer includes: a first electrode plate C1 , as shown in FIG. 14 .
  • the orthographic projection of the first plate C1 on the substrate at least partially overlaps the orthographic projection of the second plate C2 on the substrate.
  • the first electrode plate C1 is provided with a via hole, and the second electrode plate C2 is exposed through the through hole.
  • Forming the third insulating layer includes: depositing a third insulating film on the substrate on which the second metal layer is formed, and patterning the third insulating film through a patterning process to form the third insulating layer.
  • the third insulating layer is formed with a plurality of via holes.
  • the plurality of via holes include: a first via hole V1, a second via hole V2, a third via hole V3 and a fourth via hole V4 penetrating the first insulating layer, the second insulating layer and the third insulating layer, and penetrating the second insulating layer
  • the fifth via hole V5 of the layer and the third insulating layer and the sixth via hole V6 only penetrating the third insulating layer are shown in FIG. 15 .
  • the first via hole V1 exposes the active layer 31 of the third transistor.
  • the second via hole V2 exposes the active layer 21 of the second transistor.
  • the third via hole V3 exposes the active layer 81 of the eighth transistor.
  • the fourth via hole V4 exposes the active layer 71 of the seventh transistor.
  • the fifth via hole V5 exposes the second electrode plate C2.
  • the seventh via hole V7 exposes the first electrode plate C1.
  • Forming the third metal layer includes: depositing a third metal thin film on the substrate on which the third insulating layer is formed, and patterning the third metal thin film through a patterning process to form the third metal layer.
  • the third metal layer includes: the power supply connection line VL, the second pole 24 of the second transistor, the first pole 33 of the third transistor, the first pole 63 of the sixth transistor, the first pole 73 of the seventh transistor, and the eighth transistor The second pole 84 of the ninth transistor and the second pole 94 of the ninth transistor. As shown in Figure 16.
  • the second electrode 84 of the eighth transistor and the second electrode 94 of the ninth transistor are the same electrode, and the second electrode 24 of the second transistor and the first electrode 63 of the sixth transistor are the same electrode.
  • the active layer is also multiplexed into the first pole 13 of the first transistor, the second pole 14 of the first transistor, the first pole 23 of the second transistor, and the second pole of the third transistor 34.
  • the second pole 74 of the eighth transistor, the first pole 83 of the eighth transistor, and the first pole 93 of the ninth transistor is also multiplexed into the first pole 13 of the first transistor, the second pole 14 of the first transistor, the first pole 23 of the second transistor, and the second pole of the third transistor 34.
  • the power connection line VL extends along the first direction.
  • the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are the same electrode.
  • the second electrode 34 of the third transistor and the first electrode 43 of the fourth transistor are the same electrode.
  • the second electrode 44 of the fourth transistor, the first electrode 53 of the fifth transistor, and the second electrode 74 of the seventh transistor are the same electrode.
  • the second electrode 54 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 83 of the eighth transistor are the same electrode.
  • the second electrode 14 of the first transistor is connected to the active layer 11 of the first transistor through a first via hole.
  • the first electrode of the third transistor is connected to the active layer 21 of the third transistor through the second via hole V2.
  • the first electrode 53 of the sixth transistor is connected to the active layer 51 of the sixth transistor through the third via V3.
  • the second electrode 74 of the eighth transistor is connected to the active layer 71 of the eighth transistor through the fourth via hole V4.
  • the first electrode 63 of the seventh transistor is connected to the active layer 61 of the seventh transistor through the fifth via V5.
  • the first electrode 53 of the sixth transistor is connected to the second electrode plate C2 through the sixth via hole V6.
  • the power connection line VL is connected to the first plate C1 through the seventh via hole V7.
  • the first electrode 33 of the third transistor is connected to the active layer 31 of the third transistor through the first via V1.
  • the second electrode 24 of the second transistor is connected to the active layer 21 of the second transistor through the second via hole V2.
  • the second electrode 84 of the eighth transistor is connected to the active layer 81 of the eighth transistor through the third via hole V3.
  • the first electrode 73 of the seventh transistor is connected to the active layer 71 of the seventh transistor through the fourth via hole V4.
  • the second electrode 24 of the second transistor is connected to the second electrode plate C2 through the fifth via hole V5.
  • the power connection line VL is connected to the first plate C1 through the sixth via hole V6.
  • Forming the first flat layer includes: depositing a fourth insulating film on the substrate on which the third metal layer is formed, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer.
  • a first flat film is coated on the substrate on which the fourth insulating layer is formed, and a first flat layer is formed by masking, exposing and developing the flat film.
  • the fourth insulating film and the first flat layer are provided with seventh via holes V7, eighth via holes V8 and ninth via holes V9, as shown in FIG. 17 .
  • the seventh via hole V7 exposes the first electrode 23 of the third transistor.
  • the eighth via hole V8 exposes the power connection line VL.
  • the ninth via V9 exposes the second pole 84 of the eighth transistor.
  • Forming the fourth metal layer includes: depositing a fourth metal thin film on the substrate on which the first flat layer is formed, and patterning the fourth metal thin film through a patterning process to form the fourth metal layer.
  • the fourth metal layer includes: a first power supply line VDD, a data signal line Data and a pixel electrode 91, as shown in FIG. 18 .
  • the data signal line Data is connected 23 to the first electrode of the third transistor through the seventh via hole V7.
  • the first power supply line VDD is connected to the power supply connection line VL through the eighth via hole V8.
  • the connection electrode 101 is connected to the second electrode 84 of the eighth transistor through the ninth via hole V9. .
  • Forming the second flattening layer includes: coating a second flattening film on the substrate formed with the fourth metal layer, and forming the second flattening layer by masking, exposing and developing the flattening film.
  • An eleventh via hole V11 is provided on the second flat layer, as shown in FIG. 19 .
  • the tenth via hole V10 exposes the connection electrode 101, and the light emitting element is connected to the connection electrode 101 through the tenth via hole V10.
  • Forming the transparent conductive layer includes: depositing a first transparent conductive film on the substrate on which the second flat layer is formed, and patterning the first transparent conductive film through a patterning process to form a transparent conductive layer.
  • the transparent conductive layer includes a first electrode, the first electrode is formed in each light emitting element, and the first electrode is connected to the connection electrode 101 through the tenth via V10.
  • a pixel definition layer comprising: coating a pixel definition film on a substrate for forming a transparent conductive layer, forming a pixel definition layer (Pixel Define Layer) through a mask, exposure and development process, and the pixel definition layer is formed on each light-emitting In the element, the pixel definition layer in each light-emitting element is formed with an opening region exposing the first electrode.
  • a pixel definition layer Panel Define Layer
  • Forming the organic light-emitting layer includes: forming an organic light-emitting layer in the opening area of the formed pixel definition layer and on the pixel definition layer, and the organic light-emitting layer is electrically connected to the first electrode.
  • Forming the second electrode includes: coating a conductive thin film on the substrate on which the organic light-emitting layer is formed, and patterning the conductive thin film through a patterning process to form the second electrode.
  • the second electrode covers the organic light-emitting layer in each light-emitting element.
  • the second electrode is electrically connected to the organic light-emitting layer.
  • the first metal layer, the second metal layer, the third metal layer and the fourth metal layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum Any one or more of (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/ Cu/Mo and so on.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) Any one or more of these can be single layer, multi-layer or composite layer.
  • the first insulating layer is called the first gate insulating layer
  • the second insulating layer is called the second gate insulating layer
  • the third insulating layer is called the interlayer insulating layer
  • the fourth insulating layer is called the passivation layer.
  • the first flattening layer and the second flattening layer can be made of organic materials
  • the transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel definition layer may employ polyimide, acrylic, or polyethylene terephthalate.
  • the second electrode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or may Alloys made with any one or more of the above metals.
  • the active layer may be a metal oxide layer.
  • the metal oxide layer may employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin, Oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium or gallium and zinc, and the like.
  • the metal oxide layer may be a single layer, or it may be a double layer, or it may be multiple layers.
  • Embodiments of the present disclosure also provide a method for driving a display device, which is configured to drive the display device.
  • the driving method of the display device provided by the embodiment of the present disclosure includes:
  • Step S1 under the control of the first reset line and the scan signal line, the first reset sub-circuit provides the first node with a signal of the initial signal line.
  • Step S2 under the control of the third reset line, the second reset sub-circuit provides the signal of the initial signal line to the light-emitting element, and under the control of the scan signal line, the second reset line and the first node, the node control sub-circuit sends the signal to the second reset line.
  • the node provides the signal of the data signal line, and compensates to the first node through the second node and the third node, until the voltage of the first node satisfies the threshold condition.
  • Step S3 under the control of the light-emitting control line, the light-emitting control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the light-emitting element;
  • the third node provides the signal of the second node.
  • the display device is the display device provided by any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.

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Abstract

一种显示装置及其驱动方法，该装置包括：发光元件、像素电路、扫描信号线、数据信号线、初始信号线、发光控制线、第一电源线、第一复位线至第三复位线；像素电路包括：第一复位子电路设置为向第一节点提供初始信号线的信号；节点控制子电路设置为向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；在第一节点的控制下，向第三节点提供第二节点的信号；发光控制子电路设置为向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；第二复位子电路设置为向发光元件提供初始信号线的信号；位于第i行的像素电路连接的第三复位线与位于第i+1行的像素电路连接的第一复位线连接。

Description

一种显示装置及其驱动方法 技术领域
本公开涉及但不限于显示技术领域，特别涉及一种显示装置及其驱动方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)是当今显示器研究领域的热点之一。与液晶显示器(Liquid Crystal Display，简称LCD)相比，有机发光二极管OLED具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，已广泛应用于手机、平板电脑、数码相机等显示领域中。
与LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，通过稳定的电流来控制OLED发光。像素电路作为OLED显示产品的核心技术，设置为向OLED输出驱动电路，以驱动OLED发光。
发明概述
以下是对本申请详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示装置，包括：矩阵排布的发光元件、矩阵排布的像素电路、扫描信号线、数据信号线、初始信号线、发光控制线、第一电源线、第一复位线、第二复位线和第三复位线；
所述像素电路与所述发光元件一一对应；所述像素电路设置为驱动对应的发光元件发光；所述像素电路包括：第一复位子电路、节点控制子电路、发光控制子电路和第二复位子电路；
所述第一复位子电路，分别与第一复位线、扫描信号线、初始信号线和第一节点连接，设置为在第一复位线和扫描信号线的控制下，向第一节点提供初始信号线的信号；
所述节点控制子电路，分别与扫描信号线、第二复位线、数据信号线、 第一节点、第二节点、第三节点和第一电源线连接，设置为在扫描信号线、第二复位线和第一节点控制下，向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；在第一节点的控制下，向第三节点提供第二节点的信号；
所述发光控制子电路，分别与发光控制线、第一电源线、第二节点、第三节点和发光元件连接，设置为在发光控制线的控制下，向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；
所述第二复位子电路，分别与第三复位线、初始信号线和发光元件连接，设置为在第三复位线的控制下，向发光元件提供初始信号线的信号；
位于第i行的像素电路连接的第三复位线与位于第i+1行的像素电路连接的第一复位线电连接，1≤i<M，M为像素电路的总行数。
在一些可能的实现方式中，所述显示装置包括：基底以及依次设置在所述基底上的驱动结构层和发光结构层；
所述驱动结构层包括：像素电路、扫描信号线、数据信号线、初始信号线、发光控制线、第一电源线、第一复位线、第二复位线和第三复位线，所述发光结构层包括：发光元件；
所述扫描信号线、所述初始信号线、所述发光控制线、所述第一复位线、所述第二复位线和所述第三复位线沿第一方向延伸，所述数据信号线与所述第一电源线沿第二方向延伸；
所述第一方向与所述第二方向相交。
在一些可能的实现方式中，每个像素电路包括：存储电容，所述存储电容包括：第一极板和第二极板；所述第一极板与第一电源线连接，所述第二极板与第一节点连接；
所述第一极板在基底上的正投影与所述第二极板在基底上的正投影部分重叠；所述第一极板设置有过孔，所述第一极板的过孔暴露出所述第二极板；
所述扫描信号线、所述第一复位线和所述第二复位线位于所述第二极板的一侧，所述发光控制线和所述第三复位线位于所述第二极板远离所述第一复位线的一侧；
所述第一复位线位于所述扫描信号线远离第二极板的一侧，所述第二复位线位于所述扫描信号线靠近所述第二极板的一侧；所述第三复位线位于所述发光控制线远离第二极板的一侧；
所述初始信号线包括：第一初始信号线和第二初始信号线；所述第一初始信号线与所述第一复位线位于第二极板的同一侧，且位于所述第一复位线远离第二极板的一侧；所述第二初始信号线与所述第三复位线位于所述第二极板的同一侧，且位于所述第三复位线远离第二极板的一侧。
在一些可能的实现方式中，所述驱动结构层还包括：电源连接线和连接电极；
所述电源连接线与所述第一电源线异层设置，且与所述第一电源线连接，所述第一极板通过电源连接线与所述第一电源线连接；
所述电源连接线在基底上的正投影与所述第一极板在基底上的正投影至少部分重叠，且与所述第一电源线在基底上的正投影至少部分重叠；
所述连接电极设置为连接像素电路和发光元件。
在一些可能的实现方式中，所述节点控制子电路包括：写入子电路、驱动子电路、补偿子电路和储能子电路；
所述写入子电路，分别与扫描信号线、第二复位线、数据信号线和第二节点连接，设置为在扫描信号线和第二复位线的控制下，向第二节点提供数据信号线的信号，或者向第二节点放电；
所述驱动子电路，分别与第一节点、第二节点和第三节点连接，设置为在第一节点的控制下，向第三节点提供第二节点的信号；
所述补偿子电路，分别与第一节点、第二复位线和第三节点连接，设置为在第二复位线的控制下，向第一节点提供第三节点的电位，以对第一节点进行补偿，直至第一节点的电压满足阈值条件；
所述储能子电路，分别与第一电源线和第一节点连接，设置为存储第一电源线与第一节点之间的电压差。
在一些可能的实现方式中，所述第一复位子电路包括：第一晶体管和第二晶体管；
所述第一晶体管的控制极与第一复位线连接，所述第一晶体管的第一极与初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
所述第二晶体管的控制极与扫描信号端连接，所述第二晶体管的第二极与第一节点连接。
在一些可能的实现方式中，所述写入子电路包括：第三晶体管和第四晶体管；
所述第三晶体管的控制极与扫描信号线连接，所述第三晶体管的第一极与数据信号线连接，所述第三晶体管的第二极与所述第四晶体管的第一极连接；
所述第四晶体管的控制极与第二复位线连接，所述第四晶体管的第二极与第二节点连接；
所述第四晶体管的沟道区域的长度大于阈值长度，所述第四晶体管的沟道区域的宽度大于阈值宽度。
在一些可能的实现方式中，所述驱动子电路包括：第五晶体管，所述第五晶体管为驱动晶体管；所述储能子电路包括：存储电容；
所述第五晶体管的控制极与第一节点连接，所述第五晶体管的第一极与第二节点连接，所述第五晶体管的第二极与第三节点连接；
所述存储电容的第一端与第一电源线连接，所述存储电容的第二端与第一节点连接。
在一些可能的实现方式中，所述补偿子电路包括：第六晶体管；
所述第六晶体管的控制极与第二复位线连接，所述第六晶体管的第一极与第一节点连接，所述第六晶体管的第二极与第三节点连接。
在一些可能的实现方式中，所述发光控制子电路包括：第七晶体管和第八晶体管；
所述第七晶体管的控制极与发光控制线连接，所述第七晶体管的第一极与第一电源线连接，所述第七晶体管的第二极与第二节点连接；
所述第八晶体管的控制极与发光控制线连接，所述第八晶体管的第一极与第三节点连接，所述第八晶体管的第二极与发光元件连接。
在一些可能的实现方式中，所述第二复位子电路包括：第九晶体管；
所述第九晶体管的控制极与第三复位线连接，所述第九晶体管的第一极与初始信号线连接，所述第九晶体管的第二极与发光元件连接。
在一些可能的实现方式中，所述第一复位子电路包括：第一晶体管和第二晶体管；所述节点控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和存储电容，所述第五晶体管为驱动晶体管；所述发光控制子电路包括：第七晶体管和第八晶体管；所述第二复位子电路包括：第九晶体管；
所述第一晶体管的控制极与第一复位线连接，所述第一晶体管的第一极与初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
所述第二晶体管的控制极与扫描信号端连接，所述第二晶体管的第二极与第一节点连接；
所述第三晶体管的控制极与扫描信号线连接，所述第三晶体管的第一极与数据信号线连接，所述第三晶体管的第二极与所述第四晶体管的第一极连接；
所述第四晶体管的控制极与第二复位线连接，所述第四晶体管的第二极与第二节点连接；
所述第五晶体管的控制极与第一节点连接，所述第五晶体管的第一极与第二节点连接，所述第五晶体管的第二极与第三节点连接；
所述第六晶体管的控制极与第二复位线连接，所述第六晶体管的第一极与第一节点连接，所述第六晶体管的第二极与第三节点连接；
所述存储电容的第一端与第一电源线连接，所述存储电容的第二端与第一节点连接；
所述第七晶体管的控制极与发光控制线连接，所述第七晶体管的第一极与第一电源线连接，所述第七晶体管的第二极与第二节点连接；
所述第八晶体管的控制极与发光控制线连接，所述第八晶体管的第一极与第三节点连接，所述第八晶体管的第二极与发光元件连接；
所述第九晶体管的控制极与第三复位线连接，所述第九晶体管的第一极与初始信号线连接，所述第九晶体管的第二极与发光元件连接。
在一些可能的实现方式中，所述发光元件包括：有机发光二极管；
所述有机发光二极管的阳极分别与第八晶体管的第二极和第九晶体管的第二极连接，所述有机发光二极管的阴极与第二电源线连接。
在一些可能的实现方式中，所述阈值条件为所述第一节点的电压等于所述数据信号线的信号的电压与第五晶体管的阈值电压的绝对值之差。
在一些可能的实现方式中，所述扫描信号线和所述第三复位线电连接。
在一些可能的实现方式中，对于第一晶体管至第九晶体管，每个晶体管包括：有源层、控制极、第一极和第二极；
所述驱动结构层包括：沿垂直于所述基底方向依次设置的有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层、第一平坦层、第四金属层和第二平坦层；
所述有源层包括：初始信号线和所有晶体管的有源层；所述第一金属层包括：扫描信号线、第一复位线、第二复位线、第二极板、发光控制线、第三复位线和所有晶体管的控制极；所述第二金属层包括：第一极板；所述第三金属层包括：电源连接线以及部分晶体管的第一极或第二极；所述第四金属层包括：第一电源线、数据信号线和像素电极。
在一些可能的实现方式中，所述第一晶体管的控制极、所述第二晶体管的控制极、所述第三晶体管的控制极、所述第四晶体管的控制极和所述第六晶体管的控制极位于第二极板的第一侧，所述第七晶体管的控制极、所述第八晶体管的控制极和所述第九晶体管的控制极位于第二极板的第二侧，所述第一侧和所述第二侧相对设置；
所述第二晶体管的控制极位于所述第一晶体管的控制极靠近第二极板的一侧；所述第二晶体管的控制极和所述第三晶体管的控制极为一体成型结构；所述第四晶体管的控制极位于第二晶体管的控制极靠近第二极板的一侧；所 述第四晶体管的控制极和所述第六晶体管的控制极为一体成型结构；所述第二极板与所述第五晶体管的控制极为一体成型结构；所述第七晶体管的控制极和所述第八晶体管的控制极为一体成型结构，所述第九晶体管的控制极位于所述第七晶体管的控制极远离第二极板的一侧。
在一些可能的实现方式中，所述第一绝缘层、所述第二绝缘层和所述第三绝缘层上设置有第一过孔、第二过孔、第三过孔和第四过孔；所述第二绝缘层和所述第三绝缘层上设置有第五过孔；所述第三绝缘层上设置有第六过孔；所述第四绝缘层和所述第一平坦层上设置有第七过孔、第八过孔和第九过孔；所述第二平坦层包括：第十过孔；
所述第一过孔暴露出第三晶体管的有源层，所述第三晶体管的第一极通过第一过孔与所述第三晶体管的有源层连接；所述第二过孔暴露出第二晶体管的有源层，所述第二晶体管的第二极通过第二过孔与第二晶体管的有源层连接；所述第三过孔暴露出第八晶体管的有源层，所述第八晶体管的第二极通过第三过孔与第八晶体管的有源层连接；所述第四过孔暴露出第七晶体管的有源层，所述第七晶体管的第一极通过第四过孔与第七晶体管的有源层连接；所述第五过孔暴露出所述第二极板，所述第二晶体管的第二极通过第五过孔与第二极板连接；所述第六过孔暴露出所述第一极板，所述电源连接线通过第六过孔与第一极板连接；所述第七过孔暴露出第三晶体管的第一极，所述数据信号线通过第七过孔与第三晶体管的第一极连接；所述第八过孔暴露出电源连接线，所述第一电源线通过第八过孔与所述电源连接线连接；所述第九过孔暴露出第八晶体管的第二极，所述连接电极通过第九过孔与第八晶体管的第二极连接；所述第十过孔暴露出连接电极，所述发光元件通过第十过孔与连接电极连接。
在一些可能的实现方式中，所述发光元件包括：第一电极、第二电极和有机发光层；所述第一电极位于所述有机发光层靠近基底的一侧，所述第二电极位于所述有机发光层远离基底的一侧；
所述发光结构层包括：像素界定层、透明导电层、有机材料层和导电层，所述透明导电层包括：第一电极，所述有机材料层包括：有机发光层；所述导电层包括：第二电极。
第二方面，本公开还提供了一种显示装置的驱动方法，设置为驱动上述显示装置，所述方法包括：
在第一复位线和扫描信号线的控制下，第一复位子电路向第一节点提供初始信号线的信号；
在第三复位线的控制下，第二复位子电路向发光元件提供初始信号线的信号，在扫描信号线、第二复位线和第一节点控制下，节点控制子电路向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；
在发光控制线的控制下，发光控制子电路向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；在第一节点的控制下，节点控制子电路向第三节点提供第二节点的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的像素电路的结构示意图；
图2为一种示例性实施例提供的像素电路的结构示意图；
图3为一种示例性实施例提供的第一复位子电路的等效电路图；
图4为一种示例性实施例提供的节点控制子电路的等效电路图；
图5为一种示例性实施例提供的发光控制子电路的等效电路图；
图6为一种示例性实施例提供的第二复位子电路的等效电路图；
图7为一种示例性实施例提供的像素电路的等效电路图；
图8为一种示例性实施例提供的像素电路的工作时序图；
图9A为一种示例性实施例提供的像素电路在第一阶段的等效电路图；
图9B为一种示例性实施例提供的像素电路在第二阶段的等效电路图；
图9C为一种示例性实施例提供的像素电路在第三阶段的等效电路图；
图9D为一种示例性实施例提供的像素电路在第四阶段的等效电路图；
图9E为一种示例性实施例提供的像素电路在第五阶段的等效电路图；
图9F为一种示例性实施例提供的像素电路在第六阶段的等效电路图；
图10为本公开实施例提供的显示装置的结构示意图；
图11为本公开实施例提供的显示装置的部分俯视图；
图12为形成有源层的示意图；
图13为形成第一金属层的示意图；
图14为形成第二金属层的示意图；
图15为形成第三绝缘层的示意图；
图16为形成第三金属层的示意图；
图17为形成第一平坦层的示意图；
图18为形成第四金属层的示意图；
图19为形成第二平坦层的示意图。
详述
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术 方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。此外，晶体管包括：P型晶体管或N型晶体管两种，其中，P型晶体管在栅极为低电平导通，在栅极为高电平时截止，N型晶体管在栅极为高电平时导通，在栅极为低电平时截止。
随着OLED显示技术的成熟，人们对于高频OLED显示产品的需求越来越迫切。针对高频OLED显示产品，一种像素电路中包括驱动晶体管和存储电容，由于像素电路中的扫描信号保持有效电平的时间较短，导致存储电容存储的电荷量不足，对驱动晶体管的阈值电压补偿不充分，使得OLED显示产品显示不均，降低了OLED显示产品的显示效果。
图1为本公开实施例提供的像素电路的结构示意图。如图1所示，本公 开实施例提供的像素电路设置为驱动发光元件发光，像素电路包括：第一复位子电路、节点控制子电路、发光控制子电路和第二复位子电路。
第一复位子电路，分别与第一复位线RST1、扫描信号线Gate、初始信号线Vinit和第一节点N1连接，设置为在第一复位线RST1和扫描信号线Gate的控制下，向第一节点N1提供初始信号线Vinit的信号。节点控制子电路，分别与扫描信号线Gate、第二复位线RST2、数据信号线Data、第一节点N1、第二节点N2、第三节点N3和第一电源线VDD连接，设置为在扫描信号线Gate、第二复位线RST2和第一节点N1控制下，向第二节点N2提供数据信号线Data的信号，并通过第二节点N2和第三节点N3向第一节点N1进行补偿，直至第一节点N1的电压满足阈值条件，在第一节点N1的控制下，向第三节点N3提供第二节点N2的信号。发光控制子电路，分别与发光控制线EM、第一电源线VDD、第二节点N2、第三节点N3和发光元件连接，设置为在发光控制线EM的控制下，向第二节点N2提供第一电源线VDD的信号，向发光元件提供第三节点N3的信号。第二复位子电路，分别与第三复位线RST3、初始信号线Vinit和发光元件连接，设置为在第三复位线RST3的控制下，向发光元件提供初始信号线Vinit的信号。发光元件，与第二电源线VSS连接。
在一种示例性实施例中，第一复位线RST1、第二复位线RST2、第三复位线RST3、扫描信号线Gate和发光控制线EM的信号可以为脉冲信号。
在一种示例性实施例中，第一电源端VDD可以持续提供高电平信号。第二电源线VSS和初始信号线Vinit可以持续提供低电平信号。
在一种示例性实施例中，初始信号线Vinit的信号可以为电压值为0V的信号。
在一种示例性实施例中，第二电源线VSS的信号电压值和初始信号线Vinit的信号的电压值可以相同，或者可以不同。
在一种示例性实施例中，初始信号线Vinit的信号可以为发光元件和第一节点进行复位。
在一种示例性实施例中，发光元件可以为有机发光二极管OLED。有机发光二极管OLED的阳极与发光控制子电路连接，阴极与第二电源端VSS 连接。
本公开实施例提供的像素电路设置为驱动发光元件发光，像素电路包括：第一复位子电路、节点控制子电路、发光控制子电路和第二复位子电路；第一复位子电路，分别与第一复位线、扫描信号线、初始信号线和第一节点连接，设置为在第一复位线和扫描信号线的控制下，向第一节点提供初始信号线的信号；节点控制子电路，分别与扫描信号线、第二复位线、数据信号线、第一节点、第二节点、第三节点和第一电源线连接，设置为在扫描信号线、第二复位线和第一节点控制下，向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；在第一节点的控制下，向第三节点提供第二节点的信号；发光控制子电路，分别与发光控制线、第一电源线、第二节点、第三节点和发光元件连接，设置为在发光控制线的控制下，向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；第二复位子电路，分别与第三复位线、初始信号线和发光元件连接，设置为在第三复位线的控制下，向发光元件提供初始信号线的信号；发光元件，与第二电源线连接。本公开中的节点控制子电路通过扫描信号线和第二复位线同时控制对第一节点进行补偿，可以使得在数据信号端的信号写入之后，发光元件发光之前，对第一节点进行持续补偿，直至第一节点满足阈值条件，增强了补偿效果，提升了显示产品的显示效果。
图2为一种示例性实施例提供的像素电路的结构示意图。如图2所示，一种示例性实施例提供的像素电路中的节点控制子电路包括：写入子电路、驱动子电路、补偿子电路和储能子电路。
写入子电路，分别与扫描信号线Gate、第二复位线RST2、数据信号线Data和第二节点N2连接，设置为在扫描信号线Gate和第二复位线RST2的控制下，向第二节点N2提供数据信号线Data的信号，在第二复位线RST2的控制下，向第二节点N2放电。驱动子电路，分别与第一节点N1、第二节点N2和第三节点N3连接，设置为在第一节点N1的控制下，向第三节点N3提供第二节点N2的信号。补偿子电路，分别与第一节点N1、第二复位线RST2和第三节点N3连接，设置为在第二复位线RST2的控制下，向第一节点N1提供第三节点N3的电位，以对第一节点N1进行补偿，直至第一节 点N1的电压满足阈值条件。储能子电路，分别与第一电源线VDD和第一节点N1连接，设置为存储第一电源线VDD与第一节点N1之间的电压差。
图2示出了节点控制子电路的一种示例性结构，该子电路的实现方式并不限于此。
图3为一种示例性实施例提供的第一复位子电路的等效电路图。如图3所示，在一种示例性实施例中，第一复位子电路包括：第一晶体管T1和第二晶体管T2。第一晶体管T1和第二晶体管T2为开关晶体管。
第一晶体管T1的控制极与第一复位线RST1连接，第一晶体管T1的第一极与初始信号线Vinit连接，第一晶体管T1的第二极与第二晶体管T2的第一极连接。第二晶体管T2的控制极与扫描信号端Gate连接，第二晶体管T2的第二极与第一节点N1连接
图3示出了第一复位子电路的一种示例性结构，该子电路的实现方式并不限于此。
图4为一种示例性实施例提供的节点控制子电路的等效电路图。如图4所示，在一种示例性实施例中节点控制子电路中的写入子电路包括：第三晶体管T3和第四晶体管T4。驱动子电路包括：第五晶体管T5，第五晶体管T5为驱动晶体管。储能子电路包括：存储电容Cst。补偿子电路包括：第六晶体管T6。第三晶体管T3、第四晶体管T4和第六晶体管T6为开关晶体管。
第三晶体管T3的控制极与扫描信号线Gate连接，第三晶体管T3的第一极与数据信号线Data连接，第三晶体管T3的第二极与第四晶体管T4的第一极连接。第四晶体管T4的控制极与第二复位线RST2连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5的控制极与第一节点N1连接，第五晶体管T5的第一极与第二节点N2连接，第五晶体管T5的第二极与第三节点N3连接。第六晶体管T6的控制极与第二复位线RST2连接，第六晶体管T6的第一极与第一节点N1连接，第六晶体管T6的第二极与第三节点N3连接。存储电容Cst的第一端与第一电源线VDD连接，存储电容Cst的第二端与第一节点N1连接。
在一种示例性实施例中，第四晶体管T4的沟道区域的长度大于阈值长度，第四晶体管T4的沟道区域的宽度大于阈值宽度。当第四晶体管T4导通 后，第四晶体管T4的沟道区域导电，第四晶体管T4的沟道区域与控制极之间形成了电容，由于第四晶体管T4的沟道区域的长度大于阈值长度，第四晶体管T4的沟道区域的宽度大于阈值宽度，使得第四晶体管T4的沟道区域与控制极之间所形成的电容的电容值较大。此时，第四晶体管T4导通时，相当于电容，可以进行充电或放电操作。
在一种示例性实施例中，阈值长度为第二晶体管、第四晶体管和第五晶体管的导电沟道长度的最大值，阈值宽度为第二晶体管、第四晶体管和第五晶体管的导电沟道宽度的最大值。
在一种示例性实施例中，驱动晶体管可以为增强型晶体管，或者可以为耗尽型晶体管。
在一种示例性实施例中，设置的第一电源线VDD和第二电源线VSS的信号可以使得驱动晶体管在导通时处于饱和状态。
图4具体示出了节点控制子电路的示例性结构，该子电路的实现方式并不限于此。
图5为一种示例性实施例提供的发光控制子电路的等效电路图。如图5所示，一种示例性实施例中，发光控制子电路包括：第七晶体管T7和第八晶体管T8。第七晶体管T7和第八晶体管T8为开关晶体管。
第七晶体管T7的控制极与发光控制线EM连接，第七晶体管T7的第一极与第一电源线VDD连接，第七晶体管T7的第二极与第二节点N2连接。第八晶体管T8的控制极与发光控制线EM连接，第八晶体管T8的第一极与第三节点N3连接，第八晶体管T8的第二极与发光元件连接。
图5示出了发光控制子电路的一种示例性结构，该子电路的实现方式并不限于此。
图6为一种示例性实施例提供的第二复位子电路的等效电路图。如图6所示，一种示例性实施例中，第二复位子电路包括：第九晶体管T9。第九晶体管T9为开关晶体管。
第九晶体管T9的控制极与第三复位线RST3连接，第九晶体管T9的第一极与初始信号线Vinit连接，第九晶体管T9的第二极与发光元件连接。
在一种示例性实施例中，设置第二复位子电路可以消除发光元件中的界面电荷，可以提升显示产品的显示效果。
图6示出了第二复位子电路的一种示例性结构，该子电路的实现方式并不限于此。
图7为一种示例性实施例提供的像素电路的等效电路图。如图7所示，在一种示例性实施例中，第一复位子电路包括：第一晶体管T1和第二晶体管T2；节点控制子电路包括：第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和存储电容Cst，第五晶体管T5为驱动晶体管；发光控制子电路包括：第七晶体管T7和第八晶体管T8；第二复位子电路包括：第九晶体管T9。
第一晶体管T1的控制极与第一复位线RST1连接，第一晶体管T1的第一极与初始信号线Vinit连接，第一晶体管T1的第二极与第二晶体管T2的第一极连接。第二晶体管T2的控制极与扫描信号端Gate连接，第二晶体管T2的第二极与第一节点N1连接。第三晶体管T3的控制极与扫描信号线Gate连接，第三晶体管T3的第一极与数据信号线Data连接，第三晶体管T3的第二极与第四晶体管T4的第一极连接。第四晶体管T4的控制极与第二复位线RST2连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5的控制极与第一节点N1连接，第五晶体管T5的第一极与第二节点N2连接，第五晶体管T5的第二极与第三节点N3连接。第六晶体管T6的控制极与第二复位线RST2连接，第六晶体管T6的第一极与第一节点N1连接，第六晶体管T6的第二极与第三节点N3连接。存储电容Cst的第一端与第一电源线VDD连接，存储电容Cst的第二端与第一节点N1连接。第七晶体管T7的控制极与发光控制线EM连接，第七晶体管T7的第一极与第一电源线VDD连接，第七晶体管T7的第二极与第二节点N2连接。第八晶体管T8的控制极与发光控制线EM连接，第八晶体管T8的第一极与第三节点N3连接，第八晶体管T8的第二极与发光元件连接。第九晶体管T9的控制极与第三复位线RST3连接，第九晶体管T9的第一极与初始信号线Vinit连接，第九晶体管T9的第二极与发光元件连接。
在一种示例性实施例中，有机发光二极管OLED的阳极分别与第八晶体 管T8的第二极和第九晶体管T9的第二极连接，有机发光二极管OLED的阴极与第二电源线VSS连接。
在一种示例性实施例中，晶体管T1至T9均可以为N型薄膜晶体管或P型薄膜晶体管。晶体管T1至T9的类型可以相同，或者可以不同。当晶体管T1至T9的类型相同时，可以统一工艺流程，减少工艺制程，有助于提高产品的良率。
在一种示例性实施例中，晶体管T1至T9可以为低温多晶硅薄膜晶体管。低温多晶硅薄膜晶体管可以减少像素电路中的漏电极，提升像素电路的性能。
在一种示例性实施例中，晶体管T1至T9可以为底栅结构，或者可以为顶栅结构。
在一种示例性实施例中，阈值条件为第一节点N1的电压等于数据信号线Data的信号的电压与第五晶体管T5的阈值电压的绝对值之差，可以使得流向发光元件的驱动电流与驱动晶体管的阈值电压无关，保证了显示产品的均一性。
在一种示例性实施例中，扫描信号线Gate和第三复位线RST可以为不同信号线，或者可以为同一信号线。当扫描信号线和第三复位线为同一信号线时，可以减少像素电路中的信号线的数量，减少像素电路所占用的面积。
下面通过像素电路的工作过程说明一种示例性实施例提供的像素电路。
以像素电路中的晶体管T1至T9均为P型晶体管为例，图8为一种示例性实施例提供的像素电路的工作时序图，图9A为一种示例性实施例提供的像素电路在第一阶段的等效电路图；图9B为一种示例性实施例提供的像素电路在第二阶段的等效电路图；图9C为一种示例性实施例提供的像素电路在第三阶段的等效电路图；图9D为一种示例性实施例提供的像素电路在第四阶段的等效电路图；图9E为一种示例性实施例提供的像素电路在第五阶段的等效电路图；图9F为一种示例性实施例提供的像素电路在第六阶段的等效电路图。如图7至9所示，一种示例性实施例所涉及的像素电路包括：8个开关晶体管(T1、T2、T3、T4、T6、T7、T8和T9)，1个驱动晶体管(T5)、1个电容单元(Cst)，6个输入信号线(Gate、RST1、RST2、RST3、EM和Data)和3个电源端(VDD、VSS和Vinit)。
第一电源线VDD持续提供高电平信号，第二电源端VSS和初始信号线Vinit持续提供低电平信号。
一种示例性实施例提供的像素电路包括：第一阶段S1至第六阶段S6。
第一阶段S1，准备阶段，如图9A所示，第一复位线RST1的输入信号为低电平，第一晶体管T1导通。扫描信号线Gate的输入信号为高电平，第二晶体管T2和第三晶体管T3截止。第二复位线RST2的输入信号为高电平，第四晶体管T4和第六晶体管T6截止。发光控制线EM的输入信号为高电平，第七晶体管T7和第八晶体管T8截止。第三复位线RST3的输入信号为高电平，第九晶体管T9截止。由于第一晶体管T1导通，第二晶体管T2截止，第一节点N1无法被重置。第一阶段S1为第二阶段S2的准备阶段。
第二阶段S2，重置阶段，如图9B所示，第一复位线RST1的输入信号为低电平，第一晶体管T1导通。扫描信号线Gate的输入信号为低电平，第二晶体管T2和第三晶体管T3导通。由于第一晶体管T1和第二晶体管T2导通，初始信号线Vinit向第一节点N1提供初始信号，以对第一节点N1开始充电，此时，存储电容Cst开始充电，以为第三阶段的数据信号的写入做准备。由于第一节点N1的电压值与第二节点N2的电压值的差值大于第五晶体管的阈值电压，第五晶体管T5导通。第三复位线RST3的输入信号为低电平，第九晶体管T9导通，初始信号线Vinit向有机发光二极管OLED的阳极提供初始信号好，以对有机发光二极管OLED的阳极进行初始化。第二复位线RST2的输入信号为高电平，第四晶体管T4和第六晶体管T6截止。发光控制线EM的输入信号为高电平，第七晶体管T7和第八晶体管T8截止。
第三阶段S3，写入补偿阶段，如图9C所示，扫描信号线Gate的输入信号为低电平，第二晶体管T2和第三晶体管T3导通。第二复位线RST2的输入信号为低电平，第四晶体管T4和第六晶体管T6导通。由于第三晶体管T3和第四晶体管T4导通，数据信号线Data的输入信号写入第二节点N2。当第四晶体管T4导通时，第四晶体管T4相当于电容Cm，数据信号线Data的输入信号通过第三晶体管T3向电容Cm充电，数据信号线Data的输入信号通过第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6向存储电容Cst充电，以对第一节点N1进行补偿。随着充电时间的延长，第 二节点N2的电压值很快就等于数据信号线Data的输入信号的电压值Vdata，此时，电容Cm两端的电压差为V2-Vdata，其中，V2为第二复位线RST2在第三阶段的电压值。由于数据信号线Data的输入信号向存储电容Cst充电经过第五晶体管T5，随着第一节点N1的电压值的上升，流经第五晶体管T5的电流越来越小，第一节点N1的电压值的上升也越来越缓慢。由于高频显示产品的每行开启时间较少，即扫描信号线Gate的输入信号为低电平的时间较短，因此，在第三阶段S3结束时，第一节点N1的电压值小于Vdata-|Vth|，其中，Vth为第五晶体管T5的阈值电压，扫描信号线Gate的输入信号会切换为高电平，第三晶体管T3截止，数据信号线Data的输入信号写入结束。第三复位线RST3的输入信号为低电平，第九晶体管T9导通，向有机发光二极管OLED的阳极提供初始信号线Vinit的输入信号，以对有机发光二极管的阳极进行初始化。第一复位线RST1的输入信号为高电平，第一晶体管T1截止，发光控制线EM的输入信号为高电平，第七晶体管T7和第八晶体管T8截止。
第四阶段S4，补偿阶段，如图9D所示，扫描信号线Gate的输入信号为高电平，第二晶体管T2和第三晶体管T3截止，第二复位线RST3的输入信号为低电平，第四晶体管T4和第六晶体管T6导通。虽然第三晶体管T3截止，没有信号继续对存储电容Cst进行信号写入，但是第三阶段中电容Cm的一端写入了数据信号线Data的输入信号，此时，电容Cm开始放电，通过第五晶体管T5和第六晶体管T6继续向存储电容Cst进行充电，以对第一节点N1进行补偿，第一节点N1的电压值继续上升，直到第五晶体管T5截止，此时，第一节点N1的电压值满足阈值条件，即第一节点N1的电压值等于Vdata-|Vth|。由于在该阶段中，第一节点N1的电压值上升较小，消耗电容Cm的电荷有限，因此，电容Cm可以近似为恒压源。第一复位线RST1的输入信号为高电平，第一晶体管T1截止。发光控制线EM的输入信号为高电平，第七晶体管T7和第八晶体管T8截止。第三复位线RST4的输入信号为高电平，第九晶体管T9截止。
第五阶段S5，缓冲阶段，如图9E所示，第一复位线RST1的输入信号为高电平，第一晶体管T1截止。扫描信号线Gate的输入信号为高电平，第 二晶体管T2和第三晶体管T3截止。第二复位线RST2的输入信号为高电平，第四晶体管T4和第六晶体管T6截止。发光控制线EM的输入信号为高电平，第七晶体管T7和第八晶体管T8截止。第三复位线RST3的输入信号为高电平，第九晶体管T9截止。在该阶段中，第一节点N1的电压值保持不变。
在一种示例性实施例中，第五阶段S5的长短取决于发光控制线EM的输入信号的下降沿发生的时刻。
第六阶段S6，发光阶段，如图9F所示，发光控制线EM的输入信号为低电平，第七晶体管T7和第八晶体管T8导通，存储电容Cst开始放电，第五晶体管T5导通，第五晶体管T5输出驱动电流，以驱动有机发光二极管OLED发光。第一复位线RST1的输入信号为高电平，第一晶体管T1截止。扫描信号线Gate的输入信号为高电平，第二晶体管T2和第三晶体管T3截止。第二复位线RST2的输入信号为高电平，第四晶体管T4和第六晶体管T6截止。第三复位线RST3的输入信号为高电平，第九晶体管T9截止。
驱动电流I OLED满足如下公式：
IOLED＝K(Vsg-|Vth|) 2＝K(Vdd-(Vdata-|Vth|)-|Vth|) 2＝K(Vdd-Vdata) 2
其中，Vsg为第五晶体管的源电极与栅电极之间的电压差，Vdd为第一电源线的信号的电压值，K为与第五晶体管T5的工艺参数和几何尺寸有关的固定常数。
由上述电流公式的推导结果可以看出，在发光阶段，第五晶体管T5输出的驱动电流已经不受第五晶体管T5的阈值电压的影响，只与数据信号线的信号有关，从而消除了第五晶体管T5的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
本公开实施例还提供一种显示装置，图10为本公开实施例提供的显示装置的结构示意图，图11为本公开实施例提供的显示装置的部分俯视图。如图10和11所示，本公开实施例提供的显示装置包括：矩阵排布的发光元件10、矩阵排布的像素电路20、扫描信号线Gate、数据信号线Data、初始信号线Vinit、发光控制线EM、第一电源线VDD、第一复位线RST1、第二复位线RST2和第三复位线RST3。位于第i行的像素电路连接的第三复位线与位于第i+1行的像素电路连接的第一复位线电连接，1≤i<M，M为像素电路的总 行数。
像素电路20为前述任一个实施例提供的像素电路。像素电路与发光元件一一对应；像素电路设置为驱动对应的发光元件发光。
像素电路包括：第一复位子电路、节点控制子电路、发光控制子电路和第二复位子电路。第一复位子电路，分别与第一复位线、扫描信号线、初始信号线和第一节点连接，设置为在第一复位线和扫描信号线的控制下，向第一节点提供初始信号线的信号；节点控制子电路，分别与扫描信号线、第二复位线、数据信号线、第一节点、第二节点、第三节点和第一电源线连接，设置为在扫描信号线、第二复位线和第一节点控制下，向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；在第一节点的控制下，向第三节点提供第二节点的信号；发光控制子电路，分别与发光控制线、第一电源线、第二节点、第三节点和发光元件连接，设置为在发光控制线的控制下，向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；第二复位子电路，分别与第三复位线、初始信号线和发光元件连接，设置为在第三复位线的控制下，向发光元件提供初始信号线的信号。
显示装置包括：多个子像素。每个子像素包括：一个发光元件和一个像素电路。每个子像素中的发光元件与像素电路连接。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在一种示例性实施例中，显示装置可以包括：基底以及依次设置在基底上的驱动结构层和发光结构层。驱动结构层包括：像素电路、扫描信号线、数据信号线、初始信号线、发光控制线、第一电源线、第一复位线、第二复位线和第三复位线。发光结构层包括：发光元件。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，如图11所示，扫描信号线Gate、初始信号线Vinit、发光控制线EM、第一复位线RST1、第二复位线RST2和第三复位线RST3沿第一方向延伸，数据信号线Data与第一电源线VDD沿第二方向延伸。第一方向与第二方向相交。
在一种示例性实施例中，第一方向与第二方向相交指的是第一方向与第二方向的夹角可以约为70度至90度。例如，第一方向与第二方向之间的夹角可以为90度。
在一种示例性实施例中，如图11所示，每个像素电路包括：存储电容。存储电容包括：第一极板C1和第二极板C2。第一极板C1与第一电源线VDD连接，第二极板C2与第一节点N1连接。
在一种示例性实施例中，第一极板C1在基底上的正投影与第二极板在基底上的正投影部分重叠；第一极板C1设置有过孔，第一极板C1的过孔暴露出第二极板C2。
在一种示例性实施例中，如图11所示，扫描信号线Gate、第一复位线RST1和第二复位线RST2位于第二极板C2的一侧，发光控制线EM和第三复位线RST3位于第二极板C2远离第一复位线RST1的一侧。
在一种示例性实施例中，如图11所示，第一复位线RST1位于扫描信号线Gate远离第二极板C2的一侧。第二复位线RST2位于扫描信号线Gate靠近第二极板C2的一侧。第三复位线RST3位于发光控制线EM远离第二极板C2的一侧。
初始信号线Vinit包括：第一初始信号线和第二初始信号线。第一初始信号线与第一复位线位于第二极板的同一侧，且位于第一复位线远离第二极板的一侧。第二初始信号线与第三复位线位于第二极板的同一侧，且位于第三复位线远离第二极板的一侧。
在一种示例性实施例中，像素电路连接的第一初始信号线复用为上一行像素电路连接的第二初始信号线，像素电路连接的第二初始信号线复用为下一行像素电路连接的第一初始信号线。
在一种示例性实施例中，如图11所示，驱动结构层还包括：电源连接线 VL和连接电极101。
在一种示例性实施例中，电源连接线VL与第一电源线异层设置，且与第一电源线VDD连接。第一极板C1通过电源连接线VL与第一电源线VDD连接。
在一种示例性实施例中，电源连接线VL在基底上的正投影与第一极板C1在基底上的正投影至少部分重叠，且与第一电源线VDD在基底上的正投影至少部分重叠。
在一种示例性实施例中，连接电极101设置为连接像素电路和发光元件。
在一种示例性实施例中，对于像素电路中的第一晶体管至第九晶体管，每个晶体管包括：有源层、控制极、第一极和第二极。驱动结构层包括：沿垂直于基底方向依次设置的有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层、第一平坦层、第四金属层和第二平坦层。
在一种示例性实施例中，如图11所示，有源层包括：初始信号线Vinit和所有晶体管的有源层。初始信号线Vinit和所有晶体管的有源层同层设置且通过同一次构图工艺形成。
所有晶体管的有源层包括：第一晶体管的有源层、第二晶体管的有源层、第三晶体管的有源层、第四晶体管的有源层、第五晶体管的有源层、第六晶体管的有源层、第七晶体管的有源层、第八晶体管的有源层和第九晶体管的有源层。
在一种示例性实施例中，如图11所示，第一金属层包括：扫描信号线Gate、第一复位线RST1、第二复位线RST2、第二极板C2、发光控制线EM、第三复位线RST3和所有晶体管的控制极。
在一种示例性实施例中，扫描信号线Gate、第一复位线RST1、第二复位线RST2、第二极板C2、发光控制线EM、第三复位线RST3和所有晶体管的控制极同层设置且通过同一次构图工艺形成。
所有晶体管的控制极包括：第一晶体管的控制极、第二晶体管的控制极、第三晶体管的控制极、第四晶体管的控制极、第五晶体管的控制极、第六晶 体管的控制极、第七晶体管的控制极、第八晶体管的控制极和第九晶体管的控制极。
在一种示例性实施例中，第一晶体管的控制极、第二晶体管的控制极、第三晶体管的控制极、第四晶体管的控制极和第六晶体管的控制极位于第二极板的第一侧，第七晶体管的控制极、第八晶体管的控制极和第九晶体管的控制极位于第二极板的第二侧，第一侧和第二侧相对设置；
在一种示例性实施例中，第二晶体管的控制极位于第一晶体管的控制极靠近第二极板的一侧；第二晶体管的控制极和第三晶体管的控制极为一体成型结构；第四晶体管的控制极位于第二晶体管的控制极靠近第二极板的一侧；第四晶体管的控制极和第六晶体管的控制极为一体成型结构；第二极板与第五晶体管的控制极为一体成型结构；第七晶体管的控制极和第八晶体管的控制极为一体成型结构，第九晶体管的控制极位于第七晶体管的控制极远离第二极板的一侧。
在一种示例性实施例中，如图11所示，第二金属层包括：第一极板C1。
在一种示例性实施例中，如图11所示，第三金属层包括：电源连接线VL以及部分晶体管的第一极或第二极。在一种示例性实施例中，第三金属层包括：电源连接线VL、第二晶体管的第二极、第三晶体管的第一极、第六晶体管的第一极、第七晶体管的第一极、第八晶体管的第二极和第九晶体管的第二极。
在一种示例性实施例中，电源连接线VL、第二晶体管的第二极、第三晶体管的第一极、第六晶体管的第一极、第七晶体管的第一极、第八晶体管的第二极和第九晶体管的第二极同层设置且通过同一次构图工艺形成。
在一种示例性实施例中，第八晶体管的第二极和第九晶体管的第二极为同一电极，第二晶体管的第二极和第六晶体管的第一极为同一电极。
在一种示例性实施例中，有源层还复用为除第三金属层包括的部分晶体管的第一极或第二极之外的晶体管的第一极或第二极。即有源层复用为第一晶体管的第一极、第一晶体管的第二极、第二晶体管的第一极、第三晶体管的第二极、第四晶体管的第一极、第四晶体管的第二极、第五晶体管的第一极、第五晶体管的第二极、第六晶体管的第二极、第七晶体管的第二极、第 八晶体管的第一极和第九晶体管的第一极。
在一种示例性实施例中，第一晶体管的第二极14和第二晶体管的第一极23为同一电极。第三晶体管的第二极34和第四晶体管的第一极43为同一电极。第四晶体管的第二极44、第五晶体管的第一极53和第七晶体管的第二极74为同一电极。第五晶体管的第二极54、第六晶体管的第二极64和第八晶体管的第一极83为同一电极。
在一种示例性实施例中，如图11所示，第四金属层包括：第一电源线VDD、数据信号线Data和像素电极101。第一电源线VDD、数据信号线Data和像素电极101同层设置且通过同一次构图工艺形成。
在一种示例性实施例中，第一绝缘层、第二绝缘层和第三绝缘层上设置有第一过孔、第二过孔、第三过孔和第四过孔；第二绝缘层和第三绝缘层上设置有第五过孔；第三绝缘层上设置有第六过孔；第四绝缘层和第一平坦层上设置有第七过孔、第八过孔和第九过孔；第二平坦层包括：第十过孔。
第一过孔暴露出第三晶体管的有源层，第三晶体管的第一极通过第一过孔与第三晶体管的有源层连接；第二过孔暴露出第二晶体管的有源层，第二晶体管的第二极通过第二过孔与第二晶体管的有源层连接；第三过孔暴露出第八晶体管的有源层，第八晶体管的第二极通过第三过孔与第八晶体管的有源层连接；第四过孔暴露出第七晶体管的有源层，第七晶体管的第一极通过第四过孔与第七晶体管的有源层连接；第五过孔暴露出第二极板，第二晶体管的第二极通过第五过孔与第二极板连接；第六过孔暴露出第一极板，电源连接线通过第六过孔与第一极板连接；第七过孔暴露出第三晶体管的第一极，数据信号线通过第七过孔与第三晶体管的第一极连接；第八过孔暴露出电源连接线，第一电源线通过第八过孔与电源连接线连接；第九过孔暴露出第八晶体管的第二极，连接电极通过第九过孔与第八晶体管的第二极连接；第十过孔暴露出连接电极，发光元件通过第十过孔与连接电极连接。
在一种示例性实施例中，第三绝缘层的过孔数量较少，可以减少像素电路所占用的空间，有利于实现显示装置的高分辨率。
在一种示例性实施例中，发光元件包括：第一电极、第二电极和有机发光层；第一电极位于有机发光层靠近基底的一侧，第二电极位于有机发光层 远离基底的一侧。
在一种示例性实施例中，发光结构层包括：像素界定层、透明导电层、有机材料层和导电层，透明导电层包括：第一电极，有机材料层包括：有机发光层；导电层包括：第二电极。
在一种示例性实施例中，像素电路中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如该晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而控制极、第一极、第二极等则采用金属材料，例如金属铝或铝合金。这里采用的晶体管的第一极、第二极在结构上可以是对称的，所以其第一极、第二极在结构上可以是没有区别的。
下面通过显示装置的制备过程说明一种示例性实施例提供的显示装置的结构。“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
图12至图19为一种示例性实施例提供的显示装置的制备过程的示意图，示意了显示装置中一个子像素的的版图结构，每个子像素包括：一个像素电路。像素电路包括第一晶体管T1至第九晶体管T9和存储电容。存储电容包括：第一极板C1和第二极板C2。
(1)在基底形成有源层，包括：在基底上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成有源层。有源层包括初始信号线Vinit、第一晶体管的有源层11、第二晶体管的有源层21、第三晶体管的有源层31、第四晶体管的有源层41、第五晶体管的有源层51、第六晶体管的有源层61、第七晶体管的有源层71、第八晶体管的有源层81和第九晶体管的有源层91， 如图12所示。
(2)形成第一金属层，包括：在形成有有源层的基底上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成位于第一绝缘层。在第一绝缘层上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成第一金属层。第一金属层包括：扫描信号线Gate、第一复位线RST1、第二复位线RST3、第二极板C2、发光控制线EM、第三复位线RST4、第一晶体管的控制极12、第二晶体管的控制极22、第三晶体管的控制极32、第四晶体管的控制极42、第五晶体管的控制极52、第六晶体管的控制极62、第七晶体管的控制极72、第八晶体管的控制极82和第九晶体管的控制极92，如图13所示。
在一种示例性实施例中，第一复位线RST1、扫描信号线Gate、第一复位线RST1、发光控制线EM和第三复位线RST3平行设置，且沿第一方向延伸。第一复位线RST1、扫描信号线Gate和第一复位线RST1位于第二极板C2的第一侧，发光控制线EM和第三复位线RST3位于第二极板C2的第二侧，第一侧和第二侧相对设置。
在一种示例性实施例中，第一晶体管的控制极12是与第一复位线RST1连接的一体结构，且跨设在第一晶体管的有源层11上。第二晶体管的控制极22是与扫描信号线Gate连接的一体结构，且跨设在第二晶体管的有源层21上。第三晶体管的控制极32是与扫描信号线Gate连接的一体结构，且跨设在第三晶体管的有源层31上。第四晶体管的控制极42是与第二复位线RST2连接的一体结构，且跨设在第四晶体管的有源层41上。第五晶体管的控制极52是与第二极板C2连接的一体结构，且跨设在第五晶体管的有源层51上。第六晶体管的控制极62是与第二复位线RST2连接的一体结构，且跨设在第六晶体管的有源层61上。第七晶体管的控制极72是与发光控制线EM连接的一体结构，且跨设在第七晶体管的有源层71上。第八晶体管的控制极82是与发光控制线EM连接的一体结构，且跨设在第八晶体管的有源层81上。第九晶体管的控制极92是与第三复位线RST3连接的一体结构，且跨设在第九晶体管的有源层91上。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在 形成第一金属层后，利用第一晶体管的控制极12、第二晶体管的控制极22、第三晶体管的控制极32、第四晶体管的控制极42、第五晶体管的控制极52、第六晶体管的控制极62、第七晶体管的控制极72、第八晶体管的控制极82和第九晶体管的控制极92作为遮挡对有源层进行等离子体处理，被第一晶体管的控制极12、第二晶体管的控制极22、第三晶体管的控制极32、第四晶体管的控制极42、第五晶体管的控制极52、第六晶体管的控制极62、第七晶体管的控制极72、第八晶体管的控制极82和第九晶体管的控制极92遮挡区域的有源层作为晶体管的沟道区域，未被第一金属层遮挡区域的有源层被处理成导体化层，形成导体化的源漏区域和初始信号线。
(3)形成第二金属层，包括：在形成有第一金属层的基底上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成第二绝缘层。在形成有第二绝缘层的基底上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成第二金属层。第二金属层包括：第一极板C1，如图14所示。
在一种示例性实施例中，第一极板C1在基底上的正投影与第二极板C2在基底上的正投影至少部分重叠。第一极板C1设置有过孔，过孔暴露出第二极板C2。
(4)形成第三绝缘层，包括：在形成有第二金属层的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层。形成第三绝缘层开设有多个过孔。多个过孔包括：贯通第一绝缘层、第二绝缘层和第三绝缘层的第一过孔V1、第二过孔V2、第三过孔V3和第四过孔V4，贯通第二绝缘层和第三绝缘层的第五过孔V5以及仅贯通第三绝缘层的第六过孔V6，如图15所示。
在一种示例性实施例中，第一过孔V1暴露出第三晶体管的有源层31。第二过孔V2暴露出第二晶体管的有源层21。第三过孔V3暴露出第八晶体管的有源层81。第四过孔V4暴露出第七晶体管的有源层71。第五过孔V5暴露出第二极板C2。第七过孔V7暴露出第一极板C1。
(5)形成第三金属层，包括：在形成有第三绝缘层的基底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第三金属层。第三金属层包括：电源连接线VL、第二晶体管的第二极24、第三晶体管的第一 极33、第六晶体管的第一极63、第七晶体管的第一极73、第八晶体管的第二极84和第九晶体管的第二极94。如图16所示。
第八晶体管的第二极84和第九晶体管的第二极94为同一电极，第二晶体管的第二极24和第六晶体管的第一极63为同一电极。
在一种示例性实施例中，有源层还复用为第一晶体管的第一极13、第一晶体管的第二极14、第二晶体管的第一极23、第三晶体管的第二极34、第四晶体管的第一极43、第四晶体管的第二极44、第五晶体管的第一极53、第五晶体管的第二极54、第六晶体管的第二极64、第七晶体管的第二极74、第八晶体管的第一极83和第九晶体管的第一极93。
在一种示例性实施例中，电源连接线VL沿第一方向延伸。
在一种示例性实施例中，第一晶体管的第二极14和第二晶体管的第一极23为同一电极。第三晶体管的第二极34和第四晶体管的第一极43为同一电极。第四晶体管的第二极44、第五晶体管的第一极53和第七晶体管的第二极74为同一电极。第五晶体管的第二极54、第六晶体管的第二极64和第八晶体管的第一极83为同一电极。
在一种示例性实施例中，第一晶体管的第二极14通过第一过孔与第一晶体管的有源层11连接。第三晶体管的第一极通过第二过孔V2与第三晶体管的有源层21连接。第六晶体管的第一极53通过第三过孔V3与第六晶体管的有源层51连接。第八晶体管的第二极74通过第四过孔V4与第八晶体管的有源层71连接。第七晶体管的第一极63通过第五过孔V5与第七晶体管的有源层61连接。第六晶体管的第一极53通过第六过孔V6与第二极板C2连接。电源连接线VL通过第七过孔V7与第一极板C1连接。
第三晶体管的第一极33通过第一过孔V1与第三晶体管的有源层31连接。第二晶体管的第二极24通过第二过孔V2与第二晶体管的有源层21连接。第八晶体管的第二极84通过第三过孔V3与第八晶体管的有源层81连接。第七晶体管的第一极73通过第四过孔V4与第七晶体管的有源层71连接。第二晶体管的第二极24通过第五过孔V5与第二极板C2连接。电源连接线VL通过第六过孔V6与第一极板C1连接。
(6)形成第一平坦层，包括：在形成有第三金属层的基底上，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成第四绝缘层。在形成有第四绝缘层的基底上涂覆第一平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，形成第一平坦层。第四绝缘薄膜和第一平坦层上设置有第七过孔V7、第八过孔V8和第九过孔V9，如图17所示。
在一种示例性实施例中，第七过孔V7暴露出第三晶体管的第一极23。第八过孔V8暴露出电源连接线VL。第九过孔V9暴露出第八晶体管的第二极84。
(7)形成第四金属层，包括：在形成有第一平坦层的基底上，沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，形成第四金属层。第四金属层包括：第一电源线VDD、数据信号线Data和像素电极91，如图18所示。
在一种示例性实施例中，数据信号线Data通过第七过孔V7与第三晶体管的第一极连接23。第一电源线VDD通过第八过孔V8与电源连接线VL连接。连接电极101通过第九过孔V9与第八晶体管的第二极84连接。。
(8)形成第二平坦层，包括：在形成有第四金属层的基底上涂覆第二平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，形成第二平坦层。第二平坦层上设置有第十一过孔V11，如图19所示。
在一种示例性实施例中，第十过孔V10暴露出连接电极101，发光元件通过第十过孔V10与连接电极101连接。
(9)形成透明导电层，包括：在形成有第二平坦层的基底上，沉积第一透明导电薄膜，通过构图工艺对第一透明导电薄膜进行构图，形成透明导电层。透明导电层包括第一电极，第一电极形成在每个发光元件中，第一电极通过第十过孔V10与连接电极101连接。
(10)形成像素定义层，包括：在形成透明导电层的基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(Pixel Define Layer)，像素定义层形成在每个发光元件中，每个发光元件中的像素定义层形成有暴露出第一电极的开口区域。
(11)形成有机发光层，包括：在形成的像素定义层的开口区域内和像素定义层上形成有机发光层，有机发光层与第一电极电连接。
(12)形成第二电极，包括：在形成有机发光层的基底上涂覆导电薄膜，通过构图工艺对导电薄膜进行构图，形成第二电极。第二电极覆盖每个发光元件中的有机发光层。第二电极与有机发光层电连接。
(13)形成封装层，在形成第二电极的基底上形成封装层，封装层包括无机材料的第一封装层、有机材料的第二封装层和无机材料的第三封装层，第一封装层设置在第二电极上，第二封装层设置在第一封装层上，第三封装层设置在第二封装层上，形成无机材料/有机材料/无机材料的叠层结构。
在一种示例性实施例中，第一金属层、第二金属层、第三金属层和第四金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为第一栅绝缘层、第二绝缘层成为第二栅绝缘层、第三绝缘层称为层间绝缘层、第四绝缘层称为钝化层。
在一种示例性实施例中，第一平坦层和第二平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
在一种示例性实施例中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
在一种示例性实施例中，第二电极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或可以采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，有源层可以为金属氧化物层。金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、 包含硅和铟和锡的氧化物、包含铟或镓和锌的氧化物等。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
本公开实施例还提供了一种显示装置的驱动方法，设置为驱动显示装置。本公开实施例提供的显示装置的驱动方法包括：
步骤S1、在第一复位线和扫描信号线的控制下，第一复位子电路向第一节点提供初始信号线的信号。
步骤S2、在第三复位线的控制下，第二复位子电路向发光元件提供初始信号线的信号，在扫描信号线、第二复位线和第一节点控制下，节点控制子电路向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件。
步骤S3、在发光控制线的控制下，发光控制子电路向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；在第一节点的控制下，节点控制子电路向第三节点提供第二节点的信号。
显示装置为前述任一个实施例提供的显示装置，实现原理和实现效果类似，在此不再赘述。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示装置，包括：矩阵排布的发光元件、矩阵排布的像素电路、扫描信号线、数据信号线、初始信号线、发光控制线、第一电源线、第一复位线、第二复位线和第三复位线；
    所述像素电路与所述发光元件一一对应；所述像素电路设置为驱动对应的发光元件发光；所述像素电路包括：第一复位子电路、节点控制子电路、发光控制子电路和第二复位子电路；
    所述第一复位子电路，分别与第一复位线、扫描信号线、初始信号线和第一节点连接，设置为在第一复位线和扫描信号线的控制下，向第一节点提供初始信号线的信号；
    所述节点控制子电路，分别与扫描信号线、第二复位线、数据信号线、第一节点、第二节点、第三节点和第一电源线连接，设置为在扫描信号线、第二复位线和第一节点控制下，向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；在第一节点的控制下，向第三节点提供第二节点的信号；
    所述发光控制子电路，分别与发光控制线、第一电源线、第二节点、第三节点和发光元件连接，设置为在发光控制线的控制下，向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；
    所述第二复位子电路，分别与第三复位线、初始信号线和发光元件连接，设置为在第三复位线的控制下，向发光元件提供初始信号线的信号；
    位于第i行的像素电路连接的第三复位线与位于第i+1行的像素电路连接的第一复位线电连接，1≤i<M，M为像素电路的总行数。
  2. 根据权利要求1所述的装置，其中，所述显示装置包括：基底以及依次设置在所述基底上的驱动结构层和发光结构层；
    所述驱动结构层包括：像素电路、扫描信号线、数据信号线、初始信号线、发光控制线、第一电源线、第一复位线、第二复位线和第三复位线，所述发光结构层包括：发光元件；
    所述扫描信号线、所述初始信号线、所述发光控制线、所述第一复位线、所述第二复位线和所述第三复位线沿第一方向延伸，所述数据信号线与所述第一电源线沿第二方向延伸；
    所述第一方向与所述第二方向相交。
  3. 根据权利要求1或2所述的装置，其中，每个像素电路包括：存储电容，所述存储电容包括：第一极板和第二极板；所述第一极板与第一电源线连接，所述第二极板与第一节点连接；
    所述第一极板在基底上的正投影与所述第二极板在基底上的正投影部分重叠；所述第一极板设置有过孔，所述第一极板的过孔暴露出所述第二极板；
    所述扫描信号线、所述第一复位线和所述第二复位线位于所述第二极板的一侧，所述发光控制线和所述第三复位线位于所述第二极板远离所述第一复位线的一侧；
    所述第一复位线位于所述扫描信号线远离第二极板的一侧，所述第二复位线位于所述扫描信号线靠近所述第二极板的一侧；所述第三复位线位于所述发光控制线远离第二极板的一侧；
    所述初始信号线包括：第一初始信号线和第二初始信号线；所述第一初始信号线与所述第一复位线位于第二极板的同一侧，且位于所述第一复位线远离第二极板的一侧；所述第二初始信号线与所述第三复位线位于所述第二极板的同一侧，且位于所述第三复位线远离第二极板的一侧。
  4. 根据权利要求3所述的装置，其中，所述驱动结构层还包括：电源连接线和连接电极；
    所述电源连接线与所述第一电源线异层设置，且与所述第一电源线连接，所述第一极板通过电源连接线与所述第一电源线连接；
    所述电源连接线在基底上的正投影与所述第一极板在基底上的正投影至少部分重叠，且与所述第一电源线在基底上的正投影至少部分重叠；
    所述连接电极设置为连接像素电路和发光元件。
  5. 根据权利要求1至4任一项所述的装置，其中，所述节点控制子电路包括：写入子电路、驱动子电路、补偿子电路和储能子电路；
    所述写入子电路，分别与扫描信号线、第二复位线、数据信号线和第二节点连接，设置为在扫描信号线和第二复位线的控制下，向第二节点提供数据信号线的信号，或者向第二节点放电；
    所述驱动子电路，分别与第一节点、第二节点和第三节点连接，设置为在第一节点的控制下，向第三节点提供第二节点的信号；
    所述补偿子电路，分别与第一节点、第二复位线和第三节点连接，设置为在第二复位线的控制下，向第一节点提供第三节点的电位，以对第一节点进行补偿，直至第一节点的电压满足阈值条件；
    所述储能子电路，分别与第一电源线和第一节点连接，设置为存储第一电源线与第一节点之间的电压差。
  6. 根据权利要求1或5所述的装置，其中，所述第一复位子电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的控制极与第一复位线连接，所述第一晶体管的第一极与初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述第二晶体管的控制极与扫描信号端连接，所述第二晶体管的第二极与第一节点连接。
  7. 根据权利要求5所述的装置，其中，所述写入子电路包括：第三晶体管和第四晶体管；
    所述第三晶体管的控制极与扫描信号线连接，所述第三晶体管的第一极与数据信号线连接，所述第三晶体管的第二极与所述第四晶体管的第一极连接；
    所述第四晶体管的控制极与第二复位线连接，所述第四晶体管的第二极与第二节点连接；
    所述第四晶体管的沟道区域的长度大于阈值长度，所述第四晶体管的沟道区域的宽度大于阈值宽度。
  8. 根据权利要求5所述的装置，其中，所述驱动子电路包括：第五晶体管，所述第五晶体管为驱动晶体管；所述储能子电路包括：存储电容；
    所述第五晶体管的控制极与第一节点连接，所述第五晶体管的第一极与第二节点连接，所述第五晶体管的第二极与第三节点连接；
    所述存储电容的第一端与第一电源线连接，所述存储电容的第二端与第一节点连接。
  9. 根据权利要求5所述的装置，其中，所述补偿子电路包括：第六晶体管；
    所述第六晶体管的控制极与第二复位线连接，所述第六晶体管的第一极与第一节点连接，所述第六晶体管的第二极与第三节点连接。
  10. 根据权利要求1或5所述的装置，其中，所述发光控制子电路包括：第七晶体管和第八晶体管；
    所述第七晶体管的控制极与发光控制线连接，所述第七晶体管的第一极与第一电源线连接，所述第七晶体管的第二极与第二节点连接；
    所述第八晶体管的控制极与发光控制线连接，所述第八晶体管的第一极与第三节点连接，所述第八晶体管的第二极与发光元件连接。
  11. 根据权利要求1或5所述的装置，其中，所述第二复位子电路包括：第九晶体管；
    所述第九晶体管的控制极与第三复位线连接，所述第九晶体管的第一极与初始信号线连接，所述第九晶体管的第二极与发光元件连接。
  12. 根据权利要求1或5所述的装置，其中，所述第一复位子电路包括：第一晶体管和第二晶体管；所述节点控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和存储电容，所述第五晶体管为驱动晶体管；所述发光控制子电路包括：第七晶体管和第八晶体管；所述第二复位子电路包括：第九晶体管；
    所述第一晶体管的控制极与第一复位线连接，所述第一晶体管的第一极与初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极连接；
    所述第二晶体管的控制极与扫描信号端连接，所述第二晶体管的第二极与第一节点连接；
    所述第三晶体管的控制极与扫描信号线连接，所述第三晶体管的第一极与数据信号线连接，所述第三晶体管的第二极与所述第四晶体管的第一极连接；
    所述第四晶体管的控制极与第二复位线连接，所述第四晶体管的第二极与第二节点连接；
    所述第五晶体管的控制极与第一节点连接，所述第五晶体管的第一极与第二节点连接，所述第五晶体管的第二极与第三节点连接；
    所述第六晶体管的控制极与第二复位线连接，所述第六晶体管的第一极与第一节点连接，所述第六晶体管的第二极与第三节点连接；
    所述存储电容的第一端与第一电源线连接，所述存储电容的第二端与第一节点连接；
    所述第七晶体管的控制极与发光控制线连接，所述第七晶体管的第一极与第一电源线连接，所述第七晶体管的第二极与第二节点连接；
    所述第八晶体管的控制极与发光控制线连接，所述第八晶体管的第一极与第三节点连接，所述第八晶体管的第二极与发光元件连接；
    所述第九晶体管的控制极与第三复位线连接，所述第九晶体管的第一极与初始信号线连接，所述第九晶体管的第二极与发光元件连接。
  13. 根据权利要求1或12所述的装置，其中，所述发光元件包括：有机发光二极管；
    所述有机发光二极管的阳极分别与第八晶体管的第二极和第九晶体管的第二极连接，所述有机发光二极管的阴极与第二电源线连接。
  14. 根据权利要求8或12所述的装置，其中，所述阈值条件为所述第一节点的电压等于所述数据信号线的信号的电压与第五晶体管的阈值电压的绝对值之差。
  15. 根据权利要求1所述的装置，其中，所述扫描信号线和所述第三复位线电连接。
  16. 根据权利要求12所述的装置，其中，对于第一晶体管至第九晶体管，每个晶体管包括：有源层、控制极、第一极和第二极；
    所述驱动结构层包括：沿垂直于所述基底方向依次设置的有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层、第一平坦层、第四金属层和第二平坦层；
    所述有源层包括：初始信号线和所有晶体管的有源层；所述第一金属层包括：扫描信号线、第一复位线、第二复位线、第二极板、发光控制线、第三复位线和所有晶体管的控制极；所述第二金属层包括：第一极板；所述第三金属层包括：电源连接线以及部分晶体管的第一极或第二极；所述第四金属层包括：第一电源线、数据信号线和像素电极。
  17. 根据权利要求16所述的装置，其中，所述第一晶体管的控制极、所述第二晶体管的控制极、所述第三晶体管的控制极、所述第四晶体管的控制极和所述第六晶体管的控制极位于第二极板的第一侧，所述第七晶体管的控制极、所述第八晶体管的控制极和所述第九晶体管的控制极位于第二极板的第二侧，所述第一侧和所述第二侧相对设置；
    所述第二晶体管的控制极位于所述第一晶体管的控制极靠近第二极板的一侧；所述第二晶体管的控制极和所述第三晶体管的控制极为一体成型结构；所述第四晶体管的控制极位于第二晶体管的控制极靠近第二极板的一侧；所述第四晶体管的控制极和所述第六晶体管的控制极为一体成型结构；所述第二极板与所述第五晶体管的控制极为一体成型结构；所述第七晶体管的控制极和所述第八晶体管的控制极为一体成型结构，所述第九晶体管的控制极位于所述第七晶体管的控制极远离第二极板的一侧。
  18. 根据权利要求16或17所述的装置，其中，所述第一绝缘层、所述第二绝缘层和所述第三绝缘层上设置有第一过孔、第二过孔、第三过孔和第四过孔；所述第二绝缘层和所述第三绝缘层上设置有第五过孔；所述第三绝缘层上设置有第六过孔；所述第四绝缘层和所述第一平坦层上设置有第七过孔、第八过孔和第九过孔；所述第二平坦层包括：第十过孔；
    所述第一过孔暴露出第三晶体管的有源层，所述第三晶体管的第一极通过第一过孔与所述第三晶体管的有源层连接；所述第二过孔暴露出第二晶体管的有源层，所述第二晶体管的第二极通过第二过孔与第二晶体管的有源层连接；所述第三过孔暴露出第八晶体管的有源层，所述第八晶体管的第二极 通过第三过孔与第八晶体管的有源层连接；所述第四过孔暴露出第七晶体管的有源层，所述第七晶体管的第一极通过第四过孔与第七晶体管的有源层连接；所述第五过孔暴露出所述第二极板，所述第二晶体管的第二极通过第五过孔与第二极板连接；所述第六过孔暴露出所述第一极板，所述电源连接线通过第六过孔与第一极板连接；所述第七过孔暴露出第三晶体管的第一极，所述数据信号线通过第七过孔与第三晶体管的第一极连接；所述第八过孔暴露出电源连接线，所述第一电源线通过第八过孔与所述电源连接线连接；所述第九过孔暴露出第八晶体管的第二极，所述连接电极通过第九过孔与第八晶体管的第二极连接；所述第十过孔暴露出连接电极，所述发光元件通过第十过孔与连接电极连接。
  19. 根据权利要求1所述的装置，其中，所述发光元件包括：第一电极、第二电极和有机发光层；所述第一电极位于所述有机发光层靠近基底的一侧，所述第二电极位于所述有机发光层远离基底的一侧；
    所述发光结构层包括：像素界定层、透明导电层、有机材料层和导电层，所述透明导电层包括：第一电极，所述有机材料层包括：有机发光层；所述导电层包括：第二电极。
  20. 一种显示装置的驱动方法，设置为驱动如权利要求1至19任一项所述的显示装置，所述方法包括：
    在第一复位线和扫描信号线的控制下，第一复位子电路向第一节点提供初始信号线的信号；
    在第三复位线的控制下，第二复位子电路向发光元件提供初始信号线的信号，在扫描信号线、第二复位线和第一节点控制下，节点控制子电路向第二节点提供数据信号线的信号，并通过第二节点和第三节点向第一节点进行补偿，直至第一节点的电压满足阈值条件；
    在发光控制线的控制下，发光控制子电路向第二节点提供第一电源线的信号，向发光元件提供第三节点的信号；在第一节点的控制下，节点控制子电路向第三节点提供第二节点的信号。
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