WO2022012202A1 - 反熔丝存储单元状态检测电路及存储器 - Google Patents

反熔丝存储单元状态检测电路及存储器 Download PDF

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Publication number
WO2022012202A1
WO2022012202A1 PCT/CN2021/097868 CN2021097868W WO2022012202A1 WO 2022012202 A1 WO2022012202 A1 WO 2022012202A1 CN 2021097868 W CN2021097868 W CN 2021097868W WO 2022012202 A1 WO2022012202 A1 WO 2022012202A1
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WIPO (PCT)
Prior art keywords
memory cell
fuse memory
time point
node
fuse
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PCT/CN2021/097868
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English (en)
French (fr)
Inventor
季汝敏
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/445,372 priority Critical patent/US11817159B2/en
Publication of WO2022012202A1 publication Critical patent/WO2022012202A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Definitions

  • the present disclosure relates to the technical field of integrated circuits, exemplarily, to an anti-fuse memory cell state detection circuit and a memory using the circuit.
  • One-time programmable memory is widely used in various types of memory to realize redundant replacement of damaged memory cells and fine-tuning of circuit modules.
  • the commonly used one-time programmable memory utilizes the breakdown or non-breakdown state of antifuse memory cells for information storage.
  • the breakdown state of the anti-fuse memory cell is usually detected only by a simple logic gate circuit (such as an inverter, etc.).
  • a simple logic gate circuit such as an inverter, etc.
  • an inverter is used to detect the breakdown state of the anti-fuse memory cell, as shown in FIG. 1 .
  • the path resistance will be relatively small, then during the detection, the voltage generated on the Node1 node is low, so that the output D_out of the inverter is high; otherwise, If the anti-fuse memory cell 11 to be tested is in a state that has not been programmed to break down, the path resistance will be large, and the voltage generated on the Node1 node will be high, exceeding the inversion point of the inverter, so that the output D_out of the inverter is low. .
  • the resistance of the anti-fuse memory cell after being broken down will fluctuate in a wide range, and the influence of process, voltage, temperature and other factors on the inversion point of logic gate circuits such as inverters, it is easy to cause the anti-fuse memory cell to fail.
  • the storage state detection is wrong, resulting in a decrease in chip yield, so an anti-fuse memory cell state detection circuit with better performance is urgently needed.
  • the purpose of the present disclosure is to provide an anti-fuse memory cell state detection circuit and a memory using the same, which are used to at least to a certain extent overcome the storage state detection of anti-fuse memory cells due to the limitations and defects of the related art Inaccurate results.
  • an anti-fuse memory cell state detection circuit comprising: a current providing module connected to a first node for providing a constant current; an anti-fuse memory cell array connected to the first node, It includes at least one bit line, the bit line is connected to a plurality of anti-fuse memory cells and the first node; the comparator, the first input end is connected to the first node, the second input end is connected to the first reference voltage, and for detecting the storage state of the anti-fuse memory cell to be tested in the anti-fuse memory cell array.
  • the current providing module includes: an amplifier, the first input terminal is connected to the second reference voltage, the second input terminal is connected to the second node, and the output terminal is connected to the third node; the first switch element, the first end is connected to the power supply voltage, the second end is connected to the second node, the control end is connected to the third node; the reference resistor, the first end is connected to the second node, the second end is grounded; the second switching element , the first terminal is connected to the power supply voltage, the second terminal is connected to the first node, and the control terminal is connected to the third node.
  • it further includes a flip-flop, the input terminal of which is connected to the output terminal of the comparator.
  • word lines of the plurality of anti-fuse memory cells and output terminals of the comparator are both connected to a controller.
  • word lines of the plurality of anti-fuse memory cells and output terminals of the flip-flops are both connected to a controller.
  • the controller is configured to: output a first control signal to a word line of the anti-fuse memory cell to be tested at a first time point to control the anti-fuse memory cell to be tested electrically connected to a bit line; acquiring an output signal of the comparator at a second time point to determine the storage state of the anti-fuse memory cell to be tested; wherein the second time point is after the first time point .
  • the reference resistor is a ZQ calibration resistor.
  • a first end of the reference resistor is connected to the second node through a third switch element, and a control end of the third switch element is connected to a controller, and the controller sets In order to control the third switching element to be turned on at a third time point, the third time point is before the second time point.
  • the anti-fuse memory cell array includes: a plurality of anti-fuse memory cell sub-arrays, each of the anti-fuse memory cell sub-arrays corresponds to a bit line, each The anti-fuse memory cell sub-array includes a plurality of anti-fuse memory cells; a plurality of fourth switching elements corresponding to the anti-fuse memory cell sub-array, each of which is connected to a first end of the fourth switching element For the bit line of the corresponding anti-fuse memory cell sub-array, the second end of each of the fourth switching elements is connected to the first node, and the default state of the fourth switching element is an off state.
  • a control end of each of the fourth switching elements is connected to a controller, and the controller is configured to: at the fourth time point, the anti-fuse storage unit to be tested is located in the anti-fuse storage unit.
  • the fourth switch element corresponding to the filament memory cell sub-array outputs a second control signal to control the fourth switch element to be turned on; at the first time point, the first control signal is output to the word line of the anti-fuse memory cell to be tested to control the anti-fuse memory unit to be tested to be electrically connected to the bit line; obtain the output signal of the comparator at a second time point to determine the storage state of the anti-fuse memory unit to be tested; wherein, the first Four time points precede the second time point.
  • an anti-fuse memory cell state detection method which is applied to the above-mentioned anti-fuse memory cell state detection circuit, comprising: outputting a word line of the anti-fuse memory cell to be tested at a first time point a first control signal to control the anti-fuse memory cell to be tested to be electrically connected to a bit line; acquiring an output signal of the comparator at a second time point to determine the storage state of the anti-fuse memory cell to be tested; wherein , the second time point is after the first time point.
  • the anti-fuse memory cell array includes: a plurality of anti-fuse memory cell sub-arrays, each of the anti-fuse memory cell sub-arrays corresponds to a bit line, each The anti-fuse memory cell sub-array includes a plurality of anti-fuse memory cells; a plurality of fourth switching elements corresponding to the anti-fuse memory cell sub-array, each of which is connected to a first end of the fourth switching element
  • the bit line of the corresponding anti-fuse memory cell sub-array, the second terminal of each of the fourth switching elements is connected to the first node, the control terminal of each of the fourth switching elements is connected to the controller, and the second terminal of each of the fourth switching elements is connected to the controller.
  • the default state of the four switching elements is an off state; the method further includes: at a fourth time point, the fourth switching element corresponding to the anti-fuse memory cell sub-array where the anti-fuse memory cell to be tested is located outputs a second control signal to output a second control signal to The fourth switching element is controlled to be turned on, and the fourth time point is before the second time point.
  • a memory including the anti-fuse memory cell state detection circuit according to any one of the above.
  • the resistance of the anti-fuse memory cell to be tested is reflected on the voltage of the first node by using a constant current, and a comparator is used to compare the voltage of the first node with the first reference voltage to determine the anti-fuse memory cell to be tested.
  • the resistance of the anti-fuse memory cell to be tested can be judged to determine the storage state of the anti-fuse memory cell to be tested, so that the inversion point can be accurately controlled and more accurate detection results can be obtained.
  • the offset leads to misjudgment of the memory state of the antifuse memory cell.
  • FIG. 1 is a schematic diagram of an anti-fuse memory cell state detection circuit in the related art.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in an embodiment of the present disclosure.
  • FIG. 4 is another schematic circuit diagram of the anti-fuse memory cell state detection circuit in the embodiment shown in FIG. 3 .
  • FIG. 5 is a flowchart of a detection method implemented by the controller CON in the embodiment shown in FIG. 4 .
  • FIG. 6 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in yet another embodiment of the present disclosure.
  • FIG. 8 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a detection method implemented by the controller CON in the embodiment shown in FIG. 8 .
  • FIG. 10 is a schematic diagram of an anti-fuse memory cell in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous exemplary details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • the anti-fuse memory cell state detection circuit 200 may include:
  • the current providing module 21 is connected to the first node N1 for providing constant current
  • the comparator 23 has a first input terminal connected to the first node N1 and a second input terminal connected to the first reference voltage Vtrip for detecting the storage state of the anti-fuse memory cell to be tested in the anti-fuse memory cell array 22 .
  • FIGS. 1 and 10 Please refer to FIGS. 1 and 10 for the structures of the anti-fuse memory cell array 22 and the anti-fuse memory cells shown in FIG. 2 .
  • FIG. 3 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in an embodiment of the present disclosure.
  • the current providing module 21 may include:
  • the amplifier OP the first input terminal is connected to the second reference voltage Vref, the second input terminal is connected to the second node N2, and the output terminal is connected to the third node N3;
  • the first switching element M1 the first terminal is connected to the power supply voltage VDD, the second terminal is connected to the second node N2, and the control terminal is connected to the third node N3;
  • the reference resistor Rref the first end is connected to the second node N2, and the second end is grounded;
  • the second switching element M2 has a first terminal connected to the power supply voltage VDD, a second terminal connected to the first node N1, and a control terminal connected to the third node N3.
  • the first switching element M1 and the second switching element M2 are both N-type transistors, the first input terminal of the amplifier OP is a non-inverting input terminal, and the second input terminal is an inverting input terminal. If the first switching element M1 and the second switching element M2 are both P-type transistors, the first input terminal of the amplifier OP is an inverting input terminal, and the second input terminal is a non-inverting input terminal.
  • the connection mode of the amplifier by themselves according to the settings of the first switching element M1 and the second switching element M2, and the present disclosure is not limited thereto.
  • FIG. 4 is another schematic circuit diagram of the anti-fuse memory cell state detection circuit in the embodiment shown in FIG. 3 .
  • both the anti-fuse memory cell array 22 and the comparator 23 are connected to the controller CON.
  • the controller CON is connected to the word lines of each anti-fuse memory cell in the anti-fuse memory cell array 22 , and is connected to the output end of the comparator 23 .
  • FIG. 5 is a flowchart of a detection method implemented by the controller CON in the embodiment shown in FIG. 4 .
  • the controller CON may be configured to perform a detection method 500, which may include:
  • Step S1 at a first time point, the word line of the anti-fuse memory cell to be tested outputs a first control signal to control the anti-fuse memory cell to be tested to be electrically connected to the bit line;
  • Step S2 obtain the output signal of the comparator at the second time point to determine the storage state of the anti-fuse storage unit to be tested;
  • the second time point is after the first time point.
  • the first node N1 has an equivalent resistance R, and the equivalent resistance R can be the resistance R1 of the anti-fuse memory cell to be tested in the breakdown state It can also be resistor R2 in the non-breakdown state.
  • R1 and R2 are statistical results obtained by statistical analysis of R1 and R2 in the process of research and development and production of the anti-fuse memory cell.
  • the current providing module 21 provides the constant current I to the first node N1 through the current mirror structure (including the amplifier OP, the first switching element M1, the second switching element M2, and the reference resistor Rref).
  • the voltage of the second node N2 maintains the same voltage value as the second reference voltage Vref connected to the amplifier OP, so that the first current is generated in the path where the second node N2 is located through the reference resistor Rref.
  • Due to the setting of the first switching element M1 and the second switching element M2, the path where the first node N1 is located generates a second current, and the second current has a constant proportional relationship with the first current, and the ratio is determined by the first switching element M1 and the first switching element M2.
  • the size and performance of the second switching element M2 are determined. That is, the second current is also a constant current, and the second current is referred to as the constant current I in the embodiment of the present disclosure.
  • the resistance of the anti-fuse memory cell to be tested can be determined, and then the storage state of the anti-fuse memory cell to be tested can be determined.
  • the function of comparator 23 may be implemented using a differential amplifier. For example, it is possible to avoid excessive bias current traces and accurately control the flip point by setting up a differential amplifier (such as a simple two-stage comparator) as a self-biasing circuit.
  • the method of acquiring the output signal of the comparator 23 can be either reading the output signal of the comparator 23 at the second time point, or controlling the comparator 23 to change to enable at the second time point through the enable pin of the comparator 23.
  • the comparison result between the voltage of the first node N1 and the first reference voltage Vtrip is output.
  • a plurality of anti-fuse memory cells can be measured to determine the maximum resistance of the anti-fuse memory cells in the breakdown state and the minimum resistance in the non-breakdown state, and according to the breakdown state of the anti-fuse memory cells
  • the maximum resistance and the minimum resistance in the non-breakdown state determine V1 and V2
  • the first reference voltage Vtrip is set as the average value of V1 and V2, so as to reduce the probability of misjudgment as much as possible and improve the detection accuracy.
  • the differential voltage input threshold can be designed to be less than two times the difference between V1 and V2. divided by one, so that the comparator 23 can accurately output the comparison result between the voltage of the first node N1 and the first reference voltage Vtrip.
  • the differential voltage input threshold referred to here refers to the minimum voltage difference between the forward input terminal and the reverse input terminal that the comparator can identify.
  • the constant current can be adjusted by setting an appropriate resistance value of the reference resistor Rref I, and then adjust the value of V2.
  • the ZQ calibration resistor may be used as the reference resistor Rref.
  • FIG. 6 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit according to another embodiment of the present disclosure.
  • the detection circuit may further include:
  • the third switching element M3 has a first end connected to the first end of the reference resistor Rref, a second end connected to the second node N2, and a control end connected to the controller CON.
  • the controller CON may be configured to control the third switching element M3 to be turned on at a third time point, which is before the second time point, so as to provide a constant current to the first node N1.
  • controlling the switch state of the third switching element M3 can control the ZQ calibration resistor to be connected to the anti-fuse memory cell state detection circuit or disconnected from the anti-fuse memory cell state detection circuit to connect to the anti-fuse memory cell state detection circuit. Ensure the safety of the normal operation of the ZQ calibration resistor.
  • the setting of the third switching element M3 can control the time point when the current supply module 21 starts to provide the constant current I, that is, the third switching element M3 can be turned on by controlling The time point at which the constant current I appears is controlled, thereby improving the accuracy of the state detection of the anti-fuse memory cell.
  • the third time point can be either before the first time point or after the first time point.
  • FIG. 7 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in yet another embodiment of the present disclosure.
  • the detection circuit may further include:
  • the flip-flop 24, the input terminal of the flip-flop 24 is connected to the output terminal of the comparator 23, and the first output terminal and the second output terminal of the flip-flop 23 are both connected to the controller CON.
  • the flip-flop 24 can be, for example, a D flip-flop, which is used to latch the output signal of the comparator 23 so as to facilitate reading by the controller CON.
  • Those skilled in the art can design the trigger 24 according to their own needs, and the present disclosure is not limited thereto.
  • FIG. 8 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the first node N1 may be used to connect a plurality of bit lines, and the anti-fuse memory cell array 22 may include:
  • a plurality of anti-fuse memory cell sub-arrays 22m (m is a bit line serial number), each anti-fuse memory cell sub-array 22m corresponds to a bit line BLm, and each anti-fuse memory cell sub-array 22m includes a plurality of anti-fuses storage unit;
  • a plurality of fourth switching elements M4m corresponding to the anti-fuse memory cell sub-array 22m the first end of each fourth switching element M4m is connected to the bit line BLm of the corresponding anti-fuse memory cell sub-array 22m, and each fourth The second end of the switching element M4m is connected to the third node N3, the control end of each fourth switching element M4m is connected to the controller CON, and the default state of the fourth switching element M4m is an off state.
  • the storage state of the anti-fuse memory cells in the plurality of anti-fuse memory cell sub-arrays 22m is checked.
  • the detection can greatly save the circuit area.
  • the first node N1 can be connected to 16 bit lines at the same time. An exemplary manner is shown in FIG. 9 .
  • FIG. 9 is a flowchart of a detection method implemented by the controller CON in the embodiment shown in FIG. 8 .
  • controller CON can be configured to perform the following methods:
  • Step S91 at the fourth time point, the fourth switch element corresponding to the anti-fuse memory cell sub-array where the anti-fuse memory cell to be tested is located outputs a second control signal to control the fourth switch element to be turned on;
  • Step S1 at a first time point, the word line of the anti-fuse memory cell to be tested outputs a first control signal to control the anti-fuse memory cell to be tested to be electrically connected to the bit line;
  • Step S2 obtain the output signal of the comparator at the second time point to determine the storage state of the anti-fuse storage unit to be tested;
  • the first time point and the fourth time point are both before the second time point.
  • the method shown in FIG. 5 may further include step S91, and the order of step S91 and step S1 may be exchanged.
  • the fourth time point may be before the first time point, or after the first time point, and may also be equal to the first time point, as long as the fourth time point and the first time point are both Before the second time point, the configured current path can be opened and configured before starting to detect the voltage of the first node N1 at the second time point.
  • the circuit includes the third switching element M3 of the above-mentioned embodiment
  • the above-mentioned third time point, the first time point, and the fourth time point are all before the second time point.
  • the order of controlling the third switching element M3 to be turned on, the fourth switching element M4m to be turned on, and the order of controlling the anti-fuse memory cell to be tested to be electrically connected to the bit line can be reversed, as long as it is completed before the voltage comparison result is obtained at the second time point .
  • the second control signal When the fourth switch element is a P-type transistor, the second control signal is at a low level; when the fourth switch element is an N-type transistor, the second control signal is at a high level.
  • the fourth switching element is other types of elements, the second control signal can also be other types of signals, which is not particularly limited in the present disclosure.
  • FIG. 10 is a schematic diagram of an anti-fuse memory cell in an embodiment of the present disclosure.
  • the anti-fuse memory cell 101 may include:
  • the first end of the selecting switching element M is connected to the bit line of the anti-fuse memory unit 101;
  • an anti-fuse element F the first end of the anti-fuse element F is connected to the second end of the selection switch element M;
  • control end of the selection switch element M and the control end of the anti-fuse element F are both connected to the controller.
  • the anti-fuse memory cell state detection circuit provided by the embodiment of the present disclosure provides a constant current for the first node by using the current supply module, reflects the resistance of the anti-fuse memory cell to be tested on the voltage of the first node, and provides a constant current for the first node.
  • the probability of voltage misjudgment can be reduced as much as possible, making the output of the comparator more accurate, and avoiding the resistance fluctuation of the anti-fuse memory cell and the switching voltage offset of the logic gate in the related art.
  • the storage state of the anti-fuse memory cell is misjudged.
  • a memory including the anti-fuse memory cell state detection circuit according to any one of the above.
  • the memory may be, for example, a DRAM memory.
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the resistance of the anti-fuse memory cell to be tested is reflected on the voltage of the first node by using a constant current, and a comparator is used to compare the voltage of the first node with the first reference voltage to determine the anti-fuse memory cell to be tested.
  • the resistance of the anti-fuse memory cell to be tested can be judged to determine the storage state of the anti-fuse memory cell to be tested, so that the inversion point can be accurately controlled and more accurate detection results can be obtained.
  • the offset leads to misjudgment of the memory state of the antifuse memory cell.

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Abstract

一种反熔丝存储单元状态检测电路（200）及应用该电路的存储器，该电路（200）包括：电流提供模块（21），连接第一节点（N1），用于提供恒定电流；反熔丝存储单元阵列（22），连接所述第一节点（N1），包括至少一条位线，所述位线连接多个反熔丝存储单元和所述第一节点（N1）；比较器（23）第一输入端连接所述第一节点（N1），第二输入端连接第一参考电压（Vtrip），用于检测所述反熔丝存储单元阵列（22）中待测反熔丝存储单元的存储状态。该电路（200）可以提高反熔丝存储单元存储状态检测的准确度。

Description

反熔丝存储单元状态检测电路及存储器
交叉引用
本公开要求于2020年07月16日提交的申请号为202010687695.0、名称为“反熔丝存储单元状态检测电路及存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，示例性而言，涉及一种反熔丝存储单元状态检测电路及应用该电路的存储器。
背景技术
一次性可编程存储(One time programmable，OTP)广泛应用于各类存储器中，用于实现损坏存储单元的冗余替换、电路模块的微调整等。常用的一次性可编程存储利用反熔丝存储单元的击穿或未击穿状态来进行信息存储。
通常仅通过简单的逻辑门电路(如反相器等)对反熔丝存储单元的击穿状态进行检测。在相关技术中，利用反相器来对反熔丝存储单元的击穿状态进行检测，如图1所示。如果待测反熔丝存储单元11属于被编程击穿的状态，通路电阻会比较小，那么在进行检测时，Node1节点上产生的电压较低，使得反相器的输出D_out为高；反之，如果待测反熔丝存储单元11属于未被编程击穿的状态，通路电阻会较大，Node1节点上产生的电压较高，超过反相器的翻转点，使得反相器的输出D_out为低。由于反熔丝存储单元被击穿后的电阻会在较宽范围内波动，以及工艺、电压、温度等因素对反相器等逻辑门电路的翻转点的影响，容易导致反熔丝存储单元的存储状态检测错误，造成芯片良率下降，因此亟需要一种性能更优的反熔丝存储单元状态检测电路。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种反熔丝存储单元状态检测电路及应用该电路的存储器，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的反熔丝存储单元的存储状态检测结果不准确的问题。
根据本公开的一个方面，提供一种反熔丝存储单元状态检测电路，包括：电流提供模块，连接第一节点，用于提供恒定电流；反熔丝存储单元阵列，连接所述第一节点，包括至少一条位线，所述位线连接多个反熔丝存储单元和所述第一节点；比较器，第一输入端连接所述第一节点，第二输入端连接第一参考电压，用于检测所述反熔丝存储单元阵列中 待测反熔丝存储单元的存储状态。
在本公开的一种示例性实施例中，所述电流提供模块包括：放大器，第一输入端连接第二参考电压，第二输入端连接第二节点，输出端连接第三节点；第一开关元件，第一端连接电源电压，第二端连接所述第二节点，控制端连接所述第三节点；参考电阻，第一端连接所述第二节点，第二端接地；第二开关元件，第一端连接所述电源电压，第二端连接所述第一节点，控制端连接所述第三节点。
在本公开的一种示例性实施例中，还包括：触发器，输入端连接所述比较器的输出端。
在本公开的一种示例性实施例中，所述多个反熔丝存储单元的字线和所述比较器的输出端均连接控制器。
在本公开的一种示例性实施例中，所述多个反熔丝存储单元的字线和所述触发器的输出端均连接控制器。
在本公开的一种示例性实施例中，所述控制器设置为：在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以控制所述待测反熔丝存储单元电连接至位线；在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；其中，所述第二时间点在所述第一时间点之后。
在本公开的一种示例性实施例中，所述参考电阻为ZQ校准电阻。
在本公开的一种示例性实施例中，所述参考电阻的第一端通过第三开关元件连接所述第二节点，所述第三开关元件的控制端连接控制器，所述控制器设置为在第三时间点控制所述第三开关元件导通，所述第三时间点在第二时间点之前。
在本公开的一种示例性实施例中，所述反熔丝存储单元阵列包括：多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；与所述反熔丝存储单元子阵列对应的多个第四开关元件，每个所述第四开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第四开关元件的第二端连接所述第一节点，所述第四开关元件的默认状态为关断状态。
在本公开的一种示例性实施例中，每个所述第四开关元件的控制端连接控制器，所述控制器设置为：在第四时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第四开关元件输出第二控制信号以控制所述第四开关元件导通；在第一时间点对所述待测反熔丝存储单元的字线输出第一控制信号以控制所述待测反熔丝存储单元电连接至位线；在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；其中，所述第四时间点在所述第二时间点之前。
根据本公开的一个方面，提供一种反熔丝存储单元状态检测方法，应用于上述的反熔丝存储单元状态检测电路，包括：在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以控制所述待测反熔丝存储单元电连接至位线；在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；其中，所述第二时间点在所述第一时间点之后。
在本公开的一种示例性实施例中，所述反熔丝存储单元阵列包括：多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；与所述反熔丝存储单元子阵列对应的多个第四开关元件，每个所述第四开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第四开关元件的第二端连接所述第一节点，每个所述第四开关元件的控制端连接控制器，所述第四开关元件的默认状态为关断状态；所述方法还包括：在第四时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第四开关元件输出第二控制信号以控制所述第四开关元件导通，所述第四时间点在所述第二时间点之前。
根据本公开的一个方面，提供一种存储器，包括如上述任意一项所述的反熔丝存储单元状态检测电路。
本公开实施例通过使用恒定电流将待测反熔丝存储单元的电阻反映在第一节点的电压上，使用比较器比对第一节点的电压和第一参考电压判断待测反熔丝存储单元的电阻，进而判断待测反熔丝存储单元的存储状态，可以使得翻转点得到精确控制、获得更准确的检测结果，避免由于反熔丝存储单元的击穿状态电阻波动和逻辑门的翻转点偏移导致对反熔丝存储单元的存储状态误判。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中反熔丝存储单元状态检测电路的示意图。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
图3是本公开一个实施例中反熔丝存储单元状态检测电路的电路示意图。
图4是图3所示实施例中反熔丝存储单元状态检测电路的另一种电路示意图。
图5是图4所示实施例中控制器CON实现的检测方法的流程图。
图6是本公开另一个实施例的反熔丝存储单元状态检测电路的电路示意图。
图7是本公开又一个实施例中反熔丝存储单元状态检测电路的电路示意图。
图8是本公开再一个实施例中反熔丝存储单元状态检测电路的电路示意图。
图9是图8所示实施例中控制器CON实现的检测方法的流程图。
图10是本公开实施例中反熔丝存储单元的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多示例性细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它状态下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图2，反熔丝存储单元状态检测电路200可以包括：
电流提供模块21，连接第一节点N1，用于提供恒定电流；
反熔丝存储单元阵列22，连接所述第一节点N1，包括多个反熔丝存储单元，所述多个反熔丝存储单元的位线连接所述第一节点N1；
比较器23，第一输入端连接所述第一节点N1，第二输入端连接第一参考电压Vtrip，用于检测反熔丝存储单元阵列22中待测反熔丝存储单元的存储状态。
图2所示的反熔丝存储单元阵列22和反熔丝存储单元的结构请参见图1和图10。
图3是本公开一个实施例中反熔丝存储单元状态检测电路的电路示意图。
参考图3，在一个实施例中，电流提供模块21可以包括：
放大器OP，第一输入端连接第二参考电压Vref，第二输入端连接第二节点N2，输出端连接第三节点N3；
第一开关元件M1，第一端连接电源电压VDD，第二端连接第二节点N2，控制端连接第三节点N3；
参考电阻Rref，第一端连接第二节点N2，第二端接地；
第二开关元件M2，第一端连接电源电压VDD，第二端连接第一节点N1，控制端连接第三节点N3。
在图3所示实施例中，如果第一开关元件M1、第二开关元件M2均为N型晶体管，放大器OP的第一输入端为同相输入端，第二输入端为反相输入端。如果第一开关元件M1、第二开关元件M2均为P型晶体管，放大器OP的第一输入端为反相输入端，第二输入端为同相输入端。本领域技术人员可以根据第一开关元件M1和第二开关元件M2的 设置自行确定放大器的连接方式，本公开不以此为限。
图4是图3所示实施例中反熔丝存储单元状态检测电路的另一种电路示意图。
参考图4，在一个实施例中，反熔丝存储单元阵列22和比较器23均连接控制器CON。示例性可以为，控制器CON连接反熔丝存储单元阵列22中的各反熔丝存储单元的字线，连接比较器23的输出端。
图5是图4所示实施例中控制器CON实现的检测方法的流程图。
参考图5，控制器CON可以设置为执行检测方法500，检测方法500可以包括：
步骤S1，在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以控制待测反熔丝存储单元电连接至位线；
步骤S2，在第二时间点获取比较器的输出信号以确定待测反熔丝存储单元的存储状态；
其中，第二时间点在第一时间点之后。
下面结合图2～图4对图5所述的控制方法进行说明。
在第一时间点控制待测反熔丝存储单元被选中后，第一节点N1存在等效电阻R，该等效电阻R既可以为待测反熔丝存储单元在击穿状态下的电阻R1也可以为在未击穿状态下的电阻R2。上述R1和R2均是统计结果，通过在反熔丝存储单元的研发和生产过程中对R1和R2进行统计分析得出。
电流提供模块21通过电流镜结构(包括放大器OP、第一开关元件M1、第二开关元件M2、参考电阻Rref)为第一节点N1提供恒定电流I，示例性可以为：通过放大器OP的设置，第二节点N2的电压会维持与放大器OP所连接的第二参考电压Vref相同的电压值，从而通过参考电阻Rref在第二节点N2所在的通路产生第一电流。由于第一开关元件M1和第二开关元件M2的设置，使得第一节点N1所在的通路产生第二电流，该第二电流与第一电流成恒定比例关系，该比例由第一开关元件M1和第二开关元件M2的尺寸、性能决定。即，第二电流同样为恒定电流，在本公开实施例中将第二电流称为恒定电流I。
该恒定电流I与第一节点N1的等效电阻R为第一节点N1提供电压V，V＝IR。由上述分析可知，在等效电阻R约等于R1或R2的情况下，第一节点N1的电压有V1＝IR1或者V2＝IR2，即第一节点N1的电压存在V1和V2两种情况。
通过使用比较器23将第一节点N1的电压与第一参考电压Vtrip进行比较，即可判断出待测反熔丝存储单元的电阻，进而判断待测反熔丝存储单元的存储状态。在一个实施例中，可以使用差分放大器实现比较器23的功能。例如，可以通过将差分放大器(例如为简单的两级比较器)设置为自偏置电路以避免过多的偏置电流走线并准确控制翻转点。
获取比较器23的输出信号的方法既可以为在第二时间点读取比较器23的输出信号，也可以为通过比较器23的使能引脚控制比较器23在第二时间点转变为使能状态，输出第一节点N1的电压与第一参考电压Vtrip的比较结果。
在一个实施例中，可以通过测量多个反熔丝存储单元以确定反熔丝存储单元在击穿状 态下的最大电阻和在未击穿状态下的最小电阻，并根据该击穿状态下的最大电阻和未击穿状态下的最小电阻确定V1和V2，将第一参考电压Vtrip设置为V1和V2的平均值，以尽可能降低误判几率，以提高检测准确度。
需要注意的是，为了避免Vtrip与V1或V2的差值的绝对值低于比较器23的差分电压输入阈值，可以在设计比较器23时，设计差分电压输入阈值小于V1与V2差值的二分之一，以使比较器23能够准确输出第一节点N1的电压与第一参考电压Vtrip的比较结果。此处所称的差分电压输入阈值指的是比较器能否识别出的正向输入端和反向输入端的最小电压差。
此外，为了防止在待测反熔丝存储单元未击穿状态下，第一节点N1处的电压V2超过比较器23的输入电压上限，可以通过设置合适的参考电阻Rref的阻值来调节恒定电流I，进而调节V2的值。
在一些实施例中，可以使用ZQ校准电阻作为参考电阻Rref。
图6是本公开另一个实施例的反熔丝存储单元状态检测电路的电路示意图。
参考图6，检测电路还可以包括：
第三开关元件M3，第一端连接参考电阻Rref的第一端，第二端连接第二节点N2，控制端连接控制器CON。
此时控制器CON可以设置为在第三时间点控制第三开关元件M3导通，该第三时间点在第二时间点之前，以对第一节点N1提供恒定电流。
当参考电阻通过ZQ校准电阻实现时，控制第三开关元件M3的开关状态可以控制ZQ校准电阻接入反熔丝存储单元状态检测电路或断开与反熔丝存储单元状态检测电路的连接，以保障ZQ校准电阻的正常工作的安全性。
此外，无论是否通过ZQ校准电阻实现参考电阻Rref，第三开关元件M3的设置均可以使电流提供模块21开始提供恒定电流I的时间点得到控制，即可以通过控制第三开关元件M3的导通控制恒定电流I出现的时间点，从而提高反熔丝存储单元状态检测的准确度。此时，第三时间点既可以在第一时间点之前，也可以在第一时间点之后。
图7是本公开又一个实施例中反熔丝存储单元状态检测电路的电路示意图。
参考图7，在本公开的其他实施例中，检测电路还可以包括：
触发器24，触发器24的输入端连接比较器23的输出端，触发器23的第一输出端和第二输出端均连接控制器CON。
触发器24例如可以为D触发器，用于对比较器23的输出信号进行锁存，以方便控制器CON读取。本领域技术人员可以根据需要自行设计触发器24，本公开不以此为限。
图8是本公开再一个实施例中反熔丝存储单元状态检测电路的电路示意图。
参考图8，在一个实施例中，第一节点N1可以用于连接多个位线，反熔丝存储单元阵列22可以包括：
多个反熔丝存储单元子阵列22m(m为位线序号)，每个反熔丝存储单元子阵列22m 对应一条位线BLm，每个反熔丝存储单元子阵列22m包括多个反熔丝存储单元；
与反熔丝存储单元子阵列22m对应的多个第四开关元件M4m，每个第四开关元件M4m的第一端连接对应的反熔丝存储单元子阵列22m的位线BLm，每个第四开关元件M4m的第二端连接第三节点N3，每个第四开关元件M4m的控制端连接控制器CON，第四开关元件M4m的默认状态为关断状态。
通过在第一节点N1连接多个反熔丝存储单元子阵列22m，共享反熔丝存储状态检测电路，来对多个反熔丝存储单元子阵列22m中的反熔丝存储单元的存储状态进行检测，可以极大的节省电路面积，在一个实施例中，第一节点N1可以同时连接16个位线，示例性方式如图9所示。
图9是图8所示实施例中控制器CON实现的检测方法的流程图。
参考图9，在图8所示电路中，控制器CON可以设置为执行以下方法：
步骤S91，在第四时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第四开关元件输出第二控制信号以控制该第四开关元件导通；
步骤S1，在第一时间点对待测反熔丝存储单元的字线输出第一控制信号控制待测反熔丝存储单元电连接至位线；
步骤S2，在第二时间点获取比较器的输出信号以确定待测反熔丝存储单元的存储状态；
其中，第一时间点和第四时间点均在第二时间点之前。
即图5所示的方法还可以包括步骤S91，步骤S91与步骤S1的顺序可以调换。
在图9所示实施例中，第四时间点可以在第一时间点之前，也可以在第一时间点之后，还可以与第一时间点相等，只要第四时间点和第一时间点均在第二时间点之前即可，以在第二时间点开始检测第一节点N1的电压前开启配置好电流通路。
此外，当电路包含上述实施例的第三开关元件M3时，上述第三时间点与第一时间点、第四时间点均在第二时间点之前。控制第三开关元件M3导通、第四开关元件M4m导通、控制待测反熔丝存储单元电连接至位线的顺序均可以调换，只要在第二时间点获取电压比较结果之前完成即可。
当第四开关元件为P型晶体管时，第二控制信号为低电平；当第四开关元件为N型晶体管时，第二控制信号为高电平。当第四开关元件为其他类型的元件时，第二控制信号也可以为其他类型的信号，本公开对此不作特殊限制。
图10本公开实施例中反熔丝存储单元的示意图。
参考图10，反熔丝存储单元101可以包括：
选择开关元件M，选择开关元件M的第一端连接反熔丝存储单元101的位线；
反熔丝元件F，反熔丝元件F的第一端连接于选择开关元件M的第二端；
其中，选择开关元件M的控制端和反熔丝元件F的控制端均连接于控制器。
本公开实施例提供的反熔丝存储单元状态检测电路通过使用电流提供模块为第一节 点提供恒定电流，将待测反熔丝存储单元的电阻反映在第一节点的电压上，对第一节点的电压与第一参考电压进行比较，可以尽量降低电压误判概率，使比较器的输出更为准确，避免相关技术中由于反熔丝存储单元的电阻波动和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。
根据本公开的一个方面，提供一种存储器，包括如上述任意一项所述的反熔丝存储单元状态检测电路。该存储器例如可以是DRAM存储器。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过使用恒定电流将待测反熔丝存储单元的电阻反映在第一节点的电压上，使用比较器比对第一节点的电压和第一参考电压判断待测反熔丝存储单元的电阻，进而判断待测反熔丝存储单元的存储状态，可以使得翻转点得到精确控制、获得更准确的检测结果，避免由于反熔丝存储单元的击穿状态电阻波动和逻辑门的翻转点偏移导致对反熔丝存储单元的存储状态误判。

Claims (13)

  1. 一种反熔丝存储单元状态检测电路，其中，包括：
    电流提供模块，连接第一节点，用于提供恒定电流；
    反熔丝存储单元阵列，连接所述第一节点，包括至少一条位线，所述位线连接多个反熔丝存储单元和所述第一节点；
    比较器，第一输入端连接所述第一节点，第二输入端连接第一参考电压，用于检测所述反熔丝存储单元阵列中待测反熔丝存储单元的存储状态。
  2. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述电流提供模块包括：
    放大器，第一输入端连接第二参考电压，第二输入端连接第二节点，输出端连接第三节点；
    第一开关元件，第一端连接电源电压，第二端连接所述第二节点，控制端连接所述第三节点；
    参考电阻，第一端连接所述第二节点，第二端接地；
    第二开关元件，第一端连接所述电源电压，第二端连接所述第一节点，控制端连接所述第三节点。
  3. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：
    触发器，输入端连接所述比较器的输出端。
  4. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述多个反熔丝存储单元的字线和所述比较器的输出端均连接控制器。
  5. 如权利要求3所述的反熔丝存储单元状态检测电路，其中，所述多个反熔丝存储单元的字线和所述触发器的输出端均连接控制器。
  6. 如权利要求4或5所述的反熔丝存储单元状态检测电路，其中，所述控制器设置为：
    在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以控制所述待测反熔丝存储单元电连接至所述位线；
    在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；
    其中，所述第二时间点在所述第一时间点之后。
  7. 如权利要求2所述的反熔丝存储单元状态检测电路，其中，所述参考电阻为ZQ校准电阻。
  8. 如权利要求7所述的反熔丝存储单元状态检测电路，其中，所述参考电阻的第一端通过第三开关元件连接所述第二节点，所述第三开关元件的控制端连接控制器，所述控制器设置为在第三时间点控制所述第三开关元件导通，所述第三时间点在第二时间点之前。
  9. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述反熔丝存储单元阵列包括：
    多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所 述反熔丝存储单元子阵列包括多个反熔丝存储单元；
    与所述反熔丝存储单元子阵列对应的多个第四开关元件，每个所述第四开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第四开关元件的第二端连接所述第一节点，所述第四开关元件的默认状态为关断状态。
  10. 如权利要求9所述的反熔丝存储单元状态检测电路，其中，每个所述第四开关元件的控制端连接控制器，所述控制器设置为：
    在第四时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第四开关元件输出第二控制信号以控制所述第四开关元件导通；
    在第一时间点对所述待测反熔丝存储单元的字线输出第一控制信号以控制所述待测反熔丝存储单元电连接至位线；
    在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；
    其中，所述第四时间点在所述第二时间点之前。
  11. 一种反熔丝存储单元状态检测方法，其中，应用于如权利要求1～8任一项所述的反熔丝存储单元状态检测电路，包括：
    在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以控制所述待测反熔丝存储单元电连接至位线；
    在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；
    其中，所述第二时间点在所述第一时间点之后。
  12. 如权利要求11所述的反熔丝存储单元状态检测方法，其中，所述反熔丝存储单元阵列包括：多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；与所述反熔丝存储单元子阵列对应的多个第四开关元件，每个所述第四开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第四开关元件的第二端连接所述第一节点，每个所述第四开关元件的控制端连接控制器，所述第四开关元件的默认状态为关断状态；
    所述方法还包括：
    在第四时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第四开关元件输出第二控制信号以控制所述第四开关元件导通，所述第四时间点在所述第二时间点之前。
  13. 一种存储器，其中，包括如权利要求1～10任一项所述的反熔丝存储单元状态检测电路。
PCT/CN2021/097868 2020-07-16 2021-06-02 反熔丝存储单元状态检测电路及存储器 WO2022012202A1 (zh)

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