WO2022009574A1 - 送信装置、通信システム、及び情報送信方法 - Google Patents

送信装置、通信システム、及び情報送信方法 Download PDF

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Publication number
WO2022009574A1
WO2022009574A1 PCT/JP2021/021296 JP2021021296W WO2022009574A1 WO 2022009574 A1 WO2022009574 A1 WO 2022009574A1 JP 2021021296 W JP2021021296 W JP 2021021296W WO 2022009574 A1 WO2022009574 A1 WO 2022009574A1
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WIPO (PCT)
Prior art keywords
information
transmission
transmission path
data
frame
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Ceased
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PCT/JP2021/021296
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English (en)
French (fr)
Japanese (ja)
Inventor
哲史 太田
俊久 百代
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2022534957A priority Critical patent/JP7716405B2/ja
Publication of WO2022009574A1 publication Critical patent/WO2022009574A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/16—Flow control; Congestion control in connection oriented networks, e.g. frame relay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/26—Flow control; Congestion control using explicit feedback to the source, e.g. choke packets
    • H04L47/266—Stopping or restarting the source, e.g. X-on or X-off
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/66—Remote control of cameras or camera parts, e.g. by remote control devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/04—Systems for the transmission of one television signal, i.e. both picture and sound, by a single carrier

Definitions

  • This disclosure relates to a transmission device, a communication system, and an information transmission method.
  • the transmission capacity of information that can be transmitted is fixed for the transmission path, and information that exceeds the transmission capacity cannot be transmitted.
  • the transmission capacity of the transmission path cannot be effectively utilized. Therefore, the amount of information of the information source to be transmitted on the transmission path is matched with the transmission capacity of the transmission path. Is desirable.
  • invalid data also called null data
  • the transmission device that transmits the image pickup signal of the vehicle-mounted camera is often arranged on the vehicle body surface away from the power supply, it is difficult to supply a sufficient power supply, and at the same time, the temperature conditions of the operating environment are severe. For this reason, in-vehicle cameras are required to reduce power consumption as much as possible.
  • the present disclosure provides a transmission device, a communication system, and an information transmission method that can reduce power consumption during information transmission.
  • a transmission device that transmits information generated by an information source and divided into blocks to a transmission path in frame units including a plurality of the blocks.
  • the amount of information to be transmitted is less than the transmission capacity of the transmission path, one block out of several blocks in the frame either stops sending information to the transmission path or within the frame.
  • a transmission device including a transmission unit for transmitting toggle data having a longer cycle of information transition than information other than the above-mentioned one block to the transmission path.
  • the transmission unit may transmit data of a specific signal logic to the transmission path or set the transmission path to high impedance within a period of stopping the transmission of information to the transmission path.
  • the transmission unit may set the destination address of the block that stops the transmission of information to the transmission path to an address different from the address of the receiving device that receives information via the transmission path.
  • the transmission unit has a scrambler that generates scrambled data obtained by scrambling the information generated by the information source regardless of whether or not the transmission of information to the transmission path is stopped. You may.
  • the transmission unit transmits a predetermined resynchronization pattern to the transmission path after the period for stopping the transmission of information to the transmission path has elapsed and before the transmission of information to the transmission path is resumed.
  • the resynchronization pattern may be used to perform synchronous reproduction processing of information received by the receiving device via the transmission path.
  • the transmission unit selects either one of the scrambled data and a predetermined resynchronization pattern used for synchronous reproduction processing of information received by the receiving device via the transmission path to the transmission path. It may have a selector to send.
  • the transmitting unit may have a scheduler that controls selection of the selector based on a control signal transmitted by the receiving device via the transmission path.
  • the transmission unit has a scrambler that generates scrambled data obtained by scrambling the information generated by the information source.
  • the scrambler A shift register having a plurality of registers for sequentially shifting serial data according to information generated by the information source, and a shift register. It has a logical operation unit that generates scrambled data by a predetermined logical operation between the data shifted by the shift register and the serial data input to the shift register.
  • the transmission unit may transition information transmitted to the transmission path at a cycle corresponding to the number of stages of the plurality of registers in the shift register.
  • the transmitter is continuously set to 1 for the number of bits corresponding to the number of the plurality of registers in the shift register, and the transmitter has the plurality of registers in the shift register.
  • Information in which 0 is continuously continued by the number of bits per minute may be transmitted to the transmission path.
  • the transmitter selects either the number of the plurality of registers in the shift register or the number of the plurality of registers-1 by a predetermined method. 1 is continuously continued by the number of bits of the minute, and the number of bits of the number of the plurality of registers-1 and the number of the plurality of registers-2 in the shift register are selected by a predetermined method. Information in which 0 continues for the number of times may be transmitted to the transmission path.
  • the transmitter has header information whose destination address is an address different from the address of the receiving device connected to the transmission path before transmitting the information to the transmission path. May be sent to the transmission path.
  • the header information may include identification information of the toggle data.
  • the transmitter is A pseudo-random number generator that generates a pseudo-random number signal,
  • One block out of several blocks in the frame may have a scrambler that generates the toggle data based on the pseudo-random number signal.
  • the information generated by the information source is selected, and in the one block, the pseudo-random number signal is selected.
  • An error correction processing unit that adds an error correction code to the information selected in the replacement unit, and an error correction processing unit.
  • a delay device that delays the pseudo-random number signal for a predetermined period is provided. The scrambler may generate the toggle data based on the output signal of the error correction processing unit and the output signal of the delay device in one block out of several blocks in the frame.
  • the predetermined period is a period from the generation of the pseudo-random number signal by the pseudo-random number device to the input of the output signal of the error correction processing unit to the scrambler.
  • the scrambler is an exclusive OR of the output signal of the error correction processing unit and the output signal of the delay device, or the output signal of the error correction processing unit and the above.
  • the toggle data may be generated by exclusive-OR with the inverted signal of the output signal of the delay device.
  • the pseudo-random number device has a shift register having a plurality of registers.
  • the scrambler is continuously followed by the first signal logic for the number of bits corresponding to the number of the plurality of registers in the shift register, and the plurality of blocks in the shift register.
  • the toggle data may be generated in which the second signal logic is continuously continued by the number of registers of 1-the number of bits per minute.
  • the pseudo-random number device has a shift register having a plurality of registers.
  • the scrambler is a number in which one of the number of the plurality of registers in the shift register and the number of the plurality of registers-1 is selected by a predetermined method in one block out of the number of blocks in the frame.
  • the first signal logic is continuously continued by the number of bits of a minute, and either the number -1 of the plurality of registers in the shift register-1 or the number 2 of the plurality of registers-2 is selected by a predetermined method.
  • the toggle data may be generated in which the second signal logic is continuously continued by the number of bits of a minute.
  • the scrambler may generate the toggle data in which the cycle is maximized or the cycle can be arbitrarily selected in one block out of several blocks in the frame.
  • the transmission unit may transmit information to the transmission path within the period allocated by TDD (Time Division Duplex).
  • TDD Time Division Duplex
  • the master device and A slave device that transmits information generated by an information source and divided into blocks according to an instruction from the master device to the master device via a transmission path in frame units including a plurality of the blocks is provided.
  • the slave device transmits information to the transmission path in one block out of several blocks in the frame.
  • a communication system is provided that has a transmission unit that stops the operation or sends toggle data having a longer cycle of information transition than information other than the one block in the frame to the transmission path.
  • it is an information transmission method in which information generated by an information source and divided into blocks is transmitted to a transmission path in frame units including a plurality of the blocks.
  • the amount of information generated by the information source is less than the transmission capacity of the transmission path, one block out of several blocks in the frame either stops sending information to the transmission path.
  • an information transmission method for transmitting toggle data having a longer cycle of information transition than information in a block other than the one block to the transmission path is provided.
  • the figure explaining the TDD method The block diagram which shows an example of the internal structure of the downlink transmission part of FIG.
  • the figure which shows an example of the data structure of a frame The figure which shows the data structure of the frame output from a framer.
  • the figure which shows an example of the output level when the modulation method is NRZ.
  • the figure which shows an example of the output level when the modulation method is PAM4.
  • a block diagram showing an example of the internal configuration of the resynchronization pattern adder The figure which shows the output data of the framer by the 1st improvement example. The figure which shows the scramble data by the 1st improvement example. The figure which shows the output data of the resynchronization pattern adder by the 1st improvement example. The figure which shows the output data of the output amplifier by the 1st improvement example.
  • the block diagram of the 2nd improvement example of the downlink transmission part of FIG. The block diagram which shows an example of the internal structure of the LDTS replacement part. The figure which shows the data structure of the scramble data output from a scrambler. The figure which shows the output data of the LDTS replacement part.
  • the block diagram which shows the internal structure of one modification of the LDTS generator of FIG. The figure which shows the output data of the LDTS replacement part.
  • the block diagram of the 3rd improvement example of the downlink transmission part of FIG. The block diagram which shows an example of the internal structure of the LDTS replacement part.
  • the block diagram of the 1st modification of the LDTS replacement part The timing diagram of the downlink transmission part corresponding to the LDTS replacement part of FIG.
  • the figure which shows the output data of the LDTS replacement part The figure which shows the output data of the FEC part.
  • FIG. 1 is a block diagram showing a schematic configuration of the communication system 1 according to the present disclosure.
  • the communication system 1 of FIG. 1 has a first information source (Source # 1) 2, a first sink device (Sink # 2) 3, a first SerDes unit (SerDes1) 4, and a transmission path (cable). It includes a 5, a second SerDes unit (SerDes2) 6, a second sink device (Sink # 3) 7, and a second information source (Source # 4) 8.
  • Each of the first SerDes unit 4 and the second SerDes unit 6 functions as a transmitting device and a receiving device. More specifically, when the first SerDes unit 4 functions as a transmitting device, the second SerDes unit 6 functions as a receiving device.
  • the first SerDes unit 4 functions as a receiving device.
  • the second sink device 7 and the second information source 8 may be built in, for example, a host device.
  • the first SerDes unit 4 and the second SerDes unit 6 are connected by one cable (transmission path) 5, and signals are transmitted in both directions via this cable 5. More specifically, the first SerDes unit 4 and the second SerDes unit 6 transmit signals in both directions by, for example, a TDD (Time Division Duplexing) method.
  • TDD Time Division Duplexing
  • the signal path on the transmission path 5 for serially transmitting information from the first SerDes unit 4 to the second SerDes unit 6 is called a downlink or a forward channel
  • the signal path on the transmission path 5 that serially transmits information to the unit 4 is called an uplink or a reverse channel. Further, in the present embodiment, it is assumed that the downlink has a larger amount of information than the uplink.
  • the first SerDes unit 4 has a downlink transmission unit (DnTx) 11 and an uplink reception unit (UpRx) 12.
  • the second SerDes unit 6 has a downlink receiving unit (DnRx) 13 and an uplink transmitting unit (UpTx) 14.
  • the first information source 2 has, for example, one or more sensors. Each sensor outputs sensing information.
  • the sensor may include an image sensor.
  • the image sensor outputs the captured image pickup signal.
  • the image pickup signal may be a moving image signal or a still image signal.
  • various sensing information output from the first information source 2 are collectively referred to as “information”.
  • the information output from the first information source 2 is input to the downlink transmission unit 11 in the first SerDes unit 4.
  • the downlink transmission unit 11 performs packet processing on the information from the first information source 2, converts it into serial data, and sends it to the transmission path 5.
  • the information output from each information source is transmitted to the downlink transmission unit 11 in the first SerDes unit 4.
  • the uplink receiving unit 12 in the first SerDes unit 4 receives the serial data transmitted by the uplink on the transmission path 5 and converts it into parallel data.
  • This parallel data is received by the first sink device 3.
  • the parallel data received by the first sink device 3 includes a control signal from the second information source 8.
  • the control signal may include information for controlling operating conditions, operating modes, and the like of various sensors such as image sensors.
  • the control signal is transmitted and received between the first sink device 3 and the uplink receiving unit 12, for example, by I2C (Inter-Integrated Circuit) communication or GPIO (General Purpose Input / Output).
  • the second information source 8 transmits information to be transmitted to the first sink device 3 to the uplink transmission unit 14 in the second SerDes unit 6. Further, the downlink receiving unit 13 in the second SerDes unit 6 converts the received serial data into parallel data and transmits it to the second sink device 7.
  • FIG. 2 is a diagram illustrating the TDD method.
  • the sensing data of various sensors including, for example, an image sensor is transmitted from the first information source 2 to the second sink device 7 via the transmission path 5.
  • Sensing data such as an image pickup signal is transmitted by a downlink.
  • the control signal transmitted by the second information source 8 to the first sink device 3 is transmitted by the uplink.
  • the amount of downlink information on the transmission path 5 is much larger than the amount of uplink information. Therefore, as shown in FIG.
  • the period for transmitting and receiving downlink information is made longer than the period for transmitting and receiving uplink information, and the amount of information transmitted and received differs between the downlink and the uplink. ..
  • the upling information (control signal from the second information source 8 and the like) is transmitted and received at the times t1 to t2, and the down leak information (first information source 2) is transmitted and received at the subsequent times t3 to t4. (Sensing data from) is sent and received. Since the period from time t3 to t4 is longer than the period from time t1 to t2, the amount of downlink information can be increased more than the amount of uplink information.
  • the period from time t0 to t4 is 1 TDD cycle, and a plurality of TDD cycles are repeated.
  • FIG. 3 is a block diagram showing an example of the internal configuration of the downlink transmission unit 11 of FIG.
  • the downlink transmission unit 11 of FIG. 3 has a buffer 21, a framer 22, a scheduler 23, a parallel-serial converter (P / S) 24, a scrambler 25, a mapper 26, and an output amplifier 27. ..
  • the buffer 21 temporarily holds the information output from the first information source 2.
  • the buffer 21 is provided for adjusting the transmission speed. Generally, since the data rate of the sensing data output by various sensors included in the first information source 2 and the transmission rate of the transmission path 5 are different, the speed is adjusted by the buffer 21 and the framer is adjusted at an appropriate timing. Information from the first information source 2 is transmitted to 22. Normally, the transmission rate of the transmission path 5 is made faster than the data rate of the first information source 2.
  • the framer 22 generates packet data in frame units based on the information transmitted in block units from the first information source 2.
  • the data structure of the packet data constituting the frame will be described later.
  • the P / S 24 converts the packet data generated by the framer 22 into serial data.
  • the scrambler 25 performs a predetermined scramble process on the serial data output from the P / S 24 to generate scrambled data.
  • the scrambler 25, for example, performs a process of randomizing the timing at which the signal logic of serial data changes.
  • the scrambler 25 may generate scrambled data obtained by scrambling the information generated by the first information source 2, regardless of whether or not the transmission of information to the transmission path 5 is stopped. good.
  • the mapper 26 converts the signal level according to the modulation method (NRZ, PAM4, etc.).
  • the output signal of the mapper 26 is input to the output amplifier 27.
  • the output amplifier 27 adjusts the gain of the output signal of the mapper 26 and sends it to the transmission path 5.
  • FIG. 4 is a diagram showing an example of the data structure of the frame. As shown, the frame has multiple containers. Each container is created in block units within the frame. Each container has a header, a payload, and a parity.
  • the header contains address information indicating the transmission destination of the payload.
  • the payload is the body of the data contained in the signal being sent and received.
  • the payload includes an OAM (Operations, Administration, Maintenance) for controlling the first SerDes unit 4 and the second SerDes unit 6.
  • Parity is a bit or bit string for error detection or error correction processing of the payload.
  • the header has data identification information, a destination address, and other information. Data identification information is information that identifies the type of data in the payload.
  • the destination address is the address of the receiving device that receives the frame.
  • FIG. 5 is a diagram showing a data structure of a frame output from the framer 22.
  • FIG. 5 shows an example in which there is another information source (hereinafter referred to as nth information source 2a (Source # n)) in addition to the first information source 2 in the communication system 1.
  • nth information source 2a Source # n
  • FIG. 5 shows an example in which the ratio of the data rates of the first information source 2, the nth information source 2a, and the first SerDes unit 4 is 3: 1: 4.
  • the framer 22 is temporarily output from the first information source 2 and the nth information source 2a in accordance with the timing of the payload in the container based on the control from the scheduler 23.
  • the framer 22 stores the information from the first information source 2 in the payload of the container (Container # 1 to # 3), and also stores the data identification information (for example, a video signal) and the destination address (here, in this case) in the header. , The address of the second sink device 7 (Sink # 3)), and the parity is added to complete the container.
  • the framer 22 sequentially generates three containers (Containers # 1 to # 3) based on the information output from the first information source 2.
  • the framer 22 stores the information from the nth information source 2a in the payload of the container (Container # 4), and also stores the data identification information (for example, an audio signal) and the destination address (second sink device 7) in the header. (Sink # 3), parity is added to complete the container.
  • the framer 22 generates and outputs one container (Container # 4) based on the information output from the nth information source 2a.
  • the framer 22 includes three containers (Container # 1 to # 3) based on the information from the first information source 2 and one container (Container # 4) based on the information from the nth information source 2a. Is repeated in order to generate. This will generate a frame containing multiple containers. The framer 22 outputs the generated containers in order.
  • P / S24 converts the containers output in order from the framer 22 into serial data. This serial data is input to the scrambler 25 in bit units.
  • FIG. 6 is a block diagram showing an example of the internal configuration of the scrambler 25.
  • the scrambler 25 includes a shift register 31 in which L registers (L is an integer of 2 or more) connected in series, a first XOR calculator 32, and a second XOR calculation. It has a vessel 33 and.
  • the first XOR calculator 32 outputs the operation result of the exclusive OR of the output data of the register of the final stage of the shift register 31 and the output data of some registers other than the final stage.
  • the output data of the first XOR calculator 32 is input to the register of the first stage and the second XOR calculator 33.
  • the shift register 31 randomly generates serial data of 1 to 2 L-1 excluding zero. Can be done. In this way, the shift register 31 and the first XOR calculator 32 can generate a pseudo-random number.
  • the second XOR calculator 33 outputs the calculation result of the exclusive OR of the serial data output from the P / S 24 and the output data of the first XOR calculator 32. Since the output data of the first XOR calculator 32 is a pseudo-random number, the output data of the second XOR calculator 33 is also pseudo-randomized serial data.
  • the scrambler 25 outputs the output data of the second XOR calculator 33 as scrambled data.
  • the information output from the first information source 2 is a video signal, it can be serial data in which bits of the same signal logic (0 or 1) continue for a long time.
  • serial data is received by the downlink receiving unit (DnRx) 13, there is a possibility that synchronous reproduction of the received data cannot be performed correctly because there is no change point in the signal logic. Therefore, in the scrambler 25, the serial data based on the information from the first information source 2 is intentionally converted into a pseudo-random number to forcibly cause a change in the signal logic. As a result, the receiving side can normally perform the synchronous reproduction processing of the received data.
  • FIG. 7A is a diagram showing an example of an output level when the modulation method is NRZ (non-return-to-zero)
  • FIG. 7B is a diagram showing an example of an output level when the modulation method is PAM4 (4 Pulse Amplitude Modulation). Is.
  • NRZ as shown in FIG. 7A, if the scramble data is 1, the output level is set to a predetermined voltage level A, and if it is 0, the output level is set to 0.
  • PAM4 Pulse Amplitude Modulation
  • the output level is set to a predetermined voltage level B if two consecutive bits of scrambled data are (1,0), and the output level is set to (1,1). Is set to 2/3 of B, if it is (0,1), the output level is set to 1/3 of B, and if it is (0,0), the output level is set to 0.
  • the serial data whose output level has been adjusted by the mapper 26 is transmitted to the transmission path 5 via the output amplifier 27.
  • the transmission path 5 has a transmission capacity for sequentially transmitting four containers including three containers from the first information source 2 and one container from the nth information source 2a. Indicated. For example, when the nth information source 2a does not output information, the framer 22 generates only three containers even though the transmission path 5 has the transmission capacity for four containers, so that the transmission efficiency is high. Will get worse.
  • FIG. 8 is a diagram showing a data structure of a frame output from the framer 22 when the nth information source 2a does not output information.
  • the buffer 21 outputs null data, which is invalid data, at a time when the nth information source 2a should output information. Therefore, the payload of the container (Container # 4) contains null data, and the data identification information in the header becomes null.
  • the container containing null data By providing a container containing null data, it is possible to transmit information in an amount of information commensurate with the transmission capacity of the transmission path 5, but the container containing null data is meaningless information and only wastes power consumption. No. Therefore, the internal configuration of the downlink transmission unit 11 in FIG. 3 is partially changed so that power consumption is not wasted when the amount of information to be transmitted is smaller than the transmission capacity of the transmission path 5. desirable.
  • the first improvement example to the third improvement example in which the internal configuration of the downlink transmission unit 11 of FIG. 3 is changed will be described in order.
  • FIG. 9 is a block diagram of a first improvement example of the downlink transmission unit 11 of FIG.
  • the downlink transmission unit 11 of FIG. 9 has a resync pattern adder 28 in addition to the configuration of FIG.
  • the resynchronization pattern adder 28 stops sending information to the transmission path 5 in one block out of several blocks in the frame. do.
  • the resynchronization pattern adder 28 processes the scramble data output from the scrambler 25, and transmits the processed serial data to the mapper 26.
  • the resynchronization pattern adder 28 determines the timing at which the transmission of information to the transmission path 5 is stopped based on the control from the scheduler 23.
  • FIG. 10 is a block diagram showing an example of the internal configuration of the resynchronization pattern adder 28.
  • the resynchronization pattern adder 28 has a resynchronization pattern generator 34 and a selector 35.
  • the resynchronization pattern generator 34 generates a resynchronization pattern after stopping the transmission of information to the transmission path 5 and before resuming the information to the transmission path 5.
  • the resynchronization pattern is received by a receiving device (downlink receiving unit (DnRx) 13) that receives information, and is used for performing synchronous reproduction processing of information.
  • DnRx downlink receiving unit
  • the selector 35 selects either the scramble data output from the scrambler 25 or the resynchronization pattern generated by the resynchronization pattern generator 34 based on the timing control by the scheduler 23.
  • the data selected by the selector 35 is transmitted to the mapper 26.
  • the ratio of the transmission rate per unit time of the first information source 2 and the transmission device is 3: 4. Therefore, by stopping the transmission of one container for the four containers, the transmission rate of the first information source 2 and the transmission rate of the transmission device can be substantially matched.
  • 11A, 11B, 11C and 11D are timing diagrams of each part in the downlink transmission part 11 according to the first improvement example.
  • information from the first information source 2 temporarily held in the buffer 21 is sequentially input to the framer 22, and the input information is stored in the payload of the container.
  • data identification information, destination address, and parity are input to the header of the container.
  • a null is input, and an invalid address (address # X) that does not exist in the communication system 1 is input to the destination address. Since this container transmits null data to an invalid address, error correction processing is stopped for the purpose of reducing power consumption as much as possible. Therefore, parity is not required and is left blank.
  • the receiving side can ignore this container and omit the receiving process.
  • one of the four consecutive containers has invalid data, but the ratio of the containers that make invalid data is the amount of information of the first information source 2 and the transmission of the transmission path 5. It depends on the relationship with the capacity, and depending on the relationship, the ratio may be different from that in FIG. 11A.
  • the timing control signal from the scheduler 23.
  • the scheduler 23 can also generate a timing control signal based on the setting information from the second information source 8.
  • the framer 22 outputs the individual containers constituting the frame in order.
  • the P / S 24 sequentially converts the containers output from the framer 22 into serial data.
  • the scrambler 25 scrambles the serial data to generate scrambled data. As shown in FIG. 11B, scramble data is generated for each container output from the framer 22.
  • the scrambler 25 generates scrambled data corresponding to null data for one of the four containers.
  • the resynchronization pattern adder 28 removes scrambled data corresponding to null data based on the timing control signal from the scheduler 23. As a result, the transmission of information from the first SerDes unit 4 to the second SerDes unit 6 is stopped. While the transmission of information is stopped, the downlink signal logic on the transmission path 5 is fixed to 0 or 1 or set to high impedance. Therefore, the energy consumption on the transmission path 5 can be minimized.
  • the resynchronization pattern adder 28 transmits a resynchronization pattern having a predetermined time length to the transmission path 5 after temporarily stopping the transmission of information and before resuming the transmission of information. do.
  • the resynchronization pattern is preferably a randomized pattern such as PRBS (Pseudorandom Binary Sequence).
  • PRBS Physical Binary Sequence
  • the resynchronization pattern includes a part where the signal logic of 0 and 1 changes, and the receiving side receiving the resynchronization pattern uses the resynchronization pattern to synchronously reproduce the information received thereafter.
  • a clock signal can be generated.
  • the resynchronization pattern adder 28 outputs the corresponding scrambled data as it is for the container corresponding to the valid data.
  • the mapper 26 adjusts the output level of the output data of the resynchronization pattern adder 28 according to the modulation method.
  • the output amplifier 27 adjusts the gain of the output data of the mapper 26 and then sends the data to the transmission path 5. As shown in FIG. 11D, the output amplifier 27 temporarily stops the transmission of information during the transmission period of the null data container, sets the signal level of the transmission path 5 to fixed or high impedance, and then sets the signal level of the information. Before resuming transmission, the resynchronization pattern is transmitted to the transmission path 5.
  • the downlink transmission unit 11 transmits a container of invalid information in the frame.
  • the transmission of information to the transmission path 5 is temporarily stopped, and then the resynchronization pattern is transmitted to the transmission path 5 and then the transmission of information is resumed before the transmission of information is resumed.
  • the receiving side since it is not necessary to send invalid information to the transmission path 5, energy consumption during transmission can be suppressed.
  • the resynchronization pattern is transmitted to the transmission path 5 before resuming the transmission of the information to the transmission path 5, the receiving side can generate a clock for synchronous reproduction of the information based on the resynchronization pattern. .. Therefore, when the transmission of information to the transmission path 5 is temporarily stopped and then the transmission of information is resumed, the receiving side can reliably perform the synchronous reproduction process of the information.
  • FIG. 12 is a block diagram of a second improvement example of the downlink transmission unit 11 of FIG.
  • the downlink transmission unit 11 of FIG. 12 has an LDTS replacement unit (Low Density Toggle Signal Replacer) 36 instead of the resynchronization pattern adder 28 of FIG.
  • the LDTS replacement unit 36 When the amount of information to be transmitted is smaller than the transmission capacity of the transmission path 5, the LDTS replacement unit 36 has more information in one block out of several blocks in the frame than in information other than one block in the frame.
  • Generate toggle data with a long transition cycle That is, in one block out of several blocks in the frame, the cycle of information transition is made longer.
  • such toggle data with a long cycle is referred to as low density (or low cycle) toggle data.
  • the transition of information means that the signal logic on the transmission path 5 changes from 0 to 1 or from 1 to 0.
  • FIG. 13 is a block diagram showing an example of the internal configuration of the LDTS replacement unit 36.
  • the LDTS substitution unit 36 has an LDTS generator 37 for generating toggle data (hereinafter, also referred to as LDTS) and a selector 38.
  • the toggle data generated by the LDTS generator 37 is data in which the signal logic changes at a cycle corresponding to the number of connection stages L of the registers connected in series in the shift register 31 shown in FIG. 6 in the scrambler 25.
  • the LDTS generator 37 in one block out of several blocks in the frame, 1 is continuously continued by the number of bits corresponding to the number of the plurality of registers in the shift register 31, and the LDTS generator 37 is in the shift register 31. Generates toggle data in which 0 continues for the number of multiple registers of -1 minute number of bits.
  • the LDTS generator 37 determines either the number of a plurality of registers in the shift register 31 or the number of a plurality of registers -1. 1 is continuously continued for the number of bits selected by the method, and either the number of multiple registers-1 or the number of multiple registers-2 in the shift register 31 is selected by a predetermined method. Toggle data in which 0 is continuously continued for the number of bits of a minute may be generated. Further, as the method for performing the above-mentioned selection, the LDTS generator 37 can use, for example, a method of randomly selecting using a random number generator, a method of selecting based on a preset set value, or the like.
  • the ratio of the transmission rate per unit time of the first information source 2 and the transmission device is 3: 4.
  • FIG. 14A is a diagram showing a data structure of scramble data output from the scrambler 25.
  • the scrambled data corresponding to one container (Container # 4) containing invalid information is arranged after the scrambled data corresponding to each of the three containers (Container # 1 to # 3) containing valid information.
  • the scramble data corresponding to these four containers is sequentially output from the scrambler 25.
  • the payload of the container (Container # 4) containing invalid information contains invalid data, the data identification information in the header is null, and the destination address may be set to an address that does not exist in communication system 1.
  • FIG. 14B is a diagram showing output data of the LDTS replacement unit 36.
  • the LDTS replacement unit 36 leaves the header of the container (Container # 4) containing the null data as it is by the timing control signal from the scheduler 23. This is a difference from the fact that in the first improvement example, the header of the container containing null data was removed as shown in FIG. Further, the LDTS replacement unit 36 inserts toggle data (LDTS) whose signal logic changes at a low density into the container instead of the payload and parity of the container containing null data.
  • LDTS toggle data
  • the LDTS replacement unit 36 is provided on the rear side of the scrambler 25, the header portion of the scrambled data corresponding to the container containing the null data is left as it is, and the portion corresponding to the payload and parity of the container is lowered. Replace with density toggle data.
  • the reason why the header is left as it is is that the second sink device 7 that has received the low-frequency toggle data can grasp the type of the received toggle data.
  • the period in which 1 and 0 of the toggle data continue depends on the number of connection stages L of the register 30 of the shift register 31 shown in FIG. 6 in the scrambler 25.
  • the shift register 31 shown in FIG. 6 shifts serial data between a plurality of registers for each clock signal cycle. Therefore, the maximum duration of the output data "1" of the shift register 31 is the number of bits of the number of connection stages L of the register 30, and the maximum duration of the output data "0" is the number of bits of the number of connection stages L-1 of the register. It is a number. Therefore, in the output data of the shift register 31, the toggle ratio between 1 and 0 is minimized when 1 continues for L bits and 0 continues for L-1 bits. Therefore, the LDTS generator 37 generates toggle data in which 1 is followed by L bits and 0 is followed by L-1 bits.
  • the LDTS replacement unit 36 outputs the scrambled data corresponding to the container containing no null data as it is, and the scrambled data corresponding to the container containing null data leaves the header as it is, and the payload and the parity part of the container are output by the LDTS generator 37. Replace with the generated toggle data and output.
  • the output data of the LDTS replacement unit 36 is input to the mapper 26, converted into a signal level according to the modulation method, input to the output amplifier 27, gain-adjusted, and then sent to the transmission path 5.
  • the output amplifier 27 sends the data of all the containers corresponding to all the information output by the first information source 2 to the transmission path 5.
  • the toggle data having the minimum toggle ratio of 1 and 0 is used instead of the payload and parity of the container while leaving the header as it is. Is sent to the transmission path 5. Therefore, in the second SerDes unit 6 that has received the header corresponding to this toggle data, the header recognizes that the toggle data is the data for reproduction synchronization, and the toggle data is used as the clock signal for synchronization reproduction. Can be generated, and then when the transmission of information is resumed, the synchronous reproduction process can be normally performed based on the toggle data.
  • the LDTS generator 37 of FIG. 13 always generates toggle data in which 1 is followed by L bits and 0 is followed by L-1 bits. Therefore, the frequency of the toggle data becomes fixed, and there is a possibility that EMI (ElectroMagneticInterference) noise caused by this frequency may be generated. Therefore, the frequency of the toggle data may be randomly changed while not increasing the energy consumption in the transmission path 5.
  • EMI ElectroMagneticInterference
  • FIG. 15 is a block diagram showing an internal configuration of a modification of the LDTS generator 37 of FIG. 13, and FIG. 16 is a diagram showing output data of the LDTS replacement unit 36.
  • the LDTS generator 37 of FIG. 15 has an LDTS generator 37a having a configuration different from that of the LDTS generator 37 of FIG.
  • the selector 38 of FIG. 15 is similar to the selector 38 of FIG.
  • the LDTS generator 37a of FIG. 15 has a duration of L-the number of connection stages of a plurality of registers constituting the shift register 31 in the scrambler 25 or one less than that. Any one of 1 is set to the number of bits for the number selected by a predetermined method. Further, each time the toggle data outputs "0", the duration thereof is set to the number of bits corresponding to the number of bits selected by a predetermined method for L-1 or L-2.
  • the toggle data included in the output data of the LDTS replacement unit 36 is not likely to be biased to a specific frequency.
  • the toggle data generated by the LDTS generator 37a of FIG. 15 has a slightly higher toggle rate than the toggle data generated by the LDTS generator 37 of FIG. 13, but is much more than the scrambled data containing valid information.
  • the toggle ratio of 1 and 0 can be reduced, and power consumption can be suppressed.
  • the downlink transmission unit 11 when the downlink transmission unit 11 according to the second improvement example transmits the information of the container including the null data to the transmission path 5, the toggle data having a sufficiently small toggle rate and the toggle data are identified. Since the header for this purpose is transmitted to the transmission path 5, the power consumption on the transmission path 5 can be sufficiently reduced.
  • FIG. 17 is a block diagram of a third improvement example of the downlink transmission unit 11 of FIG.
  • the downlink transmission unit 11 of FIG. 17 includes a PRBS generator (pseudo-random number generator) 41, an LDTS replacement unit 42, and an FEC (Forward Error Correction) unit 43. It has a delay device 44.
  • the PRBS generator 41 generates a pseudo-random number bit string.
  • the internal configuration of the PRBS generator 41 is, for example, as in FIG. 6, exclusively for a shift register having a plurality of registers, the output of the register in the final stage in the shift register, and the output of any register other than the final stage. It has an XOR calculator that calculates the logical sum, and the output signal of the XOR calculator is input to the first-stage register in the shift register. Since the specific internal configuration of the PRBS generator 41 is not limited, various modifications can be considered.
  • the LDTS replacement unit 42 selects the pseudo-random number bit string generated by the PRBS generator 41 in one block out of several blocks in the frame, and selects the container output from the framer 22 in the other blocks.
  • FIG. 18 is a block diagram showing an example of the internal configuration of the LDTS replacement unit 42.
  • FIG. 19A is a diagram showing an example of a container output from the framer 22.
  • An invalid address not used in the communication system 1 is stored in the destination address of the header of the container corresponding to one block out of several blocks in the frame, and null data is stored in the payload. By storing an invalid address in the destination address, the reception process on the receiving side can be simplified and the power consumption can be reduced.
  • the LDTS replacement unit 42 in FIG. 18 includes an inverter 45, a first selector 46, a counter 47, and a second selector 48.
  • the inverter 45 inverts the pseudo-random number bit string generated by the PRBS generator 41.
  • the output of the inverter 45 is referred to as an inverted pseudo-random number bit string.
  • the counter 47 alternately counts for L bits and counts for L-1 bits.
  • the first selector 46 selects an inverted pseudo-random number bit string while the counter 47 is counting for L bits, and selects a pseudo-random number bit string while counting for L-1 bits.
  • the second selector 48 selects the output signal of the container or the first selector 46 output from the framer 22 based on the control signal from the scheduler 23.
  • the signal selected by the second selector 48 is the output signal of the LDTS replacement unit 42.
  • FIG. 19B is a diagram showing an example of output data of the LDTS replacement unit 42. As shown in FIG. 19B, in one block out of several blocks in the frame, the inverted pseudo-random number bit string for L bits and the pseudo-random number bit string for L-1 bits are output alternately.
  • an inverted pseudo-random number bit string! It is expressed as PRBS
  • the pseudo-random number bit string is expressed as PRBS.
  • the FEC unit 43 adds an error correction code to the output signal of the LDTS replacement unit 42.
  • the P / S 24 converts the output signal of the FEC unit 43 into serial data.
  • FIG. 19C is a diagram showing an example of the output signal of the FEC unit 43.
  • the FEC unit 43 adds an error correction code (Parity) to each container corresponding to each block. For example, an error correction code is added to the end of the pseudo-random number bit string replaced by the LDTS replacement unit 42.
  • Parity error correction code
  • the delay device 44 is a pseudo-random number bit string output from the PRBS generator 41 only for the time required for the pseudo-random number bit string output from the PRBS generator 41 to pass through the LDTS substitution unit 42, the FEC unit 43, and the P / S 24. To delay.
  • the scrambler 25 calculates the exclusive OR of the serial data output from the P / S 24 and the pseudo-random number bit string output from the delay device 44. More specifically, the scrambler 25 is an exclusive OR of the inverted pseudo-random number bit string in the serial data and the pseudo-random number bit string delayed by the delay device 44 for L bits in one block in the frame. A certain 1 is output, and for the next L-1 bit, the operation of outputting 0, which is the exclusive OR of the pseudo-random number bit string in the serial data and the pseudo-random number bit string delayed by the delay device 44, is alternately performed. repeat. As a result, the scrambler 25 outputs low-density toggle data in one block out of several blocks in the frame.
  • the scrambler 25 calculates the exclusive OR of the container output from the framer 22 and the pseudo-random number bit string delayed by the delay device 44, except for one block out of several blocks in the frame. As a result, the scrambler 25 scrambles the container output from the framer 22.
  • the output data of the scrambler 25 is adjusted in output level by the mapper 26 according to the modulation method, gain-adjusted by the output amplifier 27, and transmitted to the transmission path 5.
  • FIG. 19D is a diagram showing an example of scramble data output from the scrambler 25.
  • the scrambler 25 in one block out of several blocks in the frame, "1" is followed by the number of L bits which is the number of connection stages of the shift register 31 in the PRBS generator 41, and "0" is followed by L-1 bits. Toggle data is output.
  • the LDTS replacement unit 42 of FIG. 18 may be provided instead of the LDTS replacement unit 42 of FIG. 18, the LDTS replacement unit 42 of the first modification shown in FIG. 20 may be provided.
  • the LDTS replacement unit 42 of FIG. 20 has an inverter 51, a first counter 52, a second counter 53, a first selector 54, and a second selector 55.
  • the inverter 51 outputs an inverted pseudo-random number bit string obtained by inverting the pseudo-random number bit string generated by the PRBS generator 41.
  • the first counter 52 counts L bits or L-1 bits by a predetermined method.
  • the second counter 53 counts L-1 bits or L-2 bits by a predetermined method.
  • the first selector 54 continues to select the inverted pseudo-random number bit string output from the inverter 51 while the first counter 52 counts L bits or L-1 bits. Next, while the second counter 53 counts the L-1 bit or the L-2 bit, the selection of the pseudo-random number bit string is continued. The first selector 54 alternately selects the inverted pseudo-random number bit string and the pseudo-random number bit string.
  • the second selector 55 selects the output data of the first selector 54 for one block out of several blocks in the frame, and the frame for the remaining blocks. Select the container output from.
  • FIG. 21A to 21D are timing diagrams of the downlink transmission unit 11 corresponding to the LDTS replacement unit 42 of FIG. 20.
  • FIG. 21A is the output data of the framer 22, which is the same as that of FIG. 19A.
  • FIG. 21B is the output data of the LDTS replacement unit 42, and data different from that of FIG. 19B is output for one block out of several blocks in the frame.
  • This data is the inverted pseudo-random number data continuously output from the inverter 51 of FIG. 20 during the L bit or L-1 bit selected by the predetermined method, and the L-1 bit or the L-1 bit selected by the predetermined method. It is data including pseudo-random data continuously output from the PRBS generator 41 for L-2 bits.
  • FIG. 21C is the output data of the FEC unit 43, and similarly, the inverted pseudo-random number data continuously output from the inverter 51 of FIG. 20 for the L bit or the L-1 bit selected by a predetermined method, and a predetermined value. It is the data including the pseudo-random number data continuously output from the PRBS generator 41 during the L-1 bit or the L-2 bit selected by the method of.
  • FIG. 21D is the output data of the scrambler 25, and toggle data different from that of FIG. 19D is output.
  • the toggle data of FIG. 21D continues between "1" selected by a predetermined method for L-1 or L-1 bits and L-1 or L-2 bits selected by a predetermined method. It is the data including "0" alternately.
  • the LDTS replacement unit 42 in FIG. 20 selects the number of bits in which the signal logic "1” continues from L bits or L-1 bits by a predetermined method, and selects the number of bits in which the signal logic "0" continues from L-.
  • An example of selecting from 1 bit or L-2 bit by a predetermined method is shown, but the number of bits of the signal logic "1" and "0" may be arbitrarily set.
  • FIG. 22 is a block diagram showing the internal configuration of the LDTS replacement portion 42 of the second modification.
  • the LDTS replacement unit 42 of FIG. 22 includes an inverter 56, a first selector 57, a selection control unit 58, and a second selector 59.
  • the inverter 56 generates an inverted pseudo-random number bit string obtained by inverting the pseudo-random number bit string generated by the PRBS generator 41.
  • the first selector 57 selects either a pseudo-random number bit string generated by the PRBS generator 41 or an inverted pseudo-random number bit string output from the inverter 56 based on the control signal from the selection control unit 58. do.
  • the selection control unit 58 outputs a control signal for switching the selection of the first selector 57 at an arbitrary timing.
  • the selection control unit 58 may randomly switch the selection of the first selector 57 based on a pseudo-random number or the like.
  • a pseudo-random number or the like.
  • FIG. 22 an example in which the first selector 57 selects the inverted pseudo-random number bit string is shown, but the number of bits for which the first selector 57 continuously selects the inverted pseudo-random number bit string is arbitrary. Therefore, there is no limitation of L bit or L-1 bit as shown in FIG.
  • the second selector 59 selects either the container output from the framer or the output signal of the first selector 57 based on the control signal from the scheduler.
  • FIG. 23 is a diagram showing an example of scramble data output from the scrambler 25 when the LDTS replacement unit 42 of FIG. 22 is used.
  • the scrambled data includes three containers (Container # 1 to # 3) and one container (Container # 4) including a header, toggle data of arbitrary period, and parity. The data of these four containers are repeatedly output in order.
  • the cycle of the toggle data can be arbitrarily changed in one block out of several blocks in the frame, so that the toggle data can be lengthened to the maximum, or in some cases, the toggle data can be lengthened as much as possible.
  • the signal logic can be changed at any timing.
  • the serial data in which the error correction code is added to the pseudo-random number bit string and the pseudo-random number bit string are exclusive. Generate toggle data by XOR.
  • the error correction code since it is premised that the error correction code is not added by the FEC unit 43 for the container to be replaced with the toggle data, it is necessary to perform a process different from that of other containers. Moreover, even if there is an error in the header information of the container to be replaced with the toggle data, it cannot be remedied.
  • the container to be replaced with toggle data and the other containers can be treated in the same way, and the FEC unit 43 can add an error correction code and then convert the data into serial data.
  • the FEC unit 43 adds an error correction code and then converts it to serial data, even if there is an error in the header part, it can be relieved, and the toggle data can be transferred to other toggle data on the receiving side. There is no risk of misrecognizing it as data.
  • the present technology can have the following configurations.
  • a transmission device that transmits information generated by an information source and divided into blocks to a transmission path in frame units including a plurality of the blocks. When the amount of information to be transmitted is less than the transmission capacity of the transmission path, one block out of several blocks in the frame either stops sending information to the transmission path or within the frame.
  • a transmission device including a transmission unit that transmits toggle data having a longer cycle of information transition than information other than the above-mentioned one block to the transmission path.
  • the transmission unit transmits data of a specific signal logic to the transmission path or sets the transmission path to high impedance within a period in which the transmission of information to the transmission path is stopped (2).
  • the transmission device according to 1).
  • the transmission unit sets the destination address of the block that stops the transmission of information to the transmission path to an address different from the address of the receiving device that receives information via the transmission path (3).
  • the transmission device according to 1) or (2).
  • the transmission unit is a scrambler that generates scrambled data obtained by scrambling the information generated by the information source regardless of whether or not the transmission of information to the transmission path is stopped.
  • the transmitter according to any one of (1) to (3).
  • the transmission unit performs a predetermined resynchronization pattern on the transmission path after the period for stopping the transmission of information to the transmission path has elapsed and before the transmission of information to the transmission path is resumed.
  • the transmission unit selects either one of the scrambled data and a predetermined resynchronization pattern used for synchronous reproduction processing of information received by the receiving device via the transmission path.
  • the transmitting device according to (4) which has a selector for transmitting to a transmission path.
  • the transmission device according to (6) wherein the transmission unit has a scheduler that controls selection of the selector based on a control signal transmitted by the reception device via the transmission path.
  • the transmission unit has a scrambler that generates scrambled data obtained by scrambling the information generated by the information source.
  • the scrambler A shift register having a plurality of registers for sequentially shifting serial data according to information generated by the information source, and a shift register. It has a logical operation unit that generates scrambled data by a predetermined logical operation between the data shifted by the shift register and the serial data input to the shift register.
  • the transmission unit transfers information transmitted to the transmission path in one block out of several blocks in the frame at a cycle corresponding to the number of stages of the plurality of registers in the shift register, according to (1). Transmitter. (9) In one block out of several blocks in the frame, the transmission unit is continuously 1 by the number of bits corresponding to the number of the plurality of registers in the shift register, and the plurality of blocks in the shift register.
  • the transmission device which transmits information in which 0 is continuously continued by the number of registers-1 minute of the number of registers in the transmission path.
  • the transmission unit uses a predetermined method to select either the number of the plurality of registers in the shift register or the number of the plurality of registers-1. 1 is continuously continued for the number of bits selected, and either the number -1 of the plurality of registers in the shift register-1 or the number 2 of the plurality of registers-2 is selected by a predetermined method.
  • the transmission device which transmits information in which 0 is continuously continued by the number of bits of a minute to the transmission path.
  • the transmission unit uses an address different from the address of the receiving device connected to the transmission path as the destination address before transmitting information to the transmission path.
  • the transmission device according to any one of (8) to (10), which transmits the header information to be transmitted to the transmission path.
  • (12) The transmission device according to (11), wherein the header information includes identification information of the toggle data.
  • the transmitter is A pseudo-random number generator that generates a pseudo-random number signal,
  • the transmission device according to (1), wherein one block out of several blocks in the frame has a scrambler that generates the toggle data based on the pseudo-random number signal.
  • the information generated by the information source is selected, and in the one block, the pseudo-random number signal is selected.
  • An error correction processing unit that adds an error correction code to the information selected in the replacement unit, and an error correction processing unit.
  • a delay device that delays the pseudo-random number signal for a predetermined period is provided. 23.
  • the scrambler generates the toggle data based on the output signal of the error correction processing unit and the output signal of the delay device in one block out of several blocks in the frame. Transmitter.
  • the predetermined period is a period from the generation of the pseudo-random number signal by the pseudo-random number device to the input of the output signal of the error correction processing unit to the scrambler.
  • the scrambler is an exclusive OR of the output signal of the error correction processing unit and the output signal of the delay device, or the output signal of the error correction processing unit and the above.
  • the pseudo-random number device has a shift register having a plurality of registers.
  • the scrambler is continuously followed by the first signal logic for the number of bits corresponding to the number of the plurality of registers in the shift register, and the plurality of blocks in the shift register.
  • the pseudo-random number device has a shift register having a plurality of registers, and the scrambler has the number of the plurality of registers in the shift register and the number of the plurality of registers in the shift register in one block out of several blocks in the frame.
  • the first signal logic is continuously continued for the number of bits selected by a predetermined method from any one of the plurality of registers -1, and the number -1 of the plurality of registers in the shift register and the number -1 are described.
  • the scrambler generates the toggle data in which the cycle is maximized or the cycle can be arbitrarily selected in one block out of several blocks in the frame.
  • Device. (19) The transmission device according to any one of (1) to (18), wherein the transmission unit transmits information to the transmission path within a period allocated by TDD (Time Division Duplex). (20) Master device and A slave device that transmits information generated by an information source and divided into blocks according to an instruction from the master device to the master device via a transmission path in frame units including a plurality of the blocks is provided.
  • the slave device When the amount of information generated by the information source is smaller than the transmission capacity of the transmission path, the slave device transmits information to the transmission path in one block out of several blocks in the frame.
  • a communication system having a transmission unit that stops the operation or sends toggle data having a longer cycle of information transition than information other than the one block in the frame to the transmission path.
  • An information transmission method in which information generated by an information source and divided into blocks is transmitted to a transmission path in frame units including a plurality of the blocks. When the amount of information generated by the information source is less than the transmission capacity of the transmission path, one block out of several blocks in the frame either stops sending information to the transmission path. Alternatively, an information transmission method for transmitting toggle data having a longer cycle of information transition than information in a block other than the one block to the transmission path.
  • 1 communication system 2 1st information source, 3 1st sink device, 4 1st SerDes section, 5 transmission path, 6 2nd SerDes section, 7 2nd sink device, 8 2nd information source, 11 downlink transmitter, 12 uplink receiver, 13 downlink receiver, 14 uplink transmitter, 21 buffer, 22 framer, 23 scheduler, 24 parallel-serial converter, 25 scrambler, 26 mapper, 27 output amplifier.
  • 31 shift counter 32 first XOR calculator, 33 second XOR calculator, 34 resynchronization pattern generator, 35 selector, 36 LDTS converter, 37 LDTS generator, 38 selector, 41 PRBS generator.

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