WO2022001779A1 - 绝缘体上半导体结构的制造方法 - Google Patents

绝缘体上半导体结构的制造方法 Download PDF

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WO2022001779A1
WO2022001779A1 PCT/CN2021/101801 CN2021101801W WO2022001779A1 WO 2022001779 A1 WO2022001779 A1 WO 2022001779A1 CN 2021101801 W CN2021101801 W CN 2021101801W WO 2022001779 A1 WO2022001779 A1 WO 2022001779A1
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layer
wafer
ion
doped
manufacturing
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PCT/CN2021/101801
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French (fr)
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黄河
丁敬秀
向阳辉
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中芯集成电路（宁波）有限公司上海分公司
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Definitions

  • the present invention relates to the technical field of semiconductor device fabrication, in particular to a fabrication method of a semiconductor-on-insulator structure.
  • Semiconductors on insulators such as silicon-on-insulator (SOI), germanium-on-insulator, silicon-germanium-on-insulator, etc., all have a unique three-layer structure of "bottom semiconductor layer/buried insulating layer/top semiconductor layer” Semiconductor material, which realizes full dielectric isolation of the device (formed in the top semiconductor layer) and the substrate (ie, the bottom semiconductor layer) through an insulating buried layer (usually silicon dioxide SiO 2 ), which can completely eliminate the formation of bulk silicon, etc.
  • SOI silicon-on-insulator
  • germanium-on-insulator germanium-on-insulator
  • silicon-germanium-on-insulator etc.
  • the parasitic latch-up effect in the CMOS circuit, and the circuit based on the semiconductor-on-insulator substrate also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short-channel effect, and is especially suitable for low-voltage and low-power circuits. and other advantages. Therefore, semiconductor-on-insulator substrates are widely used in the field of microelectronics.
  • the semiconductor-on-insulator substrate manufactured by the traditional technology has problems such as a thick top semiconductor layer and surface defects, which cannot meet the demand for further improvement of device performance, and therefore needs to be improved.
  • the purpose of the present invention is to provide a method for manufacturing a semiconductor-on-insulator structure, which can make the film thickness of the top semiconductor in the semiconductor-on-insulator structure thinner, so as to meet the manufacturing requirements of high-performance devices.
  • the present invention provides a method for manufacturing a semiconductor-on-insulator structure, comprising the following steps:
  • P-type ion implantation is performed on the first wafer to form a first ion-doped layer at a predetermined depth of the first wafer, and the first wafer is located above the top of the first ion-doped layer
  • the part is the surface wafer layer, and the first wafer part below the bottom of the first ion-doped layer is the base wafer layer;
  • the first ion-doped layer is removed by an etching process to expose the surface wafer layer.
  • the surface wafer layer is a second ion-doped layer
  • the doping type is P-type or N-type
  • the doping concentration range is: 5E+14cm -3 to 5E+16cm -3 .
  • the first wafer is doped as a whole, or only the area where the surface wafer layer is located is doped, or, Only the region from the top of the surface wafer layer to the bottom of the ion-doped layer is doped.
  • the ion doping concentration of the first ion doping layer ranges from 5E+17cm -3 to 5E+19cm -3 .
  • the etching process for removing the first ion-doped layer includes a selective wet etching process.
  • the etchant of the selective wet etching process includes at least one of nitric acid, hydrofluoric acid and acetic acid, and the molar ratio of nitric acid, hydrofluoric acid and acetic acid in the solution is 1:10:60 ⁇ 1:1:1, the process temperature is 25°C to 45°C, and the etching time is 1 minute to 10 minutes.
  • the surface of the first wafer is cleaned, and a pad oxide layer is further formed on the surface of the first wafer.
  • the pad oxide layer is removed first.
  • multi-step P-type ion implantation is performed on the first wafer by using different ion implantation parameters, and each step of P-type ion implantation forms different depths of P-type ion implantation in the first wafer. and further annealing the first wafer, so that all the P-type ion-doped layers are diffused to form the first ion-doped layer.
  • the first oxidative bonding layer and/or the second oxidative bonding layer is formed by a vapor deposition process with a process temperature lower than 600°C.
  • the entire structure after bonding is annealed and strengthened, and the annealing temperature is 300°C to 1100°C, and the annealing time is 30°C. min to 180 min, the annealing gas includes at least one of nitrogen, argon and hydrogen.
  • the second wafer includes a monocrystalline silicon layer and a microcrystalline layer located between the monocrystalline silicon layer and the second oxide bonding layer;
  • the microcrystalline layer includes a polycrystalline silicon layer, a silicon germanium layer At least one of an alloy layer and a germanium layer.
  • the materials of the first oxidative bonding layer and the second oxidative bonding layer both include silicon dioxide.
  • the process of removing the base wafer layer includes a mechanical grinding process or an etching process.
  • the manufacturing method after removing the first ion-doped layer and exposing the surface wafer layer, further comprises: measuring the thickness of the surface wafer layer, and according to the measurement result , using an ion beam to perform ion reaction treatment on the entire surface or partial surface of the surface wafer layer, so as to further surface trim the surface wafer layer.
  • the ion beam gas contains at least one of NF 3 , CF 4 , CHF 3 , oxygen, nitrogen and argon, the energy is 5 watts to 500 watts, and the processing time of a single wafer is 1 minute to 30 minutes .
  • the surface of the surface wafer layer is chemically treated Mechanically polished.
  • the manufacturing method after removing the first ion-doped layer and exposing the surface wafer layer, further comprises: removing the damage on the surface of the surface wafer layer.
  • the step of the surface oxidation treatment process includes: firstly performing an oxidation treatment on the surface wafer layer to form a regenerated oxide layer on the surface wafer layer, the process temperature is 700°C to 1100°C, and the regeneration The thickness of the oxide layer is 100 angstroms to 500 angstroms; then, the regenerated oxide layer is removed by adopting at least one process including wet etching, dry etching or chemical mechanical polishing.
  • the step of the anisotropic etching process includes: using an alkaline solution to anisotropically etch the surface of the surface wafer layer to remove the damaged layer on the surface of the surface wafer layer.
  • the technical solution of the present invention has at least one of the following beneficial effects:
  • the depth and thickness of the first ion-doped layer can be used to define the thickness of the top semiconductor layer of the semiconductor-on-insulator structure to be formed, which is conducive to the formation of a thinner and more uniform top semiconductor layer, and can also be removed during removal.
  • the first ion-doped layer is used as a stop layer and a protective layer to avoid unnecessary damage to the top semiconductor layer of the semiconductor-on-insulator structure in the process of removing the base wafer layer.
  • the first ion-doped layer is doped with P-type ions, compared with some existing corrosion barrier layers formed by implanting other ions such as oxygen, nitrogen, and hydrogen, the first ion-doped layer is a
  • it can be used as a corrosion enhancement layer, which can be quickly removed by an etching process such as a selective wet etching process, and can avoid unnecessary damage to the top semiconductor layer of the semiconductor-on-insulator structure to be formed, so that the top semiconductor layer is thinner and thinner. Thicker and more even.
  • a microcrystalline layer is provided under the second oxide bonding layer on the surface of the second wafer provided, and the microcrystalline layer can form a trap rich layer in the second wafer and can hinder the insulator
  • the free carrier flow in the semiconductor structure reduces parasitics in the semiconductor-on-insulator structure and improves the electrical performance of the semiconductor-on-insulator structure.
  • the thickness of the surface wafer layer is also measured, and according to the measurement result, the surface silicon layer is treated with an ion beam. Ion bombardment is performed on the entire surface or local surface of the surface wafer layer to further surface trim the surface wafer layer, so that the thickness of the top semiconductor layer of the formed semiconductor-on-insulator structure is further reduced and the film thickness uniformity is further improved.
  • the damage on the surface of the surface wafer layer is also removed by a surface oxidation treatment process and/or an anisotropic etching process , in order to facilitate improving the performance of devices formed based on the semiconductor-on-insulator structure.
  • FIG. 1 is a flow chart of a method for fabricating a semiconductor-on-insulator structure according to an embodiment of the present invention.
  • FIGS. 2 to 10 are schematic diagrams of cross-sectional structures of devices in a method for fabricating a semiconductor-on-insulator structure according to an embodiment of the present invention.
  • 10-first wafer 100-base wafer layer; 101-first ion doping layer; 102-surface wafer layer; 102a-top semiconductor layer; 11-pad oxide layer; 12-first oxide bonding layer; 13 - regenerated oxide layer; 20 - second wafer; 200 - monocrystalline silicon layer; 201 - microcrystalline layer; 21 - second oxide bonding layer.
  • an embodiment of the present invention provides a method for manufacturing a semiconductor-on-insulator structure, including the following steps:
  • a first wafer 10 is provided, and the base material of the first wafer 10 can be any known top semiconductor layer for making a semiconductor-on-insulator substrate known to those skilled in the art materials, such as silicon, germanium, silicon germanium, etc.
  • the semiconductor-on-insulator structure fabricated in this embodiment is a silicon-on-insulator structure.
  • the semiconductor-on-insulator structure fabricated in this embodiment is a germanium-on-insulator structure, and when the substrate of the first wafer 10 is silicon germanium, the semiconductor-on-insulator structure fabricated in this embodiment is a semiconductor-on-insulator structure. Silicon germanium structure.
  • the first wafer 10 may be a wafer lightly doped with P-type ions or N-type ions as a whole, or may be an undoped substrate located at the bottom and a lightly doped layer located on the undoped substrate.
  • the lightly doped layer can be the area where the surface wafer layer 102 is subsequently divided, or the thickness area where the surface wafer layer 102 and the ion-doped layer 101 are stacked subsequently formed, and the lightly doped layer is
  • the impurity layer is doped with N-type ions or P-type ions.
  • the N-type ions include phosphorus, arsenic, antimony, etc.
  • the P-type ions include boron, indium, gallium, etc.
  • the doping concentration of the N-type ions or P-type ions doped in the lightly doped region in the first wafer 10 is low at 1E+16cm -3 .
  • the surface of the first wafer 10 may be mechanically polished. Then, chemical reagents (such as SC1, SC2, SPM, DHF, organic solvents, etc.), deionized water and other cleaning solutions can be used to clean the surface of the first wafer 10, and the cleaning process can be accompanied by ultrasonic vibration, heating , vacuuming and other physical measures to remove surface impurities and defects.
  • SC1 solution is a mixed solution composed of NH 4 OH, H 2 O 2 and H 2 O
  • SC2 solution is a mixed solution composed of HCl, H 2 O 2 and H 2 O, or HCl solution
  • SPM solution is A mixed solution consisting of H 2 SO 4 , H 2 O 2 and H 2 O
  • DHF is an HF solution, or a mixed solution consisting of HF, H 2 O 2 and H 2 O.
  • a wafer 10 with improved tunnel penetration effect during ion implantation The temperature of the thermal oxidation process is 700° C. ⁇ 1100° C., and the thickness of the pad oxide layer 11 is 100 angstroms ⁇ 500 angstroms. Compared with the vapor deposition process, the thermal oxidation process has the advantages of high density and less ionic contamination.
  • the first wafer 10 is ion-implanted by using P-type ions, so as to form a first ion-doped layer 101 at a predetermined depth of the first wafer 10 and located in the first wafer 10 .
  • the portion of the first wafer above the top of the first ion-doped layer 101 is the surface wafer layer 102 , the surface wafer layer 102 is used to fabricate the top silicon of the semiconductor-on-insulator structure, and is located in the first ion-doped layer 101
  • the first wafer portion below the bottom is the base wafer layer 100 .
  • the first wafer 10 is divided into a sandwich structure consisting of the base wafer layer 100 , the first ion-doped layer 101 and the surface wafer layer 102 .
  • the thickness of the base wafer layer 100 is, for example, 10 micrometers ( ⁇ m) to 80 micrometers
  • the thickness of the surface wafer layer 102 is, for example, That is, the height of the bottom of the first ion-doped layer 101 may be 10-80 microns, and the height of the top may be 200-10 microns.
  • P-type ions are used to form the first ion-doped layer 101 , except that the first wafer 10 can be divided into a base wafer layer 100 , a first ion-doped layer 101 and a surface wafer layer 102 that are stacked in sequence
  • the thickness of the surface wafer layer 102 (that is, the thickness of the top semiconductor layer of the semiconductor-on-insulator structure to be formed) can also be precisely defined, which is conducive to the formation of a thinner and more uniform top semiconductor layer, and can also The diffusion into the surface wafer layer 102 when other ions such as oxygen, nitrogen, and hydrogen are implanted is avoided to affect the performance of the top semiconductor layer in the finally formed semiconductor-on-insulator structure.
  • the initially provided first wafer 10 is lightly doped as a whole or within a certain thickness of the top layer of the first wafer 10 (that is, the thickness of the surface wafer layer 102 and the ion-doped layer 101 stacked)
  • ions of the same type as the first wafer 10 can be selected for ion implantation to form the first ion doped layer 101, so as to improve the efficiency of forming the first ion doped layer 101.
  • ion implantation is performed on the first wafer 10 with P-type ions to form the first ion-doped P-type ion heavily doped Layer 101.
  • the doping concentration of P-type ions in the surface wafer layer 102 and the base wafer layer 100 are both lower than the doping concentration of P-type ions in the first ion doping layer 101, and the first ion doping concentration
  • the layer 101 is heavily doped, and the ion doping concentration is higher than 1E+17cm ⁇ 3 , eg, 5E+17cm ⁇ 3 to 5E+19cm ⁇ 3 .
  • different ion implantation parameters can be used to perform multi-step P-type ion implantation (also referred to as multiple times) on the first wafer 10 P-type ion implantation), each step of P-type ion implantation forms P-type ion-doped layers (not shown, also referred to as P-type ion-doped strips) of different depths in the first wafer 10, and further The first wafer 10 is annealed to diffuse all the P-type ion-doped layers and form the first ion-doped layer 101 .
  • Each step of ion implantation is implemented with high energy, high dose and an implantation angle of 0-7 degrees.
  • the energy of the ion implantation in two adjacent steps of P rows is different, and the implantation dose is the same, so that the depths of the two P-type ion doped layers formed by the ion implantation in the adjacent two steps of P rows are different, but the thicknesses are the same.
  • the first wafer 10 is subjected to high-temperature annealing treatment.
  • the two P-type ion-doped layers can be connected up and down, so that the P-type ion-doped layers of different depths formed by the P-type ion implantation in each step are connected together after diffusion to form the first ion-doped layer 101 . And the distribution of P-type ions in the first ion-doped layer 101 is uniform.
  • the thickness of the first ion-doped layer 101 is 5 ⁇ m ⁇ 20 ⁇ m, and a thicker first ion-doped layer is beneficial to prevent the first ion-doped layer from being completely ground off during mechanical thinning.
  • step S3 first, the pad oxide layer 12 is removed by wet etching or dry etching.
  • the etchant is selected from hydrogen fluoride. Acid, the etching temperature is room temperature, and the etching time is 10 seconds to 100 seconds, for example, 60 seconds.
  • the first oxide bonding layer 12 is formed on the surface of the surface wafer layer 102 using an atomic layer deposition process or a chemical vapor deposition process with a process temperature lower than 600°C.
  • the process temperature for forming the first oxidative bonding layer 12 is controlled below 600° C., which can prevent the ions in the first ion doping layer 101 from diffusing upward to the surface wafer layer 102 and downward to the base wafer layer 101 .
  • the interfaces of the first ion-doped layer 101 and the surface wafer layer 102 and the base wafer layer 101 respectively become blurred, so that the process of the subsequent step S6 cannot well stop the surface of the first ion-doped layer 101, and the subsequent steps
  • the etching process in step S7 cannot well stop on the surface of the surface wafer layer 102 , which ultimately affects the performance of the top semiconductor layer in the semiconductor-on-insulator structure formed.
  • the material of the first oxide bonding layer 12 may include at least one of silicon dioxide and silicon oxynitride.
  • the thickness of the first oxide bonding layer 12 is 2000 angstroms to 5000 angstroms, and the thickness is too thin to provide a sufficient bonding phase fusion interface; and if the thickness is too thick, the bonding strength will be reduced to different degrees.
  • a second wafer 20 is provided, and the second wafer 20 may be any suitable base material known to those skilled in the art, such as monocrystalline silicon, germanium, silicon germanium Wait.
  • the second wafer 20 includes a monocrystalline silicon layer 200 at the bottom and a microcrystalline layer 201 on the surface of the monocrystalline silicon layer 200 , wherein the microcrystalline layer 201 may include a polycrystalline silicon layer, a silicon germanium alloy layer and germanium at least one of the layers.
  • the crystallite size of the microcrystalline layer 201 is 1 nanometer to 10 micrometers.
  • the microcrystalline layer 201 can form a trap rich layer in the second wafer 20, thereby preventing the subsequent formation of the semiconductor-on-insulator structure.
  • the free carrier flow in the semiconductor-on-insulator structure reduces the parasitic phenomenon in the semiconductor-on-insulator structure, and improves the electrical performance of the semiconductor-on-insulator structure.
  • the thickness of the microcrystalline layer 201 is 1 micrometer to 5 micrometers, and its formation process is, for example, a polysilicon process of low pressure chemical vapor deposition or an ion implantation process.
  • the thickness of the microcrystalline layer needs to be controlled to be more than 1 micron in order to have sufficient trap capability, while polysilicon with a thickness of more than 5 microns has problems in the stability and yield of the manufacturing process.
  • step S4 a thermal oxidation process or a chemical vapor deposition process is continued to form a second oxidation bonding layer 21 on the surface of the microcrystalline layer 201 , and the material of the second oxidation bonding layer 21 is At least one of silicon dioxide and silicon oxynitride may be included.
  • the thickness of the second oxide bonding layer 21 is 2000 angstroms to 5000 angstroms. If the thickness is too thin, it cannot provide enough bonding phase fusion interface; and if the thickness is too thick, the bonding strength will be reduced to varying degrees.
  • step S4 only needs to be completed before step S5, it can be performed after step S3, it can also be performed after step S1 and before step S3, it can also be performed at the same time as step S3, or it can be performed before step S1 is carried out.
  • step S2 the first wafer 10 and the second wafer 20 from which the pad oxide layer 12 has been removed are put into the same deposition process equipment to adopt the same process conditions and simultaneously form the first oxide bond
  • the bonding layer 12 and the second oxide bonding layer 21 are formed, thereby simplifying the process and improving the efficiency, that is, at this time, the steps S4 and S3 are performed simultaneously, and the first oxide bonding layer 12 and the second oxide bonding layer 21 are formed.
  • the thickness and performance are basically the same, which is beneficial to improve the bonding performance.
  • step S5 the first oxide bonding layer 12 and the second oxide bonding layer 21 are bonded together by a wafer bonding process, and annealing is performed to strengthen the first wafer 10 . ground bonded to the second wafer 20 .
  • the annealing temperature is too high, ion redistribution will occur between the base wafer layer 100 , the first ion-doped layer 101 and the surface wafer layer 102 , while the annealing temperature is too low to cause The first oxide bonding layer 12 and the second oxide bonding layer 21 are reliably bonded together. Moreover, the annealing temperature is too high and the annealing time is too long, which will lead to the longitudinal diffusion of ion doping in the first ion doping layer 101, which will have an impact on the control of the ion diffusion depth. The thickness of the top semiconductor layer is not controllable.
  • the ion implantation depth range of the first ion doping layer 101 is very narrow, even if the first ion doping layer 101 is formed by means of multiple ion implantation, the ions are actually carried out in multiple depth gradients. Implantation is performed to form a corresponding doping region (also called a doping band). Within the thickness range of the first ion doping layer 101, the concentration of the formed ion doping region at various depths is not uniform.
  • the annealing process in the first ion-doped layer 101 can further “smooth out” these uneven doping bands in the first ion-doped layer 101 to form a uniform ion-doped layer with a considerable width, which is beneficial to the removal in the subsequent step S6
  • the base wafer layer 100 and the first ion-doped layer 101 are beneficial to control the thickness of the remaining surface wafer layers. Therefore, choosing an appropriate annealing temperature and annealing time is critical.
  • the annealing temperature is 300°C to 1100°C
  • the annealing time is 30 minutes to 180 minutes
  • the annealing gas includes helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), At least one inert gas among nitrogen (N 2 ) and the like.
  • the annealing temperature is 300° C. ⁇ 500° C.
  • the annealing time is 30 minutes ⁇ 150 minutes.
  • the first oxide bonding layer 12 and the second oxide bonding layer 21 can be formed by a vapor deposition process, which is less dense than the oxide layer formed by the thermal oxidation process and can be performed at a lower annealing temperature.
  • the atoms diffuse, which in turn makes the bond strength higher.
  • step S6 the base wafer layer 100 of the first wafer 10 is removed through a backside thinning process such as a physical or chemical mechanical polishing process, a wet etching process or a dry etching process, so as to be exposed.
  • the first ion doping layer 101 is obtained.
  • the first ion-doped layer 101 can be used as the stopping point of the backside thinning process to avoid the backside thinning process affecting the surface crystals.
  • the round layer 102 is damaged.
  • step S7 after removing the base wafer layer 100 , the first ion-doped layer 101 and the surface wafer layer 102 are selectively wet etched with a high etching selectivity ratio to remove the first ion-doped layer 101 and the surface wafer layer 102 .
  • the ion-doped layer 101 may be over-etched to a certain degree in this step to further thin the surface wafer layer 102 after the ion-doped layer 101 is removed.
  • the thickness of the remaining surface wafer layer 102 may be 200 angstroms to 10 microns.
  • the used etchant includes at least one of nitric acid, hydrofluoric acid and acetic acid, such as nitric acid, hydrofluoric acid and acetic acid
  • nitric acid, hydrofluoric acid and acetic acid such as nitric acid, hydrofluoric acid and acetic acid
  • the molar ratio of nitric acid, hydrofluoric acid and acetic acid in the solution is 1:10:60 ⁇ 1:1:1, specifically 15:25:60, the process temperature is 25°C ⁇ 45°C, the etching time 1 minute to 10 minutes.
  • the etching rate of this mixed solution for high-concentration doped P+Si is very fast (greater than 10 ⁇ m/min), and the etching rate for low-concentration doped P-Si is very low (less than 0.01 ⁇ m/min), so the etching rate is very low.
  • the surface wafer layer 102 is reached, the self-stop of the etching reaction is realized.
  • chemical mechanical polishing is further performed on the surface of the surface wafer layer 102 through a fine chemical mechanical polishing process to remove the surface wafer after the selective wet etching process. residues on the layer 102 and further thinning the surface wafer layer 102 .
  • the thickness of the surface wafer layer 102 is also measured, and the surface wafer layer 102 is measured according to the measurement result. Further surface trimming is performed to make the thickness of the surface wafer layer 102 meet the requirements, and the uniformity of the film thickness is further improved. The process of thickness measurement and surface trimming can be performed in multiple cycles until the overall thickness and uniformity of the surface wafer layer 102 meet the requirements.
  • an "ion beam surface treatment machine” is used to perform ion reaction treatment on the entire surface or partial surface of the surface wafer layer 102 to further surface trim the surface wafer layer 102,
  • the ion beam gas contains at least one of NF 3 , CF 4 , CHF 3 , oxygen, nitrogen, argon, etc., the energy range is 5 watts to 500 watts, and the processing time of a single wafer is 1 minute to 30 minutes, according to actual requirements Adjust the amount of energy and processing time.
  • the process of surface trimming the surface silicon layer 102 by ion beam has higher precision, so the remaining surface wafer layer 102 (ie, the top silicon of the silicon-on-insulator structure) can be controlled to be thinner, The film thickness is more uniform.
  • the semiconductor-on-insulator structure and the top semiconductor layer 102a thereof are formed, wherein the second wafer 20 is the bottom semiconductor layer of the semiconductor-on-insulator structure, the second oxide bonding layer 21 and the first semiconductor layer 21 are formed.
  • the oxide bonding layer 12 is an insulating buried layer of the semiconductor-on-insulator structure, and the exposed surface wafer layer 102 is the top semiconductor layer 102a of the semiconductor-on-insulator structure.
  • the thickness of the top semiconductor layer 102a of the semiconductor-on-insulator structure can reach
  • the surface of the surface wafer layer 102 is trimmed by ion beam, the surface is further removed and repaired by a surface oxidation treatment process and/or an anisotropic etching process.
  • the surface of the wafer layer 102 is damaged.
  • An exemplary method for removing and repairing the surface damage of the surface wafer layer 102 is to first perform high-temperature oxidation treatment on the surface of the surface wafer layer 102, and the process temperature is 700° C. ⁇ 1100° C.
  • a regenerated oxide layer 13 is formed on the layer 102, and the thickness of the regenerated oxide layer 13 is 50 angstroms to 500 angstroms.
  • the bonding interface can be strengthened at the same time, and the thickness of the oxide takes into account the depth of the surface damage layer. Then, at least one process including wet etching, dry etching or fine chemical mechanical polishing is used to remove the regenerated oxide layer 13 .
  • Another exemplary method for removing and repairing the surface damage of the surface wafer layer 102 is to perform anisotropic etching on the surface of the surface wafer layer 102 using an alkaline solution such as tetramethylammonium hydroxide, TMAH, etc.
  • the time is 15 seconds to 2 minutes, and the etching temperature is normal temperature, for example, 25° C. ⁇ 45° C., so as to remove and repair the surface damage of the surface wafer layer 102 .
  • the characteristics of anisotropic etching of silicon by alkaline solution make the wafer surface form regular crystal planes distributed according to the crystal orientation, so as to obtain a more perfect wafer surface after removing the surface damage layer. Adjust the etching time according to actual requirements.
  • the method further includes: using a cleaning solution such as deionized water to clean the surface crystals.
  • a cleaning solution such as deionized water to clean the surface crystals.
  • the circular layer 102 is wet cleaned to remove surface contamination.
  • the first ion-doped layer is formed by performing P-type ion implantation on the first wafer, and the first wafer is divided into the base wafer layer, the first wafer, and the first wafer.
  • the circle is bonded to the second wafer, and then the base wafer layer is removed first, and then the first ion-doped layer is removed by an etching process, thereby forming a semiconductor-on-insulator structure.
  • the depth and thickness of the first ion-doped layer define the thickness of the top semiconductor layer of the semiconductor-on-insulator structure, and the first ion-doped layer is an etching enhancement layer that can be quickly removed by an etching process without affecting the top semiconductor layer. Unnecessary damage is caused, so that the top semiconductor layer is thinner and the film thickness is more uniform, which can meet the manufacturing requirements of high-performance devices.

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Abstract

本发明提供了一种绝缘体上半导体结构的制造方法，先通过对第一晶圆进行P型离子注入，形成了第一离子掺杂层，并将所述第一晶圆划分为由基底晶圆层、第一离子掺杂层和表面晶圆层组成的三明治结构，后通过表面晶圆层表面上形成的第一氧化键合层以及第二晶圆表面上形成的第二氧化键合层，将第一晶圆键合到第二晶圆上，之后先去除基底晶圆层，再通过刻蚀工艺去除第一离子掺杂层，从而形成绝缘体上半导体结构。其中第一离子掺杂层的深度和厚度限定了绝缘体上半导体结构的顶层半导体层厚度，且该第一离子掺杂层为腐蚀增强层，能通过刻蚀工艺快速去除且不会对顶层半导体层造成不必要的损伤，以使得顶层半导体层更薄、膜厚更均匀。

Description

绝缘体上半导体结构的制造方法 技术领域
本发明涉及半导体器件制作技术领域，特别涉及一种绝缘体上半导体结构的制造方法。
背景技术
绝缘体上半导体，例如绝缘体上硅(Silicon-On-Insulator，SOI)、绝缘体上锗、绝缘体上硅锗等，均是具有独特的“底层半导体层/绝缘埋层/顶层半导体层”三层结构的半导体材料，它通过绝缘埋层(通常为二氧化硅SiO 2)实现了器件(形成在顶层半导体层中)和衬底(即底层半导体层)的全介质隔离，能够彻底消除了体硅等形成的CMOS电路中的寄生闩锁效应，且基于绝缘体上半导体衬底制作的电路还具有寄生电容小、集成密度高、速度快、工艺简单、短沟道效应小及特别适用于低压低功耗电路等优势。因此，绝缘体上半导体衬底在微电子领域得到了广泛的使用。
然而，传统技术制造的绝缘体上半导体衬底存在顶层半导体层较厚且表面存在缺陷等问题，无法满足器件性能进一步提高的需求，因此亟待改进。
发明内容
本发明的目的在于提供一种绝缘体上半导体结构的制造方法，能够使得绝缘体上半导体结构中的顶层半导体的膜厚较薄，以满足高性能的器件的制造需求。
为解决上述技术问题，本发明提供一种绝缘体上半导体结构的制造方法，包括以下步骤：
提供第一晶圆；
对所述第一晶圆进行P型离子注入，以在所述第一晶圆的预设深度形成第一离子掺杂层，且位于所述第一离子掺杂层顶部以上的第一晶圆部分为表面晶圆层，位于所述第一离子掺杂层底部以下的第一晶圆部分为基底晶圆层；
在所述表面晶圆层的表面上形成第一氧化键合层；
提供第二晶圆，并在所述第二晶圆的表面上形成第二氧化键合层；
键合所述第一氧化键合层和所述第二氧化键合层，以将所述第一晶圆键合 到所述第二晶圆上；
去除所述基底晶圆层，以暴露出所述第一离子掺杂层；
通过刻蚀工艺去除所述第一离子掺杂层，以暴露出所述表面晶圆层。
可选地，所述表面晶圆层为第二离子掺杂层，掺杂类型为P型或N型，掺杂浓度范围为：5E+14cm -3～5E+16cm -3。
可选地，在对所述第一晶圆进行P型离子注入之前，所述第一晶圆是整体掺杂的，或者，仅有所述表面晶圆层所在区域是掺杂的，或者，仅有所述表面晶圆层的顶部至所述离子掺杂层的底部的区域是掺杂的。
可选地，所述第一离子掺杂层的离子掺杂浓度范围为：5E+17cm -3～5E+19cm -3。
可选地，去除所述第一离子掺杂层的刻蚀工艺包括选择性湿法刻蚀工艺。
可选地，所述选择性湿法刻蚀工艺的刻蚀剂包括硝酸、氢氟酸和醋酸中的至少一种，溶液中硝酸、氢氟酸和醋酸的摩尔比为1:10:60～1:1:1，工艺温度为25℃～45℃，刻蚀时间1分钟至10分钟。
可选地，在对所述第一晶圆进行P型离子注入之前，先对所述第一晶圆进行表面清洗，并进一步在所述第一晶圆的表面上形成衬垫氧化层。
可选地，在形成所述第一离子掺杂层之后，且在形成所述第一氧化键合层之前，先去除所述衬垫氧化层。
可选地，通过采用不同的离子注入参数，来对所述第一晶圆进行多步P型离子注入，各步P型离子注入在所述第一晶圆中形成不同深度的P型离子掺杂，进一步对所述第一晶圆进行退火处理，以使得所有的所述的P型离子掺杂层扩散形成所述第一离子掺杂层。
可选地，采用工艺温度低于600℃的气相沉积工艺来形成所述第一氧化键合层和/或所述第二氧化键合层。
可选地，在键合所述第一氧化键合层和所述第二氧化键合层之后，对键合之后的整个结构进行退火加固，退火温度为300℃～1100℃，退火时间为30分钟～180分钟，退火气体包括氮气、氩气和氢气中的至少一种。
可选地，所述第二晶圆包括单晶硅层和位于所述单晶硅层和所述第二氧化键合层之间的微晶层；所述微晶层包括多晶硅层、硅锗合金层和锗层中的至少一种。
可选地，所述第一氧化键合层和所述第二氧化键合层的材质均包括二氧化硅。
可选地，去除所述基底晶圆层的工艺包括机械研磨工艺或刻蚀工艺。
可选地，所述的制造方法，在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后，还包括：测量所述表面晶圆层的厚度，并根据所述测量结果，采用离子束对所述表面晶圆层的整体表面或者局部表面进行离子反应处理，以对所述表面晶圆层进一步表面修整。
可选地，所述离子束气体包含NF 3、CF 4、CHF 3、氧气、氮气和氩气中的至少一种，能量在5瓦～500瓦，单片晶圆处理时间1分钟～30分钟。
可选地，在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后且在对所述表面晶圆层进一步表面修整之前，先对所述表面晶圆层的表面进行化学机械抛光。
可选地，所述的制造方法，在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后，还包括：通过表面氧化处理工艺和/或各向异性刻蚀工艺，去除所述表面晶圆层表面上的损伤。
可选地，所述表面氧化处理工艺的步骤包括：先对所述表面晶圆层进行氧化处理，以在所述表面晶圆层上形成再生氧化层，工艺温度为700℃～1100℃，再生氧化层的厚度100埃～500埃；然后，采用包括湿法刻蚀、干法刻蚀或者化学机械抛光中的至少一种工艺，去除所述再生氧化层。
可选地，所述各向异性刻蚀工艺的步骤包括：采用碱性溶液各向异性刻蚀所述表面晶圆层的表面，以去除所述表面晶圆层表面上的损伤层。
与现有技术相比，本发明的技术方案至少具有以下有益效果之一：
1、可以利用第一离子掺杂层的深度和厚度来限定待形成的绝缘体上半导体结构的顶层半导体层的厚度，有利于形成膜厚更薄、更均匀的顶层半导体层，且还能在去除基底晶圆层的工艺中，利用该第一离子掺杂层作为停止层和保护层，来避免去除基底晶圆层的工艺对绝缘体上半导体结构的顶层半导体层产生不必要的损伤。
2、因为该第一离子掺杂层是P型离子掺杂的，相对现有的一些采用氧、氮、氢等其他离子注入而形成的腐蚀阻挡层而言，该第一离子掺杂层一方面，能作为腐蚀增强层，通过选择性湿法腐蚀工艺等刻蚀工艺快速去除且能避免对待形 成的绝缘体上半导体结构的顶层半导体层造成不必要的损伤，以使得顶层半导体层更薄、膜厚更均匀。
3、提供的第二晶圆的表面上的第二氧化键合层下设置有微晶层，该微晶层能够在第二晶圆中形成富陷阱层(trap rich layer)，能够阻碍绝缘体上半导体结构中的自由载流子流动，降低绝缘体上半导体结构中的寄生现象，提高绝缘体上半导体结构的电学性能。
4、在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后，还测量所述表面晶圆层的厚度，并根据所述测量结果，采用离子束对所述表面硅层的整体表面或局部表面进行离子轰击，来对所述表面晶圆层进一步表面修整，以使得形成的绝缘体上半导体结构的顶层半导体层的厚度进一步减薄，膜厚均一性进一步提高。
5、在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后，还通过表面氧化处理工艺和/或各向异性刻蚀工艺，去除所述表面晶圆层表面上的损伤，以有利于提高基于该绝缘体上半导体结构形成的器件的性能。
附图说明
图1是本发明具体实施例的绝缘体上半导体结构的制造方法流程图。
图2至图10是本发明具体实施例的绝缘体上半导体结构的制造方法中的器件剖面结构示意图。
其中的附图标记如下：
10-第一晶圆；100-基底晶圆层；101-第一离子掺杂层；102-表面晶圆层；102a-顶层半导体层；11-衬垫氧化层；12-第一氧化键合层；13-再生氧化层；20-第二晶圆；200-单晶硅层；201-微晶层；21-第二氧化键合层。
具体实施方式
以下结合附图和具体实施例对本发明提出的技术方案作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。本文中“和/或”的含义是二选一或者二者兼具。
请参考图1，本发明一实施例提供一种绝缘体上半导体结构的制造方法，包 括以下步骤：
S1，提供第一晶圆；
S2，对所述第一晶圆进行P型离子注入，以在所述第一晶圆的预设深度形成第一离子掺杂层，且位于所述第一离子掺杂层顶部以上的第一晶圆部分为表面晶圆层，位于所述第一离子掺杂层底部以下的第一晶圆部分为基底晶圆层；
S3，在所述表面晶圆层的表面上形成第一氧化键合层；
S4，提供第二晶圆，并在所述第二晶圆的表面上形成第二氧化键合层；
S5，键合所述第一氧化键合层和所述第二氧化键合层，以将所述第一晶圆键合到所述第二晶圆上；
S6，去除所述基底晶圆层，以暴露出所述第一离子掺杂层；
S7，通过刻蚀工艺去除所述第一离子掺杂层，以暴露出所述表面晶圆层。
请参考图2，在步骤S1中，首先，提供第一晶圆10，第一晶圆10的基材材料可以是本领域技术人员任意所熟知的用于制作绝缘体上半导体衬底的顶层半导体层的材料，例如是硅、锗、锗硅等，当第一晶圆10的基材为单晶硅时，本实施例制作的绝缘体上半导体结构即为绝缘体上硅结构，当第一晶圆10的基材为锗时，本实施例制作的绝缘体上半导体结构即为绝缘体上锗结构，当第一晶圆10的基材为硅锗时，本实施例制作的绝缘体上半导体结构即为绝缘体上硅锗结构。第一晶圆10可以是整体轻掺杂有P型离子或N型离子的晶圆，也可以是由位于底部的未掺杂的基材和位于未掺杂的基材上的轻掺杂层组成的晶圆，该轻掺杂层可以是后续划分出的表面晶圆层102所在区域，也可以是后续形成的表面晶圆层102和离子掺杂层101层叠的厚度区域，且该轻掺杂层中掺杂有N型离子或P型离子。其中N型离子包括磷、砷、锑等，P型离子包括硼、铟、镓等，第一晶圆10中的轻掺杂区域中掺杂的N型离子或P型离子的掺杂浓度低于1E+16cm -3。第一晶圆10的表面可以是经过机械抛光的。然后，可以采用化学试剂(例如SC1、SC2、SPM、DHF、有机溶剂等)、去离子水等清洗液对所述第一晶圆10进行表面清洗，在清洗过程中可以伴有超声振动、加热、抽真空等物理措施，以去除表面杂质和缺陷。其中，SC1溶液是由NH 4OH、H 2O 2和H 2O组成的混合溶液，SC2溶液是由HCl、H 2O 2和H 2O组成的混合溶液，或者是HCl溶液，SPM溶液是由H 2SO 4、H 2O 2和H 2O组成的混合溶液，DHF是HF溶液，或者是由HF、H 2O 2和H 2O组成的混合溶液。之后，可以通过热氧化工 艺，在第一晶圆10的表面上形成衬垫氧化层11，衬垫氧化层11能够防止第一晶圆10表面受到污染，并能在后续离子注入过程中保护第一晶圆10，并改善离子注入时的隧道穿透效应。所述热氧化工艺的温度是700℃～1100℃，衬垫氧化层11的厚度是100埃～500埃。对比气相沉积工艺，热氧化工艺具有致密性高、离子污染少的优点。
请参考图3，在步骤S2，采用P型离子对所述第一晶圆10进行离子注入，以在所述第一晶圆10的预设深度形成第一离子掺杂层101，且位于所述第一离子掺杂层101顶部以上的第一晶圆部分为表面晶圆层102，该表面晶圆层102用于制作绝缘体上半导体结构的顶层硅，位于所述第一离子掺杂层101底部以下的第一晶圆部分为基底晶圆层100。即在形成第一离子掺杂层101的同时，所述第一晶圆10被划分为由基底晶圆层100、第一离子掺杂层101和表面晶圆层102组成的三明治结构。其中，基底晶圆层100的厚度例如是10微米(μm)～80微米，表面晶圆层102的厚度例如是
Figure PCTCN2021101801-appb-000001
即第一离子掺杂层101的底部高度可以为10微米～80微米，顶部高度可以为200埃～10微米。本步骤中，利用P型离子来形成第一离子掺杂层101，除了可以将第一晶圆10分为依次层叠的基底晶圆层100、第一离子掺杂层101和表面晶圆层102之外，还可以精确定义出表面晶圆层102的厚度(即待形成的绝缘体上半导体结构的顶层半导体层的厚度)，有利于形成更薄、膜厚更均匀的顶层半导体层，并且又可以避免采用氧、氮、氢等其他离子注入时扩散到表面晶圆层102中，而影响最后形成的绝缘体上半导体结构中的顶层半导体层的性能。
可选地，当初始提供的第一晶圆10整体是轻掺杂的或者所述第一晶圆10的顶层一定厚度(即表面晶圆层102和离子掺杂层101层叠的厚度)内的部分是轻掺杂的时，可以选用与所述第一晶圆10同类型的离子来进行离子注入，以形成所述第一离子掺杂层101，以提高形成第一离子掺杂层101的效率，例如当开始提供的第一晶圆10为P型离子轻掺杂的，则采用P型离子对第一晶圆10进行离子注入，以形成P型离子重掺杂的第一离子掺杂层101。其中，表面晶圆层102和基底晶圆层100的P型离子的掺杂浓度均低于所述第一离子掺杂层101中的P型离子的掺杂浓度，所述第一离子掺杂层101是重掺杂的，离子掺杂浓度高于1E+17cm -3，例如为5E+17cm -3～5E+19cm -3。
本步骤中，为了保证形成的第一离子掺杂层101的厚度，可以通过采用不 同的离子注入参数，来对所述第一晶圆10进行多步P型离子注入(也可以称为多次P型离子注入)，各步P型离子注入在所述第一晶圆10中形成不同深度的P型离子掺杂层(未图示，也可以称为P型离子掺杂带)，进一步对所述第一晶圆10进行退火处理，以使得所有的所述的P型离子掺杂层扩散并形成所述第一离子掺杂层101。每步离子注入均采用高能量、高剂量且0～7度的注入角度来实现。可选地，相邻两步P行离子注入的能量不同，注入剂量相同，以使得相邻两步P行离子注入形成的两层P型离子掺杂层的深度不同，但是厚度相同。在完成最后一步P型离子注入之后，才对所述第一晶圆10进行高温退火处理，退火温度例如为600℃以上，退火时间120分钟以上，退火氛围为包括氦(He)、氖(Ne)、氩(Ar)、氪(Kr)、氙(Xe)、氮气(N 2)等至少一种惰性气体的氛围，以使得注入的P型离子扩散到位，相邻两步P行离子注入形成的两层P型离子掺杂层能够上下相接，由此，各步P型离子注入形成的不同深度的P型离子掺杂层在扩散后连为一体而形成第一离子掺杂层101，且第一离子掺杂层101中的P型离子分布均匀。第一离子掺杂层101的厚度是5微米～20微米，更厚的第一离子掺杂层有利于防止机械减薄时将第一离子掺杂层全部磨掉。
请参考图4，在步骤S3中，首先，通过湿法腐蚀或者干法刻蚀等工艺去除衬垫氧化层12，例如当湿法刻蚀去除衬垫氧化层12时，刻蚀剂选用氢氟酸，刻蚀温度室温，刻蚀时间为10秒～100秒，具体例如为60秒。然后，采用工艺温度低于600℃的原子层沉积工艺或化学气相沉积工艺等，在表面晶圆层102的表面上形成第一氧化键合层12。形成第一氧化键合层12的工艺温度控制在600℃以下，可以避免第一离子掺杂层101中的离子向上扩散到表面晶圆层102，以及向下扩散到基底晶圆层101中，使得第一离子掺杂层101分别与表面晶圆层102和基底晶圆层101的界面变得模糊，导致后续步骤S6的工艺不能很好地停止第一离子掺杂层101的表面，以及后续步骤S7中的刻蚀工艺不能很好地停止在表面晶圆层102的表面，进而最终影响形成的绝缘体上半导体结构中的顶层半导体层的性能。第一氧化键合层12的材质可以包括二氧化硅和氮氧化硅中的至少一种。第一氧化键合层12的厚度是2000埃～5000埃，厚度太薄，不能提供足够的键合相融界面；而厚度太厚的话，键合强度会有不同程度的降低。
请参考图5，在步骤S4中，首先，提供第二晶圆20，所述第二晶圆20可以是本领域技术人员所熟知的任意合适的基底材料，例如单晶硅、锗、硅锗等。 本实施例中，第二晶圆20包括位于底部的单晶硅层200以及位于单晶硅层200表面上的微晶层201，其中微晶层201可以包括多晶硅层、硅锗合金层和锗层中的至少一种。该微晶层201的晶粒大小为1纳米～10微米，该微晶层201能够在第二晶圆20中形成富陷阱层(trap rich layer)，由此能够阻碍后续形成的绝缘体上半导体结构中的自由载流子流动，降低绝缘体上半导体结构中的寄生现象，提高绝缘体上半导体结构的电学性能。微晶层201的厚度是1微米～5微米，其形成工艺例如低压化学气相沉积的多晶硅工艺或者离子注入工艺。微晶层厚度需要控制在1微米以上，是为了有足够多陷阱(trap)能力，而超过5微米厚度的多晶硅在制造工艺的稳定性和良率上存在问题。
请继续参考图5，在步骤S4中，继续采用热氧化工艺或者化学气相沉积工艺等工艺，在微晶层201的表面上形成第二氧化键合层21，第二氧化键合层21的材质可以包括二氧化硅和氮氧化硅中的至少一种。第二氧化键合层21的厚度是2000埃～5000埃。厚度太薄，不能提供足够的键合相融界面；而厚度太厚的话，键合强度会有不同程度的降低。
需要说明的是，步骤S4只要在步骤S5之前完成即可，其可以在步骤S3之后进行，也可以在步骤S1之后且在步骤S3之前进行，还可以和步骤S3同时进行，又可以先于步骤S1进行。可选地，在步骤S2之后，将去除衬垫氧化层12的第一晶圆10和第二晶圆20放入同一个沉积工艺设备中，来采用相同的工艺条件，同时形成第一氧化键合层12和第二氧化键合层21，由此简化工艺，提高效率，即此时步骤S4和步骤S3同步进行，由此形成的第一氧化键合层12和第二氧化键合层21的厚度和性能基本一致，有利于提高键合性能。
请参考图6，在步骤S5中，通过晶圆键合工艺将第一氧化键合层12与第二氧化键合层21键合在一起，并进行退火加固，以使得第一晶圆10可靠地键合到第二晶圆20上。
需要说明的是，本步骤中，退火温度太高会导致基底晶圆层100、第一离子掺杂层101和表面晶圆层102之间发生离子再分布，而退火温度太低，不足以使得第一氧化键合层12与第二氧化键合层21可靠地键合在一起。而且退火温度太高、退火时间太长，会导致第一离子掺杂层101中的离子掺杂的纵向扩散，对离子扩散深度控制带来影响，严重时会导致最终形成的绝缘体上半导体结构的顶层半导体层的厚度不可控。另一方面，由于第一离子掺杂层101的离子注 入深度范围很窄，即使采用多次离子注入的方式来形成第一离子掺杂层101，其实际上也是在多个深度梯度内进行离子注入，来形成相应的掺杂区(也可以称为掺杂带)，在第一离子掺杂层101的厚度范围内，形成的各个深度的离子掺杂区的浓度是不均匀的，本步骤中的退火工艺还能进一步把第一离子掺杂层101中的这些不均匀掺杂带“抹平”，形成一个均匀的、有相当宽度的离子掺杂层，有利于后续的步骤S6中去除基底晶圆层100和第一离子掺杂层101，且有利于控制剩余的表面晶圆层的厚度。所以选择一个合适的退火温度和退火时间是比较关键的。可选地，退火温度为300℃～1100℃，退火时间为30分钟～180分钟，退火气体包括氦(He)、氖(Ne)、氩(Ar)、氪(Kr)、氙(Xe)、氮气(N 2)等中的至少一种惰性气体。作为一种示例，退火温度为300℃～500℃，退火时间为30分钟～150分钟。
此外，本步骤中，第一氧化键合层12与第二氧化键合层21可采用气相沉积工艺形成，相对热氧化工艺形成的氧化层的致密性低，能够在较低的退火温度下进行原子扩散，进而使得键合结合力较高。
请参考图7，在步骤S6中，通过物理的或化学的机械抛光工艺、湿法腐蚀或干法刻蚀工艺等背面减薄工艺，去除第一晶圆10的基底晶圆层100，以裸露出第一离子掺杂层101。本步骤中，由于基底晶圆层100和第一离子掺杂层101的材质不同，因此第一离子掺杂层101可以作为背面减薄工艺的停止点，以避免该背面减薄工艺对表面晶圆层102产生损伤。
请参考图8，在步骤S7中，在去除基底晶圆层100后，采用第一离子掺杂层101和表面晶圆层102具有高刻蚀选择比的选择性湿法腐蚀，来去除第一离子掺杂层101，该步骤中可以进行一定程度的过刻蚀，以在去除离子掺杂层101之后进一步减薄表面晶圆层102。剩余的表面晶圆层102的厚度可以为200埃～10微米。其中，当采用选择性湿法刻蚀工艺去除第一离子掺杂层101时，所采用的刻蚀剂包括硝酸、氢氟酸和醋酸中的至少一种，例如为硝酸、氢氟酸和醋酸的混合溶液，溶液中硝酸、氢氟酸和醋酸的摩尔比为1:10:60～1:1:1，具体可以是15：25：60，工艺温度为25℃～45℃，刻蚀时间1分钟～10分钟。此种混合溶液对高浓度掺杂P+Si的蚀刻率很快(大于10微米/分钟)，对低浓度掺杂P-Si的蚀刻率很低(小于0.01微米/分钟)，从而在刻蚀到表面晶圆层102时，实现了刻蚀反应自停止。
可选地，在去除第一离子掺杂层101之后，进一步通过精细化学机械抛光工艺，对表面晶圆层102的表面进行化学机械抛光，以去除选择性湿法刻蚀工艺后在表面晶圆层102上的残留物，并进一步对表面晶圆层102进行厚度减薄。
进一步，在去除第一离子掺杂层101之后且在对表面晶圆层102进行抛光减薄之后，还测量表面晶圆层102的厚度，并根据所述测量结果对所述表面晶圆层102进一步表面修整(trimming)，以使得表面晶圆层102的厚度达到要求，且膜厚均一性进一步提高。该厚度测量和表面修整的过程可以多次循环执行，直至所述表面晶圆层102的整体厚度和均一性都满足要求。可选地，根据所述测量结果，采用“离子束表面处理机”对所述表面晶圆层102的整体表面或者局部表面进行离子反应处理，以对所述表面晶圆层102进一步表面修整，离子束气体包含NF 3、CF 4、CHF 3、氧气、氮气、氩气等中的至少一种，能量范围在5瓦～500瓦，单片晶圆处理时间1分钟～30分钟，根据实际要求调整能量大小和处理时间长短。采用离子束对表面硅层102进行表面修整的工艺，相对现有的精细化学机械抛光，精度更高，因此能够控制剩余的表面晶圆层102(即绝缘体上硅结构的顶层硅)更薄，膜厚更均匀。
至此，请参考图8和图10，形成了绝缘体上半导体结构及其顶层半导体层102a，其中，第二晶圆20为绝缘体上半导体结构的底层半导体层，第二氧化键合层21和第一氧化键合层12为绝缘体上半导体结构的绝缘埋层，暴露出的表面晶圆层102为绝缘体上半导体结构的顶层半导体层102a。该绝缘体上半导体结构的顶层半导体层102a的厚度可达
Figure PCTCN2021101801-appb-000002
可选地，请参考图9和图10，在采用离子束对所述表面晶圆层102表面修整之后，进一步通过表面氧化处理工艺和/或各向异性刻蚀工艺，去除和修复所述表面晶圆层102的表面损伤。一种去除和修复所述表面晶圆层102的表面损伤的示例方法是，先对表面晶圆层102的表面进行高温氧化处理，工艺温度为700℃～1100℃，以在所述表面晶圆层102上形成再生氧化层13，再生氧化层13的厚度50埃～500埃。使用高温氧化的条件除了生长再生氧化层13外，可以对键合界面同时进行加固，氧化厚度考虑到了表面损伤层的深度。然后再采用包括湿法刻蚀、干法刻蚀或者精细化学机械抛光中的至少一种工艺，去除所述再生氧化层13。另一种去除和修复所述表面晶圆层102的表面损伤的示例方法是，使用四甲基氢氧化铵TMAH等碱性溶液对表面晶圆层102的表面进行各向异性 刻蚀，刻蚀时间15秒到2分钟，刻蚀温度常温，例如为25℃～45℃，以去除和修复表面晶圆层102的表面损伤。碱性溶液对硅各向异性刻蚀的特点使晶圆表面形成按晶向分布的规则晶面，从而在去除表面损伤层后得到较完美的晶圆表面。根据实际要求调整刻蚀时间长短。
可选地，通过表面氧化处理工艺和/或各向异性刻蚀工艺，去除和修复所述表面晶圆层102的表面损伤之后，还包括：采用去离子水等清洗液，对所述表面晶圆层102进行湿法清洗，以去除表面污染。
综上所述，本发明的技术方案，通过对第一晶圆进行P型离子注入，形成了第一离子掺杂层，并将所述第一晶圆划分为由基底晶圆层、第一离子掺杂层和表面晶圆层组成的三明治结构，后通过表面晶圆层表面上形成的第一氧化键合层以及第二晶圆表面上形成的第二氧化键合层，将第一晶圆键合到第二晶圆上，之后先去除基底晶圆层，再通过刻蚀工艺去除第一离子掺杂层，从而形成绝缘体上半导体结构。其中第一离子掺杂层的深度和厚度限定了绝缘体上半导体结构的顶层半导体层厚度，且该第一离子掺杂层为腐蚀增强层，能通过刻蚀工艺快速去除且不会对顶层半导体层造成不必要的损伤，以使得顶层半导体层更薄、膜厚更均匀，能满足高性能的器件的制造需求。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于本发明技术方案的范围。

Claims (20)

  1. 一种绝缘体上半导体结构的制造方法，其特征在于，包括以下步骤：
    提供第一晶圆；
    对所述第一晶圆进行P型离子注入，以在所述第一晶圆的预设深度形成第一离子掺杂层，且位于所述第一离子掺杂层顶部以上的第一晶圆部分为表面晶圆层，位于所述第一离子掺杂层底部以下的第一晶圆部分为基底晶圆层；
    在所述表面晶圆层的表面上形成第一氧化键合层；
    提供第二晶圆，并在所述第二晶圆的表面上形成第二氧化键合层；
    键合所述第一氧化键合层和所述第二氧化键合层，以将所述第一晶圆键合到所述第二晶圆上；
    去除所述基底晶圆层，以暴露出所述第一离子掺杂层；
    通过刻蚀工艺去除所述第一离子掺杂层，以暴露出所述表面晶圆层。
  2. 如权利要求1所述的制造方法，其特征在于，所述表面晶圆层为第二离子掺杂层，掺杂类型为P型或N型，掺杂浓度范围为：5E+14cm -3～5E+16cm -3。
  3. 如权利要求1所述的制造方法，其特征在于，在对所述第一晶圆进行P型离子注入之前，所述第一晶圆是整体掺杂的，或者，仅有所述表面晶圆层所在区域是掺杂的，或者，仅有所述表面晶圆层的顶部至所述离子掺杂层的底部的区域是掺杂的。
  4. 如权利要求1所述的制造方法，其特征在于，所述第一离子掺杂层的离子掺杂浓度范围为：5E+17cm -3～5E+19cm -3。
  5. 如权利要求1所述的制造方法，其特征在于，去除所述第一离子掺杂层的刻蚀工艺包括选择性湿法刻蚀工艺。
  6. 如权利要求5所述的制造方法，其特征在于，所述选择性湿法刻蚀工艺的刻蚀剂包括硝酸、氢氟酸和醋酸，刻蚀溶液中硝酸、氢氟酸和醋酸的摩尔比为1:10:60～1:1:1，工艺温度为25℃～45℃，刻蚀时间为1分钟至10分钟。
  7. 如权利要求1所述的制造方法，其特征在于，在对所述第一晶圆进行P型离子注入之前，先对所述第一晶圆进行表面清洗，并进一步在所述第一晶圆的表面上形成衬垫氧化层。
  8. 如权利要求7所述的制造方法，其特征在于，在形成所述第一离子掺杂层之后，且在形成所述第一氧化键合层之前，先去除所述衬垫氧化层。
  9. 如权利要求1所述的制造方法，其特征在于，通过采用不同的离子注入参数，来对所述第一晶圆进行多步P型离子注入，各步P型离子注入在所述第一晶圆中形成不同深度的P型离子掺杂层，进一步对所述第一晶圆进行退火处理，以使得所有的所述的P型离子掺杂层扩散形成所述第一离子掺杂层。
  10. 如权利要求1所述的制造方法，其特征在于，采用工艺温度低于600℃的气相沉积工艺来形成所述第一氧化键合层和/或所述第二氧化键合层。
  11. 如权利要求8所述的制造方法，其特征在于，在键合所述第一氧化键合层和所述第二氧化键合层之后，对键合之后的整个结构进行退火加固，退火温度为300℃～1100℃，退火时间为30分钟～180分钟，退火气体包括氮气、氩气和氢气中的至少一种。
  12. 如权利要求1所述的制造方法，其特征在于，所述第二晶圆包括单晶硅层和位于所述单晶硅层和所述第二氧化键合层之间的微晶层；所述微晶层包括多晶硅层、硅锗合金层和锗层中的至少一种。
  13. 如权利要求1所述的制造方法，其特征在于，所述第一氧化键合层和所述第二氧化键合层的材质均包括二氧化硅。
  14. 如权利要求1所述的制造方法，其特征在于，去除所述基底晶圆层的工艺包括机械研磨工艺或刻蚀工艺。
  15. 如权利要求1所述的制造方法，其特征在于，在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后，还包括：测量所述表面晶圆层的厚度，并根据所述测量结果，采用离子束对所述表面晶圆层的整体表面或者局部表面进行离子反应处理，以对所述表面晶圆层进一步表面修整。
  16. 如权利要求15所述的制造方法，其特征在于，所述离子束气体包含NF 3、CF 4、CHF 3、氧气、氮气和氩气中的至少一种，能量在5瓦～500瓦，单片晶圆处理时间1分钟～30分钟。
  17. 如权利要求15所述的制造方法，其特征在于，在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后且在对所述表面晶圆层进一步表面修整之前，先对所述表面晶圆层的表面进行化学机械抛光。
  18. 如权利要求1～17中任一项所述的制造方法，其特征在于，在去除所述第一离子掺杂层并暴露出所述表面晶圆层之后，还包括：通过表面氧化处理工艺和/或各向异性刻蚀工艺，去除所述表面晶圆层表面上的损伤。
  19. 如权利要求18所述的制造方法，其特征在于，所述表面氧化处理工艺的步骤包括：先对所述表面晶圆层进行氧化处理，以在所述表面晶圆层上形成再生氧化层，工艺温度为700℃～1100℃，再生氧化层的厚度100埃～500埃；然后，采用包括湿法刻蚀、干法刻蚀或者化学机械抛光中的至少一种工艺，去除所述再生氧化层。
  20. 如权利要求18所述的制造方法，其特征在于，所述各向异性刻蚀工艺的步骤包括：采用碱性溶液各向异性刻蚀所述表面晶圆层的表面，以去除所述表面晶圆层表面上的损伤层。
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CN101320684A (zh) * 2007-04-03 2008-12-10 胜高股份有限公司 半导体基板的制造方法
CN102903607A (zh) * 2011-06-30 2013-01-30 上海新傲科技股份有限公司 采用选择性腐蚀制备带有绝缘埋层的衬底的制备方法
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