WO2022000715A1 - 阵列基板与显示面板 - Google Patents

阵列基板与显示面板 Download PDF

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Publication number
WO2022000715A1
WO2022000715A1 PCT/CN2020/108569 CN2020108569W WO2022000715A1 WO 2022000715 A1 WO2022000715 A1 WO 2022000715A1 CN 2020108569 W CN2020108569 W CN 2020108569W WO 2022000715 A1 WO2022000715 A1 WO 2022000715A1
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WO
WIPO (PCT)
Prior art keywords
common electrode
array substrate
gate
metal layer
spacers
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Application number
PCT/CN2020/108569
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English (en)
French (fr)
Inventor
吴咏波
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/042,134 priority Critical patent/US11637131B2/en
Publication of WO2022000715A1 publication Critical patent/WO2022000715A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • the gate layer is etched twice (Re-etch) technology is more and more used in the preparation of low temperature polysilicon array substrates, using the shielding of the gate electrode to dope the active layer, because it can save a Photomask, the production cost is greatly reduced.
  • wet etching is usually used in the first etching. After the wet etching is completed, The etching solution will stay between the two traces, and there is no channel that is quickly washed away by water, so that the etching solution stays between the two traces for too long, resulting in the traces of the gate layer due to over-etching.
  • the problem of thin or even disconnected traces has a great impact on the yield and reliability of the display panel.
  • the present application provides an array substrate and a display panel.
  • the special design of the traces can effectively avoid the problem that the traces are too thin or even disconnected due to the etching solution staying for too long during the trace etching process.
  • the present invention provides an array substrate, the array substrate comprising:
  • the first metal layer, disposed on the substrate, includes a plurality of gate wirings and common electrode wirings, the gate wirings and the common electrode wirings are parallel to each other and alternately arranged in sequence, at least one of the
  • the common electrode traces are arranged intermittently, including a plurality of common electrode spacers spaced apart from each other;
  • the second metal layer disposed on the side of the first metal layer close to or away from the substrate, includes a plurality of common electrode connection parts;
  • the first insulating layer is disposed between the first metal layer and the second metal layer, and a plurality of first through holes penetrating through the first insulating layer are formed,
  • any two adjacent common electrode spacing portions are electrically connected to one corresponding common electrode connecting portion through the corresponding two first through holes, so as to realize conduction.
  • the second metal layer is disposed on a side surface of the first metal layer close to the substrate, and further includes a light shielding portion.
  • the second metal layer is disposed on the side of the first metal layer away from the substrate, and further includes source and drain electrodes.
  • At least one of the common electrode connecting portions is correspondingly disposed in a space between two adjacent common electrode spacing portions.
  • the plurality of common electrode spacers, the plurality of first through holes, and the orthographic projections of the plurality of common electrode connecting portions on the substrate are connected to each other.
  • the plurality of common electrode spacers have the same size.
  • the plurality of common electrode spacers are arranged at equal intervals.
  • any one of the common electrode traces is arranged intermittently, and includes a plurality of common electrode spacers spaced apart from each other.
  • At least one of the gate traces is intermittently arranged, and includes a plurality of gate trace spacers that are spaced apart from each other.
  • a plurality of second through holes penetrating through the first insulating layer are formed in the first insulating layer, and a gate wiring connection part is arranged in the second metal layer, wherein any two adjacent ones of the second through holes are formed.
  • the gate wiring spacing portion is electrically connected to a corresponding gate wiring connecting portion through the corresponding two second through holes, so as to realize conduction.
  • the orthographic projections of the plurality of gate wiring spacers, the plurality of second through holes and the plurality of gate wiring connection portions on the substrate connected to each other are provided by an embodiment of the present invention.
  • the gate wiring includes a gate electrode portion and a connecting wiring portion, and discontinuous positions in the gate wiring are set in the connecting wiring portion.
  • the positions of the plurality of gate wiring spacers are the same in size.
  • the plurality of gate wiring spacers are arranged at equal intervals.
  • any one of the gate wirings is arranged intermittently, and includes a plurality of gate wiring spacers spaced apart from each other.
  • the discontinuous portion of the gate wiring and the discontinuous portion of the common electrode wiring are arranged correspondingly or staggered.
  • the present invention also provides a display panel including the aforementioned array substrate.
  • the present invention provides an array substrate and a display panel.
  • the array substrate includes a first metal layer, and includes a plurality of gate wirings and common electrode wirings.
  • the common electrode traces are arranged intermittently and are divided into a plurality of mutually spaced common electrode spacers, and then the plurality of mutually spaced common electrode spacers are electrically connected in sequence through another metal layer.
  • the discontinuous part of the common electrode trace provides a channel for the etching liquid to flow away, which can greatly reduce the occurrence of the gate trace and the common electrode trace due to the inability of the etching liquid to flow away quickly.
  • the risk of engraving is avoided, thereby effectively preventing the gate wiring and the common electrode wiring from affecting the display effect and reliability of the display panel due to thin lines or even poor disconnection.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention.
  • FIG. 4 is a schematic plan view of a gate wiring in another array substrate according to an embodiment of the present invention.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present invention, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the gate layer is etched twice (Re-etch) technology is more and more used in the preparation of low temperature polysilicon array substrates, and the active layer is doped by shielding the gate electrode. , because it can save a mask, the production cost is greatly reduced.
  • wet etching because wet etching has lower cost and better etching taper angle, wet etching is usually used in the first etching. After the wet etching is completed, The etching solution will stay between the two traces, and there is no channel that is quickly washed away by water, so that the etching solution stays between the two traces for too long, resulting in the traces of the gate layer due to over-etching. The problem of thin or even disconnected traces has a great impact on the yield and reliability of the display panel.
  • the array substrate includes:
  • the first metal layer 20, disposed on the substrate, includes a plurality of gate lines 201 and common electrode lines 202, the gate lines 201 and the common electrode lines 202 are parallel to each other and alternately arranged in sequence , at least one of the common electrode traces 202 is intermittently arranged, and includes a plurality of common electrode spacers 2021 spaced apart from each other;
  • the second metal layer 40 is disposed on the side of the first metal layer 20 close to or away from the substrate, and includes a plurality of common electrode connecting portions 401 , and the second metal layer 40 can be an array substrate except for the first metal layer. Any other metal layer other than 20 is selected according to the specific structure of the array substrate. Usually, the following two points are considered for selection. First, the thickness of the insulating layer between the first metal layer and the second metal layer , if the thickness is too thick, the difficulty of opening the first through hole and the cost will have too high requirements. Second, the resistance of the second metal layer material and the first metal layer material will not be too different. Of course, this difference is also Compensation can be done by other methods, such as adjusting the width of the traces of the common electrode connection part;
  • the first insulating layer 30 is disposed between the first metal layer 20 and the second metal layer 40, and a plurality of first through holes 301 are formed through the first insulating layer,
  • any two adjacent common electrode spacing portions 2021 are electrically connected to both ends of a corresponding common electrode connecting portion 401 through the corresponding two first through holes 301 to achieve conduction. That is, the material of the first metal layer 20 or the second metal layer 40 is formed in the first through hole 301 to connect and conduct the common electrode spacer 2021 and the common electrode connecting portion 401 provided in different layers.
  • the common electrode wiring 202 is intermittently arranged, and the discontinuous portion is connected by a common electrode connecting portion provided on another metal layer. Under the condition of ensuring the function, the discontinuous portion of the common electrode wiring 202 is after etching.
  • the elution flow of the etching solution provides a flow channel, which effectively avoids the risk of over-etching of the gate wiring and the common electrode wiring due to the inability of the etching solution to flow away quickly, thus effectively avoiding the gate wiring and the common electrode wiring. If the wiring and the common electrode wiring are thin or even broken, the reliability of the display panel can be improved.
  • the second metal layer may be a light-shielding layer in the array substrate, further comprising a light-shielding portion for shielding the active layer, and the second metal layer is disposed near the first metal layer.
  • the side surface of the substrate that is, the cross-sectional structure shown in FIG. 2 is formed. Specifically, from bottom to top, it sequentially includes the substrate 10, the common electrode connecting portion 401, the first insulating layer 30, and the common electrode spacing portion 2021.
  • the common electrode The spacer portion 2021 is electrically connected to the common electrode connecting portion 401 through the first through hole 301 to form a completed common electrode wiring. It should be explained that in FIG. 2 , only a part of the structure of the array substrate is shown, and the array substrate also includes other conventional film layer structures, such as active layers, source-drain electrodes, gates, etc., which will not be described here. Repeat.
  • the second metal layer may be a metal layer used to form source-drain electrodes in the array substrate, and the second metal layer is disposed on the side of the first metal layer away from the substrate, That is, the structure shown in FIG. 3 is formed, and specifically, from bottom to top, it sequentially includes the substrate 10 , the common electrode spacing portion 2021 , the first insulating layer 30 , and the common electrode connecting portion 401 .
  • the terminals are electrically connected to the corresponding two common electrode spacers 2021 through the first through holes 301 to form a completed common electrode wiring.
  • At least one of the common electrode connecting parts is correspondingly disposed in the space between two adjacent common electrode spacing parts, that is, one common electrode connecting part is used to connect two corresponding adjacent common electrode spacing parts.
  • any one of the common electrode traces is arranged intermittently, and includes a plurality of common electrode spacers spaced apart from each other, so as to form more etching liquid circulation channels.
  • common electrode spacers spaced apart from each other, so as to form more etching liquid circulation channels.
  • the orthographic projections of the plurality of common electrode spacers 2021 , the plurality of first through holes 301 and the plurality of common electrode connecting portions 401 on the substrate are mutually connect.
  • the plurality of common electrode spacers have the same size and are arranged at equidistant intervals so as to better perform exposure and etching to form corresponding patterns.
  • the plurality of common electrode spacers are spaced apart from each other.
  • the sizes of the parts may also be different from each other, and the spacings between the plurality of common electrode spacers may also be different from each other.
  • the above-mentioned discontinuous design can be used in the gate wiring, that is, at least one of the gate wirings is discontinuously arranged, including a plurality of gate wirings.
  • the gate wiring spacers that are spaced apart from each other, at positions corresponding to the discontinuity of the gate wiring, a plurality of second through holes penetrating the first insulating layer are formed in the first insulating layer, and the first insulating layer is formed with a plurality of second through holes.
  • the two metal layers are provided with gate wiring connecting portions, wherein any two adjacent gate wiring spacing portions are connected to a corresponding gate wiring through the corresponding two second through holes.
  • the connection parts are all electrically connected to realize conduction.
  • the specific implementation manner is the same as that of the discontinuous arrangement of the common electrodes provided in the above-mentioned embodiments, and details are not repeated here.
  • the gate wiring includes a gate electrode portion 2011 and a connecting wiring portion 2012 , and discontinuous positions 2013 in the gate wiring are set in the connecting wiring portion to ensure the gate The function of the electrode portion 2011 is not affected.
  • any one of the gate wirings is arranged intermittently, and includes a plurality of gate wiring spacers spaced apart from each other.
  • the plurality of gate trace spacers, the plurality of second through holes and the orthographic projections of the plurality of gate trace connection parts on the substrate are connected to each other.
  • the discontinuous portion of the gate wiring and the discontinuous portion of the common electrode wiring are arranged correspondingly or staggered.
  • the plurality of gate wiring spacers have the same size and are arranged at equidistant intervals.
  • the sizes of the plurality of gate wiring spacers may also be different from each other according to actual process requirements.
  • the spacings between the plurality of gate trace spacers may also be different from each other.
  • Embodiments of the present invention also provide a display panel including the array substrate provided by the foregoing embodiments.

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Abstract

本发明公开了一种阵列基板与显示面板，阵列基板包括第一金属层，包括多条栅极走线与公共电极走线，至少一条公共电极走线间断设置，包括多个相互间隔的公共电极间隔部；第二金属层，包括多个公共电极连接部；第一绝缘层，形成有多个第一通孔，相邻的两个公共电极间隔部，通过两个第一通孔，与一个公共电极连接部电性连接。

Description

阵列基板与显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板与显示面板。
 背景技术
随着显示行业的蓬勃发展，出现了越来越多的优化与创新技术。其中，栅极层进行两次蚀刻（Re-etch）的技术正越来越多地应用于低温多晶硅阵列基板的制备中，利用栅电极的遮蔽对有源层进行掺杂，因其可以节省一道光罩，生产成本大幅降低。
然而，在这种两次蚀刻技术中，由于湿法蚀刻拥有更低的成本与更优的蚀刻锥形角，通常在第一道蚀刻中采用湿法蚀刻的方法进行，在湿刻完毕后，蚀刻液会停留于两条走线之间，没有快速被水洗冲走的通道，使得蚀刻液停留于两条走线之间的时间过长，从而导致栅极层的走线存在因过刻导致的走线偏细甚至断线的问题，对显示面板的良率以及可靠性有着较大影响。
 技术问题
本申请提供一种阵列基板与显示面板，通过走线的特殊设计，可有效避免走线蚀刻过程中因蚀刻药液停留过久造成走线过细甚至断线的问题。
 技术解决方案
为解决上述问题，第一方面，本发明提供一种阵列基板，所述阵列基板包括：
基板；
第一金属层，设于所述基板上，包括多条栅极走线与公共电极走线，所述栅极走线与所述公共电极走线相互平行，且依次交替设置，至少一条所述的公共电极走线为间断设置，包括多个相互间隔的公共电极间隔部；
第二金属层，设于所述第一金属层靠近或远离所述基板的侧面，包括多个公共电极连接部；
第一绝缘层，设于所述第一金属层与所述第二金属层之间，形成有多个贯穿于所述第一绝缘层的第一通孔，
其中，任意相邻的两个所述公共电极间隔部，通过对应的两个所述第一通孔，与一个对应的公共电极连接部均电性连接，以实现导通。
在本发明实施例提供的一阵列基板中，所述第二金属层设于所述第一金属层靠近所述基板的侧面，还包括遮光部。
在本发明实施例提供的一阵列基板中，所述第二金属层设于所述第一金属层远离所述基板的侧面，还包括源漏电极。
在本发明实施例提供的一阵列基板中，至少一个所述公共电极连接部对应设置于两相邻的公共电极间隔部之间的间隔中。
在本发明实施例提供的一阵列基板中，所述多个公共电极间隔部，所述多个第一通孔以及所述多个公共电极连接部在所述基板上的正投影相互连接。
在本发明实施例提供的一阵列基板中，所述多个公共电极间隔部的大小相同。
在本发明实施例提供的一阵列基板中，所述多个公共电极间隔部等距间隔排布。
在本发明实施例提供的一阵列基板中，任意一条所述的公共电极走线均为间断设置，分别包括多个相互间隔的公共电极间隔部。
在本发明实施例提供的一阵列基板中，至少一条所述栅极走线为间断设置，包括多个相互间隔的栅极走线间隔部，在所述栅极走线间断的对应位置，所述第一绝缘层中形成有多个贯穿于所述第一绝缘层的第二通孔，所述第二金属层中设有栅极走线连接部，其中，任意相邻的两个所述栅极走线间隔部，通过对应的两个所述第二通孔，与一个对应的栅极走线连接部均电性连接，以实现导通。
在本发明实施例提供的一阵列基板中，所述多个栅极走线间隔部，所述多个第二通孔以及所述多个栅极走线连接部在所述基板上的正投影相互连接。
在本发明实施例提供的一阵列基板中，所述栅极走线包括栅电极部与连接走线部，所述栅极走线中的间断位置设于所述连接走线部中。
在本发明实施例提供的一阵列基板中，所述多个栅极走线间隔部位置的大小相同。
在本发明实施例提供的一阵列基板中，所述多个栅极走线间隔部等距间隔排布。
在本发明实施例提供的一阵列基板中，任意一条所述的栅极走线均为间断设置，分别包括多个相互间隔的栅极走线间隔部。
在本发明实施例提供的一阵列基板中，所述栅极走线的间断部位与所述公共电极走线的间断部位对应设置或交错设置。
本发明还提供了一种显示面板，包括前述的阵列基板。
 有益效果
相较于现有技术，本发明提供了一种阵列基板以及显示面板，所述阵列基板中包括第一金属层，包括多条栅极走线与公共电极走线，通过将至少一条所述的公共电极走线为间断设置，分割为多个相互间隔的公共电极间隔部，再通过另一金属层将所述多个相互间隔的公共电极间隔部依次电性连接，如此设计，在所述第一金属层蚀刻之后，公共电极走线的间断部为蚀刻药液的流走提供了通道，即可大大降低因蚀刻药液无法快速流走，而导致栅极走线与公共电极走线出现过刻现象的风险，从而也有效避免栅极走线与公共电极走线因出现线细甚至断线不良而影响显示面板的显示效果与可靠性。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种阵列基板的平面结构示意图；
图2是本发明实施例提供的一种阵列基板的截面结构示意图；
图3是本发明实施例提供的另一种阵列基板的截面结构示意图；
图4是本发明实施例提供的又一种阵列基板中栅极走线的平面结构示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本发明，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本发明。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本发明的描述变得晦涩。因此，本发明并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
在现有的阵列基板中，栅极层进行两次蚀刻（Re-etch）的技术正越来越多地应用于低温多晶硅阵列基板的制备中，利用栅电极的遮蔽对有源层进行掺杂，因其可以节省一道光罩，生产成本大幅降低。然而，在这种两次蚀刻技术中，由于湿法蚀刻拥有更低的成本与更优的蚀刻锥形角，通常在第一道蚀刻中采用湿法蚀刻的方法进行，在湿刻完毕后，蚀刻液会停留于两条走线之间，没有快速被水洗冲走的通道，使得蚀刻液停留于两条走线之间的时间过长，从而导致栅极层的走线存在因过刻导致的走线偏细甚至断线的问题，对显示面板的良率以及可靠性有着较大影响。
基于现有技术中存在的问题，本发明实施例进行相应的改进，提供一种阵列基板，结合图1示出的所述阵列基板的平面结构示意图，为了更清晰的阐明本实施例的设计要点，图1中仅示出了部分结构，以下进行详细说明：
所述阵列基板包括：
基板（图中未示出）；
第一金属层20，设于所述基板上，包括多条栅极走线201与公共电极走线202，所述栅极走线201与所述公共电极走线202相互平行，且依次交替设置，至少一条所述的公共电极走线202为间断设置，包括多个相互间隔的公共电极间隔部2021；
第二金属层40，设于所述第一金属层20靠近或远离所述基板的侧面，包括多个公共电极连接部401，所述第二金属层40可为阵列基板中除第一金属层20以外的其他任意一金属层，通过阵列基板的具体结构进行选择，通常情况下，会综合考量下述两点进行选择，第一，第一金属层与第二金属层之间绝缘层的厚度，若厚度过厚，对于第一通孔的开孔难度，成本有着过高的要求，第二，第二金属层材料与第一金属层材料的电阻不易相差太大，当然，此点差异也可通过其他方法进行补偿，例如调整公共电极连接部走线的宽度；
第一绝缘层30，设于所述第一金属层20与所述第二金属层40之间，形成有多个贯穿于所述第一绝缘层的第一通孔301，
其中，任意相邻的两个所述公共电极间隔部2021，通过对应的两个所述第一通孔301，与一个对应的公共电极连接部401的两端均电性连接，以实现导通，即所述第一通孔301中形成有第一金属层20或第二金属层40的材料，将异层设置的公共电极间隔部2021与公共电极连接部401连接并导通。
在本实施例中，通过将公共电极走线202间断设置，间断部位通过另一金属层设置的公共电极连接部进行连接，在保证功能的情形下，公共电极走线202的间断部位为蚀刻后的蚀刻药液的洗脱流走提供了流通通道，有效避免了因蚀刻药液无法快速流走，而导致栅极走线与公共电极走线出现过刻现象的风险，从而也有效避免栅极走线与公共电极走线出现线细甚至断线不良，即可提升显示面板的可靠性。
在一些实施例中，所述第二金属层可为阵列基板中的遮光层，还包括对有源层进行遮光的遮光部，则所述第二金属层设于所述第一金属层靠近所述基板的侧面，即形成图2所示的截面结构，具体地，由下至上，依次包括基板10，公共电极连接部401，第一绝缘层30，以及公共电极间隔部2021，所述公共电极间隔部2021通过第一通孔301与公共电极连接部401电性连接，以形成完成的公共电极走线。需要解释地是，在图2中，仅示出了阵列基板的部分结构，所述阵列基板还包括其他常规的膜层结构，如有源层，源漏电极，栅极等，在此不做赘述。
在一些实施例中，所述第二金属层可为阵列基板中的用于形成源漏电极的金属层，则所述第二金属层设于所述第一金属层远离所述基板的侧面，即形成如图3所示的结构，具体地，由下至上，依次包括基板10，公共电极间隔部2021，第一绝缘层30，以及公共电极连接部401，所述公共电极连接部401的两端通过第一通孔301与对应的两个公共电极间隔部2021电性连接，以形成完成的公共电极走线。
在一些实施例中，至少一个所述公共电极连接部对应设置于两相邻的公共电极间隔部之间的间隔中，即一个公共电极连接部用于连接对应相邻的两公共电极间隔部。
在一些实施例中，任意一条所述的公共电极走线均为间断设置，分别包括多个相互间隔的公共电极间隔部，以形成更多的蚀刻药液流通通道，当然根据实际的阵列基板设计需求，也可仅部分公共电极走线采用间断设计。
在一些实施例中，请继续参考图1，所述多个公共电极间隔部2021，所述多个第一通孔301以及所述多个公共电极连接部401在所述基板上的正投影相互连接。
在一些实施例中，所述多个公共电极间隔部的大小相同，且等距间隔排布，以便更好地进行曝光蚀刻形成对应图案，当然根据实际的工艺需求，所述多个公共电极间隔部的大小也可彼此不同，所述多个公共电极间隔部之间的间距也可彼此不同。
在一些实施例中，为了让蚀刻药液能更迅速的洗脱流走，将上述的间断设计可用于栅极走线中，即，至少一条所述栅极走线为间断设置，包括多个相互间隔的栅极走线间隔部，在所述栅极走线间断的对应位置，所述第一绝缘层中形成有多个贯穿于所述第一绝缘层的第二通孔，所述第二金属层中设有栅极走线连接部，其中，任意相邻的两个所述栅极走线间隔部，通过对应的两个所述第二通孔，与一个对应的栅极走线连接部均电性连接，以实现导通。具体的实施方式与上述实施例提供的公共电极间断设置的方式相同，具体不再赘述。
进一步地，请参阅图4，所述栅极走线包括栅电极部2011与连接走线部2012，所述栅极走线中的间断位置2013设于所述连接走线部中，以保证栅电极部2011的功能不受影响。
同样地，在一些实施例中，任意一条所述的栅极走线均为间断设置，分别包括多个相互间隔的栅极走线间隔部。
在一些实施例中，所述多个栅极走线间隔部，所述多个第二通孔以及所述多个栅极走线连接部在所述基板上的正投影相互连接。
在一些实施例中，所述栅极走线的间断部位与所述公共电极走线的间断部位对应设置或交错设置。
在一些实施例中，所述多个栅极走线间隔部的大小相同，且等距间隔排布，当然根据实际的工艺需求，所述多个栅极走线间隔部的大小也可彼此不同，所述多个栅极走线间隔部之间的间距也可彼此不同。
本发明的实施例还提供了一种显示面板，包括前述实施例所提供的阵列基板。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文针对其他实施例的详细描述，此处不再赘述。
以上对本发明实施例所提供的一种阵列基板与显示面板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (16)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    第一金属层，设于所述基板上，包括多条栅极走线与公共电极走线，所述栅极走线与所述公共电极走线相互平行，且依次交替设置，至少一条所述的公共电极走线为间断设置，包括多个相互间隔的公共电极间隔部；
    第二金属层，设于所述第一金属层靠近或远离所述基板的侧面，包括多个公共电极连接部；
    第一绝缘层，设于所述第一金属层与所述第二金属层之间，形成有多个贯穿于所述第一绝缘层的第一通孔，
    其中，任意相邻的两个所述公共电极间隔部，通过对应的两个所述第一通孔，与一个对应的公共电极连接部均电性连接，以实现导通。
  2. 如权利要求1所述的阵列基板，其中，所述第二金属层设于所述第一金属层靠近所述基板的侧面，还包括遮光部。
  3. 如权利要求1所述的阵列基板，其中，所述第二金属层设于所述第一金属层远离所述基板的侧面，还包括源漏电极。
  4. 如权利要求1所述的阵列基板，其中，至少一个所述公共电极连接部对应设置于两相邻的公共电极间隔部之间的间隔中。
  5. 如权利要求1所述的阵列基板，其中，所述多个公共电极间隔部，所述多个第一通孔以及所述多个公共电极连接部在所述基板上的正投影相互连接。
  6. 如权利要求1所述的阵列基板，其中，所述多个公共电极间隔部的大小相同。
  7. 如权利要求1所述的阵列基板，其中，所述多个公共电极间隔部等距间隔排布。
  8. 如权利要求1所述的阵列基板，其中，任意一条所述的公共电极走线均为间断设置，分别包括多个相互间隔的公共电极间隔部。
  9. 如权利要求1所述的阵列基板，其中，至少一条所述栅极走线为间断设置，包括多个相互间隔的栅极走线间隔部，在所述栅极走线间断的对应位置，所述第一绝缘层中形成有多个贯穿于所述第一绝缘层的第二通孔，所述第二金属层中设有栅极走线连接部，其中，任意相邻的两个所述栅极走线间隔部，通过对应的两个所述第二通孔，与一个对应的栅极走线连接部均电性连接，以实现导通。
  10. 如权利要求9所述的阵列基板，其中，所述多个栅极走线间隔部，所述多个第二通孔以及所述多个栅极走线连接部在所述基板上的正投影相互连接。
  11. 如权利要求9所述的阵列基板，其中，所述栅极走线包括栅电极部与连接走线部，所述栅极走线中的间断位置设于所述连接走线部中。
  12. 如权利要求9所述的阵列基板，其中，所述多个栅极走线间隔部的大小相同。
  13. 如权利要求9所述的阵列基板，其中，所述多个栅极走线间隔部等距间隔排布。
  14. 如权利要求9所述的阵列基板，其中，任意一条所述的栅极走线均为间断设置，分别包括多个相互间隔的栅极走线间隔部。
  15. 如权利要求9所述的阵列基板，其中，所述栅极走线的间断部位与所述公共电极走线的间断部位对应设置或交错设置。
  16. 一种显示面板，其中，所述显示面板包括权利要求1所述的阵列基板。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113538A1 (en) * 2004-12-01 2006-06-01 Lg Philips Lcd Co., Ltd. Thin film transistor substrate and fabricating method thereof
CN104155817A (zh) * 2014-07-17 2014-11-19 京东方科技集团股份有限公司 一种像素结构及其制造方法、显示基板和显示装置
CN104835782A (zh) * 2015-05-20 2015-08-12 合肥京东方光电科技有限公司 阵列基板及其制作方法、显示装置
CN105068349A (zh) * 2015-09-16 2015-11-18 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置以及阵列基板的制作方法
CN108364936A (zh) * 2018-02-26 2018-08-03 武汉华星光电技术有限公司 阵列基板及其制备方法、显示面板和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130200377A1 (en) * 2012-02-06 2013-08-08 Shenzhen China Star Optoelectronics Technology Co. Ltd Thin film transistor array substrate and method for manufacturing the same
CN206115109U (zh) * 2016-08-31 2017-04-19 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN106353943B (zh) * 2016-10-26 2019-09-17 上海天马微电子有限公司 一种阵列基板、显示面板以及驱动方法
CN107179639B (zh) * 2017-05-25 2020-01-21 上海中航光电子有限公司 阵列基板及其制作方法和显示面板
CN107608152A (zh) * 2017-09-15 2018-01-19 上海天马微电子有限公司 阵列基板及显示面板
CN107561800B (zh) * 2017-09-19 2020-08-04 武汉天马微电子有限公司 一种阵列基板、显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113538A1 (en) * 2004-12-01 2006-06-01 Lg Philips Lcd Co., Ltd. Thin film transistor substrate and fabricating method thereof
CN104155817A (zh) * 2014-07-17 2014-11-19 京东方科技集团股份有限公司 一种像素结构及其制造方法、显示基板和显示装置
CN104835782A (zh) * 2015-05-20 2015-08-12 合肥京东方光电科技有限公司 阵列基板及其制作方法、显示装置
CN105068349A (zh) * 2015-09-16 2015-11-18 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置以及阵列基板的制作方法
CN108364936A (zh) * 2018-02-26 2018-08-03 武汉华星光电技术有限公司 阵列基板及其制备方法、显示面板和显示装置

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