WO2021248862A1 - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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Publication number
WO2021248862A1
WO2021248862A1 PCT/CN2020/135923 CN2020135923W WO2021248862A1 WO 2021248862 A1 WO2021248862 A1 WO 2021248862A1 CN 2020135923 W CN2020135923 W CN 2020135923W WO 2021248862 A1 WO2021248862 A1 WO 2021248862A1
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Prior art keywords
chip
flip
substrate
semiconductor package
package structure
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PCT/CN2020/135923
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English (en)
French (fr)
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罗飞宇
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深圳市大疆创新科技有限公司
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Publication of WO2021248862A1 publication Critical patent/WO2021248862A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/481—Constructional features, e.g. arrangements of optical elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors

Definitions

  • the present invention claims the priority of a Chinese patent application whose application date is June 9, 2020, the application number is CN 202021042282.9, and the invention-creation title is "Semiconductor Package Structure".
  • the present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure.
  • Lidar is a perception system used to perceive the outside world. It can learn the three-dimensional three-dimensional information of the outside world. Its principle is to actively transmit laser pulse signals to the outside and detect the reflected echo signals according to the time difference between the transmitted signal and the received signal. , To determine the distance of the object to be measured; combined with the emission direction information of the light pulse, the three-dimensional depth information of the object to be learned can be reconstructed.
  • the laser radar can be operated at a low speed even without rotating parts when the number of lines increases sharply. Detect environmental data more comprehensively and azimuth, so as to realize solid-state lidar.
  • the purpose of the present disclosure is to provide a semiconductor package structure, thereby at least to a certain extent overcoming one or more problems caused by the limitations and defects of related technologies.
  • the present disclosure provides a semiconductor packaging structure, including: a carrying case; a first chip arranged on a first surface of the carrying case, wherein the first chip is a flip chip and includes flip chip bumps; Two chips, the second chip is a flip chip, including flip chip bumps; and a transfer substrate; wherein a part of the flip chip bumps of the first chip is electrically connected to the flip chip bumps of the second chip , Another part of the flip-chip bump of the first chip is electrically connected to the carrying case through the transfer substrate.
  • the first chip is a driving chip
  • the second chip is a photoelectric receiving sensor chip
  • the load-bearing shell includes: a tube shell cavity, the tube shell cavity is a semi-closed structure with an opening, and the inner surface of the tube shell cavity is provided with Bonding fingers; the first surface of the transfer substrate is electrically connected to the other part of the flip-chip bump of the drive chip through a preset solder block, and the second surface of the transfer substrate is provided with a first pad ; The first pad and the bonding finger are electrically connected through a wire.
  • the arrangement form of the bonding fingers is single row, double row or multiple rows; and/or, the arrangement form of the first pad is single row, double row or Multiple rows; and/or, the arrangement of the preset solder blocks is single row, double row or multiple rows.
  • a filling material layer is provided between the driving chip and the photoelectric receiving sensor chip.
  • the driving chip is disposed on the bottom of the inner surface of the package cavity through a first epoxy resin or solder; wherein, the first epoxy resin includes conductive silver Paste or non-conductive silver paste.
  • connection mode between the driving chip, the photoelectric receiving sensor chip and the transfer substrate includes: a single substrate or a single chip-to-wafer welding; or, a single substrate Or single chip to single chip soldering.
  • the carrying shell further includes glass, and the glass is connected to the tube shell cavity at the opening of the tube shell cavity through a second epoxy resin to form Seal the space.
  • the minimum distance between adjacent preset solder bumps is greater than or equal to 150 microns.
  • the preset solder block includes any one of the following solder layers: SnAg1.8 alloy layer, SnAg3.5 alloy layer, AuSn alloy layer, INP alloy layer, PbSnAg alloy layer and SnAgCu alloy layer.
  • the transfer substrate is in the shape of a "mouth” shape, and the four inner corners of the "mouth” shape include a right angle, a 45° chamfer, or an R angle.
  • the transfer substrate is one of the following substrates: FR4 material substrate, rogers material substrate, BT material substrate, and ceramic material substrate.
  • the number of layers of the transfer substrate is one of the following layers: 2 layers, 3 layers, 4 layers, and 6 layers.
  • any one of the following metal layers is preset on the first pad: a silver layer, a gold layer, a nickel/gold layer, a nickel/platinum/gold layer, and a nickel/platinum layer. /Silver/gold layer; and/or, any one of the following metal layers is preset on the preset solder block: tin layer, gold layer, nickel/gold layer and nickel/platinum/gold layer.
  • the photoelectric receiving sensor chip is one of the following chips: an avalanche photodiode, a single-photon avalanche photodiode, a photodiode, a single-photon detector, and a CMOS image sensor.
  • the carrying housing includes a first substrate and a transparent plastic packaging material, and the transparent plastic packaging material combines the photoelectric receiving sensor chip, the transfer substrate, and the photoelectric receiving sensor chip, the transfer substrate, and the photoelectric receiving sensor chip by injection molding or dispensing.
  • the driving chip and the first substrate are plastic-encapsulated as a whole.
  • a part of the flip-chip bumps of the first chip is connected to the flip-chip bumps of the second chip, and another part of the flip-chip bumps of the first chip is connected to the carrying case through the transfer substrate , Can effectively reduce the volume and process difficulty of the package structure.
  • FIG. 1 is a cross-sectional view of a semiconductor packaging structure in the prior art
  • FIG. 2 is a cross-sectional view of another semiconductor packaging structure in the prior art
  • Figure 3 is a cross-sectional view of a chip structure in the prior art
  • FIG. 5 is a cross-sectional view of a semiconductor package structure according to an example embodiment of the present disclosure.
  • FIG. 6 is a cross-sectional view of a customization process of an example embodiment of the present disclosure.
  • FIG. 7 is a top view of a customization process of an example embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view of a flip-chip bump according to an example embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view of an interposer substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view of a semiconductor package structure according to another example embodiment of the present disclosure.
  • FIG. 11 is a top view of a semiconductor package structure according to another example embodiment of the present disclosure.
  • FIG. 12 is a cross-sectional view of a semiconductor package structure according to still another example embodiment of the present disclosure.
  • the area array photoelectric receiving sensor such as APD (Avalanche Photodiode)
  • the corresponding small signal amplification and signal acquisition and processing circuit also needs to achieve area array and miniaturization, and the area array photoelectric sensor chip 101 needs to be realized.
  • IO Input/Output
  • PCB printed circuit board
  • the ASIC driver chip based on the COMS (Complementary Metal Oxide Semiconductor) process needs to be gold-plated on the AlPad (aluminum pad), such as Ti/Ni/Au (titanium/nickel) /Gold) layer and other metallization systems.
  • AlPad aluminum pad
  • Ti/Ni/Au (titanium/nickel) /Gold titanium/Ni/Au (titanium/nickel) /Gold
  • This solution adopts 0.35um specifications and other backward processes for special factory customization, and the evolution of each process node requires special customization, which is not compatible with traditional CMOS processes and cannot be advanced with advanced technology. The rapid evolution and evolution of CMOS nanotechnology cannot improve integration and performance.
  • the current traditional CMOS process chip one is the wire bonding chip 301 as shown in Figure 3, the AlPad window 303 leads the IO signal on the chip (Die) through the bonding wire; the other is shown in Figure 4
  • the UBM (Under Bump Metallurgy) on the chip forms a Solder bump (solder bump) 403 or Cu pillar (copper bump) to solder the IO signal to the substrate and lead the signal out.
  • an embodiment of the present disclosure provides a semiconductor package structure, including: a carrying case; a first chip 501 disposed on a first surface of the carrying case, wherein the first chip 501 is a flip chip, including Flip-chip bumps 505; second chip 502, second chip 502 is flip-chip, including flip-chip bumps 506; and transfer substrate 503; wherein, a part of the flip-chip bumps of the first chip 501 and the second chip 502
  • the flip-chip bumps of the first chip 501 are electrically connected, and the other part of the flip-chip bumps of the first chip 501 are electrically connected to the carrier shell through the transfer substrate 503.
  • the first surface of the carrying case is the upper surface of the carrying case as shown in FIG. 5.
  • the flip chip bumps can be flip chip copper bumps.
  • the driver chip without the need for a special customized process, the driver chip only needs to adopt the traditional flip chip solder ball or copper bump structure packaging process to realize the chip-to-chip and transfer basic-to-chip welding interconnection.
  • the transfer substrate can be wire-welded using mature ultrasonic bonding technology to draw out the power ground and IO signals that need to be drawn.
  • the package size of the semiconductor package structure can be greatly reduced, and the transfer substrate can be made of FR4 (a flame-resistant material grade) PCB material, or BT (bismaleimide) Triazine) resin material, do not need to use more costly through silicon via insertion, the packaging cost can be greatly reduced.
  • the driver chip does not require special customization, which can achieve rapid evolution with Moore's Law, shorten the development cycle, and save customization costs.
  • the first chip 501 may be a driver chip, such as an ASIC chip, and the second chip 502 may be a photoelectric receiving sensor chip.
  • flip-chip copper bumps 601 need to be implemented on the same chip and aluminum pad openings 602 must be retained.
  • the present disclosure proposes a die-to-die interconnection package structure based on the evolution and decoupling of the traditional CMOS flip-chip process ASIC chip.
  • the ASIC chip does not need to adopt the mainstream wafer manufacturer's customized process, but only adopts as shown in the figure.
  • the traditional CMOS process flip-chip process shown in 4 can continuously evolve through Moore's Law to improve integration and performance, which can not only meet the signal interconnection and communication between the photoelectric receiving sensor chip and the driver chip, but also make it easier for the IO that needs to be drawn out. And more reliable lead and external hardware circuit interconnection communication, thereby reducing the difficulty of packaging process and improving reliability.
  • the photoelectric receiving sensor chip is usually a 4 to 6 inch wafer, while the ASIC chip uses a CMOS process to usually 8 to 12 inches.
  • Image Sensor The mainstream through-silicon via welding or hybrid bonding (hybrid bonding).
  • the carrying shell may be a shell cavity 504, the shell cavity 504 is a semi-closed structure with an opening, and a bonding finger is provided on the inner surface of the shell cavity. 507;
  • the first surface of the interposer substrate 503 is electrically connected to another part of the flip-chip bumps of the driver chip 501 through a preset solder block 514, and the second surface of the interposer substrate 503 is provided with a first pad 508; a first pad 508 and the bonding finger 507 are electrically connected by a wire 509.
  • the wire 509 may be a gold wire.
  • the flip-chip bump of the flip chip includes a copper bump 801 and a solder layer 802, and a stress buffer layer 803 is provided under the copper bump 801.
  • the stress buffer layer 803 may be formed of PI (Polyimide, polyimide) material, which can relieve the stress on the chip.
  • a bump to bump (bump to bump) chip bonding process is adopted. Since the upper chip and the lower chip both contain flip-chip bumps, there is a PI layer under the flip-chip bumps as the stress buffer layer, which is equivalent to the stress buffer layer on the upper chip and the lower chip, and the height of the bumps on both sides , The upper bump and the lower bump are superimposed, and the distance between the chips increases, which also helps to reduce the stress on the upper chip and the lower chip, effectively avoiding bump crack and E-lowK cracking caused by stress, thereby improving The reliability of chip-to-chip interconnection is improved.
  • the first surface of the transfer substrate is the lower surface of the transfer substrate.
  • the pad and plating process on the first surface of the transfer substrate includes pre-set solder blocks, OSP (Organic Solderability Preservatives, organic solder mask), and pad electroplating metal layer.
  • OSP Organic Solderability Preservatives, organic solder mask
  • the preset solder block 514 includes any of the following solder layers: SnAg1.8 (tin-silver, in which the content of silver is 1.8%) alloy layer, SnAg3.5 (tin-gold, in which the content of gold is 3.5%) alloy layer, AuSn( Copper-tin) alloy layer, INP (indium phosphide) alloy layer, PbSnAg (lead tin silver) alloy layer and SnAgCu (tin silver copper) alloy layer.
  • a tin layer, a gold layer, a nickel/gold layer, or a nickel/platinum/gold layer can be preset on the preset solder block 514, and it is not limited thereto.
  • the nickel/gold layer has a two-layer structure including a nickel layer and a gold layer
  • the nickel/platinum/gold layer has a three-layer structure including a nickel layer, a platinum layer, and a gold layer.
  • the preset solder block 514 is arranged on the first surface of the transfer substrate.
  • the preset solder block can be processed by the flattening process or not processed by the flattening process, and is used for flip-chip soldering with the flip-chip bumps on the ASIC chip Make the interconnection.
  • the preset solder block is connected to the first pad 508 through vias and traces.
  • the first pad 508 may be electroplated with any metal layer such as a silver layer, a gold layer, a nickel/gold layer, a nickel/platinum/gold layer, and a nickel/platinum/silver/gold layer, and is not limited thereto.
  • the nickel/platinum/silver/gold layer has a four-layer structure including a nickel layer, a platinum layer, a silver layer, and a gold layer.
  • the power ground and signal IO can be led out by welding gold or copper wires by ultrasonic welding technology.
  • the arrangement of the first pads 508 can be single row, double row, or multiple rows according to the number of signals to be drawn out.
  • the bonding fingers 507 and the preset solder blocks 514 can be in a single row or a double row, or can be designed in multiple rows according to the number of signals to be derived.
  • the minimum distance between adjacent preset solder bumps 514 is greater than or equal to 150 microns.
  • the driving chip is disposed on the bottom of the inner surface of the shell cavity through the first epoxy resin 511 or solder; wherein, the first epoxy resin includes conductive silver paste or non-conductive silver paste.
  • the carrying shell further includes glass 512, and the glass is connected to the shell cavity 504 at the opening of the shell cavity through the second epoxy resin 513 to form a sealed space.
  • connection mode between the driving chip, the photoelectric receiving sensor chip and the transfer substrate 503 may be a single substrate or a single chip-to-wafer soldering; or, a single substrate or a single chip-to-single chip soldering.
  • the transfer substrate 901 has a "mouth” shape, and the four inner corners of the "mouth” shape include a right angle, a 45° chamfer, or an R angle.
  • the word “ ⁇ " in the transfer substrate can be formed by processing methods such as die punching or laser cutting.
  • the four inner corners can be right angles, 45° chamfering or R-angle processing can also be used to help alleviate the stress on the bumps at the four corners.
  • the transfer substrate 514 may be an FR4 material substrate, a Rogers (a kind of plate) material substrate, a BT material substrate or a ceramic material substrate, and is not limited thereto.
  • BT may be a LOW CTE core (low thermal expansion core) BT material
  • CTE may be a BT material of 3 ppm to 8 ppm.
  • ppm is a unit of defective rate
  • 1 ppm is one part per million.
  • the preset solder block 514 is connected to the first pad 508 through vias 902 and traces.
  • the number of layers of the transfer substrate 514 can be 2, 3, 4, or 6, and is not limited thereto.
  • the photoelectric receiving sensor chip can be APD (Avalanche Photo Diode, avalanche photodiode), SAPD (single photon Avalanche Diode, single photon avalanche photodiode), PD (photodiode, photodiode), SPD (single photon detector, single photon detector) Or CIS (CMOS Image sensor, CMOS image sensor), but it is not limited to this.
  • APD Avalanche Photo Diode, avalanche photodiode
  • SAPD single photon Avalanche Diode, single photon avalanche photodiode
  • PD photodiode, photodiode
  • SPD single photon detector, single photon detector
  • CIS CMOS Image sensor, CMOS image sensor
  • the photoelectric receiving sensor and the transfer substrate can be absorbed by the bond head of the chip bonding equipment, and the flux (flux) can be placed on the ASIC.
  • the flip-chip bumps of the chip the flip-chip bumps of the photoelectric receiving sensor and the preset solder bumps of the transfer substrate correspond to the flip-chip bumps of the ASIC chip respectively, and the transfer substrate and the transfer substrate are fixed by the viscosity of the flux itself.
  • the photoelectric receives the sensor chip, and the three are reflowed (reflow soldering) through the reflow oven.
  • the flux residues between the flip chip bumps and the flux residues and foreign objects on the light receiving surface of the photoelectric receiving sensor chip, that is, the pixel surface are cleaned through a cleaning process to avoid affecting the light collection efficiency.
  • a filling material layer 510 is provided between the driving chip 501 and the photoelectric receiving sensor chip 502.
  • the filling material of the filling material layer may be underfill (underfill).
  • the underfill device When the filling material layer is formed, it needs to be cleaned, and then the underfill device is used to point the underfill in the gel state on the reserved dispensing edge of the ASIC chip.
  • the underfill is filled between the flip-chip bumps under capillary action Then, the underfill is cured by baking in an oven.
  • the cured underfill can protect the flip-chip bumps and increase reliability. At the same time, it can support the transfer substrate and avoid subsequent ultrasonic welding. Causes problems such as bump cracks during wire welding.
  • the three-component combination after the underfill has been cured is sucked by the chip bonding equipment, and placed in the shell cavity, and soldered with the shell cavity through the first epoxy resin or solder.
  • the first epoxy resin is cured or soldered
  • the first pad on the upper surface of the transfer substrate including the power ground and the signal IO is connected to the finger (bonding finger) on the package cavity substrate by ultrasonic bonding wire welding.
  • the airtight cavity is beneficial to improve the light collection efficiency and dust resistance of the photoelectric receiving sensor chip, and the light transmittance of the transparent resin is only about 90%.
  • the above packaging process is only a typical packaging process.
  • the key transfer substrate and the photoelectric receiving sensor chip are soldered to the ASIC chip.
  • Flux and The reflow soldering process can also use TC bond (thermo-compression) or other soldering methods, such as adding reducing gases such as hydrogen, a mixture of hydrogen and nitrogen during the soldering process, so as to avoid flux residue and
  • the volatilization pollutes the light receiving area of the photoelectric receiving chip thereby affecting the light receiving efficiency and response, and at the same time reducing the cleaning process, thereby simplifying the packaging process and reducing the packaging cost.
  • the process flow of the semiconductor packaging structure shown in FIG. 5 forming a sealed cavity by the glass cover is only a packaging process of the embodiments of the present disclosure.
  • transparent plastic molding materials or dispensing methods can also be used to form a sealed cavity.
  • the photoelectric receiving sensor chip, the transfer substrate, the driving chip, the wire and the first substrate are molded and protected by plastic packaging.
  • the carrying case may include a first substrate 1201 and a transparent plastic packaging material 1202.
  • the transparent plastic packaging material plasticizes the photoelectric receiving sensor chip, the transfer substrate, the driving chip, and the first substrate into one body by injection molding or dispensing.
  • a part of the flip-chip bumps of the first chip is connected to the flip-chip bumps of the second chip, and another part of the flip-chip bumps of the first chip is connected to the carrying case through the transfer substrate , It can effectively reduce the volume and process difficulty of the packaging structure, and simply and conveniently realize the area array photoelectric receiving sensor with thousands or tens of thousands of lines.

Abstract

一种半导体封装结构，包括：承载壳体；第一芯片（501），设置于所述承载壳体的第一表面，其中，所述第一芯片（501）为倒装芯片，包括倒装凸块（505）；第二芯片（502），所述第二芯片（502）为倒装芯片，包括倒装凸块（506）；和转接基板（503）；其中，所述第一芯片（501）的一部分倒装凸块（505）与所述第二芯片（502）的倒装凸块（506）电连接，所述第一芯片（501）的另一部分倒装凸块（505）通过所述转接基板（503）与所述承载壳体电连接。所述半导体封装结构可以有效减小封装结构的体积和工艺难度。

Description

半导体封装结构
本发明要求申请日为2020年06月09日、申请号为CN 202021042282.9、发明创造名称为《半导体封装结构》的中国专利申请的优先权。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体封装结构。
背景技术
激光雷达是用于对外界进行感知的感知系统，可以获知外界的立体三维信息，其原理为，主动对外发射激光脉冲信号，探测到反射的回波信号，根据发射信号和接收信号之间的时间差，判断被测物体的距离；再结合光脉冲的发射方向信息，便可重建待获知物体的三维深度信息。
如何在特定的时间内实现对视场中尽可能多的方位进行测量是激光雷达的一个技术难点。
一种解决方法是使用单线、多线光源发光传感器和单线、多线接收传感器收发组合配合转动部件对多个方向进行探测，以有效增大探测的方位，从而获取空间分辨率更高的环境数据。但这种叠加的方式，一般叠加线数有限，从单线，6线，12线，16线，32线，64线，128线，再增大叠加线数时，加工难度、体积和成本急剧增加，且线数增大时需要旋转部件增加探测方位，旋转部件的长期可靠性存在挑战。
如果存在更多线数如几千，几万线甚至更多线的面阵光电接收传感器，则可以在线数急剧增加的情况下，实现激光雷达的低转速动，甚至不需要转动部件，即可更全面方位地探测环境数据，从而实现固态激光雷达。
现有技术中的技术方案无法简单方便地有效减小封装结构的体积和工艺难度，进而实现几千或几万线等多线数的面阵光电接收传感器。
发明内容
本公开的目的在于提供一种半导体封装结构，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开提供一种半导体封装结构，包括：承载壳体；第一芯片，设置于所述承载壳体的第一表面，其中，所述第一芯片为倒装芯片，包括倒装凸块；第二芯片，所述第二芯片为倒装芯片，包括倒装凸块；和转接基板；其中，所述第一芯片的一部分倒装凸块与所述第二芯片的倒装凸块电连接，所述第一芯片的另一部分倒装凸块通过所述转接基板与所述 承载壳体电连接。
在本公开的一种示例性实施例中，所述第一芯片为驱动芯片，所述第二芯片为光电接收传感器芯片。
在本公开的一种示例性实施例中，所述承载壳体包括：管壳腔体，所述管壳腔体为具有开口的半封闭结构，所述管壳腔体的内表面上设置有键合指；所述转接基板的第一表面通过预置焊料块与所述驱动芯片的所述另一部分倒装凸块电连接，所述转接基板的第二表面设置有第一焊盘；所述第一焊盘与所述键合指通过导线电连接。
在本公开的一种示例性实施例中，所述键合指的排列形式为单排、双排或者多排；和/或，所述第一焊盘的排列形式为单排、双排或者多排；和/或，所述预置焊料块的排列形式为单排、双排或者多排。
在本公开的一种示例性实施例中，所述驱动芯片和所述光电接收传感器芯片之间设置有填充材料层。
在本公开的一种示例性实施例中，所述驱动芯片通过第一环氧树脂或焊料设置于所述管壳腔体的内表面的底部；其中，所述第一环氧树脂包括导电银浆或不导电银浆。
在本公开的一种示例性实施例中，所述驱动芯片、所述光电接收传感器芯片和所述转接基板之间的连接方式包括：单个基板或者单个芯片到晶圆焊接；或者，单个基板或者单个芯片到单个芯片焊接。
在本公开的一种示例性实施例中，所述承载壳体还包括玻璃，所述玻璃通过第二环氧树脂与所述管壳腔体在所述管壳腔体的开口处连接，形成密封空间。
在本公开的一种示例性实施例中，相邻的所述预置焊料块间的最小间距大于或等于150微米。
在本公开的一种示例性实施例中，所述预置焊料块包括以下任一种焊料层：SnAg1.8合金层，SnAg3.5合金层，AuSn合金层，INP合金层，PbSnAg合金层和SnAgCu合金层。
在本公开的一种示例性实施例中，所述转接基板呈“口”字形，所述“口”字形的四个内角包括直角、45°倒角或者R角。
在本公开的一种示例性实施例中，转接基板为下列基板其中之一：FR4材料基板、rogers材料基板、BT材料基板和陶瓷材料基板。
在本公开的一种示例性实施例中，所述转接基板的层数为下列层数其中之一：2层、3层、4层和6层。
在本公开的一种示例性实施例中，所述第一焊盘上预置有以下任一种金属层：银层、金层、镍/金层、镍/铂/金层和镍/铂/银/金层；和/或，所述预置焊料块上预置有以下任一种金属层：锡层、金层、镍/金层和镍/铂/金层。
在本公开的一种示例性实施例中，所述光电接收传感器芯片为下列芯片其中之一：雪崩光电二极管、单光子雪崩光电二极管、光电二极管、单光子探测器和CMOS图像传感器。
在本公开的一种示例性实施例中，所述承载壳体包括第一基板和透明塑封材料，所述透明塑封材料通过注塑或者点胶方式将光电接收传感器芯片、所述转接基板、所述驱动芯片和所述第一基板塑封为一体。
本公开的技术方案中，通过将第一芯片的一部分倒装凸块和第二芯片的倒装凸块连接，并将第一芯片的另一部分倒装凸块通过转接基板连接到承载壳体，可以有效减小封装结构的体积和工艺难度。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1为现有技术中一种半导体封装结构的剖视图；
图2为现有技术中另一种半导体封装结构的剖视图；
图3为现有技术中一种芯片结构的剖视图；
图4为现有技术中另一种芯片封装结构的剖视图；
图5为本公开一种示例实施方式的半导体封装结构的剖视图；
图6为本公开一种示例实施方式的定制工艺的剖视图；
图7为本公开一种示例实施方式的定制工艺的俯视图；
图8为本公开一种示例实施方式的倒装凸块的剖视图；
图9为本公开一种示例实施方式的转接基板的剖视图；
图10为本公开另一种示例实施方式的半导体封装结构的剖视图；
图11为本公开另一种示例实施方式的半导体封装结构的俯视图；
图12为本公开又一种示例实施方式的半导体封装结构的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接” 设置在其它结构上。
用语“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，要实现面阵化的光电接收传感器如APD(雪崩光电二极管)，对应小信号放大和信号采集处理电路也需要实现面阵化、小型化，并需要实现面阵光电接传感器芯片101和ASIC(Application-Specific Integrated Circuit，专用集成电路)驱动芯片102之间的Die to Die(芯片到芯片)互联通信，同时也需要引出部分IO(Input/Output，输入输出)信号引脚103与PCB(印刷电路板)上其他硬件连接，其电路互联如图1所示。
如图1所示，基于COMS(Complementary Metal Oxide Semiconductor，互补型金属氧化物半导体)工艺的ASIC驱动芯片需要在AlPad(铝焊盘)上进行镀金制程，如镀Ti/Ni/Au(钛/镍/金)层等金属化体系，该方案采用0.35um规格等较落后的工艺进行工厂特殊定制，且每个工艺节点的演进，均需要特殊定制，无法与传统的CMOS工艺兼容，无法随着先进CMOS纳米工艺的快速演进而演进、无法提升集成度和性能。
如图2所示，为了实现面阵光电接收传感器201与传统CMOS的ASIC驱动芯片202的互联，且不需要与工厂特殊定制工艺，往往需要引入TSV(Through Silicon Via，硅通孔)203Si(硅)interposer(插入)工艺实现side by side(并排)互联。这样CMOS的ASIC驱动芯片202不需要采用特殊定制工艺，采用传统COMS工艺即可以实现随着摩尔定律每间隔18～24个月演进一代，可以从55nm，28nm，16nm，10nm，7nm，5nm至3nm不断演进，以提升集成度和性能，但采用cowos(Chip-on-Wafer-on-Substrate，衬底上的晶圆上的芯片)封装技术并排的互联存在诸多问题，例如封装尺寸大，成本高，芯片间互联信号走线长，寄生电容电感大等，从而影响电性能。
当前的传统的CMOS工艺芯片，一种是如图3所示的线焊接芯片301，Al Pad开窗303通过焊接线将芯片(Die)上的IO信号引出；另外一种是如图4所示的倒装芯片401，芯片上UBM(Under Bump Metallurgy，底部凸块金属化)形成Solder bump(焊锡凸块)403或者Cu pillar(铜凸点)将IO信号与基板焊接，将信号引出。
如果需要线焊接铝焊盘和倒装焊锡凸块或者铜凸点同时在同一芯片(Die)上通过芯片(Die)Hybrid bond(混合焊接)实现，如图4所示，需要进行特殊工艺定制，而且CMOS工艺遵循摩尔定律，如果有这种需求的ASIC芯片需要跟随摩尔定律演进和提升集成度和性能，就需要每一代工艺均进行特殊定制，这样会导致ASIC芯片的演进定制成本高，时间长甚至无晶圆厂商可以实现。
可见，相关技术方案无法简单方便地有效减小封装结构的体积和工艺难度，进而实现几千或几万线等多线数的面阵光电接收传感器。
如图5所示，本公开实施例提供一种半导体封装结构，包括：承载壳体；第一芯片501，设置于承载壳体的第一表面，其中，第一芯片501为倒装芯片，包括倒装凸块505； 第二芯片502，第二芯片502为倒装芯片，包括倒装凸块506；和转接基板503；其中，第一芯片501的一部分倒装凸块与第二芯片502的倒装凸块电连接，第一芯片501的另一部分倒装凸块通过转接基板503与承载壳体电连接。
这里，承载壳体的第一表面为如图5所示的承载壳体的上表面。倒装凸块可以为倒装铜凸点。
在本公开实施例中，在不需要特殊定制工艺的条件下，驱动芯片上仅需采用传统倒装焊锡球或者铜凸块结构封装工艺即可实现芯片到芯片、转接基本到芯片的焊接互联，同时转接基板可以采用成熟的工艺超声波键合技术进行线焊接，将需要引出的电源地和IO信号引出。
相比较cowos并排互联方式，采用本公开实施例的技术方案，半导体封装结构的封装尺寸可以大幅缩小，同时转接基板可以采用FR4(一种耐燃材料等级)的PCB材料，也可以采用BT(bismaleimide triazine)树脂材料，不需要采用较成本较高的硅通孔插入，封装成本可以大幅减少。另外，驱动芯片不需要特殊定制，可以实现随摩尔定律快速演进，缩短了开发周期，同时节省了定制成本。
在本公开实施例中，第一芯片501可以为驱动芯片，例如ASIC芯片，第二芯片502可以为光电接收传感器芯片。
如图6和图7所示，在一种主流晶圆厂商定制工艺中，同一芯片上需要实现倒装铜凸点601又要保留铝焊盘开窗602。
本公开提出了一种基于传统CMOS倒装工艺ASIC芯片演进解耦的芯片到芯片(Die to Die)互联的封装结构，ASIC芯片不需要采用该主流晶圆厂商定制工艺，而是仅仅采用如图4所示的传统CMOS工艺倒装工艺，即可以通过摩尔定律不断演进提升集成度和性能，既可以满足光电接收传感器芯片与驱动芯片的信号互联通信，同时也可以将需要外引出的IO更容易和更可靠的引出与外面硬件电路互联通信，从而降低封装工艺难度和提升可靠性。
通过对面阵光电接收传感器芯片与传统CMOS的ASIC驱动芯片的小型化和集成化，可以实现固态激光雷达。其中，面阵光电接收传感器芯片与传统CMOS的ASIC驱动芯片的芯片到芯片互联方案是关键，存在需要晶圆厂商特殊定制工艺和采用如图2所示的cowos并排互联方案封装尺寸过大、成本高的问题。
光电接收传感器芯片通常是4至6寸的晶圆，而ASIC芯片采用CMOS工艺通常是8寸至12寸晶圆，晶圆尺寸不一样，无法实现晶圆至晶圆的焊接，如CIS(CMOS Image Sensor，图像传感器)主流的硅通孔焊接或者复合焊接(hybrid bond)。本公开实施例的技术方案可以很好地解决的不同尺寸晶圆之间芯片到芯片的互联。
如图5所示，在一种实施例中，承载壳体可以为管壳腔体504，管壳腔体504为具有开口的半封闭结构，管壳腔体的内表面上设置有键合指507；转接基板503的第一表面通过预置焊料块514与驱动芯片501的另一部分倒装凸块电连接，转接基板503的第二表面 设置有第一焊盘508；第一焊盘508与键合指507通过导线509电连接。
这里，导线509可以为金线。
如图7所示，倒装芯片的倒装凸块包括铜凸块801和焊锡层802，铜凸块801的下方具有应力缓冲层803。应力缓冲层803可以由PI(Polyimide，聚酰亚胺)材料形成，可以减缓芯片受到的应力。
如图1所示的芯片到芯片连接结构中，采用bump to pad(凸块到焊盘)的芯片焊接工艺，只有上芯片有bump(凸块)单侧有PI应力缓冲层。
本公开实施例的半导体封装结构中，如图5所示，在芯片到芯片的互联中，采用bump to bump(凸块到凸块)的芯片焊接工艺。由于上芯片和下芯片均包含倒装凸块，倒装凸块下均有一层PI层做为应力缓冲层，相当上芯片和下芯片均有应力缓冲层，同时两侧均有凸块的高度，上凸块和下凸块叠加，芯片间的间距增加，也有利减缓上芯片和下芯片受到的应力，有效避免由于应力原因导致的bump crack(凸块开裂)和E-lowK开裂，从而提升了芯片到芯片互联的可靠性。
如图5所示，转接基板的第一表面为转接基板的下表面。
转接基板第一表面的焊盘及镀层处理工艺包含预置预置焊料块、OSP(Organic Solderability Preservatives，有机保焊膜)和焊盘电镀金属层。
预置焊料块514包括以下任一种焊料层：SnAg1.8(锡银，其中银的含量为1.8％)合金层，SnAg3.5(锡金，其中金的含量为3.5％)合金层，AuSn(铜锡)合金层，INP(磷化铟)合金层，PbSnAg(铅锡银)合金层和SnAgCu(锡银铜)合金层。
预置焊料块514上可以预置锡层、金层、镍/金层或镍/铂/金层，且并不局限于此。这里，镍/金层为包含镍层和金层的双层结构，镍/铂/金层为包含镍层、铂层和金层的三层结构。
预置焊料块514设置在转接基板的第一表面，预置焊料块可以经过压平工艺处理，也可以不经压平工艺处理，用于与ASIC芯片上的倒装凸块通过倒装焊接进行互联。
预置焊料块通过via(过孔)和走线与第一焊盘508连接。第一焊盘508可以电镀银层、金层、镍/金层、镍/铂/金层和镍/铂/银/金层等任一种金属层，且并不局限于此。这里，镍/铂/银/金层为包含镍层、铂层、银层和金层的四层结构。
电镀金属层后，可以通过超声波焊接技术焊接金线或铜线将电源地和信号IO引出。
第一焊盘508的排列形式可以为单排、双排，也可以根据需要引出的信号数量设计为多排。
键合指507和预置焊料块514可以为单排、双排，也可以根据需要引出的信号数量设计为多排。
为了便于印制，相邻的预置焊料块间514的最小间距大于或等于150微米。
驱动芯片通过第一环氧树脂511或焊料设置于管壳腔体的内表面的底部；其中，第一环氧树脂包括导电银浆或不导电银浆。
承载壳体还包括玻璃512，玻璃通过第二环氧树脂513与管壳腔体504在管壳腔体的开口处连接，形成密封空间。
驱动芯片、光电接收传感器芯片和转接基板503之间的连接方式可以为单个基板或者单个芯片到晶圆焊接；或者，单个基板或者单个芯片到单个芯片焊接。
如图9所示，转接基板901呈“口”字形，“口”字形的四个内角包括直角、45°倒角或者R角。转接基板内”口”字可以采用模具冲制或者激光切割等加工方法形成。四个内角可以采用直角，也可以采用45°倒角或者R角处理，以有利于减缓四角处凸块受到应力。
转接基板514可以为FR4材料基板、rogers(罗杰斯，一种板材)材料基板、BT材料基板或陶瓷材料基板，且并不局限于此。其中，BT可以为LOW CTE core(low thermal expansion core，低膨胀系数核心)BT材料，CTE可以为3ppm至8ppm的BT材料。这里，ppm为不良率单位，1ppm为百万分之一。
如图10所示，预置焊料块514通过via(过孔)902和走线与第一焊盘508连接。
转接基板514的层数可以为2层、3层、4层或6层，且并不局限于此。
光电接收传感器芯片可以为APD(Avalanche Photo Diode，雪崩光电二极管)，SAPD(single photon Avalanche Diode，单光子雪崩光电二极管)，PD(photodiode，光电二极管)，SPD(single photon detector，单光子探测器)或者CIS(CMOS Image sensor，CMOS图像传感器)，但并不局限于此。
如图11所示的本公开中的半导体封装结构的封装流程中，可以通过芯片焊接设备的bond head(焊接头)吸取光电接收传感器和转接基板，并沾flux(助焊剂)后放置到ASIC芯片的倒装凸块上，光电接收传感器的倒装凸块和转接基板的预置焊料块分别与ASIC芯片的倒装凸块一一对应，通过助焊剂本身的粘性固定住转接基板和光电接收传感器芯片，三者再通过回流焊炉进行Reflow(回流焊接)。
焊接完成后，通过清洗工序将倒装凸块间的助焊剂残留和光电接收传感芯片的光接收面即pixel(像素)面的助焊剂残留和外来物清洗干净，以避免影响收光效率。
驱动芯片501和光电接收传感器芯片502之间设置有填充材料层510。填充材料层的填充材料可以为underfill(底部填充剂)。
在形成填充材料层时，需清洗干净后通过点underfill设备在ASIC芯片的预留点胶边上点上凝胶态的底部填充剂，底部填充剂在毛细作用下填充到倒装凸块之间的空隙，再通过烤箱烘烤固化底部填充剂，固化后的底部填充剂可以对倒装凸块起到保护和增加可靠性的作用，同时对转接基板起到支撑的作用，避免后续超声波焊接线焊接时造成凸块裂纹等问题。
之后，通过芯片焊接设备将底部填充剂固化后的三者结合体吸取，并放置到管壳腔体内，通过第一环氧树脂或焊料与管壳腔体进行焊接。第一环氧树脂烘烤固化或者焊料焊接后，通过超声波键合线焊接将转接基板上表面的包括电源地和信号IO的第一焊盘与管壳 腔体基板上的finger(键合指)进行互联和引出，最后将玻璃通过第二环氧树脂或者焊料与管壳腔体封合，形成密闭空腔封装。
密闭空腔利于提升光电接收传感器芯片收光效率和防尘，如果填充透明树脂透光率仅有90％左右。
助焊剂污染和清洁直接影响光电接收传感器芯片的收光效率，上述封装工艺流程仅为典型封装流程，其中关键的转接基板和光电接收传感芯片与ASIC芯片的焊接，可以不采用助焊剂和回流焊接的制程，也可采用TC bond(thermo-compression，热压焊)或者其他焊接方式，例如在焊接过程中增加氢气，氢气和氮气的混合气等还原性气体，这样可以避免助焊剂残留和挥发污染光电接收芯片的光接收区，从而影响收光效率和响应，同时也减少清洗制程，从而简化封装工艺流程和降低封装成本。
如图5所示的半导体封装结构的工艺流程的玻璃封盖形成密闭空腔仅为本公开实施例的一种封装工艺，除此之外，也可以采用透明塑封料注塑或者点胶等方式将光电接收传感器芯片、转接基板、驱动芯片、导线和第一基板等进行塑封成型和保护。
如图12所示，承载壳体可以包括第一基板1201和透明塑封材料1202，透明塑封材料通过注塑或者点胶方式将光电接收传感器芯片、转接基板、驱动芯片和第一基板塑封为一体。
本公开的技术方案中，通过将第一芯片的一部分倒装凸块和第二芯片的倒装凸块连接，并将第一芯片的另一部分倒装凸块通过转接基板连接到承载壳体，可以有效减小封装结构的体积和工艺难度，简单方便地实现几千或几万线等多线数的面阵光电接收传感器。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围由所附的权利要求指出。

Claims (16)

  1. 一种半导体封装结构，其特征在于，包括：
    承载壳体；
    第一芯片，设置于所述承载壳体的第一表面，其中，所述第一芯片为倒装芯片，包括倒装凸块；
    第二芯片，所述第二芯片为倒装芯片，包括倒装凸块；和
    转接基板；
    其中，所述第一芯片的一部分倒装凸块与所述第二芯片的倒装凸块电连接，所述第一芯片的另一部分倒装凸块通过所述转接基板与所述承载壳体电连接。
  2. 根据权利要求1所述的半导体封装结构，其特征在于，所述第一芯片为驱动芯片，所述第二芯片为光电接收传感器芯片。
  3. 根据权利要求2所述的半导体封装结构，其特征在于，所述承载壳体包括：
    管壳腔体，所述管壳腔体为具有开口的半封闭结构，所述管壳腔体的内表面上设置有键合指；
    所述转接基板的第一表面通过预置焊料块与所述驱动芯片的所述另一部分倒装凸块电连接，所述转接基板的第二表面设置有第一焊盘；
    所述第一焊盘与所述键合指通过导线电连接。
  4. 根据权利要求3所述的半导体封装结构，其特征在于，所述键合指的排列形式为单排、双排或者多排；和/或，
    所述第一焊盘的排列形式为单排、双排或者多排；和/或，
    所述预置焊料块的排列形式为单排、双排或者多排。
  5. 根据权利要求3所述的半导体封装结构，其特征在于，所述驱动芯片和所述光电接收传感器芯片之间设置有填充材料层。
  6. 根据权利要求3所述的半导体封装结构，其特征在于，所述驱动芯片通过第一环氧树脂或焊料设置于所述管壳腔体的内表面的底部；其中，所述第一环氧树脂包括导电银浆或不导电银浆。
  7. 根据权利要求3所述的半导体封装结构，其特征在于，所述驱动芯片、所述光电接收传感器芯片和所述转接基板之间的连接方式包括：单个基板或者单个芯片到晶圆焊接；或者，单个基板或者单个芯片到单个芯片焊接。
  8. 根据权利要求3所述的半导体封装结构，其特征在于，所述承载壳体还包括玻璃，所述玻璃通过第二环氧树脂与所述管壳腔体在所述管壳腔体的开口处连接，形成密封空间。
  9. 根据权利要求3所述的半导体封装结构，其特征在于，相邻的所述预置焊料块间的最小间距大于或等于150微米。
  10. 根据权利要求3所述的半导体封装结构，其特征在于，所述预置焊料块包括 以下任一种焊料层：SnAg1.8合金层，SnAg3.5合金层，AuSn合金层，INP合金层，PbSnAg合金层和SnAgCu合金层。
  11. 根据权利要求2所述的半导体封装结构，其特征在于，所述转接基板呈“口”字形，所述“口”字形的四个内角包括直角、45°倒角或者R角。
  12. 根据权利要求2所述的半导体封装结构，其特征在于，转接基板为下列基板其中之一：FR4材料基板、rogers材料基板、BT材料基板和陶瓷材料基板。
  13. 根据权利要求2所述的半导体封装结构，其特征在于，所述转接基板的层数为下列层数其中之一：2层、3层、4层和6层。
  14. 根据权利要求3所述的半导体封装结构，其特征在于，所述第一焊盘上预置有以下任一种金属层：银层、金层、镍/金层、镍/铂/金层和镍/铂/银/金层；和/或，所述预置焊料块上预置有以下任一种金属层：锡层、金层、镍/金层和镍/铂/金层。
  15. 根据权利要求2所述的半导体封装结构，其特征在于，所述光电接收传感器芯片为下列芯片其中之一：雪崩光电二极管、单光子雪崩光电二极管、光电二极管、单光子探测器和CMOS图像传感器。
  16. 根据权利要求2所述的半导体封装结构，其特征在于，所述承载壳体包括第一基板和透明塑封材料，所述透明塑封材料通过注塑或者点胶方式将光电接收传感器芯片、所述转接基板、所述驱动芯片和所述第一基板塑封为一体。
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