WO2021248543A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2021248543A1
WO2021248543A1 PCT/CN2020/096973 CN2020096973W WO2021248543A1 WO 2021248543 A1 WO2021248543 A1 WO 2021248543A1 CN 2020096973 W CN2020096973 W CN 2020096973W WO 2021248543 A1 WO2021248543 A1 WO 2021248543A1
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WIPO (PCT)
Prior art keywords
signal
transistor
electrically connected
level
node
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Application number
PCT/CN2020/096973
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English (en)
French (fr)
Inventor
肖军城
田超
管延庆
周永祥
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to EP20855851.0A priority Critical patent/EP4163908A4/en
Priority to US16/965,360 priority patent/US10977979B1/en
Publication of WO2021248543A1 publication Critical patent/WO2021248543A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • the production process reduces the cost of the product in two aspects.
  • the existing GOA circuit structure is relatively complicated, which is not conducive to layout design, and it is difficult to realize a narrow frame.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problems that the existing GOA circuit has a complicated structure, is not conducive to layout design, and is difficult to achieve a narrow frame.
  • the embodiment of the present application provides a GOA circuit, which includes an N-level GOA unit.
  • the n-th level GOA unit includes a forward scan control module, a reverse scan control module, a pull-up module, a pull-down module, and a functional module, where 2 ⁇ n ⁇ N-1, n and N are all positive integers;
  • the forward scan control module is connected to the forward signal, the n+1th level clock signal and the n-2th level scan signal, and is electrically connected to the first node and the second node, and the forward scan control module is used for Pulling up the potential of the first node and controlling the potential of the second node according to the forward signal, the n+1th stage clock signal, and the n-2th stage scan signal;
  • the reverse scan control module receives a reverse signal, an n-1th level clock signal, and an n+2th level scan signal, and is electrically connected to the first node and the second node, and the reverse The scan control module is configured to raise the potential of the first node and control the potential of the second node according to the reverse signal, the n-1th level clock signal, and the n+2th level scan signal ;
  • the pull-up module is connected to a constant-voltage low-level signal, a constant-voltage high-level signal, and an nth-level clock signal, and is electrically connected to the first node and a scan signal output terminal, and the pull-up module is used for Controlling the potential of the scan signal output terminal according to the constant voltage low level signal, the constant voltage high level signal, the nth stage clock signal, and the potential of the first node;
  • the pull-down module is connected to the constant voltage high-level signal and the constant voltage low-level signal, and is electrically connected to the first node, the second node, and the scan signal output terminal.
  • the pull-down module is configured to pull down the potential of the first node and the potential of the scan signal output terminal according to the constant voltage high-level signal, the constant voltage low-level signal, and the potential of the second node;
  • the function module is connected to a first function control signal, a second function control signal, a third function control signal, and a fourth function control signal, and is electrically connected to the pull-down module and the scanning signal output terminal.
  • the function The module is used to control the potential of the first node and the scanning signal output according to the first function control signal, the second function control signal, the third function control signal, and the fourth function control signal Potential at the end.
  • the forward scan control module includes a first transistor and a third transistor
  • the gate of the first transistor is electrically connected to the n-2th level scan signal, and the source of the first transistor is electrically connected to the forward scan signal and the gate of the third transistor,
  • the drain of the first transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the n+1th stage clock signal, and the drain of the third transistor is electrically connected Connected to the second node.
  • the reverse scan control module includes a second transistor and a fourth transistor
  • the gate of the second transistor is electrically connected to the n+2th level scan signal, and the source of the second transistor is electrically connected to the reverse scan signal and the gate of the fourth transistor,
  • the drain of the second transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the n-1 level clock signal, and the drain of the fourth transistor is electrically connected Connected to the second node.
  • the pull-up module includes a seventh transistor, a ninth transistor, and a first capacitor;
  • the gate of the seventh transistor is electrically connected to the constant voltage high-level signal, the source of the seventh transistor is electrically connected to the first node, and the drain of the seventh transistor is electrically connected At the gate of the ninth transistor, the gate of the ninth transistor is electrically connected to the nth stage clock signal, and the gate of the ninth transistor is electrically connected to the scan signal output terminal, so One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the constant voltage low level signal.
  • the pull-down module includes a fifth transistor, a sixth transistor, an eighth transistor, a tenth transistor, and a second capacitor;
  • the gate of the fifth transistor, the drain of the sixth transistor, the drain of the eighth transistor, the gate of the tenth transistor, and one end of the second capacitor are all electrically connected to the third Node; the source of the fifth transistor, the source of the sixth transistor, the source of the tenth transistor, and the other end of the second capacitor are all electrically connected to the constant voltage low level signal
  • the drain of the fifth transistor and the gate of the sixth transistor are electrically connected to the first node; the gate of the eighth transistor is electrically connected to the second node, the first The source of the eight transistor is electrically connected to the constant voltage high-level signal, and the drain of the tenth transistor is electrically connected to the scan signal output terminal.
  • the functional module includes an eleventh transistor and a twelfth transistor
  • the gate of the eleventh transistor is electrically connected to the first function control signal, the source of the eleventh transistor is electrically connected to the third function control signal, and the drain of the eleventh transistor is Electrically connected to the third node;
  • the gate of the twelfth transistor is electrically connected to the second function control signal, the source of the twelfth transistor is electrically connected to the fourth function control signal, and the drain of the twelfth transistor is The pole is electrically connected to the scanning signal output terminal.
  • the GOA circuit has a reset mode, an abnormal power-off mode, and a full shutdown mode;
  • the first function control signal, the second function control signal, and the fourth function control signal are all at a high level, and the third function control signal is at a low level ;
  • the second function control signal is at a high level
  • the fourth function control signal is at a low level
  • the GOA circuit accesses a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal;
  • the 4k+1 level clock signal is the same signal as the first clock signal
  • the 4k+2 level clock signal is the same signal as the second clock signal
  • the 4k+3 level clock signal is the same as the third clock signal It is the same signal
  • the 4k+4th level clock signal and the fourth clock signal are the same signal, where k is greater than or equal to 0, and k is an integer.
  • the GOA circuit accesses a first start signal and a second start signal
  • the first level GOA unit is connected to the first start signal
  • the second level GOA unit is connected to the second start signal
  • the Nth level GOA unit accesses the first start signal
  • the N-1 level GOA unit accesses the second start signal
  • An embodiment of the present application also provides a display panel, which includes a GOA circuit, the GOA circuit includes an N-level GOA unit, and the nth-level GOA unit includes a forward scan control module, a reverse scan control module, a pull-up module, and a pull-down module And functional modules, where 2 ⁇ n ⁇ N-1, n and N are both positive integers;
  • the forward scan control module is connected to the forward signal, the n+1th level clock signal and the n-2th level scan signal, and is electrically connected to the first node and the second node, and the forward scan control module is used for Pulling up the potential of the first node and controlling the potential of the second node according to the forward signal, the n+1th stage clock signal, and the n-2th stage scan signal;
  • the reverse scan control module receives a reverse signal, an n-1th level clock signal, and an n+2th level scan signal, and is electrically connected to the first node and the second node, and the reverse The scan control module is configured to raise the potential of the first node and control the potential of the second node according to the reverse signal, the n-1th level clock signal, and the n+2th level scan signal ;
  • the pull-up module is connected to a constant-voltage low-level signal, a constant-voltage high-level signal, and an nth-level clock signal, and is electrically connected to the first node and a scan signal output terminal, and the pull-up module is used for Controlling the potential of the scan signal output terminal according to the constant voltage low level signal, the constant voltage high level signal, the nth stage clock signal, and the potential of the first node;
  • the pull-down module is connected to the constant voltage high-level signal and the constant voltage low-level signal, and is electrically connected to the first node, the second node, and the scan signal output terminal.
  • the pull-down module is configured to pull down the potential of the first node and the potential of the scan signal output terminal according to the constant voltage high-level signal, the constant voltage low-level signal, and the potential of the second node;
  • the function module is connected to a first function control signal, a second function control signal, a third function control signal, and a fourth function control signal, and is electrically connected to the pull-down module and the scanning signal output terminal.
  • the function The module is used to control the potential of the first node and the scanning signal output according to the first function control signal, the second function control signal, the third function control signal, and the fourth function control signal Potential at the end.
  • the forward scan control module includes a first transistor and a third transistor
  • the gate of the first transistor is electrically connected to the n-2th level scan signal, and the source of the first transistor is electrically connected to the forward scan signal and the gate of the third transistor,
  • the drain of the first transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the n+1th stage clock signal, and the drain of the third transistor is electrically connected Connected to the second node.
  • the reverse scan control module includes a second transistor and a fourth transistor
  • the gate of the second transistor is electrically connected to the n+2th level scan signal, and the source of the second transistor is electrically connected to the reverse scan signal and the gate of the fourth transistor,
  • the drain of the second transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the n-1 level clock signal, and the drain of the fourth transistor is electrically connected Connected to the second node.
  • the pull-up module includes a seventh transistor, a ninth transistor, and a first capacitor;
  • the gate of the seventh transistor is electrically connected to the constant voltage high-level signal, the source of the seventh transistor is electrically connected to the first node, and the drain of the seventh transistor is electrically connected At the gate of the ninth transistor, the gate of the ninth transistor is electrically connected to the nth stage clock signal, and the gate of the ninth transistor is electrically connected to the scan signal output terminal, so One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the constant voltage low level signal.
  • the pull-down module includes a fifth transistor, a sixth transistor, an eighth transistor, a tenth transistor, and a second capacitor;
  • the gate of the fifth transistor, the drain of the sixth transistor, the drain of the eighth transistor, the gate of the tenth transistor, and one end of the second capacitor are all electrically connected to the third Node; the source of the fifth transistor, the source of the sixth transistor, the source of the tenth transistor, and the other end of the second capacitor are all electrically connected to the constant voltage low level signal
  • the drain of the fifth transistor and the gate of the sixth transistor are electrically connected to the first node; the gate of the eighth transistor is electrically connected to the second node, the first The source of the eight transistor is electrically connected to the constant voltage high-level signal, and the drain of the tenth transistor is electrically connected to the scan signal output terminal.
  • the functional module includes an eleventh transistor and a twelfth transistor
  • the gate of the eleventh transistor is electrically connected to the first function control signal, the source of the eleventh transistor is electrically connected to the third function control signal, and the drain of the eleventh transistor is Electrically connected to the third node;
  • the gate of the twelfth transistor is electrically connected to the second function control signal, the source of the twelfth transistor is electrically connected to the fourth function control signal, and the drain of the twelfth transistor is The pole is electrically connected to the scanning signal output terminal.
  • the GOA circuit has a reset mode, an abnormal power-off mode, and a full-off mode
  • the first function control signal, the second function control signal, and the fourth function control signal are all at a high level, and the third function control signal is at a low level ;
  • the second function control signal is at a high level
  • the fourth function control signal is at a low level
  • the GOA circuit accesses a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal;
  • the 4k+1 level clock signal is the same signal as the first clock signal
  • the 4k+2 level clock signal is the same signal as the second clock signal
  • the 4k+3 level clock signal is the same as the third clock signal It is the same signal
  • the 4k+4th level clock signal and the fourth clock signal are the same signal, where k is greater than or equal to 0, and k is an integer.
  • the GOA circuit is connected to a first start signal and a second start signal
  • the first level GOA unit is connected to the first start signal
  • the second level GOA unit is connected to the second start signal
  • the Nth level GOA unit accesses the first start signal
  • the N-1 level GOA unit accesses the second start signal
  • the GOA circuit and the display panel provided by the embodiments of the present application can achieve a narrow frame by simplifying the circuit structure and reduce the risk of manufacturing process and stability.
  • FIG. 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of the first circuit of the GOA unit in the GOA circuit provided by the embodiment of the application;
  • FIG. 3 is a schematic diagram of a second circuit of the GOA unit in the GOA circuit provided by the embodiment of the application;
  • FIG. 4 is a schematic diagram of a third circuit of the GOA unit in the GOA circuit provided by the embodiment of the application;
  • FIG. 5 is a schematic diagram of a fourth circuit of the GOA unit in the GOA circuit provided by the embodiment of this application;
  • FIG. 6 is a schematic diagram of a fifth circuit of the GOA unit in the GOA circuit provided by the embodiment of this application;
  • FIG. 7 is a signal timing diagram of the GOA unit shown in FIG. 2.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application are all N-type transistors or P-type transistors, where N-type transistors are turned on when the gate is high and turned off when the gate is low; P-type transistors are low when the gate is low. Turn on when the level is high, and turn off when the gate is high.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel 100 provided by the embodiment of the present application includes a display area 20 and a GOA circuit area 10 arranged outside the display area 20.
  • the display area 20 is provided with a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel units defined by the intersection of the plurality of scan lines and the plurality of data lines.
  • the GOA circuit area 10 is provided with a GOA circuit, the GOA circuit includes N-level GOA units, and the GOA units are connected to the scan lines in a one-to-one correspondence, that is, the number of GOA units is equal to the number of scan lines.
  • the GOA circuit includes multiple cascaded odd-numbered GOA units and multiple cascaded even-numbered GOA units.
  • the plurality of cascaded odd-numbered GOA units are arranged on one side of the display area 20, and the plurality of cascaded even-numbered GOA units are arranged on the other side of the display area 20.
  • N when N is an even number, the first level GOA unit, the third level GOA unit, the fifth level GOA unit,..., the N-1 level GOA unit are set in cascade, the second level GOA unit, the fourth level GOA Unit, level 6 GOA unit,..., N level GOA unit cascade setting. It should be noted that, in the embodiments of the present application, N may be an even number or an odd number, which is not limited here.
  • the GOA circuit accesses the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, the fourth clock signal ck4, the first start signal STV1, and the second start signal STV2.
  • the multiple cascaded odd-numbered GOA units are connected to the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, the fourth clock signal ck4, and the first start signal STV1.
  • the multiple cascaded even-numbered GOA units are connected to the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, the fourth clock signal ck4, and the second start signal STV2.
  • FIG. 2 is a schematic diagram of the first circuit of the GOA unit in the GOA circuit provided by the embodiment of the application.
  • the n-th GOA unit 100 includes a forward scan control module 101, a reverse scan control module 102, a pull-up module 103, a pull-down module 104, and Function module 105, 2 ⁇ n ⁇ N-1, n and N are both positive integers.
  • the forward scanning control module 101 accesses the forward signal U2D, the n+1th stage clock signal CK(n+1), and the n-2th stage scan signal G(n-2), and is electrically connected to the first Node Q and the second node M.
  • the forward scanning control module 101 is configured to raise the potential of the first node Q according to the forward signal U2D, the n+1th stage clock signal CK(n+1), and the n-2th stage scan signal G(n-2) And control the potential of the second node M.
  • the reverse scan control module 102 accesses the reverse signal D2U, the n-1th level clock signal CK(n-1), and the n+2th level scan signal G(n+2), and is electrically connected to the first Node Q and the second node M.
  • the reverse scan control module 102 is used to raise the potential of the first node Q according to the reverse signal D2U, the n-1th stage clock signal CK(n-1), and the n+2th stage scan signal G(n+2) And control the potential of the second node M.
  • the pull-up module 103 is connected to the constant voltage low level signal VGL, the constant voltage high level signal VGH, and the n-th stage clock signal CK(n), and is electrically connected to the first node Q and the scan signal output terminal G.
  • the pull-up module 103 is used for controlling the electric potential of the scanning signal output terminal G according to the constant voltage low level signal VGL, the constant voltage high level signal VGH, the nth stage clock signal CK(n) and the electric potential of the first node Q.
  • the pull-down module 104 is connected to the constant voltage high level signal VGH and the constant voltage low level signal VGL, and is electrically connected to the first node Q, the second node M, and the scan signal output terminal G.
  • the pull-down module 104 is configured to pull down the potential of the first node Q and the potential of the scan signal output terminal G according to the constant voltage high-level signal VGH, the constant voltage low-level signal VGL, and the potential of the second node.
  • the function module 105 is connected to the first function control signal GAS1, the second function control signal GAS2, the third function control signal GAS3, and the fourth function control signal GAS4, and is electrically connected to the pull-down module 104 and the scan signal output terminal G.
  • the function module 105 is configured to control the potential of the first node Q and the potential of the scan signal output terminal G according to the first function control signal GAS1, the second function control signal GAS2, the third function control signal GAS3, and the fourth function control signal GAS4.
  • the 4k+1th level clock signal CK(4k+1) and the first clock signal ck1 are the same signal
  • the 4k+2 level clock signal CK(4k+2) and the second clock signal ck2 are the same signal
  • the 4k+3 level clock signal CK(4k+3) and the third clock signal ck3 are the same signal
  • the 4k+4 level clock signal CK(4k+4) and the fourth clock signal ck4 are the same signal, where k It is greater than or equal to 0, and k is an integer.
  • the first-level clock signal CK(1), the fifth-level clock signal CK(5), the ninth-level clock signal CK(9),... the 4k+1th-level clock signal CK(4k+1) and the first The clock signal ck1 is the same signal.
  • Level 2 clock signal CK(2), Level 6 clock signal CK(6), Level 10 clock signal CK(10),... 4k+2 level clock signal CK(4k+2) and second clock signal Both ck2 are the same signal.
  • Level 3 clock signal CK(3), Level 7 clock signal CK(7), Level 11 clock signal CK(11),... 4k+3 level clock signal CK(4k+3) and third clock signal Both are the same signal.
  • the 4th level clock signal CK(4), the 8th level clock signal CK(8), the 12th level clock signal CK(12),... the 4k+4th level clock signal CK(4k+4) and the fourth clock signal ck4 are all the same signal.
  • the forward scan control module 101 includes a first transistor NT1 and a third transistor NT3; the gate of the first transistor NT1 is electrically connected to the n-2th stage scan signal G(n-2), The source of a transistor NT1 is electrically connected to the forward scan signal U2D and the gate of the third transistor NT3, the drain of the first transistor NT1 is electrically connected to the first node Q, and the source of the third transistor NT3 is electrically connected At the n+1th stage clock signal CK(n+1), the drain of the third transistor NT3 is electrically connected to the second node M.
  • the reverse scan control module 102 includes a second transistor NT2 and a fourth transistor NT4; the gate of the second transistor NT2 is electrically connected to the n+2 level scan signal G(n+2), and the second transistor NT2
  • the source of the transistor NT2 is electrically connected to the reverse scan signal D2U and the gate of the fourth transistor NT4
  • the drain of the second transistor NT2 is electrically connected to the first node Q
  • the source of the fourth transistor NT4 is electrically connected to With the n-1th stage clock signal CK(n-1), the drain of the fourth transistor NT4 is electrically connected to the second node M.
  • the pull-up module 103 includes a seventh transistor NT7, a ninth transistor NT9, and a first capacitor C1; the gate of the seventh transistor NT7 is electrically connected to the constant voltage high-level signal VGH, and the The source is electrically connected to the first node Q, the drain of the seventh transistor NT7 is electrically connected to the gate of the ninth transistor NT9, and the gate of the ninth transistor NT9 is electrically connected to the nth stage clock signal CK(n) , The gate of the ninth transistor NT9 is electrically connected to the scan signal output terminal G, one end of the first capacitor C1 is electrically connected to the first node Q, and the other end of the first capacitor C1 is electrically connected to the constant voltage low level signal VGL.
  • the pull-down module 104 includes a fifth transistor NT5, a sixth transistor NT6, an eighth transistor NT8, a tenth transistor NT10, and a second capacitor C2; the gate of the fifth transistor NT5 and the drain of the sixth transistor NT6 , The drain of the eighth transistor NT8, the gate of the tenth transistor NT10, and one end of the second capacitor C2 are electrically connected to the third node N; the source of the fifth transistor NT5, the source of the sixth transistor NT6, and the The source of the ten transistor NT10 and the other end of the second capacitor C2 are electrically connected to the constant voltage low level signal VGL; the drain of the fifth transistor NT5 and the gate of the sixth transistor NT6 are both electrically connected to the first node Q; The gate of the eighth transistor NT8 is electrically connected to the second node M, the source of the eighth transistor NT8 is electrically connected to the constant voltage high-level signal VGH, and the drain of the tenth transistor NT10 is
  • the functional module 105 includes an eleventh transistor NT11 and a twelfth transistor NT12; the gate of the eleventh transistor NT11 is electrically connected to the first function control signal GAS1, and the source of the eleventh transistor NT11 is electrically connected to the first function control signal GAS1. Is electrically connected to the third function control signal GAS3, the drain of the eleventh transistor NT11 is electrically connected to the third node N; the gate of the twelfth transistor NT12 is electrically connected to the second function control signal GAS2, the twelfth transistor The source of NT12 is electrically connected to the fourth function control signal GAS4, and the drain of the twelfth transistor NT12 is electrically connected to the scanning signal output terminal G.
  • the GOA circuit provided by the embodiment of the present application may be in a forward scan mode or a reverse scan mode.
  • the GOA circuit When the GOA circuit is in the forward scan mode, among the multiple cascaded odd-numbered GOA units, the GOA circuit starts sequentially from the first-level GOA unit to the N-1th-level GOA unit; in the multiple cascaded even-numbered GOA units In the level GOA unit, the GOA circuit starts from the second level GOA unit to the N level GOA unit in sequence.
  • the GOA circuit When the GOA circuit is in the reverse scan mode, among the multiple cascaded odd-numbered GOA units, the GOA circuit starts sequentially from the N-1 level GOA unit to the first level GOA unit; in the multiple cascaded even-numbered GOA units In the level GOA unit, the GOA circuit is activated sequentially from the Nth level GOA unit to the 2nd level GOA unit.
  • the first level GOA unit when the GOA circuit is in the forward scan mode, the first level GOA unit is connected to the first start signal STV1, and the second level GOA unit is connected to the second start signal SYV2.
  • the circuit diagrams of the N-1 level GOA unit and the N level GOA unit can be referred to as shown in FIG. 2, and will not be repeated here.
  • FIG. 3 is a schematic diagram of a second circuit of the GOA unit in the GOA circuit provided by the embodiment of the application.
  • the difference between the first-level GOA unit and the nth-level GOA unit is that the gate of the first transistor NT1 in the first-level GOA unit is electrically connected to the first one.
  • the source of the fourth transistor NT4 is connected to the open source.
  • FIG. 4 is a schematic diagram of a third circuit of the GOA unit in the GOA circuit provided by the embodiment of the application.
  • the difference between the second-level GOA unit and the n-th level GOA unit is that the gate of the first transistor NT1 in the second-level GOA unit is electrically connected to the second For the start signal STV2, the source of the fourth transistor NT4 is connected to the open source.
  • the Nth level GOA unit accesses the first start signal STV1
  • the N-1 level GOA unit accesses the second start signal STV2.
  • the circuit diagrams of the second-level GOA unit and the first-level GOA unit can be referred to as shown in FIG. 2 and will not be repeated here.
  • FIG. 5 is a schematic diagram of a fourth circuit of the GOA unit in the GOA circuit provided by the embodiment of the application.
  • the difference between the Nth-stage GOA unit and the nth-stage GOA unit is that the gate of the second transistor NT2 in the Nth-stage GOA unit is electrically connected to the first one.
  • the source of the third transistor NT3 is connected to the open source.
  • FIG. 6 is a schematic diagram of a fifth circuit of the GOA unit in the GOA circuit provided by the embodiment of the application.
  • the difference between the N-1 level GOA unit and the n level GOA unit is: the gate electrical property of the second transistor NT2 in the N-1 level GOA unit Connected to the second start signal STV2, the source of the third transistor NT3 is connected to the open source.
  • FIG. 7 is a signal timing diagram of the GOA unit shown in FIG. 2.
  • the third transistor NT3, the eighth transistor NT8, the fifth transistor NT5, and the tenth transistor NT10 are all turned on, and the constant voltage low level signal VGL It is output to the first node Q through the fifth transistor NT5, and the constant voltage low level signal VGL is output to the scan signal output terminal G through the tenth transistor NT10, that is, the potential of the first node Q and the potential of the scan signal G(n) are both Was pulled down.
  • the n+2 level scan signal G(n+2) is at a high level
  • the second transistor NT2 is turned on, and the reverse signal D2U is output to the first node Q to maintain the first node Q at a low level.
  • the GOA circuit has a reset mode, an abnormal power-off mode, and a full shutdown mode.
  • the first function control signal GAS1 and the third function control signal GAS3 are high.
  • the first function control signal GAS1, the second function control signal GAS2, and the fourth function control signal GAS4 are all high, and the third function control signal GAS3 is low.
  • the second function control signal GAS2 is at a high level
  • the fourth function control signal GAS4 is at a low level.
  • the GOA circuit when the GOA circuit is in the reset mode, the first function control signal GAS1 and the third function control signal GAS3 are at high potential, and the eleventh transistor NT11 is turned on. At this time, the potential of the third node N is at a high potential, so that the first The five transistor NT5 is turned on, and the electric potential of the first node Q is pulled down, so that the first node Q is reset.
  • the first function control signal GAS1, the second function control signal GAS2, and the fourth function control signal GAS4 are all high, the third function control signal GAS3 is low, and the eleventh transistor NT11 Turn on, at this time, the potential of the third node N is at the potential; at the same time, the twelfth transistor NT12 is turned on, and the scan signal G(n) output by the scan signal output terminal G is at a high potential, so that when the GOA circuit is abnormally powered off, The GOA circuit can still continue to work.
  • the second function control signal GAS2 is at a high level
  • the fourth function control signal GAS4 is at a low level
  • the twelfth transistor NT12 is turned on
  • the scan signal G(n) output by the scan signal output terminal G It is a low level, so as to realize the GOA circuit full-off mode, that is, the scan signal output by each GOA unit is at a low level.
  • the GOA circuit and the display panel provided by the embodiments of the present application can achieve a narrow frame by simplifying the circuit structure and reduce the risk of manufacturing process and stability.

Abstract

一种GOA电路及显示面板(100)， GOA电路包括N级GOA单元，第n级GOA单元包括正向扫描控制模块(101)、反向扫描控制模块(102)、上拉模块(103)、下拉模块(104)以及功能模块(105)，其中，2＜n＜N-1，n、N均为正整数，通过精简电路架构，从而可以实现窄边框，降低制程和稳定性的风险。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术是将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，从材料成本和制作工艺两方面降低产品成本。现有的GOA电路结构较复杂，不利于版图设计，且难以实现窄边框。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够解决现有的GOA电路结构较复杂，不利于版图设计，且难以实现窄边框的技术问题。
 技术解决方案
本申请实施例提供一种GOA电路，包括N级GOA单元，第n级GOA单元包括正向扫描控制模块、反向扫描控制模块、上拉模块、下拉模块以及功能模块，其中，2<n<N-1，n、N均为正整数；
所述正向扫描控制模块接入正向信号、第n+1级时钟信号以及第n-2级扫描信号，并电性连接于第一节点以及第二节点，所述正向扫描控制模块用于根据所述正向信号、所述第n+1级时钟信号以及所述第n-2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
所述反向扫描控制模块接入反向信号、第n-1级时钟信号以及第n+2级扫描信号，并电性连接于所述第一节点以及所述第二节点，所述反向扫描控制模块用于根据所述反向信号、所述第n-1级时钟信号以及所述第n+2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
所述上拉模块接入恒压低电平信号、恒压高电平信号以及第n级时钟信号，并电性连接于所述第一节点以及扫描信号输出端，所述上拉模块用于根据所述恒压低电平信号、所述恒压高电平信号、所述第n级时钟信号以及所述第一节点的电位，控制所述扫描信号输出端的电位；
所述下拉模块接入所述恒压高电平信号以及所述恒压低电平信号，并电性连接于所述第一节点、所述第二节点以及所述扫描信号输出端，所述下拉模块用于根据所述恒压高电平信号、所述恒压低电平信号以及所述第二节的电位，拉低所述第一节点的电位以及所述扫描信号输出端的电位；
所述功能模块接入第一功能控制信号、第二功能控制信号、第三功能控制信号以及第四功能控制信号，并电性连接于所述下拉模块以及所述扫描信号输出端，所述功能模块用于根据所述第一功能控制信号、所述第二功能控制信号、所述第三功能控制信号以及所述第四功能控制信号，控制所述第一节点的电位以及所述扫描信号输出端的电位。
在本申请所述的GOA电路中，所述正向扫描控制模块包括第一晶体管以及第三晶体管；
所述第一晶体管的栅极电性连接于所述第n-2级扫描信号，所述第一晶体管的源极电性连接于所述正向扫描信号以及所述第三晶体管的栅极，所述第一晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第n+1级时钟信号，所述第三晶体管的漏极电性连接于所述第二节点。
在本申请所述的GOA电路中，所述反向扫描控制模块包括第二晶体管以及第四晶体管；
所述第二晶体管的栅极电性连接于所述第n+2级扫描信号，所述第二晶体管的源极电性连接于所述反向扫描信号以及所述第四晶体管的栅极，所述第二晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第n-1级时钟信号，所述第四晶体管的漏极电性连接于所述第二节点。
在本申请所述的GOA电路中，所述上拉模块包括第七晶体管、第九晶体管以及第一电容；
所述第七晶体管的栅极电性连接于所述恒压高电平信号，所述第七晶体管的源极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述第九晶体管的栅极，所述第九晶体管的栅极电性连接于所述第n级时钟信号，所述第九晶体管的栅极电性连接于所述扫描信号输出端，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的GOA电路中，所述下拉模块包括第五晶体管、第六晶体管、第八晶体管、第十晶体管以及第二电容；
所述第五晶体管的栅极、所述第六晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的栅极以及所述第二电容的一端均电性连接于第三节点；所述第五晶体管的源极、所述第六晶体管的源极、所述第十晶体管的源极以及所述第二电容的另一端均电性连接于所述恒压低电平信号；所述第五晶体管的漏极以及所述第六晶体管的栅极均电性连接于所述第一节点；所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极电性连接于所述恒压高电平信号，所述第十晶体管的漏极电性连接于所述扫描信号输出端。
在本申请所述的GOA电路中，所述功能模块包括第十一晶体管以及第十二晶体管；
所述第十一晶体管的栅极电性连接于所述第一功能控制信号，所述第十一晶体管的源极电性连接于所述第三功能控制信号，所述第十一晶体管的漏极电性连接于所述第三节点；
所述第十二晶体管的栅极电性连接于所述第二功能控制信号，所述第十二晶体管的源极电性连接于所述第四功能控制信号，所述第十二晶体管的漏极电性连接于所述扫描信号输出端。
在本申请所述的GOA电路中，所述GOA电路具有复位模式、异常断电模式以及全关断模式；
当所述GOA电路处于复位模式时，所述第一功能控制信号以及所述第三功能控制信号为高电位；
当所述GOA电路处于异常断电模式时，所述第一功能控制信号、所述第二功能控制信号以及所述第四功能控制信号均为高电位，所述第三功能控制信号为低电位；
当所述GOA电路处于全关断模式时，所述第二功能控制信号为高电位，所述第四功能控制信号为低电位。
在本申请所述的GOA电路中，所述GOA电路接入第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号；
第4k+1级时钟信号与所述第一时钟信号为同一信号，第4k+2级时钟信号与所述第二时钟信号为同一信号，第4k+3级时钟信号与所述第三时钟信号为同一信号，第4k+4级时钟信号与所述第四时钟信号为同一信号，其中，k大于等于0，且k为整数。
在本申请所述的GOA电路中，所述GOA电路接入第一起始信号以及第二起始信号；
当所述GOA电路处于正向扫描模式时，第1级GOA单元接入所述第一起始信号，第2级GOA单元接入所述第二起始信号；
当所述GOA电路处于反向扫描模式时，第N级GOA单元接入所述第一起始信号，第N-1级GOA单元接入所述第二起始信号。
本申请实施例还提供一种显示面板，其包括GOA电路，所述GOA电路包括N级GOA单元，第n级GOA单元包括正向扫描控制模块、反向扫描控制模块、上拉模块、下拉模块以及功能模块，其中，2<n<N-1，n、N均为正整数；
所述正向扫描控制模块接入正向信号、第n+1级时钟信号以及第n-2级扫描信号，并电性连接于第一节点以及第二节点，所述正向扫描控制模块用于根据所述正向信号、所述第n+1级时钟信号以及所述第n-2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
所述反向扫描控制模块接入反向信号、第n-1级时钟信号以及第n+2级扫描信号，并电性连接于所述第一节点以及所述第二节点，所述反向扫描控制模块用于根据所述反向信号、所述第n-1级时钟信号以及所述第n+2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
所述上拉模块接入恒压低电平信号、恒压高电平信号以及第n级时钟信号，并电性连接于所述第一节点以及扫描信号输出端，所述上拉模块用于根据所述恒压低电平信号、所述恒压高电平信号、所述第n级时钟信号以及所述第一节点的电位，控制所述扫描信号输出端的电位；
所述下拉模块接入所述恒压高电平信号以及所述恒压低电平信号，并电性连接于所述第一节点、所述第二节点以及所述扫描信号输出端，所述下拉模块用于根据所述恒压高电平信号、所述恒压低电平信号以及所述第二节的电位，拉低所述第一节点的电位以及所述扫描信号输出端的电位；
所述功能模块接入第一功能控制信号、第二功能控制信号、第三功能控制信号以及第四功能控制信号，并电性连接于所述下拉模块以及所述扫描信号输出端，所述功能模块用于根据所述第一功能控制信号、所述第二功能控制信号、所述第三功能控制信号以及所述第四功能控制信号，控制所述第一节点的电位以及所述扫描信号输出端的电位。
在本申请所述的显示面板中，所述正向扫描控制模块包括第一晶体管以及第三晶体管；
所述第一晶体管的栅极电性连接于所述第n-2级扫描信号，所述第一晶体管的源极电性连接于所述正向扫描信号以及所述第三晶体管的栅极，所述第一晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第n+1级时钟信号，所述第三晶体管的漏极电性连接于所述第二节点。
在本申请所述的显示面板中，所述反向扫描控制模块包括第二晶体管以及第四晶体管；
所述第二晶体管的栅极电性连接于所述第n+2级扫描信号，所述第二晶体管的源极电性连接于所述反向扫描信号以及所述第四晶体管的栅极，所述第二晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第n-1级时钟信号，所述第四晶体管的漏极电性连接于所述第二节点。
在本申请所述的显示面板中，所述上拉模块包括第七晶体管、第九晶体管以及第一电容；
所述第七晶体管的栅极电性连接于所述恒压高电平信号，所述第七晶体管的源极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述第九晶体管的栅极，所述第九晶体管的栅极电性连接于所述第n级时钟信号，所述第九晶体管的栅极电性连接于所述扫描信号输出端，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的显示面板中，所述下拉模块包括第五晶体管、第六晶体管、第八晶体管、第十晶体管以及第二电容；
所述第五晶体管的栅极、所述第六晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的栅极以及所述第二电容的一端均电性连接于第三节点；所述第五晶体管的源极、所述第六晶体管的源极、所述第十晶体管的源极以及所述第二电容的另一端均电性连接于所述恒压低电平信号；所述第五晶体管的漏极以及所述第六晶体管的栅极均电性连接于所述第一节点；所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极电性连接于所述恒压高电平信号，所述第十晶体管的漏极电性连接于所述扫描信号输出端。
在本申请所述的显示面板中，所述功能模块包括第十一晶体管以及第十二晶体管；
所述第十一晶体管的栅极电性连接于所述第一功能控制信号，所述第十一晶体管的源极电性连接于所述第三功能控制信号，所述第十一晶体管的漏极电性连接于所述第三节点；
所述第十二晶体管的栅极电性连接于所述第二功能控制信号，所述第十二晶体管的源极电性连接于所述第四功能控制信号，所述第十二晶体管的漏极电性连接于所述扫描信号输出端。
在本申请所述的显示面板中，所述GOA电路具有复位模式、异常断电模式以及全关断模式；
当所述GOA电路处于复位模式时，所述第一功能控制信号以及所述第三功能控制信号为高电位；
当所述GOA电路处于异常断电模式时，所述第一功能控制信号、所述第二功能控制信号以及所述第四功能控制信号均为高电位，所述第三功能控制信号为低电位；
当所述GOA电路处于全关断模式时，所述第二功能控制信号为高电位，所述第四功能控制信号为低电位。
在本申请所述的显示面板中，所述GOA电路接入第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号；
第4k+1级时钟信号与所述第一时钟信号为同一信号，第4k+2级时钟信号与所述第二时钟信号为同一信号，第4k+3级时钟信号与所述第三时钟信号为同一信号，第4k+4级时钟信号与所述第四时钟信号为同一信号，其中，k大于等于0，且k为整数。
在本申请所述的显示面板中，所述GOA电路接入第一起始信号以及第二起始信号；
当所述GOA电路处于正向扫描模式时，第1级GOA单元接入所述第一起始信号，第2级GOA单元接入所述第二起始信号；
当所述GOA电路处于反向扫描模式时，第N级GOA单元接入所述第一起始信号，第N-1级GOA单元接入所述第二起始信号。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过精简电路架构，从而可以实现窄边框，降低制程和稳定性的风险。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的结构示意图；
图2为本申请实施例提供的GOA电路中的GOA单元的第一种电路示意图；
图3为本申请实施例提供的GOA电路中的GOA单元的第二种电路示意图；
图4为本申请实施例提供的GOA电路中的GOA单元的第三种电路示意图；
图5为本申请实施例提供的GOA电路中的GOA单元的第四种电路示意图；
图6为本申请实施例提供的GOA电路中的GOA单元的第五种电路示意图；
图7为图2所示的GOA单元的信号时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管均为N 型晶体管或P型晶体管，其中，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止；P 型晶体管为在栅极为低电平时导通，在栅极为高电平时截止。
请参阅图1，图1为本申请实施例提供的显示面板的结构示意图。如图1所示，本申请实施例提供的显示面板100包括显示区域20以及设置在显示区域20外的GOA电路区域10。显示区域20上设置有多条扫描线、多条数据线以及多条扫描线与多条数据线交叉限定的多个子像素单元。GOA电路区域10上设置有GOA电路，该GOA电路包括N级GOA单元，GOA单元与扫描线一一对应连接，即GOA单元的数量与扫描线的数量相等。
其中，该GOA电路包括多个级联的奇数级GOA单元以及多个级联的偶数级GOA单元。该多个级联的奇数级GOA单元设置在显示区域20的一侧，该多个级联的偶数级GOA单元设置在显示区域20的另一侧。
比如，当N为偶数时，第1级GOA单元、第3级GOA单元、第5级GOA单元、……、第N-1级GOA单元级联设置，第2级GOA单元、第4级GOA单元、第6级GOA单元、……、第N级GOA单元级联设置。需要说明的是，在本申请实施例中，N可以为偶数，也可以为奇数，在此不做限制。
其中，该GOA电路接入第一时钟信号ck1、第二时钟信号ck2、第三时钟信号ck3、第四时钟信号ck4、第一起始信号STV1以及第二起始信号STV2。具体的，该多个级联的奇数级GOA单元接入第一时钟信号ck1、第二时钟信号ck2、第三时钟信号ck3、第四时钟信号ck4以及第一起始信号STV1。该多个级联的偶数级GOA单元接入第一时钟信号ck1、第二时钟信号ck2、第三时钟信号ck3、第四时钟信号ck4以及第二起始信号STV2。
进一步的，请参阅图2，图2为本申请实施例提供的GOA电路中的GOA单元的第一种电路示意图。结合图1、图2所示，在本申请实施例提供的GOA电路中，第n级GOA单元100包括正向扫描控制模块101、反向扫描控制模块102、上拉模块103、下拉模块104以及功能模块105，2<n<N-1，n、N均为正整数。
其中，正向扫描控制模块101接入正向信号U2D、第n+1级时钟信号CK(n+1)以及第n-2级扫描信号G(n-2)，并电性连接于第一节点Q以及第二节点M。正向扫描控制模块101用于根据正向信号U2D、第n+1级时钟信号CK(n+1)以及第n-2级扫描信号G(n-2)，拉高第一节点Q的电位以及控制第二节点M的电位。
其中，反向扫描控制模块102接入反向信号D2U、第n-1级时钟信号CK(n-1)以及第n+2级扫描信号G(n+2)，并电性连接于第一节点Q以及第二节点M。反向扫描控制模块102用于根据反向信号D2U、第n-1级时钟信号CK(n-1)以及第n+2级扫描信号G(n+2)，拉高第一节点Q的电位以及控制第二节点M的电位。
其中，上拉模块103接入恒压低电平信号VGL、恒压高电平信号VGH以及第n级时钟信号CK（n），并电性连接于第一节点Q以及扫描信号输出端G。上拉模块103用于根据恒压低电平信号VGL、恒压高电平信号VGH、第n级时钟信号CK（n）以及第一节点Q的电位，控制扫描信号输出端G的电位。
其中，下拉模块104接入恒压高电平信号VGH以及恒压低电平信号VGL，并电性连接于第一节点Q、第二节点M以及扫描信号输出端G。下拉模块104用于根据恒压高电平信号VGH、恒压低电平信号VGL以及第二节的电位，拉低第一节点Q的电位以及扫描信号输出端G的电位。
其中，功能模块105接入第一功能控制信号GAS1、第二功能控制信号GAS2、第三功能控制信号GAS3以及第四功能控制信号GAS4，并电性连接于下拉模块104以及扫描信号输出端G。功能模块105用于根据第一功能控制信号GAS1、第二功能控制信号GAS2、第三功能控制信号GAS3以及第四功能控制信号GAS4，控制第一节点Q的电位以及扫描信号输出端G的电位。
需要说明的是，第4k+1级时钟信号CK(4k+1)与第一时钟信号ck1为同一信号，第4k+2级时钟信号CK(4k+2)与第二时钟信号ck2为同一信号，第4k+3级时钟信号CK(4k+3)与第三时钟信号ck3为同一信号，第4k+4级时钟信号CK(4k+4)与第四时钟信号ck4为同一信号，其中，k大于等于0，且k为整数。
例如，第1级时钟信号CK(1)、第5级时钟信号CK(5)、第9级时钟信号CK(9)、……第4k+1级时钟信号CK(4k+1)与第一时钟信号ck1均为同一信号。第2级时钟信号CK(2)、第6级时钟信号CK(6)、第10级时钟信号CK(10)、……第4k+2级时钟信号CK(4k+2)与第二时钟信号ck2均为同一信号。第3级时钟信号CK(3)、第7级时钟信号CK(7)、第11级时钟信号CK(11)、……第4k+3级时钟信号CK(4k+3)与第三时钟信号均为同一信号。第4级时钟信号CK(4)、第8级时钟信号CK(8)、第12级时钟信号CK(12)、……第4k+4级时钟信号CK(4k+4)与第四时钟信号ck4均为同一信号。
在一些实施例中，该正向扫描控制模块101包括第一晶体管NT1以及第三晶体管NT3；第一晶体管NT1的栅极电性连接于第n-2级扫描信号G（n-2），第一晶体管NT1的源极电性连接于正向扫描信号U2D以及第三晶体管NT3的栅极，第一晶体管NT1的漏极电性连接于第一节点Q，第三晶体管NT3的源极电性连接于第n+1级时钟信号CK(n+1)，第三晶体管NT3的漏极电性连接于第二节点M。
在一些实施例中，反向扫描控制模块102包括第二晶体管NT2以及第四晶体管NT4；第二晶体管NT2的栅极电性连接于第n+2级扫描信号G（n+2），第二晶体管NT2的源极电性连接于反向扫描信号D2U以及第四晶体管NT4的栅极，第二晶体管NT2的漏极电性连接于第一节点Q，第四晶体管NT4的源极电性连接于第n-1级时钟信号CK(n-1)，第四晶体管NT4的漏极电性连接于第二节点M。
在一些实施例中，上拉模块103包括第七晶体管NT7、第九晶体管NT9以及第一电容C1；第七晶体管NT7的栅极电性连接于恒压高电平信号VGH，第七晶体管NT7的源极电性连接于第一节点Q，第七晶体管NT7的漏极电性连接于第九晶体管NT9的栅极，第九晶体管NT9的栅极电性连接于第n级时钟信号CK（n），第九晶体管NT9的栅极电性连接于扫描信号输出端G，第一电容C1的一端电性连接于第一节点Q，第一电容C1的另一端电性连接于恒压低电平信号VGL。
在一些实施例中，下拉模块104包括第五晶体管NT5、第六晶体管NT6、第八晶体管NT8、第十晶体管NT10以及第二电容C2；第五晶体管NT5的栅极、第六晶体管NT6的漏极、第八晶体管NT8的漏极、第十晶体管NT10的栅极以及第二电容C2的一端均电性连接于第三节点N；第五晶体管NT5的源极、第六晶体管NT6的源极、第十晶体管NT10的源极以及第二电容C2的另一端均电性连接于恒压低电平信号VGL；第五晶体管NT5的漏极以及第六晶体管NT6的栅极均电性连接于第一节点Q；第八晶体管NT8的栅极电性连接于第二节点M，第八晶体管NT8的源极电性连接于恒压高电平信号VGH，第十晶体管NT10的漏极电性连接于扫描信号输出端G。
在一些实施例中，功能模块105包括第十一晶体管NT11以及第十二晶体管NT12；第十一晶体管NT11的栅极电性连接于第一功能控制信号GAS1，第十一晶体管NT11的源极电性连接于第三功能控制信号GAS3，第十一晶体管NT11的漏极电性连接于第三节点N；第十二晶体管NT12的栅极电性连接于第二功能控制信号GAS2，第十二晶体管NT12的源极电性连接于第四功能控制信号GAS4，第十二晶体管NT12的漏极电性连接于扫描信号输出端G。
此外，本申请实施例提供的GOA电路可以处于正向扫描模式或者反向扫描模式。当该GOA电路处于正向扫描模式时，在多个级联的奇数级GOA单元中，该GOA电路从第1级GOA单元至第N-1级GOA单元依次启动；在多个级联的偶数级GOA单元中，该GOA电路从第2级GOA单元至第N级GOA单元依次启动。当该GOA电路处于反向扫描模式时，在多个级联的奇数级GOA单元中，该GOA电路从第N-1级GOA单元至第1级GOA单元依次启动；在多个级联的偶数级GOA单元中，该GOA电路从第N级GOA单元至第2级GOA单元依次启动。
在一种实施方式中，当GOA电路处于正向扫描模式时，第1级GOA单元接入第一起始信号STV1，第2级GOA单元接入第二起始信号SYV2。此外，第N-1级GOA单元以及第N级GOA单元的电路示意图可参照图2所示，在此不做赘述。
具体的，请参阅图3，图3为本申请实施例提供的GOA电路中的GOA单元的第二种电路示意图。如图3所示，当GOA电路处于正向扫描模式时，第1级GOA单元与第n级GOA单元区别在于：第1级GOA单元中的第一晶体管NT1的栅极电性连接于第一起始信号STV1，第四晶体管NT4的源极空接。
具体的，请参阅图4，图4为本申请实施例提供的GOA电路中的GOA单元的第三种电路示意图。如图4所示，当GOA电路处于正向扫描模式时，第2级GOA单元与第n级GOA单元区别在于：第2级GOA单元中的第一晶体管NT1的栅极电性连接于第二起始信号STV2，第四晶体管NT4的源极空接。
在另一种实施方式中，当GOA电路处于反向扫描模式时，第N级GOA单元接入第一起始信号STV1，第N-1级GOA单元接入第二起始信号STV2。此外，第2级GOA单元以及第1级GOA单元的电路示意图可参照图2所示，在此不做赘述。
具体的，请参阅图5，图5为本申请实施例提供的GOA电路中的GOA单元的第四种电路示意图。如图5所示，当GOA电路处于反向扫描模式时，第N级GOA单元与第n级GOA单元区别在于：第N级GOA单元中的第二晶体管NT2的栅极电性连接于第一起始信号STV1，第三晶体管NT3的源极空接。
具体的，请参阅图6，图6为本申请实施例提供的GOA电路中的GOA单元的第五种电路示意图。如图6所示，当GOA电路处于反向扫描模式时，第N-1级GOA单元与第n级GOA单元区别在于：第N-1级GOA单元中的第二晶体管NT2的栅极电性连接于第二起始信号STV2，第三晶体管NT3的源极空接。
下面将以该GOA电路处于正向扫描模式为例进行说明，当该GOA电路处于正向扫描模式时，正向信号U2D为高电平，反向信号D2U为低电平。请结合图2、图7，图7为图2所示的GOA单元的信号时序图。结合图2、图3所示，当第n-2级扫描信号G（n-2）为高电位，第n级时钟信号CK（n）为高电位时，第一晶体管NT1、第七晶体管NT7以及第九晶体管NT9均打开，扫描信号输出端G输出高电位，即第n级扫描信号G（n）为高电位。随后，当第n+1级时钟信号CK(n+1)为高电位时，第三晶体管NT3、第八晶体管NT8、第五晶体管NT5以及第十晶体管NT10均打开，恒压低电平信号VGL经第五晶体管NT5输出至第一节点Q，恒压低电平信号VGL经第十晶体管NT10输出至扫描信号输出端G，即，第一节点Q的电位以及扫描信号G（n）的电位均被拉低。最后，第n+2级扫描信号G（n+2）为高电位，第二晶体管NT2打开，反向信号D2U输出至第一节点Q，以维持第一节点Q处于低电位。
进一步的，该GOA电路具有复位模式、异常断电模式以及全关断模式。当GOA电路处于复位模式时，第一功能控制信号GAS1以及第三功能控制信号GAS3为高电位。当GOA电路处于异常断电模式时，第一功能控制信号GAS1、第二功能控制信号GAS2以及第四功能控制信号GAS4均为高电位，第三功能控制信号GAS3为低电位。当GOA电路处于全关断模式时，第二功能控制信号GAS2为高电位，第四功能控制信号GAS4为低电位。
具体的，当GOA电路处于复位模式时，第一功能控制信号GAS1以及第三功能控制信号GAS3为高电位，第十一晶体管NT11打开，此时，第三节点N的电位为高电位，使得第五晶体管NT5打开，第一节点Q的电位被拉低，从而实现对第一节点Q进行复位。
当GOA电路处于异常断电模式时，第一功能控制信号GAS1、第二功能控制信号GAS2以及第四功能控制信号GAS4均为高电位，第三功能控制信号GAS3为低电位，第十一晶体管NT11打开，此时，第三节点N的电位为电位；与此同时第十二晶体管NT12打开，扫描信号输出端G输出的扫描信号G（n）为高电位，从而实现GOA电路异常断电时，GOA电路仍能继续工作。
当GOA电路处于全关断模式时，第二功能控制信号GAS2为高电位，第四功能控制信号GAS4为低电位，第十二晶体管NT12打开，扫描信号输出端G输出的扫描信号G（n）为低电位，从而实现GOA电路全关断模式，即每个GOA单元输出的扫描信号均为低电位。
本申请实施例提供的GOA电路及显示面板，通过精简电路架构，从而可以实现窄边框，降低制程和稳定性的风险。
以上仅为本申请的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种GOA电路，其包括N级GOA单元，第n级GOA单元包括正向扫描控制模块、反向扫描控制模块、上拉模块、下拉模块以及功能模块，其中，2<n<N-1，n、N均为正整数；
    所述正向扫描控制模块接入正向信号、第n+1级时钟信号以及第n-2级扫描信号，并电性连接于第一节点以及第二节点，所述正向扫描控制模块用于根据所述正向信号、所述第n+1级时钟信号以及所述第n-2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
    所述反向扫描控制模块接入反向信号、第n-1级时钟信号以及第n+2级扫描信号，并电性连接于所述第一节点以及所述第二节点，所述反向扫描控制模块用于根据所述反向信号、所述第n-1级时钟信号以及所述第n+2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
    所述上拉模块接入恒压低电平信号、恒压高电平信号以及第n级时钟信号，并电性连接于所述第一节点以及扫描信号输出端，所述上拉模块用于根据所述恒压低电平信号、所述恒压高电平信号、所述第n级时钟信号以及所述第一节点的电位，控制所述扫描信号输出端的电位；
    所述下拉模块接入所述恒压高电平信号以及所述恒压低电平信号，并电性连接于所述第一节点、所述第二节点以及所述扫描信号输出端，所述下拉模块用于根据所述恒压高电平信号、所述恒压低电平信号以及所述第二节的电位，拉低所述第一节点的电位以及所述扫描信号输出端的电位；
    所述功能模块接入第一功能控制信号、第二功能控制信号、第三功能控制信号以及第四功能控制信号，并电性连接于所述下拉模块以及所述扫描信号输出端，所述功能模块用于根据所述第一功能控制信号、所述第二功能控制信号、所述第三功能控制信号以及所述第四功能控制信号，控制所述第一节点的电位以及所述扫描信号输出端的电位。
  2. 根据权利要求1所述的GOA电路，其中，所述正向扫描控制模块包括第一晶体管以及第三晶体管；
    所述第一晶体管的栅极电性连接于所述第n-2级扫描信号，所述第一晶体管的源极电性连接于所述正向扫描信号以及所述第三晶体管的栅极，所述第一晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第n+1级时钟信号，所述第三晶体管的漏极电性连接于所述第二节点。
  3. 根据权利要求1所述的GOA电路，其中，所述反向扫描控制模块包括第二晶体管以及第四晶体管；
    所述第二晶体管的栅极电性连接于所述第n+2级扫描信号，所述第二晶体管的源极电性连接于所述反向扫描信号以及所述第四晶体管的栅极，所述第二晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第n-1级时钟信号，所述第四晶体管的漏极电性连接于所述第二节点。
  4. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括第七晶体管、第九晶体管以及第一电容；
    所述第七晶体管的栅极电性连接于所述恒压高电平信号，所述第七晶体管的源极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述第九晶体管的栅极，所述第九晶体管的栅极电性连接于所述第n级时钟信号，所述第九晶体管的栅极电性连接于所述扫描信号输出端，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括第五晶体管、第六晶体管、第八晶体管、第十晶体管以及第二电容；
    所述第五晶体管的栅极、所述第六晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的栅极以及所述第二电容的一端均电性连接于第三节点；所述第五晶体管的源极、所述第六晶体管的源极、所述第十晶体管的源极以及所述第二电容的另一端均电性连接于所述恒压低电平信号；所述第五晶体管的漏极以及所述第六晶体管的栅极均电性连接于所述第一节点；所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极电性连接于所述恒压高电平信号，所述第十晶体管的漏极电性连接于所述扫描信号输出端。
  6. 根据权利要求5所述的GOA电路，其中，所述功能模块包括第十一晶体管以及第十二晶体管；
    所述第十一晶体管的栅极电性连接于所述第一功能控制信号，所述第十一晶体管的源极电性连接于所述第三功能控制信号，所述第十一晶体管的漏极电性连接于所述第三节点；
    所述第十二晶体管的栅极电性连接于所述第二功能控制信号，所述第十二晶体管的源极电性连接于所述第四功能控制信号，所述第十二晶体管的漏极电性连接于所述扫描信号输出端。
  7. 根据权利要求6所述的GOA电路，其中，所述GOA电路具有复位模式、异常断电模式以及全关断模式；
    当所述GOA电路处于复位模式时，所述第一功能控制信号以及所述第三功能控制信号为高电位；
    当所述GOA电路处于异常断电模式时，所述第一功能控制信号、所述第二功能控制信号以及所述第四功能控制信号均为高电位，所述第三功能控制信号为低电位；
    当所述GOA电路处于全关断模式时，所述第二功能控制信号为高电位，所述第四功能控制信号为低电位。
  8. 根据权利要求1所述的GOA电路，其中，所述GOA电路接入第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号；
    第4k+1级时钟信号与所述第一时钟信号为同一信号，第4k+2级时钟信号与所述第二时钟信号为同一信号，第4k+3级时钟信号与所述第三时钟信号为同一信号，第4k+4级时钟信号与所述第四时钟信号为同一信号，其中，k大于等于0，且k为整数。
  9. 根据权利要求1所述的GOA电路，其中，所述GOA电路接入第一起始信号以及第二起始信号；
    当所述GOA电路处于正向扫描模式时，第1级GOA单元接入所述第一起始信号，第2级GOA单元接入所述第二起始信号；
    当所述GOA电路处于反向扫描模式时，第N级GOA单元接入所述第一起始信号，第N-1级GOA单元接入所述第二起始信号。
  10. 一种显示面板，其包括GOA电路，所述GOA电路包括N级GOA单元，第n级GOA单元包括正向扫描控制模块、反向扫描控制模块、上拉模块、下拉模块以及功能模块，其中，2<n<N-1，n、N均为正整数；
    所述正向扫描控制模块接入正向信号、第n+1级时钟信号以及第n-2级扫描信号，并电性连接于第一节点以及第二节点，所述正向扫描控制模块用于根据所述正向信号、所述第n+1级时钟信号以及所述第n-2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
    所述反向扫描控制模块接入反向信号、第n-1级时钟信号以及第n+2级扫描信号，并电性连接于所述第一节点以及所述第二节点，所述反向扫描控制模块用于根据所述反向信号、所述第n-1级时钟信号以及所述第n+2级扫描信号，拉高所述第一节点的电位以及控制所述第二节点的电位；
    所述上拉模块接入恒压低电平信号、恒压高电平信号以及第n级时钟信号，并电性连接于所述第一节点以及扫描信号输出端，所述上拉模块用于根据所述恒压低电平信号、所述恒压高电平信号、所述第n级时钟信号以及所述第一节点的电位，控制所述扫描信号输出端的电位；
    所述下拉模块接入所述恒压高电平信号以及所述恒压低电平信号，并电性连接于所述第一节点、所述第二节点以及所述扫描信号输出端，所述下拉模块用于根据所述恒压高电平信号、所述恒压低电平信号以及所述第二节的电位，拉低所述第一节点的电位以及所述扫描信号输出端的电位；
    所述功能模块接入第一功能控制信号、第二功能控制信号、第三功能控制信号以及第四功能控制信号，并电性连接于所述下拉模块以及所述扫描信号输出端，所述功能模块用于根据所述第一功能控制信号、所述第二功能控制信号、所述第三功能控制信号以及所述第四功能控制信号，控制所述第一节点的电位以及所述扫描信号输出端的电位。
  11. 根据权利要求10所述的显示面板，其中，所述正向扫描控制模块包括第一晶体管以及第三晶体管；
    所述第一晶体管的栅极电性连接于所述第n-2级扫描信号，所述第一晶体管的源极电性连接于所述正向扫描信号以及所述第三晶体管的栅极，所述第一晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述第n+1级时钟信号，所述第三晶体管的漏极电性连接于所述第二节点。
  12. 根据权利要求10所述的显示面板，其中，所述反向扫描控制模块包括第二晶体管以及第四晶体管；
    所述第二晶体管的栅极电性连接于所述第n+2级扫描信号，所述第二晶体管的源极电性连接于所述反向扫描信号以及所述第四晶体管的栅极，所述第二晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第n-1级时钟信号，所述第四晶体管的漏极电性连接于所述第二节点。
  13. 根据权利要求10所述的显示面板，其中，所述上拉模块包括第七晶体管、第九晶体管以及第一电容；
    所述第七晶体管的栅极电性连接于所述恒压高电平信号，所述第七晶体管的源极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述第九晶体管的栅极，所述第九晶体管的栅极电性连接于所述第n级时钟信号，所述第九晶体管的栅极电性连接于所述扫描信号输出端，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
  14. 根据权利要求10所述的显示面板，其中，所述下拉模块包括第五晶体管、第六晶体管、第八晶体管、第十晶体管以及第二电容；
    所述第五晶体管的栅极、所述第六晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的栅极以及所述第二电容的一端均电性连接于第三节点；所述第五晶体管的源极、所述第六晶体管的源极、所述第十晶体管的源极以及所述第二电容的另一端均电性连接于所述恒压低电平信号；所述第五晶体管的漏极以及所述第六晶体管的栅极均电性连接于所述第一节点；所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极电性连接于所述恒压高电平信号，所述第十晶体管的漏极电性连接于所述扫描信号输出端。
  15. 根据权利要求14所述的显示面板，其中，所述功能模块包括第十一晶体管以及第十二晶体管；
    所述第十一晶体管的栅极电性连接于所述第一功能控制信号，所述第十一晶体管的源极电性连接于所述第三功能控制信号，所述第十一晶体管的漏极电性连接于所述第三节点；
    所述第十二晶体管的栅极电性连接于所述第二功能控制信号，所述第十二晶体管的源极电性连接于所述第四功能控制信号，所述第十二晶体管的漏极电性连接于所述扫描信号输出端。
  16. 根据权利要求15所述的显示面板，其中，所述GOA电路具有复位模式、异常断电模式以及全关断模式；
    当所述GOA电路处于复位模式时，所述第一功能控制信号以及所述第三功能控制信号为高电位；
    当所述GOA电路处于异常断电模式时，所述第一功能控制信号、所述第二功能控制信号以及所述第四功能控制信号均为高电位，所述第三功能控制信号为低电位；
    当所述GOA电路处于全关断模式时，所述第二功能控制信号为高电位，所述第四功能控制信号为低电位。
  17. 根据权利要求10所述的显示面板，其中，所述GOA电路接入第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号；
    第4k+1级时钟信号与所述第一时钟信号为同一信号，第4k+2级时钟信号与所述第二时钟信号为同一信号，第4k+3级时钟信号与所述第三时钟信号为同一信号，第4k+4级时钟信号与所述第四时钟信号为同一信号，其中，k大于等于0，且k为整数。
  18. 根据权利要求10所述的显示面板，其中，所述GOA电路接入第一起始信号以及第二起始信号；
    当所述GOA电路处于正向扫描模式时，第1级GOA单元接入所述第一起始信号，第2级GOA单元接入所述第二起始信号；
    当所述GOA电路处于反向扫描模式时，第N级GOA单元接入所述第一起始信号，第N-1级GOA单元接入所述第二起始信号。
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