WO2021258460A1 - 驱动电路、显示面板及显示装置 - Google Patents

驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2021258460A1
WO2021258460A1 PCT/CN2020/103155 CN2020103155W WO2021258460A1 WO 2021258460 A1 WO2021258460 A1 WO 2021258460A1 CN 2020103155 W CN2020103155 W CN 2020103155W WO 2021258460 A1 WO2021258460 A1 WO 2021258460A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
level
signal
node
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Application number
PCT/CN2020/103155
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English (en)
French (fr)
Inventor
田超
管延庆
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/971,483 priority Critical patent/US11961490B2/en
Publication of WO2021258460A1 publication Critical patent/WO2021258460A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • This application relates to the field of display technology, in particular to a driving circuit, a display panel and a display device.
  • GOA driving is a technology that uses the existing thin-film transistor liquid crystal display array (Array) process to fabricate a row scan driving signal circuit on an array substrate to realize a row-by-row scan driving method.
  • the GOA drive circuit is divided into NMOS circuit, PMOS circuit and CMOS circuit.
  • the NMOS circuit eliminates the PP (P doping) layer of the mask and the process, which is of great benefit to improving the yield and reducing the cost. Therefore, the development of a stable NMOS circuit has a realistic industrial demand.
  • the carriers of NMOSTFT are electrons, and the mobility is relatively high.
  • the device is relatively easy to damage PMOS (carriers are holes).
  • the display on the panel is the lack of high-temperature reliability of the product.
  • the current ITP panel usually needs to be within one frame Insert several touch period (TP Term), used to realize the touch function, but NMOS GOA maintains the high potential required for stage transmission through the capacitance of the Q point, but the thin film transistor (TFT) is not an ideal device, even in the off state, there will still be a certain amount of leakage current; the touch period (TP Term) continues If the time is longer, the pause level of the touch panel (TP) needs to maintain a high potential for a long time, thus reducing the level of GOA transmission stability. It is easy to cause GOA driver failure, split screen phenomenon, especially in-cell touch panel (In-Cell Touch Panel, ITP), the split screen phenomenon is more likely to occur at the TP pause level.
  • the embodiments of the present application provide a driving circuit, a display panel, and a display device to improve the stability of the driving circuit.
  • the present application provides a driving circuit, wherein the driving circuit includes a plurality of cascaded driving units, and the first-level driving unit includes:
  • the forward and reverse scanning control module is used to control the driving circuit to perform forward scanning according to a forward scanning control signal or to control the driving circuit to perform reverse scanning according to a reverse scanning control signal;
  • the node signal control module is used to control the driving circuit to output the gate driving signal during the abnormal operation stage according to the clock signal of the second-level driving unit and the gate driving signal output by the third-level driving unit;
  • the level of the gate driving signal is less than the preset level
  • the second-level driving unit is the upper-level driving unit of the first-level driving unit
  • the third-level driving unit is the next-level of the first-level driving unit Drive unit;
  • the output control module is located between the first node and the output terminal of the first-stage drive unit, and is used to control the output of the first-stage gate drive signal during the forward scan or reverse scan of the drive circuit; wherein A node is the node of the output terminal of the forward and reverse scan control module;
  • the first voltage stabilizing module is connected to the forward and backward scanning control module and the output control module, and is used to maintain the level of the output signal of the forward and backward scanning control module;
  • the first pull-down module is used to pull down the level of the second node
  • the second pull-down module is configured to pull-down the voltage at the first node and the voltage at the output terminal of the first-level driving unit according to the control signal provided by the node signal control module;
  • the leakage control module is connected to the forward and backward scanning control module, the first pull-down module, and the second pull-down module, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the leakage control module includes a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the gate of the first thin film transistor is connected to the first node, the source of the first thin film transistor is connected to a constant voltage high potential signal, and the drain of the first thin film transistor is connected to the drain of the second thin film transistor.
  • the electrode of the second thin film transistor is connected to the drain of the third thin film transistor; the gate of the second thin film transistor is connected to a constant voltage low potential signal, the source of the second thin film transistor is connected to the first node, and the third thin film transistor
  • the gate is connected to the second node, and the third thin film transistor is connected to a constant voltage low potential signal.
  • the first-stage driving unit further includes a third voltage stabilizing module for maintaining the level of the third node, the third voltage stabilizing module includes a first capacitor, and the first capacitor One end is connected to the third node, and the other end is connected to the first-stage gate drive signal.
  • the forward scan control module includes a fourth thin film transistor and a fifth thin film transistor
  • the source of the fourth thin film transistor is connected to the forward scan control signal, and the gate of the fourth thin film transistor is connected to the gate driving signal of the fourth-level driving unit; the drain of the fourth thin film transistor is respectively Connected to the drain of the fifth thin film transistor, the first pull-down module and the first node;
  • the source of the fifth thin film transistor is connected to the reverse scan control signal, and the gate of the fifth thin film transistor is connected to the gate driving signal of the fifth level driving unit, and the fourth level driving unit is the third level The next-level driving unit of the driving unit, and the second-level driving unit is the upper-level driving unit of the first-level driving unit.
  • the node signal control module includes a sixth thin film transistor, a seventh thin film transistor, and an eleventh thin film transistor;
  • the gate of the sixth thin film transistor is connected to the source of the fourth thin film transistor, the source of the sixth thin film transistor is connected to the second-level clock signal, and the drain of the sixth thin film transistor is connected to the seventh
  • the drain of the thin film transistor is connected to the gate of the eleventh thin film transistor;
  • the gate of the seventh thin film transistor is connected to the source of the fifth thin film transistor, and the source of the seventh thin film transistor is connected to the third-level clock Signal;
  • the source of the eleventh thin film transistor is connected to a constant voltage high potential signal, and the drain of the eleventh thin film transistor is connected to the second node.
  • the first pull-down module includes a ninth thin film transistor, the gate of the ninth thin film transistor is connected to the drain of the fifth thin film transistor, and the source of the ninth thin film transistor is connected to Inputting the constant voltage low potential signal, the drain of the ninth thin film transistor is connected to the second node.
  • the first voltage stabilizing module includes a tenth thin film transistor, the gate of the tenth thin film transistor is connected to a constant voltage high potential signal, and the source of the tenth thin film transistor is connected to the The first node is connected.
  • the output control module includes a twelfth thin film transistor, the gate of the twelfth thin film transistor is connected to the drain of the tenth thin film transistor, and the The source is connected to the first-level clock signal.
  • a display panel includes the drive circuit, the drive circuit includes a plurality of cascaded drive units, and the first-level drive unit includes:
  • the forward and reverse scanning control module is used to control the driving circuit to perform forward scanning or reverse scanning according to the forward scanning control signal or the reverse scanning control signal;
  • the node signal control module is used to control the driving circuit to output a gate driving signal during an abnormal operation stage according to the clock signal of the second-level driving unit and the gate driving signal output by the third-level driving unit; wherein, the driving circuit
  • the level of the output gate driving signal is less than the preset level
  • the second-level driving unit is the upper-level driving unit of the first-level driving unit
  • the third-level driving unit is the lower-level driving unit of the first-level driving unit.
  • the output control module is located between the first node and the output terminal of the first-stage drive unit, and is used to control the output of the first-stage gate drive signal during the forward scan or reverse scan of the drive circuit, wherein the first-stage gate drive signal is A node is the node of the output terminal of the forward and reverse scan control module;
  • the first voltage stabilizing module is connected to the forward and backward scanning control module and the output control, and is used to maintain the level of the output signal of the forward and backward scanning control module;
  • the first pull-down module is used to pull down the level of the second node
  • a second pull-down module configured to pull down the voltage at the first node and the voltage at the output terminal according to the control signal provided by the node signal control module;
  • the leakage control module is connected to the forward and backward scanning control module, the first pull-down module, and the second pull-down module, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the leakage control module includes a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the gate of the first thin film transistor is connected to the first node, the source of the first thin film transistor is connected to a constant voltage high potential signal, and the drain of the first thin film transistor is connected to the drain of the second thin film transistor.
  • the electrode of the second thin film transistor is connected to the drain of the third thin film transistor; the gate of the second thin film transistor is connected to a constant voltage low potential signal, the source of the second thin film transistor is connected to the first node, and the third thin film transistor
  • the gate is connected to the second node, and the third thin film transistor is connected to a constant voltage low potential signal.
  • the first-stage driving unit further includes a third voltage stabilizing module for maintaining the level of the third node, and the third voltage stabilizing module includes a first capacitor, and the first capacitor One end is connected to the third node, and the other end is connected to the first-stage gate drive signal.
  • the forward scan control module includes a fourth thin film transistor and a fifth thin film transistor
  • the source of the fourth thin film transistor is connected to the forward scan control signal, and the gate of the fourth thin film transistor is connected to the gate driving signal of the fourth-level driving unit; the drain of the fourth thin film transistor is respectively Connected to the drain of the fifth thin film transistor, the first pull-down module and the first node;
  • the source of the fifth thin film transistor is connected to the reverse scan control signal, and the gate of the fifth thin film transistor is connected to the gate driving signal of the fifth level driving unit, and the fourth level driving unit is the third level The next-level driving unit of the driving unit, and the second-level driving unit is the upper-level driving unit of the first-level driving unit.
  • the node signal control module includes a sixth thin film transistor, a seventh thin film transistor, and an eleventh thin film transistor;
  • the gate of the sixth thin film transistor is connected to the source of the fourth thin film transistor, the source of the sixth thin film transistor is connected to the second-level clock signal, and the drain of the sixth thin film transistor is connected to the seventh
  • the drain of the thin film transistor is connected to the gate of the eleventh thin film transistor;
  • the gate of the seventh thin film transistor is connected to the source of the fifth thin film transistor, and the source of the seventh thin film transistor is connected to the third-level clock Signal;
  • the source of the eleventh thin film transistor is connected to a constant voltage high potential signal, and the drain of the eleventh thin film transistor is connected to the second node.
  • the first pull-down module includes a ninth thin film transistor, the gate of the ninth thin film transistor is connected to the drain of the fifth thin film transistor, and the source of the ninth thin film transistor is connected to Inputting the constant voltage low potential signal, the drain of the ninth thin film transistor is connected to the second node.
  • the first voltage stabilizing module includes a tenth thin film transistor, the gate of the tenth thin film transistor is connected to a constant voltage high potential signal, and the source of the tenth thin film transistor is connected to the The first node is connected.
  • the output control module includes a twelfth thin film transistor, the gate of the twelfth thin film transistor is connected to the drain of the tenth thin film transistor, and the The source is connected to the first-level clock signal.
  • a display device the display panel includes a driving circuit, the driving circuit includes a plurality of cascaded driving units, and the first-level driving unit includes:
  • the forward and reverse scanning control module is used to control the driving circuit to perform forward scanning or reverse scanning according to the forward scanning control signal or the reverse scanning control signal;
  • the node signal control module is used to control the driving circuit to output a gate driving signal during an abnormal operation stage according to the clock signal of the second-level driving unit and the gate driving signal output by the third-level driving unit; wherein, the driving circuit
  • the level of the output gate driving signal is less than the preset level
  • the second-level driving unit is the upper-level driving unit of the first-level driving unit
  • the third-level driving unit is the lower-level driving unit of the first-level driving unit.
  • the output control module is located between the first node and the output terminal of the first-stage drive unit, and is used to control the output of the first-stage gate drive signal during the forward scan or reverse scan of the drive circuit, wherein the first-stage gate drive signal is A node is the node of the output terminal of the forward and reverse scan control module;
  • the first voltage stabilizing module is connected to the forward and backward scanning control module and the output control, and is used to maintain the level of the output signal of the forward and backward scanning control module;
  • the first pull-down module is used to pull down the level of the second node
  • a second pull-down module configured to pull down the voltage at the first node and the voltage at the output terminal according to the control signal provided by the node signal control module;
  • the leakage control module is connected to the forward and backward scanning control module, the first pull-down module, and the second pull-down module, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the leakage control module includes a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the gate of the first thin film transistor is connected to the first node, the source of the first thin film transistor is connected to a constant voltage high potential signal, and the drain of the first thin film transistor is connected to the drain of the second thin film transistor.
  • the electrode of the second thin film transistor is connected to the drain of the third thin film transistor; the gate of the second thin film transistor is connected to the constant voltage low level point, the source of the second thin film transistor is connected to the first node, and the third thin film transistor.
  • the gate of the transistor is connected to the second node, and the gate source of the third thin film transistor is connected to a constant voltage low potential signal.
  • the first-stage driving unit further includes a third voltage stabilizing module for maintaining the level of the third node, and the third voltage stabilizing module includes a first capacitor, and the first capacitor One end is connected to the third node, and the other end is connected to the first-stage gate drive signal.
  • the forward scan control module includes a fourth thin film transistor and a fifth thin film transistor
  • the source of the fourth thin film transistor is connected to the forward scan control signal, and the gate of the fourth thin film transistor is connected to the gate driving signal of the fourth-level driving unit; the drain of the fourth thin film transistor is respectively Connected to the drain of the fifth thin film transistor, the first pull-down module and the first node;
  • the source of the fifth thin film transistor is connected to the reverse scan control signal, and the gate of the fifth thin film transistor is connected to the gate driving signal of the fifth level driving unit, and the fourth level driving unit is the third level The next-level driving unit of the driving unit, and the second-level driving unit is the upper-level driving unit of the first-level driving unit.
  • the driving circuit, the display panel and the display device of the present application add a leakage control module.
  • the first node will The high-level signal is output to the leakage control module. Since the voltage of the leakage control module is also in a high-level state, the first node does not generate leakage current, so the stability of the first node can be improved, and the drive circuit can be increased The stability.
  • FIG. 1 is a schematic diagram of the module connection relationship of the n-th GOA driving unit in an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of a GOA driver provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the structure of the n-th GOA unit of the GOA driving circuit in an embodiment of the application.
  • FIG. 4 is a schematic diagram of the structure of the n+2th GOA unit of the GOA driving circuit in the embodiment of the application.
  • FIG. 5 is a timing diagram of the GOA driving circuit of the 4CK architecture display panel in an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a GOA driving circuit provided by another embodiment of this application.
  • the present application provides a driving circuit, a display panel, and a display device.
  • a driving circuit a display panel
  • a display device a display device
  • the driving circuit provided in the embodiment of the present application takes a GOA driving circuit as an example.
  • the GOA drive circuit includes a plurality of cascaded GOA drive units. Specifically, please refer to FIG. 1.
  • the GOA drive units of each stage of the cascaded GOA drive units include: leakage control module 100, forward and backward scanning control module 200, node signal control module 300, output control module 400, first voltage stabilizing module 500, A pull-down module 600 and a second pull-down module 700.
  • the forward and reverse scanning control module 200 is used to control the driving circuit to perform forward scanning according to a forward scanning control signal or to control the driving circuit to perform reverse scanning according to a reverse scanning control signal.
  • the node signal control module 300 is used to control the driving circuit to output a gate driving signal in an abnormal operation stage according to the clock signal of the second-level driving unit and the gate driving signal output by the third-level driving unit; wherein, the gate The level of the pole driving signal is less than the preset level, that is, a low-level gate driving signal is output.
  • the second-level driving unit is the upper-level driving unit of the first-level driving unit
  • the third-level driving unit is It is the next level of drive unit of the first level of drive unit.
  • the output control module 400 located between the first node Q and the output terminal of the first-level driving unit, is used to control the output of the first-level gate driving signal during the forward scan or the reverse scan of the driving circuit.
  • the first node is a node of the output terminal of the forward and reverse scan control module.
  • the first voltage stabilizing module 500 is connected to the forward and backward scanning control module 200 and the output control module 400 to maintain the level of the output signal of the forward and backward scanning control module 200.
  • the first pull-down module 600 is used to pull down the level of the second node P.
  • the second pull-down module 700 is configured to pull down the voltage at the first node Q and the voltage at the output terminal of the first-level driving unit according to the control signal provided by the node signal control module 300.
  • the leakage control module 100 is connected to the forward and backward scanning control module 200, the first pull-down module 600, and the second pull-down module 700, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the leakage control module 100 is connected to the forward and reverse scan control module 300, the first pull-down module 600, and the second pull-down module 700, and is used to maintain the electrical output of the forward and reverse scan control module 200. flat.
  • the driving circuit, display panel, and display device of the present application add a leakage control module.
  • the first node maintains a high level.
  • a node outputs a high-level signal to the leakage control module. Since the voltage of the leakage control module is also in a high-level state, the first node does not generate leakage current, so the stability of the first node can be improved, and the The stability of the drive circuit is improved.
  • the GOA drive unit structure of each stage of the multiple cascaded GOA drive units is the same, for example, the GOA circuit of the application includes m cascaded GOAs
  • the driving unit namely the first-level driving unit, the second-level driving unit...the n-1th level driving unit, the nth level driving unit, the n+1th level driving unit...the mth level driving unit, where m ⁇ n ⁇ 1, the GOA drive circuit in the embodiment of the present application includes the above m GOA drive units.
  • the output of the nth GOA circuit unit is connected to the input of the next (n+1) GOA circuit unit, and the input of the nth GOA circuit unit is connected to the input of a (n-1) GOA circuit.
  • the leakage control module 100 includes a first thin film transistor NT1, a second thin film transistor NT2, and a third thin film transistor NT3.
  • the gate of the first thin film transistor NT1 is connected to the first node Q, the source is connected to a constant voltage high potential signal, and the drain is connected to the drain of the second thin film transistor NT2 and the drain of the third thin film transistor NT3;
  • the gate of the second thin film transistor NT2 is connected to a constant voltage low potential signal, the source is connected to the first node Q, the gate of the third thin film transistor NT3 is connected to the second node P, and the source is connected to the constant voltage low Potential signal VGL.
  • the forward and reverse scanning control module 200 is used for controlling the GOA drive to perform forward scanning or reverse scanning according to the forward scanning control signal U2D or the reverse scanning control signal D2U.
  • the forward scanning control module 200 includes a fourth thin film transistor NT4 and a fifth thin film transistor NT5; the source of the fourth thin film transistor NT4 is connected to the forward scanning control signal, and the gate is connected to the n-2th stage GOA
  • the gate drive signal of the driving unit; the drain is respectively connected to the drain of the fifth thin film transistor NT5, the second pull-down module 600 and the fourth node; the source of the fifth thin film transistor NT5 is connected
  • the gate is connected to the gate driving signal of the n+2th GOA driving unit.
  • the node signal control module 300 is used to control the GOA unit of the current level, that is, the GOA unit of the nth level, according to the n+1th level clock signal CK(n+1) and the n-1th level clock signal CK(n-1).
  • the working phase outputs a low-potential gate drive signal, where the abnormal working phase may be, for example, a working phase when the power is suddenly cut off or a working phase when the screen is abnormally black.
  • the node signal control module 300 includes a sixth thin film transistor NT6, a seventh thin film transistor NT7, and an eleventh thin film transistor NT11; the gate of the sixth thin film transistor NT6 is connected to the source of the third thin film transistor NT3, The source is connected to the n+1th stage clock signal, the drain is connected to the drain of the seventh thin film transistor NT7 and the gate of the eleventh thin film transistor NT11; the gate of the seventh thin film transistor NT7 is connected to the fifth thin film transistor The source of NT5 is connected, and the source is connected to the n-1 level clock signal; the source of the eleventh thin film transistor NT11 is connected to the constant voltage high potential signal, and the drain is connected to the second node P.
  • the output control module 400 is used to control the output of the gate driving signal of the current stage (the nth stage) according to the clock signal CK(n) of the current stage (the nth stage).
  • the output control module 400 includes a twelfth thin film transistor NT12, the gate of the twelfth thin film transistor NT12 is connected to the drain of the tenth thin film transistor NT10, and the source is connected to the clock of the current stage (nth stage) Signal.
  • the first voltage stabilizing module 500 is used to maintain the level of the first node Q.
  • the first voltage stabilizing module 500 includes a ninth thin film transistor NT9, the gate of the ninth thin film transistor NT9 is connected to a constant voltage high-potential signal, and the source is connected to the first node Q.
  • the first pull-down module 600 is used to pull down the level of the second node P.
  • the first pull-down module 600 includes a ninth thin film transistor NT9, the gate of the ninth thin film transistor NT9 is connected to the drain of the fifth thin film transistor NT5, and the source is connected to the constant voltage low potential signal VGL , The drain is connected to the second node P
  • the second pull-down module 700 is used to pull down the level of the gate driving signal G(n) of the current stage (the nth stage).
  • the second pull-down module 700 includes an eighth thin film transistor NT8.
  • the gate of the eighth thin film transistor NT8 is connected to the second node P and connected to the drain of the eleventh transistor NT11, and the source is connected to the constant voltage low potential signal VGL, The drain is connected to the gate drive signal G(n) of this stage (the nth stage).
  • the GOA driving unit may further include a third pull-down module 800, a pull-up module 900, and a second capacitor C2.
  • the third pull-down module 800 includes a fifteenth thin film transistor NT15.
  • the gate of the fifteenth thin film transistor NT15 is connected to the second global signal GAS2, the source is connected to the constant voltage low potential signal VGL, and the drain is connected to the gate of the current stage.
  • the drive signal G(n) is connected, and the third pull-down module 800 is used to pull down the current level (the nth level) gate drive signal G(n) according to the second global signal GAS2 when the display panel is in the second working state. flat.
  • the pull-up module 900 includes a thirteenth thin film transistor NT13 and a fourteenth thin film transistor NT14.
  • the drain and gate of the thirteenth thin film transistor NT13 are both connected to the first global signal Gas1, and the source is driven by the gate of the current stage.
  • the signal G(n) is connected; the gate of the fourteenth thin film transistor NT14 is connected to the first global signal Gas1, the source is connected to the constant voltage low potential signal VGL, and the drain is connected to the gate of the eleventh thin film transistor T11.
  • the pull-up module 900 is used for controlling the GOA unit of the current stage (nth stage) to output a high-level gate driving signal according to the first global signal GAS1 when the display panel is in the first working state.
  • the first working state is a black screen touch working state or an abnormal power-off state. It can be understood that when the display panel is in the first working state, the first global signal GAS1 is at a high level, and all GOA units output high-level gate driving signals.
  • the second working state is a display touch operation period, at which time the second global signal GAS2 is at a high level.
  • one end of the second capacitor C2 is connected to the second node P, and the other end is connected to the constant voltage low potential signal VGL.
  • the left GOA circuit and the right GOA circuit are respectively provided on both sides of the display panel.
  • the left GOA circuit drives the scan lines of odd rows
  • the right GOA circuit drives the scan lines of even rows.
  • the GOA circuit circulates with 2 basic units as the minimum repeating unit.
  • the n-th GOA unit and the n+2th GOA unit can jointly form a GOA repeating unit.
  • Figure 5 shows the timing diagram of the GOA circuit corresponding to the display panel of the 4CK architecture.
  • the nth stage clock signal of the unit is the first clock signal CK1
  • the n+1th stage clock signal of the nth GOA unit is the second clock signal CK2
  • the n-1th stage clock signal of the nth GOA unit is the first clock signal CK1.
  • 4 Clock signal CK4 when the nth stage clock signal of the n+2 stage GOA unit is the third clock signal CK3, the n+1 stage clock signal of the n+2 stage GOA unit is the fourth clock signal, and the nth stage The n-1 level clock signal of the +2 level GOA unit is the second clock signal.
  • the node signal control module 300 of the nth level GOA unit is connected to the second and fourth clock signals, and the output control module 400 is connected to the first clock signal, then the first clock signal is connected to the output control module 400.
  • the node signal control module of the n+1 level GOA unit is connected to the first and third clock signals, and the output control module 400 of the n+1 level GOA unit is connected to the second clock signal.
  • the node signal control module 300 of the nth level GOA unit is connected to the second and fourth clock signals correspondingly, and the output control module 400 is connected to the third clock signal, then the n+1th level The node signal control module 300 of the GOA unit is connected to the second and fourth clock signals, and the output control module 400 of the n+1 level GOA unit is connected to the fourth clock signal.
  • the duty cycle of the 4 CK signals can be 50% or 25%, etc.
  • the duty cycle used in Figure 5 is 25%.
  • the display panel can also use the 8CK architecture, and the GOA circuit circulates with 4 basic units as the smallest repeating unit.
  • first global signal GAS1 and the second global signal GAS2 are both at a low level when the display panel is working normally, and the second global signal GAS2 changes from a low level to a high level during the display period T1 to the touch period T2.
  • VGL and D2U under normal conditions, the voltages of VGL and D2U are the same. Under heavy load images (such as pixel inversion and other images), the display area is connected to the VGL signal through NT10, and VGL is most affected by the couple of the display area. Compared with the D2U signal, VGL has greater fluctuations. Therefore, although the voltage of VGL and D2U are the same, but the instantaneous voltage of VGL affected by the coupling (Couple) is higher than that of D2U, then the G(N+2) signal will not be pulled down, because The gate of the third thin film transistor NT3 of the next-stage GOA unit is connected to G(N+2), resulting in the risk of the third thin film transistor NT3 being turned on instantaneously.
  • the embodiment of the present application adds the first thin film transistor NT1 and the second thin film transistor NT2 by adding the first voltage stabilizing unit 100, and modifies the original Q point through the drain circuit of the third thin film transistor NT3 to VGL to VGH passes through the first thin film transistor NT1 and the third thin film transistor NT3 to the VGL leakage path, reducing the Q point through the second thin film transistor NT2 and the third thin film transistor NT3 to the VGL leakage path; during the stage transfer and touch screen (TP) period, Q The point is high.
  • TP stage transfer and touch screen
  • the first thin film transistor NT1 is turned on, and it outputs VGH to the connection point of the first thin film transistor NT1, the second thin film transistor NT2 and the third thin film transistor NT3.
  • the source of the second thin film transistor NT2 is connected to
  • the drain voltages are all VGH, so there will be no Q point and no leakage to VGL through the third thin film transistor NT3, so as to ensure the stability of the Q point voltage; adding the first voltage stabilizing unit 100 can reduce the Q point leakage path and improve
  • the GOA drive circuit is stable in level transmission, and compared with the original circuit structure, it does not increase the number of signal lines and does not change the timing.
  • FIG. 6 is a GOA circuit diagram of another embodiment of this application.
  • the structures and functions of the other modules are the same as those of the previous embodiment, and will not be repeated here.
  • the third voltage stabilizing module 110 is used to maintain the level of the third node Qa.
  • the third voltage stabilizing module 110 includes a first capacitor C1. One end of the first capacitor C1 is connected to the third node Qa, and the other end is connected to the third node Qa.
  • the connection of the gate drive signal of this stage (the nth stage) is conducive to the increase of the potential of the Qa point and the output of the gate drive signal G(n) of this stage (the nth stage).
  • the embodiment of the present application also provides a display panel.
  • the GOA drive circuit is integrated in the display panel.
  • the GOA drive circuit uses For driving the display panel, the GOA driving circuit includes a plurality of cascaded driving units, and the GOA driving unit of each stage of the plurality of cascaded GOA driving units includes: leakage control module 100, forward and reverse scanning control The module 200, the node signal control module 300, the output control module 400, the first voltage stabilizing module 500, the first pull-down module 600, and the second pull-down module 700.
  • the forward and reverse scanning control module 200 is used to control the driving circuit to perform forward scanning according to a forward scanning control signal or to control the driving circuit to perform reverse scanning according to a reverse scanning control signal.
  • the node signal control module 300 is used to control the driving circuit to output a gate driving signal in an abnormal operation stage according to the clock signal of the second-level driving unit and the gate driving signal output by the third-level driving unit; wherein, the gate The level of the pole driving signal is less than the preset level, that is, a low-level gate driving signal is output.
  • the second-level driving unit is the upper-level driving unit of the first-level driving unit
  • the third-level driving unit is It is the next level of drive unit of the first level of drive unit.
  • the output control module 400 located between the first node Q and the output terminal of the first-level driving unit, is used to control the output of the first-level gate driving signal during the forward scan or the reverse scan of the driving circuit.
  • the first node is a node of the output terminal of the forward and reverse scan control module.
  • the first voltage stabilizing module 500 is connected to the forward and backward scanning control module and the output control module, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the first pull-down module 600 is used to pull down the level of the second node.
  • the second pull-down module 700 is configured to pull down the voltage at the first node Q and the voltage at the output terminal of the first-level driving unit according to the control signal provided by the node signal control module 300.
  • the leakage control module 100 is connected to the forward and backward scanning control module 200, the first pull-down module 600, and the second pull-down module 700, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the leakage control module 100 is connected to the forward and reverse scan control module 300, the first pull-down module 600, and the second pull-down module 700, and is used to maintain the electrical output of the forward and reverse scan control module 200. flat.
  • the display panel provided by the embodiment of the present application includes the GOA circuit, and the GOA driving circuit adds a leakage control module, the signal is transmitted during each level of the driving unit and the touch panel is used. Since the Q point remains high, At this time, point Q outputs a high-level signal to the leakage control module. Since the voltage of the leakage control module is also at a high level, no leakage current is generated at point Q, so the stability of point Q can be improved, and The level transmission stability of the driving circuit is improved, thereby improving the display stability of the display panel.
  • An embodiment of the present application also provides a display device, the display panel is integrated in the display device, the display device performs display through the display panel, and the display panel includes the GOA circuit,
  • the driving circuit includes:
  • the GOA driving circuit includes a plurality of cascaded driving units, and the first-level driving unit includes:
  • the forward and reverse scanning control module is used to control the driving circuit to perform forward scanning or reverse scanning according to the forward scanning control signal or the reverse scanning control signal;
  • the node signal control module is used to control the driving circuit to output a gate driving signal during an abnormal operation stage according to the clock signal of the second-level driving unit and the gate driving signal output by the third-level driving unit; wherein, the driving circuit
  • the level of the output gate driving signal is less than the preset level
  • the second-level driving unit is the upper-level driving unit of the first-level driving unit
  • the third-level driving unit is the lower-level driving unit of the first-level driving unit.
  • the output control module is located between the first node and the output terminal of the first-stage drive unit, and is used to control the output of the first-stage gate drive signal during the forward scan or reverse scan of the drive circuit, wherein the first-stage gate drive signal is A node is the node of the output terminal of the forward and reverse scan control module;
  • the first voltage stabilizing module is connected to the forward and backward scanning control module and the output control, and is used to maintain the level of the output signal of the forward and backward scanning control module;
  • the first pull-down module is used to pull down the level of the second node
  • a second pull-down module configured to pull down the voltage at the first node and the voltage at the output terminal according to the control signal provided by the node signal control module;
  • the leakage control module is connected to the forward and backward scanning control module, the first pull-down module, and the second pull-down module, and is used to maintain the level of the output signal of the forward and backward scanning control module.
  • the embodiment of the application adds a leakage control module to the GOA drive circuit in the display device.
  • a leakage control module to the GOA drive circuit in the display device.
  • the signal is output to the leakage control module. Since the voltage of the leakage control module is also at a high level, no leakage current will be generated at the Q point, so the stability of the Q point can be improved, and the level transmission stability of the drive circuit can be increased , Thereby improving the display stability of the display panel, thereby improving the stability of the display performance of the display device.
  • the display device may include, but is not limited to, mobile phones, tablet computers, notebook computers, televisions, MID (Mobile Internet Devices, mobile Internet equipment), PDA (Personal Digital Assistant, personal digital assistant) and so on.
  • each of the above units or structures can be implemented as independent entities, or can be combined arbitrarily, and implemented as the same or several entities.
  • each of the above units or structures please refer to the previous method embodiments. No longer.

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Abstract

公开一种驱动电路、显示面板以及显示装置，所述驱动电路包括多个级联的驱动单元，其中第一级驱动单元包括：正反向扫描控制模块、节点信号控制模块、输出控制模块、第一稳压模块、第一下拉模块、第二下拉模块以及漏电控制模块，所述漏电控制模块用于维持正反向扫描控制模块的输出信号的电平。

Description

驱动电路、显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别是涉及一种驱动电路、显示面板及显示装置。
 背景技术
目前，液晶显示装置作为电子设备的显示部件已经广泛的应用于各种电子产品中，而阵列基板行驱动（Gate Driver On Array，GOA）电路是液晶显示装置中的一个重要组成部分。其中，GOA驱动是利用现有薄膜晶体管液晶显示器阵列（Array）制程将行扫描驱动信号电路制作在阵列（Array）基板上，实现对行（Gate）逐行扫描的驱动方式的一项技术。
GOA驱动电路分为NMOS电路，PMOS电路以及CMOS电路。NMOS电路相比于CMOS电路由于省去PP（P掺杂）这一层光罩及工序，对于提高良率以及降低成本都大有裨益，所以开发稳定的NMOS电路具有现实的产业需求。
NMOSTFT载流子为电子，迁移率较高，器件相对与PMOS（载流子为空穴）较容易损伤，表现在面板上就是产品的高温信赖性不足，当前ITP的面板通常需要在一帧内插入若干个触控期（TP Term），用于实现触摸功能，但是NMOS GOA通过Q点的电容维持级传所需要的高电位，但是薄膜晶体管（TFT）并不是理想器件，即使在关态的情况下，依然会存在一定的漏电流；触控期（TP Term）持续时间较长，触摸面板(TP)的暂停级需要维持高电位的时间就会很长，因此降低了GOA的级传稳定性。容易出现GOA驱动失效，出现分屏现象，尤其是内嵌式触控面板（In-Cell Touch Panel,ITP），在TP暂停级更容易出现分屏现象。
 技术问题
本申请实施例提供一种驱动电路、显示面板及显示装置，以提高驱动电路的稳定性。
 技术解决方案
第一方面，本申请提供一种驱动电路，其中的驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
正反向扫描控制模块，用于根据正向扫描控制信号控制所述驱动电路进行正向扫描或根据反向扫描控制信号控制所述驱动电路进行反向扫描；
节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，驱动电路输出的栅极驱动信号的电平小于预设电平,所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元；
输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号；其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
第一稳压模块，与所述正反向扫描控制模块和输出控制模块连接，用于维持正反向扫描控制模块的输出信号的电平；
第一下拉模块，用于下拉第二节点的电平；
第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及第一级驱动单元输出端处的电压；
漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
在本申请的驱动电路中，所述漏电控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
所述第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极接入恒压高电位信号，所述第一薄膜晶体管的漏极与第二薄膜晶体管的漏极和第三薄膜晶体管的漏极连接；所述第二薄膜晶体管的栅极接入恒压低电位信号，所述第二薄膜晶体管的源极与第一节点连接，所述第三薄膜晶体管的栅极与第二节点连接，所述第三薄膜晶体管的接入恒压低电位信号。
在本申请的驱动电路中，所述第一级驱动单元还包括第三稳压模块，用于维持第三节点的电平，所述第三稳压模块包括第一电容，所述第一电容一端与所述第三节点连接，另一端与第一级栅极驱动信号连接。
在本申请的驱动电路中，所述正向扫描控制模块包括第四薄膜晶体管、第五薄膜晶体管；
所述第四薄膜晶体管的源极接入所述正向扫描控制信号，所述第四薄膜晶体管的栅极连接第四级驱动单元的栅极驱动信号；所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极、所述第一下拉模块以及所述第一节点连接；
所述第五薄膜晶体管的源极接入所述反向扫描控制信号，第五薄膜晶体管的栅极接入第五级驱动单元的栅极驱动信号，所述第四级驱动单元为第三级驱动单元的下一级驱动单元，所述第二级驱动单元为第一级驱动单元的上一级驱动单元。
在本申请的驱动电路中，所述节点信号控制模块包括第六薄膜晶体管、第七薄膜晶体管以及第十一薄膜晶体管；
所述第六薄膜晶体管的栅极与所述第四薄膜晶体管的源极连接，所述第六薄膜晶体管的源极接入第二级时钟信号，所述第六薄膜晶体管的漏极与第七薄膜晶体管的漏极以及第十一薄膜晶体管的栅极连接；第七薄膜晶体管的栅极与所述第五薄膜晶体管的源极连接，所述第七薄膜晶体管的源极接入第三级时钟信号；第十一薄膜晶体管的源极接入恒压高电位信号，第十一薄膜晶体管的漏极与第二节点连接。
在本申请的驱动电路中，所述第一下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极与所述第五薄膜晶体管的漏极连接，第九薄膜晶体管的源极接入所述恒压低电位信号，第九薄膜晶体管的漏极与所述第二节点连接。
在本申请的驱动电路中，所述第一稳压模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极接入恒压高电位信号，所述第十薄膜晶体管的源极与所述第一节点连接。
在本申请的驱动电路中，所述输出控制模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极与所述第十薄膜晶体管的漏极连接，所述第十二薄膜晶体管的源极接入第一级时钟信号。
一种显示面板，包括所述的驱动电路，所述驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制驱动电路进行正向扫描或反向扫描；
节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述驱动电路输出的栅极驱动信号的电平小于预设电平, 所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元。
输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
第一稳压模块，与所述正反向扫描控制模块和输出控制连接，用于维持正反向扫描控制模块的输出信号的电平；
第一下拉模块，用于下拉第二节点的电平；
第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及输出端处的电压；
漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
在本申请的显示面板中，所述漏电控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
所述第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极接入恒压高电位信号，所述第一薄膜晶体管的漏极与第二薄膜晶体管的漏极和第三薄膜晶体管的漏极连接；所述第二薄膜晶体管的栅极接入恒压低电位信号，所述第二薄膜晶体管的源极与第一节点连接，所述第三薄膜晶体管的栅极与第二节点连接，所述第三薄膜晶体管的接入恒压低电位信号。
在本申请的显示面板中，所述第一级驱动单元还包括第三稳压模块，用于维持第三节点的电平，所述第三稳压模块包括第一电容，所述第一电容一端与所述第三节点连接，另一端与第一级栅极驱动信号连接。
在本申请的显示面板中，所述正向扫描控制模块包括第四薄膜晶体管、第五薄膜晶体管；
所述第四薄膜晶体管的源极接入所述正向扫描控制信号，所述第四薄膜晶体管的栅极连接第四级驱动单元的栅极驱动信号；所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极、所述第一下拉模块以及所述第一节点连接；
所述第五薄膜晶体管的源极接入所述反向扫描控制信号，第五薄膜晶体管的栅极接入第五级驱动单元的栅极驱动信号，所述第四级驱动单元为第三级驱动单元的下一级驱动单元，所述第二级驱动单元为第一级驱动单元的上一级驱动单元。
在本申请的显示面板中，所述节点信号控制模块包括第六薄膜晶体管、第七薄膜晶体管以及第十一薄膜晶体管；
所述第六薄膜晶体管的栅极与所述第四薄膜晶体管的源极连接，所述第六薄膜晶体管的源极接入第二级时钟信号，所述第六薄膜晶体管的漏极与第七薄膜晶体管的漏极以及第十一薄膜晶体管的栅极连接；第七薄膜晶体管的栅极与所述第五薄膜晶体管的源极连接，所述第七薄膜晶体管的源极接入第三级时钟信号；第十一薄膜晶体管的源极接入恒压高电位信号，第十一薄膜晶体管的漏极与第二节点连接。
在本申请的显示面板中，所述第一下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极与所述第五薄膜晶体管的漏极连接，第九薄膜晶体管的源极接入所述恒压低电位信号，第九薄膜晶体管的漏极与所述第二节点连接。
在本申请的显示面板中，所述第一稳压模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极接入恒压高电位信号，所述第十薄膜晶体管的源极与所述第一节点连接。
在本申请的显示面板中，所述输出控制模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极与所述第十薄膜晶体管的漏极连接，所述第十二薄膜晶体管的源极接入第一级时钟信号。
一种显示装置，所述显示面板中包括驱动电路，所述驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制驱动电路进行正向扫描或反向扫描；
节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述驱动电路输出的栅极驱动信号的电平小于预设电平, 所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元。
输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
第一稳压模块，与所述正反向扫描控制模块和输出控制连接，用于维持正反向扫描控制模块的输出信号的电平；
第一下拉模块，用于下拉第二节点的电平；
第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及输出端处的电压；
漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
在本申请的显示装置中，所述漏电控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
所述第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极接入恒压高电位信号，所述第一薄膜晶体管的漏极与第二薄膜晶体管的漏极和第三薄膜晶体管的漏极连接；所述第二薄膜晶体管的栅极接入恒压低电平点位，所述第二薄膜晶体管的源极与第一节点连接，所述第三薄膜晶体管的栅极与第二节点连接，所述第三薄膜晶体管的栅极源极接入恒压低电位信号。
在本申请的显示装置中，所述第一级驱动单元还包括第三稳压模块，用于维持第三节点的电平，所述第三稳压模块包括第一电容，所述第一电容一端与所述第三节点连接，另一端与第一级栅极驱动信号连接。
在本申请的显示装置中，所述正向扫描控制模块包括第四薄膜晶体管、第五薄膜晶体管；
所述第四薄膜晶体管的源极接入所述正向扫描控制信号，所述第四薄膜晶体管的栅极连接第四级驱动单元的栅极驱动信号；所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极、所述第一下拉模块以及所述第一节点连接；
所述第五薄膜晶体管的源极接入所述反向扫描控制信号，第五薄膜晶体管的栅极接入第五级驱动单元的栅极驱动信号，所述第四级驱动单元为第三级驱动单元的下一级驱动单元，所述第二级驱动单元为第一级驱动单元的上一级驱动单元。
 有益效果
本申请的驱动电路、显示面板及显示装置，相比现有的驱动电路增加了漏电控制模块，信号在各级驱动单元级传期间，由于第一节点保持高电平，此时第一节点将高电平信号输出至所述漏电控制模块，由于所述漏电控制模块的电压也处于高电平状态，因此第一节点不会产生漏电电流，因此可以提高第一节点稳定性，增加了驱动电路的稳定性。
 附图说明
图1为本申请实施例中第n级GOA驱动单元的模块连接关系示意图。
图2为本申请一实施例提供的GOA驱动的结构示意图。
图3为本申请实施例中GOA驱动电路的第n级GOA单元的结构示意图。
图4为本申请实施例中GOA驱动电路的第n+2级GOA单元的结构示意图。
图5为本申请实施例中4CK架构的显示面板的GOA驱动电路的时序图。
图6为本申请又一实施例提供的GOA驱动电路的结构示意图。
 本发明的实施方式
本申请提供一种驱动电路、显示面板及显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供的驱动电路以GOA驱动电路为例。
本申请实施例提供一种GOA驱动电路，所述GOA驱动电路包括多个级联的GOA驱动单元，具体地，请参阅图1，图1为本申请的驱动单元中各个模块连接关系示意图，多个级联的GOA驱动单元中每一级的GOA驱动单元均包括：漏电控制模块100、正反向扫描控制模块200、节点信号控制模块300、输出控制模块400、第一稳压模块500、第一下拉模块600、第二下拉模块700。
其中，正反向扫描控制模块200，用于根据正向扫描控制信号控制所述驱动电路进行正向扫描或根据反向扫描控制信号控制所述驱动电路进行反向扫描。
节点信号控制模块300，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述栅极驱动信号的电平小于预设电平,即输出低电平的栅极驱动信号，所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元。
输出控制模块400，位于第一节点Q和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点。
第一稳压模块500，与所述正反向扫描控制模块200和输出控制模块400的连接，用于维持正反向扫描控制模块200的输出信号的电平。
第一下拉模块600，用于下拉第二节点P的电平。
第二下拉模块700，用于根据所述节点信号控制模块300提供的控制信号下拉所述第一节点Q处的电压以及第一级驱动单元输出端处的电压。
漏电控制模块100，与所述正反向扫描控制模块200、所述第一下拉模块600、第二下拉模块700连接，用于维持正反向扫描控制模块的输出信号的电平。
所述漏电控制模块100，与所述正反向扫描控制模300块、所述第一下拉模块600、第二下拉模块700连接，用于维持正反向扫描控制模块200的输出信号的电平。
本申请的驱动电路、显示面板及显示装置，相比现有技术增加了漏电控制模块，信号在各级驱动单元级传期间或启用触摸面板期间，由于第一节点保持高电平，此时第一节点将高电平信号输出至所述漏电控制模块，由于所述漏电控制模块的电压也处于高电平状态，因此第一节点不会产生漏电电流，因此可以提高第一节点稳定性，增加了驱动电路的稳定性。
由于本申请实施例中的GOA驱动电路中，多个级联的GOA驱动单元中每一级的GOA驱动单元结构都是相同的，例如，在申请的GOA电路中包括有m个级联的GOA驱动单元，即第一级驱动单元、第二级驱动单元……第n-1级驱动单元、第n级驱动单元、第n+1级驱动单元……第m级驱动单元，其中，m≥n≥1，本申请实施例中的GOA驱动电路包括以上m个GOA驱动单元组成。
例如，第n个GOA电路单元的输出端连接下一(第n+1)个GOA电路单元的输入端，第n个GOA电路单元的输入端连接上一(第n-1)个GOA电路的输出端，其中，n为不小于1的自然数。如图2所示，以第n级驱动单元为例介绍驱动单元的结构为例做介绍，所述漏电控制模块100包括第一薄膜晶体管NT1、第二薄膜晶体管NT2以及第三薄膜晶体管NT3。所述第一薄膜晶体管NT1的栅极与第一节点Q连接，源极接入恒压高电位信号，漏极与第二薄膜晶体管NT2的漏极和第三薄膜晶体管NT3的漏极连接；所述第二薄膜晶体管NT2的栅极接入恒压低电位信号，源极与第一节点Q连接，所述第三薄膜晶体管NT3的栅极与第二节点P连接，源极接入恒压低电位信号VGL。
正反向扫描控制模块200用于根据正向扫描控制信号U2D或反向扫描控制信号D2U控制GOA驱动进行正向扫描或反向扫描。所述正向扫描控制模块200包括第四薄膜晶体NT4、第五薄膜晶体管NT5；所述第四薄膜晶体管NT4的源极接入所述正向扫描控制信号，栅极连接第n-2级GOA驱动单元的栅极驱动信号；漏极分别与所述第五薄膜晶体管NT5的漏极、所述第二下拉模块600以及所述第四节点连接；所述第五薄膜晶体管NT5的源极接入所述反向扫描控制信号，栅极接入第n+2级GOA驱动单元的栅极驱动信号。
节点信号控制模块300用于根据第n+1级时钟信号CK(n+1)和第n-1级时钟信号CK(n-1)控制本级GOA单元，即第n级GOA单元，在异常工作阶段输出低电位的栅极驱动信号，其中，所述异常工作阶段可以例如为突然断电时的工作阶段或异常黑屏的工作阶段。
所述节点信号控制模块300包括第六薄膜晶体管NT6、第七薄膜晶体管NT7以及第十一薄膜晶体管NT11；所述第六薄膜晶体管NT6的栅极与所述第三薄膜晶体管NT3的源极连接，源极接入第n+1级时钟信号，漏极与第七薄膜晶体管NT7的漏极以及第十一薄膜晶体管NT11的栅极连接；第七薄膜晶体管NT7的栅极与所述第五薄膜晶体管NT5的源极连接，源极接入第n-1级时钟信号；第十一薄膜晶体管NT11的源极接入恒压高电位信号，漏极与第二节点P连接。
输出控制模块400用于根据本级（第n级）时钟信号CK(n)控制本级（第n级）栅极驱动信号的输出。所述输出控制模块400包括第十二薄膜晶体NT12，所述第十二薄膜晶体管NT12的栅极与所述第十薄膜晶体管NT10的漏极连接，源极接入本级（第n级）时钟信号。
第一稳压模块500用于维持第一节点Q的电平。所述第一稳压模块500包括第九薄膜晶体管NT9，所述第九薄膜晶体管NT9的栅极接入恒压高电位信号，源极与所述第一节点Q连接。第一下拉模块600用于下拉第二节点P的电平。所述第一下拉模块600包括第九薄膜晶体管NT9，所述第九薄膜晶体管NT9的栅极与所述第五薄膜晶体管NT5的漏极连接，源极接入所述恒压低电位信号VGL，漏极与所述第二节点P连接
第二下拉模块700用于下拉本级（第n级）栅极驱动信号G(n)的电平。所述第二下拉模块700包括第八薄膜晶体管NT8，第八薄膜晶体管NT8的栅极与第二节点P连接与第十一晶体管NT11的漏极连接，源极接入恒压低电位信号VGL，漏极连接本级（第n级）栅极驱动信号G(n)连接。
所述GOA驱动单元还可包括第三下拉模块800以及上拉模块900、第二电容C2。
所述第三下拉模块800包括第十五薄膜晶体管NT15，第十五薄膜晶体管NT15的栅极与第二全局信号GAS2连接，源极与恒压低电位信号VGL连接，漏极与本级栅极驱动信号G(n)连接，所述第三下拉模块800用于根据第二全局信号GAS2在显示面板处于第二工作状态时下拉本级（第n级）栅极驱动信号G(n)的电平。
所述上拉模块900包括第十三薄膜晶体管NT13和第十四薄膜晶体管NT14，第十三薄膜晶体管NT13的漏极和栅极均与第一全局信号Gas1连接，源极与本级栅极驱动信号G(n)连接；第十四薄膜晶体管NT14的栅极与第一全局信号Gas1连接，源极与恒压低电位信号VGL连接，漏极与第十一薄膜晶体管T11的栅极连接。所述上拉模块900用于根据第一全局信号GAS1在显示面板处于第一工作状态时控制本级（第n级）GOA单元输出高电平的栅极驱动信号。第一工作状态为黑屏触控工作状态或者异常断电状态。可以理解的是，当显示面板处于第一工作状态时，第一全局信号GAS1为高电平，所有GOA单元都输出高电平的栅极驱动信号。第二工作状态为显示触控工作期间，此时第二全局信号GAS2为高电平。
在一些实施例中，第二电容C2的一端与第二节点P连接，另一端接入恒压低电位信号VGL。
当显示面板处于正向扫描状态时，U2D为高电平，D2U为低电平，此时GOA驱动则由上向下逐行扫描，反之，当显示面板处于反向扫描状态时，U2D为低电平，D2U为高电平，此时GOA驱动则由下向上逐行扫描。
在显示面板的两侧分别设置左侧GOA电路和右侧GOA电路，在一实施方式中，左侧GOA电路驱动奇数行的扫描线，右侧GOA电路驱动偶数行的扫描线。当显示面板为4CK架构时，GOA电路以2个基本单元为最小重复单元进行循环。如图2和图3所示，第n级GOA单元和第n+2级GOA单元可以共同构成一个GOA重复单元。结合图5，图5所示为4CK架构的显示面板对应的GOA电路的时序图，GOA电路中共有4个时钟信号CK：第1时钟信号CK1至第4条时钟信号CK4，当第n级GOA单元的第n级时钟信号为第1时钟信号CK1时，第n级GOA单元的第n+1级时钟信号为第2时钟信号CK2，第n级GOA单元的第n-1级时钟信号为第4时钟信号CK4，当第n+2级GOA单元的第n级时钟信号为第3时钟信号CK3时，第n+2级GOA单元的第n+1级时钟信号为第4时钟信号，第n+2级GOA单元的第n-1级时钟信号为第2时钟信号。请结合图5和图3所示，如果第n级GOA单元的节点信号控制模块300对应接入的是第2和第4时钟信号，输出控制模块400接入的是第1时钟信号，那么第n+1级GOA单元的节点信号控制模块接入的就是第1条和第3条时钟信号，第n+1级GOA单元的输出控制模块400接入的是第2时钟信号。如图4所示，如果第n级GOA单元的节点信号控制模块300对应接入的是第2和第4时钟信号，输出控制模块400接入的是第3时钟信号，那么第n+1级GOA单元的节点信号控制模块300接入的就是第2条和第4条时钟信号，第n+1级GOA单元的输出控制模块400接入的是第4时钟信号。
其中，4个CK信号的占空比可以是50%或25%等，图5采用的占空比为25%。当然显示面板也可使用8CK架构，GOA电路以4个基本单元为最小重复单元进行循环。
此外，第一全局信号GAS1和第二全局信号GAS2在显示面板正常工作时都为低电平，第二全局信号GAS2在显示期间T1转换为触控期间T2由低电平变为高电平。
返回图2，在正常情况下VGL与D2U的电压相同，在重载画面下(比如像素点反转等画面)，显示区域通过NT10与VGL信号相连，VGL受显示区域的Couple的影响最大。VGL相对于D2U信号，有更大的波动，所以虽然VGL与D2U电压相同，但是存在VGL受耦合（Couple）影响瞬间电压高于D2U，那么对于G(N+2)信号不被拉低，由于下一级GOA单元的第三薄膜晶体管NT3的栅极接入G(N+2)，导致第三薄膜晶体管NT3存在被瞬间打开的风险。如果第三薄膜晶体管NT3打开，且此时Q点为高电位，则Q点电位存在被释放(拉低)的风险，因此无法继续维持高电位，无法实现正常的级传功能，引起GOA电路的失效。
相比于现有技术，本申请实施例通过增加第一稳压单元100增加了第一薄膜晶体管NT1和第二薄膜晶体管NT2，将原来Q点经第三薄膜晶体管NT3至VGL的漏电路修改为VGH经第一薄膜晶体管NT1、第三薄膜晶体管NT3至VGL漏电路径，降低Q点经第二薄膜晶体管NT2、第三薄膜晶体管NT3至VGL的漏电路径；在级传和触摸屏（TP）期间，Q点为高电位，此时第一薄膜晶体管NT1开启，其将VGH输出至第一薄膜晶体管NT1、第二薄膜晶体管NT2与第三薄膜晶体管NT3连接点，此时第二薄膜晶体管NT2的源极与漏级电压均为VGH，所以不会出现Q点不会再通过第三薄膜晶体管NT3向VGL漏电，从而保证Q点电压稳定性；增加第一稳压单元100可以减少Q点漏电的路径，提高GOA驱动电路级传的稳定性，且相对于原电路结构，不增加信号线数目，不改变时序。
本申请还提供又一个实施例，请参阅图6，图6为本申请又一实施例的GOA电路图，本实施例在上一实施例的基础上增加了第三稳压模110，本实施例其余模块的与上一实施例的结构和功能相同，在此不再赘述。第三稳压模110用于维持第三节点Qa的电平，所述第三稳压模块110包括第一电容C1，所述第一电容C1一端与所述第三节点Qa连接，另一端与本级（第n级）栅极驱动信号连接,有利于Qa点电位提升，有利于本级（第n级）栅极驱动信号G(n)输出。
为了更好实施本申请实施例中的GOA驱动电路，在GOA驱动电路的基础之上，本申请实施例还提供了一种显示面板，该GOA驱动电路集成于显示面板中，该GOA驱动电路用于驱动所述显示面板，所述GOA驱动电路包括多个级联的驱动单元，多个级联的GOA驱动单元中每一级的GOA驱动单元均包括：漏电控制模块100、正反向扫描控制模块200、节点信号控制模块300、输出控制模块400、第一稳压模块500、第一下拉模块600、第二下拉模块700。
其中，正反向扫描控制模块200，用于根据正向扫描控制信号控制所述驱动电路进行正向扫描或根据反向扫描控制信号控制所述驱动电路进行反向扫描。
节点信号控制模块300，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述栅极驱动信号的电平小于预设电平,即输出低电平的栅极驱动信号，所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元。
输出控制模块400，位于第一节点Q和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点。
第一稳压模块500，与所述正反向扫描控制模块和输出控制模块连接，用于维持正反向扫描控制模块的输出信号的电平。
第一下拉模块600，用于下拉第二节点的电平。
第二下拉模块700，用于根据所述节点信号控制模块300提供的控制信号下拉所述第一节点Q处的电压以及第一级驱动单元输出端处的电压。
漏电控制模块100，与所述正反向扫描控制模块200、所述第一下拉模块600、第二下拉模块700连接，用于维持正反向扫描控制模块的输出信号的电平。
所述漏电控制模块100，与所述正反向扫描控制模300块、所述第一下拉模块600、第二下拉模块700连接，用于维持正反向扫描控制模块200的输出信号的电平。
由于本申请实施例提供的显示面板包含了所述的GOA电路，而GOA驱动电路增加了漏电控制模块，信号在各级驱动单元级传期间以及使用触摸面板期间，由于Q点保持高电平，此时Q点将高电平信号输出至所述漏电控制模块，由于所述漏电控制模块的电压也处于高电平状态，因此Q点不会产生漏电电流，因此可以提高Q点稳定性，增加了驱动电路的级传稳定性，进而提高显示面板显示的稳定性。
本申请实施例还提供了一种显示装置，所述显示面板集成于所述的显示装置中，所述显示装置通过所述显示面板进行显示，而所述显示面板包含了所述的GOA电路，所述驱动电路包括：
所述GOA驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制驱动电路进行正向扫描或反向扫描；
节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述驱动电路输出的栅极驱动信号的电平小于预设电平, 所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元。
输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
第一稳压模块，与所述正反向扫描控制模块和输出控制连接，用于维持正反向扫描控制模块的输出信号的电平；
第一下拉模块，用于下拉第二节点的电平；
第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及输出端处的电压；
漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
本申请实施例通过在显示装置中的GOA驱动电路增加了漏电控制模块，信号在各级驱动单元级传期间以及使用触摸面板期间，由于Q点保持高电平，此时Q点将高电平信号输出至所述漏电控制模块，由于所述漏电控制模块的电压也处于高电平状态，因此Q点不会产生漏电电流，因此可以提高Q点稳定性，增加了驱动电路的级传稳定性，进而提高显示面板显示的稳定性，从而提高了该显示装置显示性能的稳定性。
需要说明的是，所述显示装置可以包括但不限于具有上述显示面板的手机、平板电脑、笔记本电脑、电视机、MID(Mobile Internet Devices，移动互联网设备)、PDA(Personal Digital Assistant，个人数字助理)等等。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文针对其他实施例的详细描述，此处不再赘述。
具体实施时，以上各个单元或结构可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，以上各个单元或结构的具体实施可参见前面的方法实施例，在此不再赘述。
以上对本申请实施例所提供的一种GOA驱动电路、显示面板以及显示装置进行了详细介绍，本申请实施例中应用了具体个例对本申请实施例的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本申请实施例的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请实施例的限制。

Claims (20)

  1. 一种驱动电路，其中，所述驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
    正反向扫描控制模块，用于根据正向扫描控制信号控制所述驱动电路进行正向扫描或根据反向扫描控制信号控制所述驱动电路进行反向扫描；
    节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，驱动电路输出的栅极驱动信号的电平小于预设电平,所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元；
    输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号；其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
    第一稳压模块，与所述正反向扫描控制模块和输出控制模块连接，用于维持正反向扫描控制模块的输出信号的电平；
    第一下拉模块，用于下拉第二节点的电平；
    第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及第一级驱动单元输出端处的电压；
    漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
  2. 根据权利要求1所述的驱动电路，其中，所述漏电控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
    所述第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极接入恒压高电位信号，所述第一薄膜晶体管的漏极与第二薄膜晶体管的漏极和第三薄膜晶体管的漏极连接；所述第二薄膜晶体管的栅极接入恒压低电位信号，所述第二薄膜晶体管的源极与第一节点连接，所述第三薄膜晶体管的栅极与第二节点连接，所述第三薄膜晶体管的接入恒压低电位信号。
  3. 根据权利要求1所述的驱动电路，其中，所述第一级驱动单元还包括第三稳压模块，用于维持第三节点的电平，所述第三稳压模块包括第一电容，所述第一电容一端与所述第三节点连接，另一端与第一级栅极驱动信号连接。
  4. 根据权利要求1所述的驱动电路，其中，所述正向扫描控制模块包括第四薄膜晶体管、第五薄膜晶体管；
    所述第四薄膜晶体管的源极接入所述正向扫描控制信号，所述第四薄膜晶体管的栅极连接第四级驱动单元的栅极驱动信号；所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极、所述第一下拉模块以及所述第一节点连接；
    所述第五薄膜晶体管的源极接入所述反向扫描控制信号，第五薄膜晶体管的栅极接入第五级驱动单元的栅极驱动信号，所述第四级驱动单元为第三级驱动单元的下一级驱动单元，所述第二级驱动单元为第一级驱动单元的上一级驱动单元。
  5. 根据权利要求4所述的驱动电路，其中，所述节点信号控制模块包括第六薄膜晶体管、第七薄膜晶体管以及第十一薄膜晶体管；
    所述第六薄膜晶体管的栅极与所述第四薄膜晶体管的源极连接，所述第六薄膜晶体管的源极接入第二级时钟信号，所述第六薄膜晶体管的漏极与第七薄膜晶体管的漏极以及第十一薄膜晶体管的栅极连接；第七薄膜晶体管的栅极与所述第五薄膜晶体管的源极连接，所述第七薄膜晶体管的源极接入第三级时钟信号；第十一薄膜晶体管的源极接入恒压高电位信号，第十一薄膜晶体管的漏极与第二节点连接。
  6. 根据权利要求5所述的驱动电路，其中，所述第一下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极与所述第五薄膜晶体管的漏极连接，第九薄膜晶体管的源极接入所述恒压低电位信号，第九薄膜晶体管的漏极与所述第二节点连接。
  7. 根据权利要求1-6任一权利要求所述的驱动电路，其中，所述第一稳压模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极接入恒压高电位信号，所述第十薄膜晶体管的源极与所述第一节点连接。
  8. 根据权利要求7所述的驱动电路，其中，所述输出控制模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极与所述第十薄膜晶体管的漏极连接，所述第十二薄膜晶体管的源极接入第一级时钟信号。
  9. 一种显示面板，其中，包括如权利要求1所述的驱动电路，所述驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
    正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制驱动电路进行正向扫描或反向扫描；
    节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述驱动电路输出的栅极驱动信号的电平小于预设电平, 所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元。
    输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
    第一稳压模块，与所述正反向扫描控制模块和输出控制连接，用于维持正反向扫描控制模块的输出信号的电平；
    第一下拉模块，用于下拉第二节点的电平；
    第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及输出端处的电压；
    漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
  10. 根据权利要求9所述的显示面板，其中，所述漏电控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
    所述第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极接入恒压高电位信号，所述第一薄膜晶体管的漏极与第二薄膜晶体管的漏极和第三薄膜晶体管的漏极连接；所述第二薄膜晶体管的栅极接入恒压低电位信号，所述第二薄膜晶体管的源极与第一节点连接，所述第三薄膜晶体管的栅极与第二节点连接，所述第三薄膜晶体管的接入恒压低电位信号。
  11. 根据权利要求9所述的显示面板，其中，所述第一级驱动单元还包括第三稳压模块，用于维持第三节点的电平，所述第三稳压模块包括第一电容，所述第一电容一端与所述第三节点连接，另一端与第一级栅极驱动信号连接。
  12. 根据权利要求9所述的显示面板，其中，所述正向扫描控制模块包括第四薄膜晶体管、第五薄膜晶体管；
    所述第四薄膜晶体管的源极接入所述正向扫描控制信号，所述第四薄膜晶体管的栅极连接第四级驱动单元的栅极驱动信号；所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极、所述第一下拉模块以及所述第一节点连接；
    所述第五薄膜晶体管的源极接入所述反向扫描控制信号，第五薄膜晶体管的栅极接入第五级驱动单元的栅极驱动信号，所述第四级驱动单元为第三级驱动单元的下一级驱动单元，所述第二级驱动单元为第一级驱动单元的上一级驱动单元。
  13. 根据权利要求12所述的显示面板，其中，所述节点信号控制模块包括第六薄膜晶体管、第七薄膜晶体管以及第十一薄膜晶体管；
    所述第六薄膜晶体管的栅极与所述第四薄膜晶体管的源极连接，所述第六薄膜晶体管的源极接入第二级时钟信号，所述第六薄膜晶体管的漏极与第七薄膜晶体管的漏极以及第十一薄膜晶体管的栅极连接；第七薄膜晶体管的栅极与所述第五薄膜晶体管的源极连接，所述第七薄膜晶体管的源极接入第三级时钟信号；第十一薄膜晶体管的源极接入恒压高电位信号，第十一薄膜晶体管的漏极与第二节点连接。
  14. 根据权利要求13所述的显示面板，其中，所述第一下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极与所述第五薄膜晶体管的漏极连接，第九薄膜晶体管的源极接入所述恒压低电位信号，第九薄膜晶体管的漏极与所述第二节点连接。
  15. 根据权利要求9所述的显示面板，其中，所述第一稳压模块包括第十薄膜晶体管，所述第十薄膜晶体管的栅极接入恒压高电位信号，所述第十薄膜晶体管的源极与所述第一节点连接。
  16. 根据权利要求15所述的显示面板，其中，所述输出控制模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的栅极与所述第十薄膜晶体管的漏极连接，所述第十二薄膜晶体管的源极接入第一级时钟信号。
  17. 一种显示装置，其中，所述显示面板中包括驱动电路，所述驱动电路包括多个级联的驱动单元，第一级驱动单元包括：
    正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制驱动电路进行正向扫描或反向扫描；
    节点信号控制模块，用于根据第二级驱动单元的时钟信号和第三级驱动单元输出的栅极驱动信号,控制所述驱动电路在异常工作阶段输出栅极驱动信号；其中，所述驱动电路输出的栅极驱动信号的电平小于预设电平, 所述第二级驱动单元为第一级驱动单元的上一级驱动单元，所述第三级驱动单元为第一级驱动单元的下一级驱动单元；
    输出控制模块，位于第一节点和第一级驱动单元的输出端之间，用于在驱动电路进行正向扫描或反向扫描期间，控制输出第一级栅极驱动信号，其中，所述第一节点为所述正反向扫描控制模块输出端的节点；
    第一稳压模块，与所述正反向扫描控制模块和输出控制连接，用于维持正反向扫描控制模块的输出信号的电平；
    第一下拉模块，用于下拉第二节点的电平；
    第二下拉模块，用于根据所述节点信号控制模块提供的控制信号下拉所述第一节点处的电压以及输出端处的电压；
    漏电控制模块，与所述正反向扫描控制模块、所述第一下拉模块、第二下拉模块连接，用于维持正反向扫描控制模块的输出信号的电平。
  18. 根据权利要求17所述的显示装置，其中，所述漏电控制模块包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
    所述第一薄膜晶体管的栅极与所述第一节点连接，所述第一薄膜晶体管的源极接入恒压高电位信号，所述第一薄膜晶体管的漏极与第二薄膜晶体管的漏极和第三薄膜晶体管的漏极连接；所述第二薄膜晶体管的栅极接入恒压低电平点位，所述第二薄膜晶体管的源极与第一节点连接，所述第三薄膜晶体管的栅极与第二节点连接，所述第三薄膜晶体管的栅极源极接入恒压低电位信号。
  19. 根据权利要求17所述的显示装置，其中，所述第一级驱动单元还包括第三稳压模块，用于维持第三节点的电平，所述第三稳压模块包括第一电容，所述第一电容一端与所述第三节点连接，另一端与第一级栅极驱动信号连接。
  20. 根据权利要求17所述的显示装置，其中，所述正向扫描控制模块包括第四薄膜晶体管、第五薄膜晶体管；
    所述第四薄膜晶体管的源极接入所述正向扫描控制信号，所述第四薄膜晶体管的栅极连接第四级驱动单元的栅极驱动信号；所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极、所述第一下拉模块以及所述第一节点连接；
    所述第五薄膜晶体管的源极接入所述反向扫描控制信号，第五薄膜晶体管的栅极接入第五级驱动单元的栅极驱动信号，所述第四级驱动单元为第三级驱动单元的下一级驱动单元，所述第二级驱动单元为第一级驱动单元的上一级驱动单元。
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