WO2019085268A1 - 一种goa驱动电路 - Google Patents

一种goa驱动电路 Download PDF

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Publication number
WO2019085268A1
WO2019085268A1 PCT/CN2018/071663 CN2018071663W WO2019085268A1 WO 2019085268 A1 WO2019085268 A1 WO 2019085268A1 CN 2018071663 W CN2018071663 W CN 2018071663W WO 2019085268 A1 WO2019085268 A1 WO 2019085268A1
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Prior art keywords
thin film
film transistor
pull
control module
signal
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PCT/CN2018/071663
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English (en)
French (fr)
Inventor
戴荣磊
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武汉华星光电技术有限公司
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Priority to US15/969,246 priority Critical patent/US10431178B2/en
Publication of WO2019085268A1 publication Critical patent/WO2019085268A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of electronic circuits, and in particular to a GOA driving circuit.
  • Thin film transistor liquid crystal display has become the mainstream display on the market.
  • the basic principle is that the liquid crystal in the display is deflected by the voltage, changing the direction of light propagation and making the display display. different color.
  • the Gate Driver On Array (GOA) circuit is a technology for integrating a gate driving circuit on an array substrate of a liquid crystal display panel to realize progressive scanning of the gate lines.
  • the liquid crystal panel will have a residual level due to the pixel capacitance, resulting in image sticking.
  • the invention provides a gate driving circuit to avoid the phenomenon that the liquid crystal screen generates image sticking in the case of power failure, thereby improving the viewing property.
  • a first aspect of the embodiments of the present invention provides a GOA driving circuit, including: a multi-level GOA driving unit; wherein, the nth-level GOA driving unit includes: a pull-up control module, a pull-up output module, a pull-down control module, and a pull-down output module, a first global control module, a reset module, and a second global control module;
  • the pull-up control module is configured to generate a first control signal when the power is off;
  • the pull-up output module is configured to stop outputting a clock signal to an output end of the n-th stage GOA driving unit under the action of the first control signal;
  • the pull-down control module is configured to generate a second control signal when the power is off;
  • the pull-down output module is configured to stop outputting a low-level signal to an output end of the n-th stage GOA driving unit under the action of the second control signal;
  • the first global control module is configured to output a high level signal to an output end of the nth stage GOA driving unit when the power is off;
  • the reset module is configured to stop outputting a reset signal to an output end of the pull-down control module when the power is off.
  • the second global control module is configured to stop outputting a low level signal to an output end of the nth stage GOA driving unit when the power is off.
  • the pull-up control module includes: a first thin film transistor, a second thin film transistor, a fifth thin film transistor, and a seventh thin film transistor;
  • the gate of the first thin film transistor is connected to an output signal of the n-2th stage GOA driving unit, the source is connected to the forward scanning signal, and the drain is electrically connected to the source of the seventh thin film transistor;
  • the gate of the second thin film transistor is connected to the output signal of the n+2th stage GOA driving unit, the source is connected to the reverse scan signal, and the drain is electrically connected to the source of the seventh thin film transistor;
  • the gate of the fifth thin film transistor The pole is connected to the output end of the pull-down control module, the source is connected to the low level signal, the drain is electrically connected to the source of the seventh thin film transistor;
  • the gate of the seventh thin film transistor is connected to the high level signal,
  • the drain is connected to the output end of the pull-up control module; wherein the pull-up control module is configured to generate a first control signal when the power is off, and the first control signal is a low level signal, thereby controlling The pull-up output module is turned off.
  • the pull-up output module includes: a tenth thin film transistor
  • the gate of the tenth thin film transistor is connected to the output end of the pull-up control module, the source is connected to the nth-level clock signal, and the drain is connected to the output end of the n-th stage GOA driving unit;
  • the pull-up output module is turned off by the low-level signal generated by the pull-up control module when the power is off, and does not output a low-level signal to the output end of the n-th stage GOA driving unit.
  • the pull-down control module includes: a third thin film transistor, a fourth thin film transistor, a sixth thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a twelfth thin film transistor;
  • the gate and the source of the third thin film transistor are connected to the n+1th clock signal, the drain is electrically connected to the source of the eighth thin film transistor, and the source and the drain of the fourth thin film transistor are connected.
  • the drain is electrically connected to the source of the ninth thin film transistor;
  • the gate of the sixth thin film transistor is electrically connected to the source of the seventh thin film transistor, and the source is connected to the low level signal a drain is connected to an output end of the pull-down control module;
  • a gate of the eighth thin film transistor is connected to a forward scan signal, and a drain is connected to an output end of the pull-down control module;
  • the gate is connected to the reverse scan signal, and the drain is connected to the output end of the pull-down control module;
  • the gate of the twelfth thin film transistor is connected to the first global control signal, and the source is connected to the low level signal, and the drain is The pole is connected to the output end of the pull-down control module; wherein the pull-down control module is configured to
  • the pull-down output module includes: an eleventh thin film transistor
  • the gate of the eleventh thin film transistor is connected to the output end of the pull-down control module, the source is connected to the low level signal, and the drain is connected to the output end of the nth stage GOA driving unit;
  • the pull-down output module is turned off by the low-level signal generated by the pull-down control module when the power is off, and thus does not output a low-level signal to the output end of the n-th stage GOA driving unit.
  • the first global control module includes: a fourteenth thin film transistor
  • the gate and the source of the fourteenth thin film transistor are connected to the first global control signal, and the drain drain is connected to the output end of the nth stage GOA driving unit; wherein the first global control module is When the power is off, it is used to output a high level signal to the output end of the nth stage GOA driving unit.
  • the reset module includes: a thirteenth thin film transistor
  • the gate and the source of the thirteenth thin film transistor are connected to the reset signal, and the drain is connected to the output end of the pull-down control module; wherein the reset module is used to control the power when the power is off
  • the output of the pull-down control module generates a low level signal.
  • the reset module includes: a fifteenth thin film transistor
  • the gate of the fifteenth thin film transistor is connected to the second global control signal, the source is connected to the low level signal, and the drain is connected to the output end of the nth stage GOA driving unit; wherein the second global The control module is configured to control the output end of the nth stage GOA driving unit to output a high level signal when the power is off.
  • the nth stage GOA driving unit further includes: a first capacitor and a second capacitor;
  • the first end of the first capacitor is electrically connected to the source of the seventh thin film transistor, and the second end is connected to the low level signal; the first end of the second capacitor is connected to the output of the pull-down control module End, the second end is connected to the low level signal; wherein, in the power off, the first capacitor is used to maintain the potential of the source of the seventh thin film transistor, and the second capacitor is used to maintain the pull down The potential at the output of the control module.
  • the gates of the first thin film transistors are all connected to the start signal; in the last-numbered first stage GOA driving In the cell and the penultimate stage driving unit, the gate of the second thin film transistor is connected to the start signal, wherein the start signal is a high level signal.
  • the GOA driving circuit in the technical solution of the embodiment of the present invention wherein the GOA driving units of each level include a pull-up control module, a pull-down control module, a pull-up output module, a pull-down output module, and a first global control module, and are powered off.
  • the pull-up control module When the pull-up control module generates a low-level signal, the pull-up output module is controlled to be turned off, so that the output of the pull-up output module does not affect the output end of the GOA driving unit; the pull-down control module generates a low-level signal, and the reset module generates a low level signal, controlling the pull-down output module to be turned off, so that the output of the pull-down output module does not affect the output end of the GOA driving unit; the first global control module and the second global control signal control the output of the GOA driving unit to be high
  • the image on the screen can be quickly cleared in the case of sudden power failure during the use of the liquid crystal screen, thereby avoiding the residual image of the previous display screen, which is beneficial to the user's visual experience.
  • FIG. 1 is a schematic diagram of functional modules of a GOA driving unit of the present invention
  • FIG. 2 is a circuit diagram of a GOA driving unit of the present invention
  • Figure 3 is a signal timing diagram of the GOA driving circuit of the present invention.
  • references to "an embodiment” herein mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the invention.
  • the appearances of the phrases in various places in the specification are not necessarily referring to the same embodiments, and are not exclusive or alternative embodiments that are mutually exclusive. Those skilled in the art will understand and implicitly understand that the embodiments described herein can be combined with other embodiments.
  • FIG. 1 is a schematic diagram of a functional module of a GOA driving unit according to an embodiment of the present invention.
  • the GOA driving unit in the embodiment of the present invention includes the following modules: a pull-up control module 101 and an upper The output module 102, the pull-down control module 103, the pull-down output module 104, the first global control module 105, the reset module 106, and the second global control module 107 are pulled.
  • the pull-up control module 101 is electrically connected to the pull-down control module 103 and the pull-up output module 102, and the pull-up output module 102 and the pull-down output module 104 and the first global control module 105.
  • the second global control module 107 is electrically connected, the pull-down control module 103 is electrically connected to the pull-down output module 104, the reset module 106, the pull-down output module 104 and the first global control module 105,
  • the second global control module 107 is electrically connected, and the first global control module 105 is electrically connected to the second global control module 107.
  • the pull-up control module is configured to generate a first control signal when the power is off; the pull-up output module is configured to stop the driving to the n-th stage GOA by the first control signal
  • the output terminal outputs a clock signal;
  • the pull-down control module is configured to generate a second control signal when the power is off;
  • the pull-down output module is configured to stop to the nth level by the second control signal
  • the output of the GOA driving unit outputs a low level signal;
  • the first global control module is configured to output a high level signal to an output end of the nth stage GOA driving unit when the power is off;
  • the output of the reset signal to the output of the pull-down control module is stopped when the power is turned off.
  • the second global control module is configured to stop outputting a low level signal to an output of the nth stage GOA driving unit when the power is off.
  • the GOA driving circuit in the technical solution of the embodiment of the present invention wherein the GOA driving units of each level include a pull-up control module, a pull-down control module, a pull-up output module, a pull-down output module, and a first global control module, and are powered off.
  • the pull-up control module When the pull-up control module generates a low-level signal, the pull-up output module is controlled to be turned off, so that the output of the pull-up output module does not affect the output end of the GOA driving unit; the pull-down control module generates a low-level signal, and the reset module generates a low level signal, controlling the pull-down output module to be turned off, so that the output of the pull-down output module does not affect the output end of the GOA driving unit; the first global control module and the second global control signal control the output of the GOA driving unit to be high
  • the image on the screen can be quickly cleared in the case of sudden power failure during the use of the liquid crystal screen, thereby avoiding the residual image of the previous display screen, which is beneficial to the user's visual experience.
  • FIG. 2 The wiring diagram of a GOA driving unit according to the second embodiment of the present invention is shown in FIG. 2 .
  • FIG. 2 is a schematic diagram of the wiring of the pull-up control module in the embodiment of the present invention.
  • the pull-up control module 101 includes: a first thin film transistor NT1, a second thin film transistor NT2, and a fifth thin film transistor. NT5 and seventh thin film transistor NT7.
  • the gate of the first thin film transistor NT1 is connected to the output signal G(n-2) of the n-2th stage GOA driving unit, the source is connected to the forward scanning signal U2D, and the drain is connected to the seventh thin film transistor NT7.
  • the source is electrically connected;
  • the gate of the second thin film transistor NT2 is connected to the output signal G(n+2) of the n+2th stage GOA driving unit, the source is connected to the reverse scanning signal D2U, and the drain is connected to the seventh
  • the source of the thin film transistor NT7 is electrically connected;
  • the gate of the fifth thin film transistor NT5 is connected to the output end of the pull-down control module 103, the source is connected to the low level signal VGL, and the drain is connected to the seventh thin film transistor NT7.
  • the source is electrically connected; the gate of the seventh thin film transistor NT7 is connected to the high level signal VGH, and the drain is connected to the output end of the pull-up control module 101.
  • the pull-up control module is configured to generate a first control signal when the power is off, and the first control signal is a low-level signal, thereby controlling the pull-up output module to be turned off.
  • the forward scan signal U2D becomes a low level signal
  • the output signal G(n-2) of the n-2th GOA driving unit is a high level signal
  • the first thin film transistor NT1 is controlled.
  • the drain of the first thin film transistor NT1 is made low.
  • the reverse scan signal D2U becomes a low level signal
  • the output signal G(n+2) of the n+2th GOA driving unit is a high level signal
  • the second thin film transistor NT2 is controlled to be turned on, thereby making the second thin film transistor The drain of NT2 is low.
  • the gate of the fifth thin film transistor NT5 is connected to the output terminal of the pull-down control module 103, the output terminal is at a low level in the following description, and the fifth thin film transistor NT5 is in a closed state.
  • the gate of the seventh thin film transistor NT7 is connected to the high level signal, so the seventh thin film transistor NT7 is in an on state, and since the source receives the low level signal input from the first thin film transistor NT1 and the second thin film transistor NT2, Therefore, its drain outputs a low level signal, and the output of the pull-up control circuit is a low level signal.
  • FIG. 2 is a schematic diagram of the wiring of the pull-up output module in the embodiment of the present invention, and the pull-up output module 102 includes a tenth thin film transistor NT10.
  • the gate of the tenth thin film transistor NT10 is connected to the output end of the pull-up control module 101, the source is connected to the n-th clock signal CK(n), and the drain is connected to the n-th stage GOA driving unit. Output G(n).
  • the pull-up output module is turned off under the action of the low-level signal generated by the pull-up control module when the power is off, and thus does not output the low level to the output end of the n-th stage GOA driving unit. signal.
  • the nth stage clock signal CK(n) becomes a low level signal
  • the gate of the tenth thin film transistor NT10 is connected to the output end of the pull-up control module 101 due to the pull-up control module 101.
  • the low-level signal is output, so that the tenth thin film transistor NT10 is turned off, and thus the drain of the tenth thin film transistor NT10 is not output to the output terminal G(n) of the nth stage GOA driving unit.
  • FIG. 2 is a schematic diagram of the connection of the pull-down control module in the embodiment of the present invention.
  • the pull-down control module 103 includes: a third thin film transistor NT3, a fourth thin film transistor NT4, and a sixth thin film transistor NT6.
  • the gate and the source of the third thin film transistor NT3 are connected to the n+1th clock signal CK(n+1), and the drain is electrically connected to the source of the eighth thin film transistor NT8; the fourth film
  • the source and the drain of the transistor NT4 are connected to the n-1th stage clock signal CK(n-1), the drain is electrically connected to the source of the ninth thin film transistor NT9, and the gate and the sixth thin film transistor NT6 are connected.
  • the source of the seven thin film transistor NT7 is electrically connected, the source is connected to the low level signal VGL, the drain is connected to the output end of the pull-down control module 103; the gate of the eighth thin film transistor NT8 is connected to the forward scan signal.
  • the drain is connected to the output end of the pull-down control module 103;
  • the gate of the ninth thin film transistor NT9 is connected to the reverse scan signal D2U, and the drain is connected to the output end of the pull-down control module 103;
  • the gate of the twelfth thin film transistor NT12 is connected to the first global control signal GAS1, the source is connected to the low level signal VGL, and the drain is connected to the output terminal of the pull-down control module 103.
  • the pull-down control module is configured to generate a second control signal when the power is off, and the second control signal is a low-level signal, thereby controlling the pull-down output module to be turned off.
  • the n+1th clock signal CK(n+1) becomes a low level signal
  • the third thin film transistor NT3 is turned off, and the forward scan signal U2D is changed to a low level signal.
  • the eighth thin film transistor NT8 is in a off state
  • the n-1th clock signal CK(n-1) is changed to a low level signal
  • the fourth thin film transistor NT4 is turned off, and the reverse scan signal D2U is turned to a low level.
  • the signal, and thus the ninth thin film transistor NT9, is turned off.
  • the sixth thin film transistor NT6 Since the gate of the sixth thin film transistor NT6 is connected to the drain of the second thin film transistor NT2, and the drain of the second thin film transistor is at a low level, the sixth thin film transistor NT6 is in a closed state.
  • the gate of the twelfth thin film transistor NT12 is connected to the first global control signal GAS1, and the first global control signal is at a high level, so the twelfth thin film transistor NT12 is turned on, and the source of the twelfth transistor NT12 is connected.
  • the low level signal, and thus the drain of the twelfth transistor outputs a low level signal to the output of the pull-down control module.
  • FIG. 2 is a wiring diagram of a pull-down output module in the embodiment of the present invention, and the pull-down output module 104 includes an eleventh thin film transistor NT11.
  • the gate of the eleventh thin film transistor NT11 is connected to the output end of the pull-down control module 103, the source is connected to the low level signal VGL, and the drain is connected to the output terminal G of the nth stage GOA driving unit ( n).
  • the pull-down output module is turned off by the low-level signal generated by the pull-down control module when the power is off, and the low-level signal is not outputted to the output end of the n-th stage GOA driving unit.
  • the source of the eleventh thin film transistor NT11 is connected to the low level signal, and the gate is electrically connected to the output end of the pull-down control module 103. Since the pull-down control module 103 outputs a low level signal, The eleven thin film transistor NT11 is in a closed state, and thus the drain of the eleventh thin film transistor NT11 is not output to the output terminal G(n) of the nth stage GOA driving unit.
  • FIG. 2 is a schematic diagram of the wiring of the first global control module in the embodiment of the present invention.
  • the first global control module 105 includes a fourteenth thin film transistor NT14.
  • the gate and the source of the fourteenth thin film transistor NT14 are connected to the first global control signal GAS1, and the drain drain is connected to the output terminal G(n) of the nth stage GOA driving unit;
  • a global control module is configured to output a high level signal to an output of the nth stage GOA driving unit when the power is off.
  • the fourteenth thin film transistor NT14 When the power is off, the first global control signal GAS1 becomes a high level signal, and since the gate and the source of the fourteenth thin film transistor NT14 are connected to the first global control signal GAS1, the fourteenth thin film transistor NT14 In the on state, the drain of the fourteenth thin film transistor NT14 outputs a high level signal to the output terminal G(n) of the nth stage GOA driving unit.
  • FIG. 2 is a schematic diagram of the wiring of the reset module in the embodiment of the present invention.
  • the reset module 106 includes a thirteenth thin film transistor NT13.
  • the gate and the source of the thirteenth thin film transistor NT13 are connected to the reset signal Reset, and the drain is connected to the output end of the pull-down control module 103.
  • the reset module is used when the power is off. Controlling an output of the pull-down control module to generate a low level signal.
  • the reset signal Reset becomes a low level signal
  • the gate and the source of the thirteenth thin film transistor NT13 are connected to the reset signal Reset
  • the thirteenth thin film transistor NT13 is turned off, and thus The drain of the thirteenth thin film transistor NT13 is output to the output terminal of the pull-down control module 103 to output a high level signal.
  • 107 is a wiring diagram of a second global control module in the embodiment of the present invention, and the second global control module 107 includes a fifteenth thin film transistor NT15.
  • the gate of the fifteenth thin film transistor NT15 is connected to the second global control signal GAS2, the source is connected to the low level signal VGL, and the drain is connected to the output terminal G(n) of the nth stage GOA driving unit.
  • the second global control module is configured to control an output end of the nth stage GOA driving unit to output a high level signal when the power is off.
  • the second global control signal GAS2 becomes a low level signal
  • the gate of the fifteenth thin film transistor NT15 is connected to the second global control signal GAS2
  • the source is connected to the low level signal, so
  • the thirteenth thin film transistor NT13 is in a closed state, and thus the drain of the fifteenth thin film transistor NT15 is not output to the output terminal G(n) of the nth stage GOA driving unit.
  • the GOA driving unit may further include: a first capacitor C1 and a second capacitor C2, wherein the first end of the first capacitor C1 is electrically connected to the source of the seventh thin film transistor NT7, and the second The first end of the second capacitor C2 is connected to the output end of the pull-down control module 103, and the second end is connected to the low level signal VGL; wherein, when the power is off, the The first capacitor is for maintaining a potential of a source of the seventh thin film transistor, and the second capacitor is for maintaining a potential of an output terminal of the pull-down control module.
  • the GOA driving circuit can be formed by the connection relationship between these stages.
  • the gate of the first thin film transistor NT1 of the third stage driving unit is electrically connected to the output terminal G(1) of the first stage driving unit
  • the gate of the second thin film transistor NT2 of the third stage driving unit is The output terminal G(5) of the fifth stage drive unit is electrically connected.
  • the access signal is the start signal STV;
  • the gate of the second thin film transistor NT2 of the countdown first stage driving unit and the penultimate stage driving unit does not have an output terminal of the GOA driving unit that is not connected, so the access signal is also the start signal, wherein the start signal STV is a high level signal.
  • FIG. 3 it is a timing change diagram, wherein the first timing is an input signal level of the GOA driving circuit at a certain moment when the liquid crystal screen is normally operated, and the second timing is a GOA driving circuit when the liquid crystal panel is powered off.
  • the level of change in the input signal It can be seen that, at the time of power-off, the start signal STV and the first global control signal GAS1 become a high level, the forward scan signal U2D, the reverse scan signal D2U, the clock signal CK, the second global control signal GAS2, and the reset The signal Reset becomes a low level, thereby controlling each level of the GOA driving unit of the GOA driving circuit to output a high level signal, thereby realizing the gate full function (All Gate On).
  • the GOA driving circuit in the technical solution of the embodiment of the present invention wherein the GOA driving units of each level include a pull-up control module, a pull-down control module, a pull-up output module, a pull-down output module, and a first global control module, and are powered off.
  • the pull-up control module When the pull-up control module generates a low-level signal, the pull-up output module is controlled to be turned off, so that the output of the pull-up output module does not affect the output end of the GOA driving unit; the pull-down control module generates a low-level signal, and the reset module generates a low level signal, controlling the pull-down output module to be turned off, so that the output of the pull-down output module does not affect the output end of the GOA driving unit; the first global control module and the second global control signal control the output of the GOA driving unit to be high
  • the image on the screen can be quickly cleared in the case of sudden power failure during the use of the liquid crystal screen, thereby avoiding the residual image of the previous display screen, which is beneficial to the user's visual experience.

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种GOA驱动电路，包括多级GOA驱动单元；在断电时第n级GOA驱动单元中，上拉控制模块（101）控制上拉输出模块（102）停止输出时钟信号，下拉控制模块（103）控制下拉输出模块（104）停止输出低电平信号，第一全局控制模块（105）输出高电平信号，复位模块（106）停止输出复位信号，第二全局控制模块（107）停止输出低电平信号。能够避免液晶屏在断电时产生残影的现象。

Description

一种GOA驱动电路 技术领域
本发明涉及领域电子电路领域，具体涉及一种GOA驱动电路。
背景技术
薄膜晶体管液晶显示器(Thin film transistor liquid crystal display，TFT-LCD)现已成为市场上主流的显示器，其基本原理是显示器中的液晶在电压的驱动下发生偏转，改变光的传播方向从而使显示器显示不同的颜色。阵列基板栅极驱动(Gate Driver On Array，GOA)电路，是将栅极驱动电路集成在液晶显示面板的阵列基板上，以实现对栅线逐行扫描的一项技术。在异常断电的情况下，液晶屏由于像素电容中会残留电平，从而导致残影现象。现有技术中，缺乏行之有效的机制来防止该现象的产生。
发明内容
本发明提供了一种栅极驱动电路，以避免液晶屏在断电的情况下产生残影的现象，进而提高观赏性。
本发明实施例第一方面提供一种GOA驱动电路，包括：多级GOA驱动单元；其中，第n级GOA驱动单元包括：上拉控制模块，上拉输出模块，下拉控制模块，下拉输出模块，第一全局控制模块、复位模块、第二全局控制模块；
所述上拉控制模块，用于在断电时产生第一控制信号；
所述上拉输出模块，用于在所述第一控制信号的作用下，停止向所述第n级GOA驱动单元的输出端输出时钟信号；
所述下拉控制模块，用于在断电时产生第二控制信号；
所述下拉输出模块，用于在所述第二控制信号的作用下，停止向所述第n级GOA驱动单元的输出端输出低电平信号；
所述第一全局控制模块，用于在断电时向所述第n级GOA驱动单元的输出端输出高电平信号；
所述复位模块，用于在断电时停止向所述下拉控制模块的输出端输出复位信号。
所述第二全局控制模块，用于在断电时停止向所述第n级GOA驱动单元的输出端输出低电平信号。
结合第一方面在一些可能的实现方式中，所述上拉控制模块包括：第一薄膜晶体管、第二薄膜晶体管、第五薄膜晶体管以及第七薄膜晶体管；
其中，所述第一薄膜晶体管的栅极接入第n-2级GOA驱动单元的输出信号，源极接入正向扫描信号，漏极与第七薄膜晶体管的源极电连接；所述第二薄膜晶体管的栅极接入第n+2级GOA驱动单元的输出信号，源极接入反向扫描信号，漏极与第七薄膜晶体管的源极电连接；所述第五薄膜晶体管的栅极接入所述下拉控制模块的输出端，源极接入低电平信号，漏极与第七薄膜晶体管的源极电连接；所述第七薄膜晶体管的栅极接入高电平信号，漏极接入所述上拉控制模块的输出端；其中，所述上拉控制模块，在断电时，用于产生第一控制信号，所述第一控制信号为低电平信号，进而控制所述上拉输出模块关闭。
结合第一方面在一些可能的实现方式中，所述上拉输出模块包括：第十薄膜晶体管；
其中，所述第十薄膜晶体管的栅极接入所述上拉控制模块的输出端，源极接入第n级时钟信号，漏极接入第n级GOA驱动单元的输出端；其中，所述上拉输出模块，在断电时，在所述上拉控制模块产生的低电平信号的作用下关闭， 进而不向所述第n级GOA驱动单元的输出端输出低电平信号。
结合第一方面在一些可能的实现方式中，所述下拉控制模块包括：第三薄膜晶体管、第四薄膜晶体管、第六薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十二薄膜晶体管；
其中，所述第三薄膜晶体管的栅极与源极接入第n+1级时钟信号，漏极与第八薄膜晶体管的源极电连接；所述第四薄膜晶体管的源极与漏极接入第n-1级时钟信号，漏极与第九薄膜晶体管的源极电连接；所述第六薄膜晶体管的栅极与第七薄膜晶体管的源极电连接，源极接入低电平信号，漏极接入所述下拉控制模块的输出端；所述第八薄膜晶体管的栅极接入正向扫描信号，漏极接入所述下拉控制模块的输出端；所述第九薄膜晶体管的栅极接入反向扫描信号，漏极接入所述下拉控制模块的输出端；所述第十二薄膜晶体管的栅极接入第一全局控制信号，源极接入低电平信号，漏极接入所述下拉控制模块的输出端；其中，所述下拉控制模块，在断电时，用于产生第二控制信号，所述第二控制信号为低电平信号，进而控制所述下拉输出模块关闭。
结合第一方面在一些可能的实现方式中，所述下拉输出模块包括：第十一薄膜晶体管；
其中，所述第十一薄膜晶体管的栅极接入所述下拉控制模块的输出端，源极接入低电平信号，漏极接入第n级GOA驱动单元的输出端；其中，所述下拉输出模块，在断电时，在所述下拉控制模块产生的低电平信号的作用下关闭，进而不向所述第n级GOA驱动单元的输出端输出低电平信号。
结合第一方面在一些可能的实现方式中，所述第一全局控制模块包括：第十四薄膜晶体管；
其中，所述第十四薄膜晶体管的栅极与源极接入第一全局控制信号，漏极 漏极接入第n级GOA驱动单元的输出端；其中，所述第一全局控制模块，在断电时，用于向所述第n级GOA驱动单元的输出端输出高电平信号。
结合第一方面在一些可能的实现方式中，所述复位模块包括：第十三薄膜晶体管；
其中，所述第十三薄膜晶体管的栅极与源极接入复位信号，漏极接入所述下拉控制模块的输出端；其中，所述复位模块，在断电时，用于控制所述下拉控制模块的输出端产生低电平信号。
结合第一方面在一些可能的实现方式中，所述复位模块包括：第十五薄膜晶体管；
其中，所述第十五薄膜晶体管的栅极接入第二全局控制信号，源极接入低电平信号，漏极接入第n级GOA驱动单元的输出端；其中，所述第二全局控制模块，在断电时，用于控制所述第n级GOA驱动单元的输出端输出高电平信号。
结合第一方面在一些可能的实现方式中，所述第n级GOA驱动单元还包括：第一电容、第二电容；
其中，所述第一电容的第一端与第七薄膜晶体管的源极电连接，第二端接入低电平信号；所述第二电容的第一端接入所述下拉控制模块的输出端，第二端接入低电平信号；其中，在断电时，所述第一电容用于保持所述第七薄膜晶体管的源极的电位，所述第二电容用于保持所述下拉控制模块的输出端的电位。
结合第一方面在一些可能的实现方式中，在第一级GOA驱动单元和第二级驱动单元中，所述第一薄膜晶体管的栅极均接入起始信号；在倒数第一级GOA驱动单元与倒数第二级驱动单元中，所述第二薄膜晶体管的栅极均接入起始信号，其中，所述起始信号为高电平信号。
可以看出，本发明实施例技术方案中的GOA驱动电路，其中各级GOA驱 动单元包括上拉控制模块、下拉控制模块、上拉输出模块、下拉输出模块、第一全局控制模块，在断电时，上拉控制模块产生低电平信号，控制所述上拉输出模块关闭，进而使上拉输出模块的输出不影响GOA驱动单元的输出端；下拉控制模块产生低电平信号，复位模块产生低电平信号，控制所述下拉输出模块关闭，进而使下拉输出模块的输出不影响GOA驱动单元的输出端；第一全局控制模块与第二全局控制信号控制GOA驱动单元的输出为高电平信号，通过实施本发明实施例能够在使用液晶屏过程中突然发生断电的情况下，迅速清除屏幕上的影像，避免出现之前显示画面的残影，有利于用户的视觉体验。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的GOA驱动单元的功能模块示意图；
图2是本发明的GOA驱动单元的电路图；
图3是本发明的GOA驱动电路的信号时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本发明的说明书和权利要求书及上述附图中的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
需要说明的是，下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。
在本发明的描述中，需要说明的是，除非另有规定和限定，术语“安装”、“相连”、“连接”、“接”应做广义理解，例如，可以是机械连接或电连接，也可以是两个元件内部的连通，可以是直接相连，也可以通过中间媒介间接相连，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参阅图1，图1是本发明实施例提供的一种GOA驱动单元的功能模块示意图，如图1所示，本发明实施例中的GOA驱动单元包括以下模块：上拉控制模块101、上拉输出模块102、下拉控制模块103、下拉输出模块104、第一全局控制模块105、复位模块106以及第二全局控制模块107。
其中，所述上拉控制模块101与所述下拉控制模块103、所述上拉输出模块102电连接，所述上拉输出模块102与所述下拉输出模块104、所述第一全局控制模块105、所述第二全局控制模块107电连接，所述下拉控制模块103与所述下拉输出模块104、所述复位模块106电连接，所述下拉输出模块104与所述第一全局控制模块105、所述第二全局控制模块107电连接，所述第一全局控制模块105与所述第二全局控制模块107电连接。
所述上拉控制模块，用于在断电时产生第一控制信号；所述上拉输出模块，用于在所述第一控制信号的作用下，停止向所述第n级GOA驱动单元的输出端输出时钟信号；所述下拉控制模块，用于在断电时产生第二控制信号；所述下拉输出模块，用于在所述第二控制信号的作用下，停止向所述第n级GOA驱动单元的输出端输出低电平信号；所述第一全局控制模块，用于在断电时向所述第n级GOA驱动单元的输出端输出高电平信号；所述复位模块，用于在断电时停止向所述下拉控制模块的输出端输出复位信号。所述第二全局控制模块，用 于在断电时停止向所述第n级GOA驱动单元的输出端输出低电平信号。
可以看出，本发明实施例技术方案中的GOA驱动电路，其中各级GOA驱动单元包括上拉控制模块、下拉控制模块、上拉输出模块、下拉输出模块、第一全局控制模块，在断电时，上拉控制模块产生低电平信号，控制所述上拉输出模块关闭，进而使上拉输出模块的输出不影响GOA驱动单元的输出端；下拉控制模块产生低电平信号，复位模块产生低电平信号，控制所述下拉输出模块关闭，进而使下拉输出模块的输出不影响GOA驱动单元的输出端；第一全局控制模块与第二全局控制信号控制GOA驱动单元的输出为高电平信号，通过实施本发明实施例能够在使用液晶屏过程中突然发生断电的情况下，迅速清除屏幕上的影像，避免出现之前显示画面的残影，有利于用户的视觉体验。
其中，本发明第二实施例提供的一种GOA驱动单元的接线示意图请参照图2所示。
下面对每个电路模块进行具体的介绍。
如图2所示，图2中101是本发明实施例中的上拉控制模块的接线示意图，所述上拉控制模块101包括：第一薄膜晶体管NT1、第二薄膜晶体管NT2、第五薄膜晶体管NT5以及第七薄膜晶体管NT7。
其中，所述第一薄膜晶体管NT1栅极接入第n-2级GOA驱动单元的输出信号G(n-2)，源极接入正向扫描信号U2D，漏极与第七薄膜晶体管NT7的源极电连接；所述第二薄膜晶体管NT2的栅极接入第n+2级GOA驱动单元的输出信号G(n+2)，源极接入反向扫描信号D2U，漏极与第七薄膜晶体管NT7的源极电连接；所述第五薄膜晶体管NT5的栅极接入所述下拉控制模块103的输出端， 源极接入低电平信号VGL，漏极与第七薄膜晶体管NT7的源极电连接；所述第七薄膜晶体管NT7的栅极接入高电平信号VGH，漏极接入所述上拉控制模块101的输出端。其中，所述上拉控制模块，在断电时，用于产生第一控制信号，所述第一控制信号为低电平信号，进而控制所述上拉输出模块关闭。
具体地，在断电时，正向扫描信号U2D变为低电平信号，第n-2级GOA驱动单元的输出信号G(n-2)为高电平信号，控制第一薄膜晶体管NT1导通，进而使第一薄膜晶体管NT1的漏极为低电。反向扫描信号D2U变为低电平信号，第n+2级GOA驱动单元的输出信号G(n+2)为高电平信号，控制第二薄膜晶体管NT2导通，进而使第二薄膜晶体管NT2的漏极为低电平。由于第五薄膜晶体管NT5的栅极接入下拉控制模块103的输出端，而在后述的描述中该输出端为低电平，所述第五薄膜晶体管NT5为关闭状态。第七薄膜晶体管NT7的栅极接入高电平信号，所以第七薄膜晶体管NT7为导通状态，由于其源极接收第一薄膜晶体管NT1以及第二薄膜晶体管NT2输入来的低电平信号，所以其漏极输出低电平信号，进而上拉控制电路的输出为低电平信号。
如图2所示，图2中102是本发明实施例中的上拉输出模块的接线示意图，所述上拉输出模块102包括：第十薄膜晶体管NT10。
其中，所述第十薄膜晶体管NT10的栅极接入所述上拉控制模块101的输出端，源极接入第n级时钟信号CK(n)，漏极接入第n级GOA驱动单元的输出端G(n)。其中，所述上拉输出模块，在断电时，在所述上拉控制模块产生的低电平信号的作用下关闭，进而不向所述第n级GOA驱动单元的输出端输出低电平信号。
具体地，在断电时，第n级时钟信号CK(n)变为低电平信号，而第十薄膜晶 体管NT10的栅极接入上拉控制模块101的输出端，由于上拉控制模块101输出低电平信号，所以第十薄膜晶体管NT10为关闭状态，进而不使第十薄膜晶体管NT10的漏极向第n级GOA驱动单元的输出端G(n)输出低电平信号。
如图2所示，图2中103是本发明实施例中的下拉控制模块的接线示意图，所述下拉控制模块103包括：第三薄膜晶体管NT3、第四薄膜晶体管NT4、第六薄膜晶体管NT6、第八薄膜晶体管NT8、第九薄膜晶体管NT9以及第十二薄膜晶体管NT12。
其中，所述第三薄膜晶体管NT3的栅极与源极接入第n+1级时钟信号CK(n+1)，漏极与第八薄膜晶体管NT8的源极电连接；所述第四薄膜晶体管NT4的源极与漏极接入第n-1级时钟信号CK(n-1)，漏极与第九薄膜晶体管NT9的源极电连接；所述第六薄膜晶体管NT6的栅极与第七薄膜晶体管NT7的源极电连接，源极接入低电平信号VGL，漏极接入所述下拉控制模块103的输出端；所述第八薄膜晶体管NT8的栅极接入正向扫描信号U2D，漏极接入所述下拉控制模块103的输出端；所述第九薄膜晶体管NT9的栅极接入反向扫描信号D2U，漏极接入所述下拉控制模块103的输出端；所述第十二薄膜晶体管NT12的栅极接入第一全局控制信号GAS1，源极接入低电平信号VGL，漏极接入所述下拉控制模块103的输出端。其中，所述下拉控制模块，在断电时，用于产生第二控制信号，所述第二控制信号为低电平信号，进而控制所述下拉输出模块关闭。
具体地，在断电时，第n+1级时钟信号CK(n+1)变为低电平信号，进而第三薄膜晶体管NT3为关闭状态，正向扫描信号U2D变为低电平信号，进而第八薄膜晶体管NT8为关闭状态，第n-1级时钟信号CK(n-1)变为低电平信号，进而第四薄膜晶体管NT4为关闭状态，反向扫描信号D2U变为低电平信号，进而第九 薄膜晶体管NT9为关闭状态。由于第六薄膜晶体管NT6的栅极接入第二薄膜晶体管NT2的漏极，而第二薄膜晶体管的漏极为低电平，所以第六薄膜晶体管NT6为关闭状态。第十二薄膜晶体管NT12的栅极接入第一全局控制信号GAS1，而第一全局控制信号为高电平，所以第十二薄膜晶体管NT12导通，又第十二晶体管NT12的源极接入低电平信号，进而第十二晶体管的漏极向下拉控制模块的输出端输出低电平信号。
如图2所示，图2中104是本发明实施例中的下拉输出模块的接线示意图，所述下拉输出模块104包括：第十一薄膜晶体管NT11。
其中，所述第十一薄膜晶体管NT11的栅极接入所述下拉控制模块103的输出端，源极接入低电平信号VGL，漏极接入第n级GOA驱动单元的输出端G(n)。其中，所述下拉输出模块，在断电时，在所述下拉控制模块产生的低电平信号的作用下关闭，进而不向所述第n级GOA驱动单元的输出端输出低电平信号。
具体地，在断电时，第十一薄膜晶体管NT11的源极接入低电平信号，栅极与下拉控制模块103的输出端电连接，由于下拉控制模块103输出低电平信号，所以第十一薄膜晶体管NT11为关闭状态，进而不使第十一薄膜晶体管NT11的漏极向第n级GOA驱动单元的输出端G(n)输出低电平信号。
如图2所示，图2中105是本发明实施例中的第一全局控制模块的接线示意图，所述第一全局控制模块105包括：第十四薄膜晶体管NT14。
其中，所述第十四薄膜晶体管NT14的栅极与源极接入第一全局控制信号GAS1，漏极漏极接入第n级GOA驱动单元的输出端G(n)；其中，所述第一全局控制模块，在断电时，用于向所述第n级GOA驱动单元的输出端输出高电平 信号。
具体地，在断电时，第一全局控制信号GAS1变为高电平信号，由于第十四薄膜晶体管NT14的栅极与源极接入第一全局控制信号GAS1，所以第十四薄膜晶体管NT14为导通状态，进而第十四薄膜晶体管NT14的漏极向第n级GOA驱动单元的输出端G(n)输出高电平信号。
如图2所示，图2中106是本发明实施例中的复位模块的接线示意图，所述复位模块106包括：第十三薄膜晶体管NT13。
其中，所述第十三薄膜晶体管NT13的栅极与源极接入复位信号Reset，漏极接入所述下拉控制模块103的输出端；其中，所述复位模块，在断电时，用于控制所述下拉控制模块的输出端产生低电平信号。
具体地，在断电时，复位信号Reset变为低电平信号，由于第十三薄膜晶体管NT13的栅极与源极接入复位信号Reset，所以第十三薄膜晶体管NT13为关闭状态，进而不使第十三薄膜晶体管NT13的漏极向下拉控制模块103的输出端输出高电平信号。
如图2所示，图2中107是本发明实施例中的第二全局控制模块的接线示意图，所述第二全局控制模块107包括：第十五薄膜晶体管NT15。
其中，所述第十五薄膜晶体管NT15的栅极接入第二全局控制信号GAS2，源极接入低电平信号VGL，漏极接入第n级GOA驱动单元的输出端G(n)。其中，所述第二全局控制模块，在断电时，用于控制所述第n级GOA驱动单元的输出端输出高电平信号。
具体地，在断电时，第二全局控制信号GAS2变为低电平信号，由于第十 五薄膜晶体管NT15的栅极接入第二全局控制信号GAS2，源极接入低电平信号，所以第十三薄膜晶体管NT13为关闭状态，进而不使第十五薄膜晶体管NT15的漏极向第n级GOA驱动单元的输出端G(n)输出高电平信号。
可选地，所述GOA驱动单元还可以进一步包括：第一电容C1、第二电容C2，其中，所述第一电容C1的第一端与第七薄膜晶体管NT7的源极电连接，第二端接入低电平信号VGL；所述第二电容C2的第一端接入所述下拉控制模块103的输出端，第二端接入低电平信号VGL；其中，在断电时，所述第一电容用于保持所述第七薄膜晶体管的源极的电位，所述第二电容用于保持所述下拉控制模块的输出端的电位。
需要说明的是，如图2所示，在所述GOA驱动单元的电路中，存在第n-2级GOA驱动单元输出信号G(n-2)、第n级GOA驱动单元输出信号G(n)以及第n+2级GOA驱动单元输出信号G(n+2)，可以理解的是，通过这些级与级之间的连接关系便可以组成GOA驱动电路。举例来说，第三级驱动单元的第一薄膜晶体管NT1的栅极与第一级驱动单元的输出端G(1)电连接，且第三级驱动单元的第二薄膜晶体管NT2的栅极与第五级驱动单元的输出端G(5)电连接。进一步地，由于第一级驱动单元、第二级驱动单元的第一薄膜晶体管NT1的栅极不存在接入没有的GOA驱动单元的输出端，所以其接入的是起始信号STV；又由于倒数第一级驱动单元、倒数第二级驱动单元的第二薄膜晶体管NT2的栅极不存在接入没有的GOA驱动单元的输出端，所以其接入的也是起始信号，其中，起始信号STV为高电平信号。
如图3所示，是一种时序变化图，其中，第一时序为液晶屏正常工作时的 某一时刻GOA驱动电路的输入信号电平，第二时序为液晶屏断电时GOA驱动电路的输入信号的变化电平。可以看出，在断电时，起始信号STV与第一全局控制信号GAS1变为高电平，正向扫描信号U2D、反向扫描信号D2U、时钟信号CK、第二全局控制信号GAS2以及复位信号Reset变为低电平，进而控制GOA驱动电路的每一级GOA驱动单元输出高电平信号，从而实现栅线全开功能(All Gate On)。
可以看出，本发明实施例技术方案中的GOA驱动电路，其中各级GOA驱动单元包括上拉控制模块、下拉控制模块、上拉输出模块、下拉输出模块、第一全局控制模块，在断电时，上拉控制模块产生低电平信号，控制所述上拉输出模块关闭，进而使上拉输出模块的输出不影响GOA驱动单元的输出端；下拉控制模块产生低电平信号，复位模块产生低电平信号，控制所述下拉输出模块关闭，进而使下拉输出模块的输出不影响GOA驱动单元的输出端；第一全局控制模块与第二全局控制信号控制GOA驱动单元的输出为高电平信号，通过实施本发明实施例能够在使用液晶屏过程中突然发生断电的情况下，迅速清除屏幕上的影像，避免出现之前显示画面的残影，有利于用户的视觉体验。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本发明实施例所提供的一种热插拔放电电路进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (10)

  1. 一种GOA驱动电路，其中，所述GOA驱动电路包括：多级GOA驱动单元；其中，第n级GOA驱动单元包括：上拉控制模块，上拉输出模块，下拉控制模块，下拉输出模块，第一全局控制模块，复位模块，第二全局控制模块；
    所述上拉控制模块，用于在断电时产生第一控制信号；
    所述上拉输出模块，用于在所述第一控制信号的作用下，停止向所述第n级GOA驱动单元的输出端输出时钟信号；
    所述下拉控制模块，用于在断电时产生第二控制信号；
    所述下拉输出模块，用于在所述第二控制信号的作用下，停止向所述第n级GOA驱动单元的输出端输出低电平信号；
    所述第一全局控制模块，用于在断电时向所述第n级GOA驱动单元的输出端输出高电平信号；
    所述复位模块，用于在断电时停止向所述下拉控制模块的输出端输出复位信号；
    所述第二全局控制模块，用于在断电时停止向所述第n级GOA驱动单元的输出端输出低电平信号。
  2. 根据权利要求1所述的GOA驱动电路，其中，所述上拉控制模块包括：第一薄膜晶体管(NT1)、第二薄膜晶体管(NT2)、第五薄膜晶体管(NT5)以及第七薄膜晶体管(NT7)；
    其中，所述第一薄膜晶体管(NT1)的栅极接入第n-2级GOA驱动单元的输出信号，源极接入正向扫描信号，漏极与第七薄膜晶体管(NT7)的源极电连接；
    所述第二薄膜晶体管(NT2)的栅极接入第n+2级GOA驱动单元的输出信号，源极接入反向扫描信号，漏极与第七薄膜晶体管(NT7)的源极电连接；
    所述第五薄膜晶体管(NT5)的栅极接入所述下拉控制模块的输出端，源极接入低电平信号，漏极与第七薄膜晶体管(NT7)的源极电连接；
    所述第七薄膜晶体管(NT7)的栅极接入高电平信号，漏极接入所述上拉控制模块的输出端；
    其中，所述上拉控制模块，在断电时，用于产生第一控制信号，所述第一控制信号为低电平信号，进而控制所述上拉输出模块关闭。
  3. 根据权利要求2所述的GOA驱动电路，其中，所述上拉输出模块包括：第十薄膜晶体管(NT10)；
    其中，所述第十薄膜晶体管(NT10)的栅极接入所述上拉控制模块的输出端，源极接入第n级时钟信号，漏极接入第n级GOA驱动单元的输出端；
    其中，所述上拉输出模块，在断电时，在所述上拉控制模块产生的低电平信号的作用下关闭，进而不向所述第n级GOA驱动单元的输出端输出低电平信号。
  4. 根据权利要求3所述的GOA驱动电路，其中，所述下拉控制模块包括：第三薄膜晶体管(NT3)、第四薄膜晶体管(NT4)、第六薄膜晶体管(NT6)、第八薄膜晶体管(NT8)、第九薄膜晶体管(NT9)以及第十二薄膜晶体管(NT12)；
    其中，所述第三薄膜晶体管(NT3)的栅极与源极接入第n+1级时钟信号，漏极与第八薄膜晶体管(NT8)的源极电连接；
    所述第四薄膜晶体管(NT4)的源极与漏极接入第n-1级时钟信号，漏极与第 九薄膜晶体管(NT9)的源极电连接；
    所述第六薄膜晶体管(NT6)的栅极与第七薄膜晶体管(NT7)的源极电连接，源极接入低电平信号，漏极接入所述下拉控制模块的输出端；
    所述第八薄膜晶体管(NT8)的栅极接入正向扫描信号，漏极接入所述下拉控制模块的输出端；
    所述第九薄膜晶体管(NT9)的栅极接入反向扫描信号，漏极接入所述下拉控制模块的输出端；
    所述第十二薄膜晶体管(NT12)的栅极接入第一全局控制信号，源极接入低电平信号，漏极接入所述下拉控制模块的输出端；
    其中，所述下拉控制模块，在断电时，用于产生第二控制信号，所述第二控制信号为低电平信号，进而控制所述下拉输出模块关闭。
  5. 根据权利要求4所述的GOA驱动电路，其中，所述下拉输出模块包括：第十一薄膜晶体管(NT11)；
    其中，所述第十一薄膜晶体管(NT11)的栅极接入所述下拉控制模块的输出端，源极接入低电平信号，漏极接入第n级GOA驱动单元的输出端；
    其中，所述下拉输出模块，在断电时，在所述下拉控制模块产生的低电平信号的作用下关闭，进而不向所述第n级GOA驱动单元的输出端输出低电平信号。
  6. 根据权利要求5所述的GOA驱动电路，其中，所述第一全局控制模块包括：第十四薄膜晶体管(NT14)；
    其中，所述第十四薄膜晶体管(NT14)的栅极与源极接入第一全局控制信号， 漏极漏极接入第n级GOA驱动单元的输出端；
    其中，所述第一全局控制模块，在断电时，用于向所述第n级GOA驱动单元的输出端输出高电平信号。
  7. 根据权利要求6所述的GOA驱动电路，其中，所述复位模块包括：第十三薄膜晶体管(NT13)；
    其中，所述第十三薄膜晶体管(NT13)的栅极与源极接入复位信号，漏极接入所述下拉控制模块的输出端；
    其中，所述复位模块，在断电时，用于控制所述下拉控制模块的输出端产生低电平信号。
  8. 根据权利要求7所述的GOA驱动电路，其中，所述第二全局控制模块包括：第十五薄膜晶体管(NT15)；
    其中，所述第十五薄膜晶体管(NT15)的栅极接入第二全局控制信号，源极接入低电平信号，漏极接入第n级GOA驱动单元的输出端；
    其中，所述第二全局控制模块，在断电时，用于控制所述第n级GOA驱动单元的输出端输出高电平信号。
  9. 根据权利要求8所述的GOA驱动电路，其中，所述第n级GOA驱动单元还包括：第一电容、第二电容；
    其中，所述第一电容的第一端与第七薄膜晶体管(NT7)的源极电连接，第二端接入低电平信号；所述第二电容的第一端接入所述下拉控制模块的输出端，第二端接入低电平信号；
    其中，在断电时，所述第一电容用于保持所述第七薄膜晶体管(NT7)的源极的电位，所述第二电容用于保持所述下拉控制模块的输出端的电位。
  10. 根据权利要求8所述的GOA驱动电路，其中，在第一级GOA驱动单元和第二级驱动单元中，所述第一薄膜晶体管(NT1)的栅极均接入起始信号；在倒数第一级GOA驱动单元与倒数第二级驱动单元中，所述第二薄膜晶体管(NT2)的栅极均接入起始信号，其中，所述起始信号为高电平信号。
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