WO2021237892A1 - 一种应用于显示屏的led芯片及其制备方法 - Google Patents

一种应用于显示屏的led芯片及其制备方法 Download PDF

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WO2021237892A1
WO2021237892A1 PCT/CN2020/101182 CN2020101182W WO2021237892A1 WO 2021237892 A1 WO2021237892 A1 WO 2021237892A1 CN 2020101182 W CN2020101182 W CN 2020101182W WO 2021237892 A1 WO2021237892 A1 WO 2021237892A1
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layer
gallium nitride
type gallium
transparent conductive
electrode
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PCT/CN2020/101182
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English (en)
French (fr)
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刘伟
刘英策
邬新根
黄瑄
周弘毅
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厦门乾照光电股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • This application relates to the field of semiconductor technology, and in particular to an LED chip applied to a display screen and a preparation method thereof.
  • the LED display is composed of LED dot matrix and LED PC panel. It displays text, pictures, animations, video screens, etc. by turning on and off the LED chips in three colors of R (red), G (green), and B (blue). , The displayed content can be adjusted differently according to the needs of different occasions, and each part of the component is a display device with a modular structure.
  • the LED chip ie, light-emitting diode
  • the LED chip applied to the display screen presents a low current and normal back pressure working state. When according to its reverse cut-off characteristics, it is in the cut-off state by applying a reverse voltage to it , The display screen with the LED chip displays black and is in a non-working display state.
  • the production of LED chips applied to the display screen involves four processes of MESA, ITO, PAD, and PV.
  • the inclination angle of the ITO and MESA structure of each LED chip in the existing LED display screen is relatively small, so that the When the normal reverse voltage is applied to the LED chip to make it fall into the reverse cut-off state, it is easy to cause the passivation layer (that is, the PV layer) in the LED chip to crack, and cause the LED display to appear light weakening and light leakage. Therefore, the existing The reliability of LED chips needs to be improved.
  • the embodiments of the present application provide an LED chip applied to a display screen and a preparation method thereof, so as to improve the reliability of the LED chip.
  • An LED chip applied to a display screen including:
  • An epitaxial wafer located on the surface of the substrate includes a stacked N-type gallium nitride layer, an active layer, and a P-type gallium nitride layer, and the first region of the epitaxial wafer exposes the N-type nitrogen Part of the surface of the gallium oxide layer;
  • a composite conductive layer located on the surface of the P-type gallium nitride layer, the composite conductive layer including a laminated ohmic contact layer and at least two transparent conductive layers;
  • a first passivation layer located on one side of the composite conductive layer, the first passivation layer covering the surface of the composite conductive layer and extending to cover a part of the surface of the exposed area of the N-type gallium nitride layer;
  • the density of each transparent conductive layer in the at least two transparent conductive layers gradually decreases along a preset direction, and the preset direction is from the ohmic contact layer to the transparent conductive layer; the composite conductive layer is close to
  • the value range of the angle formed by the side surface of the first region and the first region is 140 degrees to 160 degrees, including the endpoint value.
  • the composite conductive layer has a first through hole, and the first through hole exposes the surface of the P-type gallium nitride layer, and the P electrode communicates with the P-type nitride layer through the first through hole.
  • the angle formed by the sidewall of the first through hole and the bottom of the first through hole ranges from 140 degrees to 160 degrees, including the endpoint value.
  • the thickness of the ohmic contact layer ranges from 50 angstroms to 200 angstroms, including endpoint values.
  • the N electrode covers a part of the surface of the first passivation layer.
  • the ratio of the area of the N electrode covering the surface of the first passivation layer to the entire area of the N electrode ranges from 10% to 50%, including the endpoint value.
  • the material of the first passivation layer is SiO 2 , SiN x or Al 2 O 3 .
  • the refractive index of the first passivation layer ranges from 1.46 to 1.48, inclusive;
  • the refractive index of the first passivation layer ranges from 1.9 to 2.0, inclusive;
  • the refractive index of the first passivation layer ranges from 1.7 to 1.8, inclusive.
  • it also includes:
  • a second passivation layer located on the side of the composite conductive layer away from the substrate, the second passivation layer completely covers the epitaxial wafer and the composite conductive layer, and the second passivation layer has a second passivation layer A through hole and a third through hole, the second through hole exposes the surface of the P electrode part, and the third through hole exposes the surface of the N electrode part;
  • a P electrode pad that is electrically connected to the P electrode through the second through hole
  • a method for preparing LED chips applied to display screens includes:
  • An epitaxial wafer is formed on a substrate, the epitaxial wafer includes a stacked N-type gallium nitride layer, an active layer, and a P-type gallium nitride layer, and the first region of the epitaxial wafer exposes the N-type gallium nitride Part of the surface;
  • the composite conductive layer including a laminated ohmic contact layer and at least two transparent conductive layers;
  • a first passivation layer is formed on the side of the composite conductive layer away from the epitaxial wafer, the first passivation layer covers the surface of the composite conductive layer and extends to cover part of the surface of the exposed area of the N-type gallium nitride layer ;
  • the density of each transparent conductive layer in the at least two transparent conductive layers gradually decreases along a preset direction, and the preset direction is from the ohmic contact layer to the transparent conductive layer; the composite conductive layer is close to
  • the value range of the angle formed by the side surface of the first region and the first region is 140 degrees to 160 degrees, including the endpoint value.
  • forming a composite conductive layer on the surface of the P-type gallium nitride layer includes:
  • the evaporation rate of each transparent conductive layer in the at least two transparent conductive layers is gradually reduced along a predetermined direction, and the predetermined direction is directed from the ohmic contact layer to the transparent conductive layer.
  • the vapor deposition rate of each transparent conductive layer in the at least two transparent conductive layers is formed in a value range of 0.5 A/S to 2.5 A/S, inclusive.
  • using a sputtering deposition process to form an ohmic contact layer on the surface of the P-type gallium nitride layer includes:
  • the radio frequency power during the formation of the contact layer ranges from 400W to 800W, including the endpoint value; the voltage power ranges from 50W to 200W, including the endpoint value;
  • the annealing temperature of the contact layer ranges from 400° C. to 600° C., including endpoint values.
  • it also includes:
  • the structure composed of the ohmic contact layer and the at least two transparent conductive layers is etched to form a first through hole, and the first through hole exposes part of the surface of the P-type gallium nitride layer, and the P electrode Electrically connected to the P-type gallium nitride layer through the first through hole;
  • the angle formed by the sidewall of the first through hole and the bottom of the first through hole ranges from 140 degrees to 160 degrees.
  • etching the structure composed of the ohmic contact layer and the at least two transparent conductive layers to form the first through hole includes:
  • the structure composed of the ohmic contact layer and the at least two transparent conductive layers is etched to form a first through hole, and the sidewall of the first through hole and the bottom of the first through hole are formed
  • the value range of the angle is 140 degrees to 160 degrees;
  • the first concentration is greater than the second concentration.
  • a first passivation layer is formed on the side of the composite conductive layer away from the epitaxial wafer, and the first passivation layer covers the surface of the composite conductive layer and extends to cover the N-type gallium nitride layer Part of the surface of the exposed area includes:
  • first passivation layer Forming a first passivation layer on the side of the composite conductive layer away from the P-type gallium nitride layer, the first passivation layer covering the surface of the composite conductive layer and the exposed surface of the N-type gallium nitride layer;
  • the first passivation layer is etched corresponding to the part of the exposed surface area of the N-type gallium nitride layer, so that the first passivation layer covers part of the surface of the exposed area of the N-type gallium nitride layer, and exposes the Part of the surface of the exposed area of the N-type gallium nitride layer.
  • the deposition temperature of the first passivation layer is 280°C to 340°C, including the endpoint value
  • the deposition gas includes SiH 4 and N 2 O
  • the ratio of SiH 4 to N 2 O gas ranges from 0.1 to 0.4, including endpoint values.
  • forming an epitaxial wafer on a substrate includes:
  • the epitaxial structure including a stacked N-type gallium nitride layer, an active layer and a P-type gallium nitride layer;
  • the etching gas includes: Cl 2 , Ar and O 2 .
  • the ratio of O 2 in the etching gas ranges from 10% to 30%, including endpoint values; the ratio of Cl 2 in the etching gas ranges from 60% to 80%, Include endpoint values.
  • the LED chip includes a substrate, an epitaxial wafer, a composite conductive layer, a first passivation layer, a P electrode, and an N electrode, wherein the composite conductive layer It includes an ohmic contact layer and at least two transparent conductive layers.
  • the density of the at least two transparent conductive layers is gradually reduced along a predetermined direction, so that the at least two transparent conductive layers are etched, and the composite conductive layer is only located at On the surface of the P-type gallium nitride layer, the distance from the side surface of the composite conductive layer close to the first region to the first region can be gradually increased in a preset direction, thereby increasing the composite conductive layer.
  • the angle between the side surface of the conductive layer close to the first region and the first region is such that the angle is within the range of 140 degrees to 160 degrees, so as to improve the subsequent formation of the first passivation layer.
  • the covering property of the first passivation layer on the side surface of the composite conductive layer reduces the probability of fracture of the portion of the first passivation layer located on the side surface of the composite conductive layer, and improves the reliability of the LED.
  • FIG. 1 is a schematic diagram of the structure of an LED chip provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the structure of an LED chip provided by another embodiment of the application.
  • FIG. 3 is a flowchart of a method for manufacturing an LED chip provided by an embodiment of the application.
  • Figures 4 to 16 are schematic diagrams of the structure of the LED chip manufacturing method provided by an embodiment of the application after the completion of each process step.
  • the size of the blue and green chips in the LED display is getting smaller and smaller, and the distance between the P electrode and the N electrode is getting smaller and smaller, so that when a reverse voltage is applied to the LED chip, the LED The reverse electric field in the chip becomes larger and larger, causing the PV layer (passivation layer) in the LED chip to be more prone to cracking and covering at the edge of the ITO (transparent conductive layer) and MESA, causing ITO to float.
  • LED display screens are more prone to light decay, leakage and other phenomena when they work under normal reverse pressure.
  • the embodiments of the present application provide an LED chip applied to a display screen and a preparation method to improve the reliability of the LED chip.
  • the following describes the LED chip and the LED chip applied to the display screen provided by the embodiment of the present application with reference to the accompanying drawings. The preparation method is described.
  • the LED chip applied to the display screen provided by the embodiment of the present application includes:
  • the substrate 10, optionally, the substrate 10 is a sapphire substrate;
  • the epitaxial wafer 20 is located on the surface of the substrate 10.
  • the epitaxial wafer 20 includes a stacked N-type gallium nitride layer 21, an active layer 22, and a P-type gallium nitride layer 23, and the first epitaxial wafer 20 Area exposing part of the surface of the N-type gallium nitride layer 21;
  • the density of each transparent conductive layer in the at least two transparent conductive layers 32 gradually decreases along a predetermined direction, and the predetermined direction is directed from the ohmic contact layer to the transparent conductive layer; the composite conductive layer 30
  • the value range of the angle formed by the side surface close to the first area and the first area is 140 degrees to 160 degrees, including the endpoint value.
  • the angle formed by the sidewall of the epitaxial wafer close to the first region and the exposed surface of the N-type gallium nitride layer ranges from 135 degrees to 160 degrees. , Including the endpoint value, to improve the subsequent coating of the first passivation layer on the side surface of the epitaxial layer.
  • the composite conductive layer includes an ohmic contact layer and at least two transparent conductive layers, and the density of the at least two transparent conductive layers gradually decreases along a predetermined direction, so that only the P-type nitrogen
  • the distance from the side surface of the composite conductive layer close to the first region to the first region can be gradually increased in a preset direction, thereby increasing the
  • the angle between the side surface of the composite conductive layer close to the first region and the first region is such that the value of the angle is within the range of 140 degrees to 160 degrees, so as to improve the subsequent formation of the first passivation layer.
  • the covering property of the first passivation layer on the side surface of the composite conductive layer reduces the probability of fracture of the part of the first passivation layer located on the side surface of the composite conductive layer, and improves the reliability of the LED.
  • the composite conductive layer 30 includes:
  • An ohmic contact layer 31 located on the surface of the P-type gallium nitride layer 23;
  • the at least two transparent conductive layers 32 include a first transparent layer on the surface of the ohmic contact layer 31.
  • each transparent conductive layer in the at least two transparent conductive layers is gradually reduced along a preset direction, and the preset direction is directed from the ohmic contact layer to the transparent conductive layer, that is, the first The density of the transparent conductive layer is greater than the density of the second transparent conductive layer.
  • the material of the ohmic contact layer, the first transparent conductive layer, and the second transparent conductive layer is ITO
  • the formation process of the ohmic contact layer is sputter deposition Process
  • the forming process of the first transparent conductive layer and the second transparent conductive layer is an electron beam evaporation process, but this application is not limited to this, and it depends on the situation.
  • the thickness of the ohmic contact layer ranges from 50 angstroms to 200 angstroms, including endpoints, so that the composite conductive layer and the epitaxial wafer form Good ohmic contact.
  • the density of the first transparent conductive layer and the second transparent conductive layer is gradually reduced along a predetermined direction, so that the composite conductive layer may be close to the first transparent conductive layer.
  • the distance between the side surface of the area and the first area gradually increases along the preset direction, which is beneficial for the side surface of the composite conductive layer close to the first area to form a larger angle with the first area, which improves
  • the first passivation layer is coated on the side surface of the composite conductive layer.
  • the composite conductive layer may further include a third transparent conductive layer, a fourth transparent conductive layer, etc., so that the side slope transition of the composite conductive layer is more smooth, but this application does not Make restrictions, depending on the situation.
  • the composite conductive layer 30 has a first through hole, and the first through hole exposes the surface of the P-type gallium nitride layer 23, and the P electrode 50 is electrically connected to the P-type gallium nitride layer 23 through the first through hole.
  • the P electrode is electrically connected to the P-type gallium nitride layer 23 through the first through hole, so that the P electrode can be directly connected to the P-type of the epitaxial wafer.
  • the gallium nitride layer is electrically connected, which facilitates that in actual work, the current of the P electrode in the LED chip directly flows into the epitaxial wafer.
  • this application is not limited to this.
  • the P electrode may also be electrically connected through the composite conductive layer and the P-type gallium nitride layer of the epitaxial wafer. Connection depends on the situation.
  • the angle formed by the sidewall of the first through hole and the bottom of the first through hole ranges from 140 degrees to 160 degrees, including the endpoints, and Therefore, the covering property of the P electrode on the side wall of the first through hole is better, and the probability of the P electrode being broken is reduced.
  • the first passivation layer there is a first passivation layer between the composite conductive layer and the P electrode, and the first passivation layer has high density, so that the first passivation
  • the chemical layer acts as a current blocking layer, changing the current path between the P electrode and the N electrode, increasing the distance between the P electrode and the N electrode, and reducing the reverse piezoelectric field in the LED chip under normal reverse pressure, The reliability of the LED chip under normal reverse pressure is improved.
  • the material of the first passivation layer is SiO 2 , SiN x or Al 2 O 3 , which is not limited in this application.
  • the material of the first passivation layer may also be other materials, depending on the situation.
  • the refractive index of the first passivation layer ranges from 1.46 to 1.48 , Including the endpoint value to ensure that the first passivation layer has a higher density; if the first passivation layer is an SiO 2 layer, the refractive index of the first passivation layer ranges from 1.9 to 2.0, including the endpoint value to ensure that the first passivation layer has a higher density; if the first passivation layer is an Al 2 O 3 layer, the refractive index of the first passivation layer ranges from It is 1.7 to 1.8, including the endpoint value, to ensure that the first passivation layer has a relatively high density.
  • the N electrode covers a part of the surface of the first passivation layer to further change the current path between the P electrode and the N electrode, and increase The distance between the P electrode and the N electrode is increased, and the reverse piezoelectric field in the LED chip under normal reverse pressure is reduced, thereby improving the reliability of the LED when working under normal reverse pressure.
  • the ratio of the area of the N electrode 60 covering the surface of the first passivation layer 40 to the entire area of the N electrode ranges from 10. % ⁇ 50%, including the endpoint value, but this application does not limit this, and it depends on the situation.
  • the P electrode and the N electrode are metal electrodes to improve the electrical performance of the P electrode and the N electrode in the LED chip, but this application is not limited to this, specifically It depends on the situation.
  • the LED chip further includes:
  • the second passivation layer 70 has a second through hole and a third through hole.
  • the second through hole exposes a part of the surface of the P electrode 50
  • the third through hole exposes a part of the surface of the N electrode 60;
  • the material of the second passivation layer is SiO 2 , SiN x or Al 2 O 3 , which is not limited in this application.
  • the material of the second passivation layer may also be other materials, depending on the situation.
  • the second passivation layer 70 wraps the sidewall of the P electrode 50 and is away from the P electrode 50 Part of the area of the surface of one side of the substrate 10, as well as the sidewall of the N electrode 60 and the part of the area of the surface of the N electrode 60 away from the substrate 10, optionally, the second passivation
  • the value range of the partial width X of the surface of the P electrode and the N electrode is in the range of 2um to 4um, including the endpoint value, to prevent the contact area of the P electrode and the P electrode pad and the welding of the N electrode and the N electrode.
  • the contact area of the disk is oxidized, which affects the electrical contact performance of the P electrode and the P electrode pad and the electrical contact performance of the N electrode and the N electrode pad.
  • the composite conductive layer includes an ohmic contact layer and at least two transparent conductive layers.
  • the direction is gradually reduced, so that only when the composite conductive layer is formed on the surface of the P-type gallium nitride layer, the distance between the side surface of the composite conductive layer close to the first region and the first region can be made Gradually increase along the preset direction, thereby increasing the angle between the side surface of the composite conductive layer close to the first area and the first area, so that the value of the angle is within the range of 140 degrees to 160 degrees,
  • reduce the part of the first passivation layer on the side of the composite conductive layer The probability of breakage increases the reliability of the LED.
  • an embodiment of the present application also provides a method for manufacturing an LED chip applied to a display screen, which is used to manufacture the LED chip applied to a display screen provided in any of the foregoing embodiments.
  • the manufacturing method of the LED chip applied to the display screen includes:
  • an epitaxial wafer 20 is formed on the substrate 10.
  • the epitaxial wafer 20 includes a stacked N-type gallium nitride layer 21, an active layer 22, and a P-type gallium nitride layer 23, and
  • the first region of the epitaxial wafer 20 exposes part of the surface of the N-type gallium nitride layer 21.
  • the substrate is a sapphire substrate, but the present application is not limited to this. In other embodiments of the present application, the substrate may also be a sapphire substrate. Substrates of other materials, depending on the situation.
  • the angle formed by the sidewall of the epitaxial wafer close to the first region and the exposed surface of the N-type gallium nitride layer ranges from 135 degrees to 160 degrees. , Including the endpoint value, to improve the subsequent coating of the first passivation layer on the side surface of the epitaxial layer.
  • forming an epitaxial wafer on a substrate includes:
  • an epitaxial structure 2 is formed on a substrate 10.
  • the epitaxial structure 2 includes a stacked N-type gallium nitride layer 21, an active layer 22, and a P-type gallium nitride layer 23;
  • a photolithography process and a dry etching process are used to etch the first area of the epitaxial structure 2 so that the epitaxial structure 2 exposes the first area of the N-type gallium nitride layer 21
  • the surface of the N-type gallium nitride layer 21 exposed in the epitaxial structure 2 is used to subsequently form an N electrode electrically connected to the N-type gallium nitride layer.
  • etching the first region of the epitaxial structure 2 includes: using an inductively coupled plasma (ICP) process to etch the first region of the epitaxial structure 2
  • ICP inductively coupled plasma
  • the etching gas includes Cl 2 , Ar and O 2 .
  • this application does not limit this, and it depends on the situation.
  • the etching depth of the first region may be the sum of the thickness of the P-type gallium nitride layer and the active layer, or may be greater than the thickness of the P-type nitride layer.
  • the sum of the thickness of the gallium oxide layer and the active layer is smaller than the sum of the thickness of the P-type gallium nitride layer, the active layer, and the N-type gallium nitride layer.
  • the proportion of O 2 in the etching gas ranges from 10% to 30%, including the endpoint value; in the etching gas, Cl 2
  • the value range of the ratio is 60% to 80%, including the endpoint value, which is not limited in this application, and it depends on the situation.
  • the ratio of the etching gases Cl 2 , Ar, and O 2 is 5:1:2, so that the epitaxial wafer is close to the sidewall of the first region The slope is large.
  • the angle formed by the sidewall of the epitaxial wafer close to the first region and the surface area of the epitaxial wafer that exposes the N-type gallium nitride layer The value range is 135 degrees to 160 degrees, including the endpoint value, but this application does not limit this, and it depends on the situation.
  • a composite conductive layer 30 is formed on the surface of the P-type gallium nitride layer 23.
  • the composite conductive layer 30 includes a laminated ohmic contact layer 31 and at least two transparent conductive layers 32;
  • the density of each transparent conductive layer in the at least two transparent conductive layers 32 gradually decreases along a preset direction, the preset direction is from the ohmic contact layer 31 to the transparent conductive layer;
  • the composite conductive layer 30 is close to The value range of the angle formed by the side surface of the first region and the first region is 140 degrees to 160 degrees, including the endpoint value.
  • forming a composite conductive layer on the surface of the P-type gallium nitride layer includes:
  • an ohmic contact layer 31 is formed on the surface of the P-type gallium nitride layer 23.
  • the thickness of the ohmic contact layer ranges from 50 angstroms to 200 angstroms, including endpoints;
  • At least two transparent conductive layers 32 are formed on the surface of the ohmic contact layer 31 facing away from the P-type gallium nitride layer 23;
  • the evaporation rate of each transparent conductive layer in the at least two transparent conductive layers is gradually reduced along a predetermined direction, and the predetermined direction is directed from the ohmic contact layer to the transparent conductive layer.
  • using a sputtering deposition process to form an ohmic contact layer on the surface of the P-type gallium nitride layer includes:
  • the radio frequency power during the formation of the contact layer ranges from 400W to 800W, including the endpoint; the voltage power ranges from 50W to 200W, including the endpoint Value; the annealing temperature of the contact layer ranges from 400° C. to 600° C., including the endpoint value, which is not limited in this application, and it depends on the situation.
  • an electron beam evaporation process is used to set the ohmic contact layer 31 away from the P-type gallium nitride layer.
  • Forming at least two transparent conductive layers 32 on one side surface of the ohmic contact layer 31 includes: forming a first transparent conductive layer 321 on the surface of the ohmic contact layer 31; forming a second transparent conductive layer 322 on the surface of the first transparent conductive layer 321; The vapor deposition rate of the transparent conductive layer is lower than the vapor deposition rate of the first transparent conductive layer.
  • the vapor deposition rate of the first transparent conductive layer is 2A/S (that is, the vapor deposition rate of the first transparent conductive layer with a thickness of 2A per second), and the vapor deposition rate of the second transparent conductive layer is 1A/S ( That is, the second transparent conductive layer with a thickness of 1A is vapor deposited per second), but this application is not limited to this, and it depends on the situation.
  • the composite conductive layer may further include a third transparent conductive layer, a fourth transparent conductive layer, etc., but this application is not limited thereto, and it depends on the situation.
  • the evaporation rate of each transparent conductive layer in the at least two transparent conductive layers is formed in the range of 0.5A/S to 2.5A/S, including
  • the endpoint value that is, the evaporation rate of the transparent conductive layer directly in contact with the ohmic contact layer in the at least two transparent conductive layers is not greater than 2.5A/S, and the distance between the at least two transparent conductive layers
  • the evaporation rate of the transparent conductive layer farthest from the ohmic contact layer is not less than 0.5A/S.
  • A/S represents angstroms/second (that is, the thickness of the vapor-deposited transparent conductive layer per second).
  • the evaporation rate of the first transparent conductive layer and the second transparent conductive layer is gradually reduced along a preset direction, so that the composite conductive layer may be subsequently etched .
  • the distance from the side surface of the composite conductive layer close to the first region to the first region is along a preset direction Gradually increasing, it is beneficial for the side surface of the composite conductive layer close to the first region to form a larger angle with the first region, which improves the subsequent formation of the first passivation layer, the first passivation The coating property of the layer on the side of the composite conductive layer.
  • the material of the ohmic contact layer, the first transparent conductive layer, and the second transparent conductive layer is ITO, which is not limited in the present application, and it depends on the situation. Depends.
  • forming a composite conductive layer 30 on the surface of the P-type gallium nitride layer 23 includes:
  • a composite conductive structure 3 is formed on the side of the epitaxial wafer 20 away from the substrate 10.
  • the composite conductive structure includes an ohmic contact layer and at least two transparent conductive layers, and completely covers the epitaxial wafer. The surface on the side facing away from the substrate;
  • a layer of photoresist is applied to the surface of the composite conductive structure 3 away from the epitaxial wafer 20 to form a first photoresist layer, and the first photoresist layer is exposed and developed And after the film is hardened, a first photoresist pattern 33 is formed;
  • the composite conductive structure is etched to remove the part of the composite conductive structure located on the exposed surface of the N-type gallium nitride layer and all The composite conductive structure is located on the part of the epitaxial wafer facing the side surface of the first region, and only the part of the composite conductive structure located on the surface of the P-type gallium nitride layer is retained to form a composite conductive layer, and the composite conductive layer
  • the value range of the angle formed by the side surface close to the first area and the first area is 140 degrees to 160 degrees, including the endpoint value.
  • the value range of the hard film temperature of the first photoresist layer is 80° C. to 100° C., including the endpoint value.
  • the preparation method further includes:
  • the structure composed of the ohmic contact layer 31 and the at least two transparent conductive layers 32 is etched to form a first through hole, and the first through hole exposes a part of the surface of the P-type gallium nitride layer 23, so The P electrode 50 is electrically connected to the P-type gallium nitride layer 23 through the first through hole;
  • the value range of the angle formed by the side wall of the first through hole and the bottom of the first through hole is 140 degrees to 160 degrees, including the endpoint value, so that the P electrode formed subsequently is in the
  • the sidewall of the first through hole has better covering properties, which reduces the probability of the P electrode being broken.
  • the P electrode is electrically connected to the P-type gallium nitride layer 23 through the first through hole, so that the P electrode can be directly connected to the P-type of the epitaxial wafer.
  • the gallium nitride layer is electrically connected, which facilitates that in actual work, the current of the P electrode in the LED chip directly flows into the epitaxial wafer, but this application is not limited to this, and in other embodiments of the application .
  • etching the structure composed of the ohmic contact layer and the at least two transparent conductive layers to form the first through hole includes:
  • the structure composed of the ohmic contact layer and the at least two transparent conductive layers is etched to form a first through hole, and the sidewall of the first through hole and the bottom of the first through hole are formed
  • the value range of the angle is 140 degrees to 160 degrees, including the endpoint value
  • the first concentration is greater than the second concentration.
  • the structure composed of the ohmic contact layer and the at least two transparent conductive layers is etched first by using an etching solution with a higher concentration and a first concentration, so as to use a faster
  • the structure formed by the ohmic contact layer and the at least two transparent conductive layers is etched at an etch rate, and the structure formed by the ohmic contact layer and the at least two transparent conductive layers is etched through to expose the Part of the surface of the P-type gallium nitride layer is to avoid etching residue, and then the structure composed of the ohmic contact layer and the at least two transparent conductive layers is etched by using an etching solution with a lower concentration and a second concentration.
  • the side wall of the first through hole has a larger inclination rate, so that the side wall of the first through hole and the bottom of the first through hole form a larger angle.
  • a first passivation layer 40 is formed on the side of the composite conductive layer 30 away from the epitaxial wafer 20, and the first passivation layer 40 covers the surface of the composite conductive layer 30 and extends to Cover a part of the surface of the exposed area of the N-type gallium nitride layer 21.
  • forming a first passivation layer on the side of the composite conductive layer away from the epitaxial wafer includes: using a PECVD device to place the composite conductive layer away from the epitaxial layer.
  • the first passivation layer is deposited on one side of the wafer.
  • This application is not limited to this. In other embodiments of the present application, other methods may be used to form the first passivation on the side of the composite conductive layer away from the epitaxial wafer. The level depends on the situation.
  • the material of the first passivation layer is SiO 2 , SiN x or Al 2 O 3 , which is not limited in this application.
  • the material of the first passivation layer may also be other materials, depending on the situation.
  • the refractive index of the first passivation layer ranges from 1.46 to 1.48 , Including the endpoint value to ensure that the first passivation layer has a higher density; if the first passivation layer is an SiO 2 layer, the refractive index of the first passivation layer ranges from 1.9 to 2.0, including the endpoint value to ensure that the first passivation layer has a higher density; if the first passivation layer is an Al 2 O 3 layer, the refractive index of the first passivation layer ranges from It is 1.7 to 1.8, including the endpoint value, to ensure that the first passivation layer has a relatively high density.
  • a first passivation layer is formed on the side of the composite conductive layer away from the epitaxial wafer, and the first passivation layer covers the surface of the composite conductive layer And extending to cover part of the surface of the exposed area of the N-type gallium nitride layer includes:
  • first passivation layer Forming a first passivation layer on the side of the composite conductive layer away from the P-type gallium nitride layer, the first passivation layer covering the surface of the composite conductive layer and the exposed surface of the N-type gallium nitride layer;
  • a partial area of the first passivation layer corresponding to the exposed surface of the N-type gallium nitride layer is etched so that the first passivation layer covers the A part of the surface of the exposed area of the N-type gallium nitride layer is exposed, and a part of the surface of the exposed area of the N-type gallium nitride layer is exposed.
  • the deposition temperature of the first passivation layer ranges from 280° C. to 340° C., inclusive, so as to deposit the first passivation layer at a high temperature. layer such that the first passivation layer having a high denseness; deposition gas comprises SiH 4 and N 2 O, the deposition gas SiH 4 and N 2 O gas ratio in the range of 0.1 to 0.4, inclusive , But this application does not limit this, and it depends on the specific circumstances.
  • a first passivation layer is formed on the side of the composite conductive layer away from the epitaxial wafer, the The first passivation layer covering the surface of the composite conductive layer and extending to cover part of the surface of the exposed area of the N-type gallium nitride layer includes:
  • a first passivation layer is formed on the side of the composite conductive layer away from the P-type gallium nitride layer, and the first passivation layer covers the surface of the composite conductive layer, the first through hole region and the N The exposed surface of the type gallium nitride layer;
  • the first passivation layer 40 corresponds to the first through hole area and the first passivation layer 40 corresponds to the part of the exposed surface area of the N-type gallium nitride layer to etch, so that the first passivation
  • the layer 40 corresponds to the first through hole region to expose the P-type gallium nitride layer 23, and the first passivation layer 40 covers a part of the surface of the N-type gallium nitride layer 21 in the exposed region, and exposes the N-type gallium nitride layer.
  • Part of the surface of the exposed area of the gallium nitride layer 21 includes:
  • a fourth photoresist pattern using the fourth photoresist pattern as a mask, first use a BOE etching solution of a first concentration to etch, and the first passivation layer corresponds to the first through hole area and the The first passivation layer is etched corresponding to a part of the exposed surface area of the N-type gallium nitride layer; then a second concentration of BOE etchant is used to etch, and the first passivation layer is corresponding to the first through hole area And the first passivation layer is etched corresponding to a partial area of the exposed surface of the N-type gallium nitride layer, so that the first passivation layer corresponds to the first through hole area to expose the P-type gallium nitride layer , And the first pass
  • the BOE etching solution of the first concentration and the BOE etching solution of the second concentration are mixed with an HF solution and an NH 4 F solution, optionally ,
  • the concentration range of the BOE etching solution of the first concentration is 1:5 ⁇ 1:10, including the endpoint value
  • the concentration value range of the BOE etching solution of the second concentration is 1:10 ⁇ 1:20, including the endpoint value .
  • the BOE etching solution of HF concentration of the first solution and the concentration ratio of NH 4 F. Solution is 1: 5
  • the concentration ratio of the F solution is 1:20, but this application does not limit this, and it depends on the situation.
  • a P electrode 50 electrically connected to the P-type gallium nitride layer 23 is formed on the side of the P-type gallium nitride layer 23 away from the active layer 22.
  • the first passivation layer there is a first passivation layer between the composite conductive layer and the P electrode, and the first passivation layer has high density, so that the first passivation
  • the chemical layer acts as a current blocking layer, changing the current path between the P electrode and the N electrode formed subsequently, increasing the distance between the P electrode and the N electrode, and reducing the back pressure in the LED chip under normal back pressure
  • the electric field improves the reliability of the LED chip under normal reverse pressure.
  • the N electrode covers a part of the surface of the first passivation layer to further change the gap between the P electrode and the N electrode.
  • the current path increases the distance between the P electrode and the N electrode, reduces the inverse piezoelectric field in the LED chip under normal reverse pressure, and thereby improves the LED’s performance when working under normal reverse pressure. reliability.
  • the ratio of the area of the N electrode 60 covering the surface of the first passivation layer 40 to the entire area of the N electrode ranges from 10. % ⁇ 50%, including the endpoint value, but this application does not limit this, and it depends on the situation.
  • the P electrode and the N electrode are metal electrodes to improve the electrical performance of the P electrode and the N electrode in the LED chip, but this application is not limited to this, specifically It depends on the situation.
  • a P type electrically connected to the P type gallium nitride layer is formed on the side of the P type gallium nitride layer away from the active layer.
  • An electrode, forming an N electrode in the first area that is electrically connected to the exposed area of the N-type gallium nitride layer includes:
  • the fifth photoresist layer covers the epitaxial wafer and the composite conductive layer.
  • the P electrode is vapor-deposited at the first through hole, so that the P electrode electrically connected to the P-type gallium nitride layer is vaporized in the first region
  • the N electrode is plated, so that an N electrode electrically connected to the exposed area of the N-type gallium nitride layer is formed in the first area.
  • the preparation method further includes:
  • a second passivation layer 70 is formed on the side of the first passivation layer 40 away from the substrate 10, and the second passivation layer 70 completely covers the epitaxial wafer 20 and the composite conductive layer 30.
  • the second passivation layer 70 has a second through hole and a third through hole. The second through hole exposes a part of the surface of the P electrode 50, and the third through hole exposes a part of the surface of the N electrode 60;
  • forming a second passivation layer on the side of the first passivation layer away from the epitaxial wafer includes: using a PECVD equipment to set the composite conductive layer away from the place
  • the second passivation layer is deposited on one side of the epitaxial wafer, which is not limited in this application, and it depends on the situation.
  • the material of the second passivation layer is SiO 2 , SiN x or Al 2 O 3 , which is not limited in this application.
  • the material of the second passivation layer may also be other materials, depending on the situation.
  • the deposition temperature of the second passivation layer ranges from 200°C to 275°C, including the endpoint value
  • the deposition gas includes SiH 4 and N 2 O
  • the ratio of SiH 4 and N 2 O in the deposition gas ranges from 0.1 to 0.4, including the endpoint value, which is not limited in this application, as the case may be.
  • the second passivation layer having a second through hole and a third through hole includes:
  • the second passivation layer is etched using an inductively coupled plasma (ICP) etching process, so that the second passivation layer has a second through hole And the third through hole.
  • ICP inductively coupled plasma
  • the second passivation layer 70 wraps the sidewall of the P electrode 50 and is away from the P electrode 50 Part of the area of the surface of one side of the substrate 10, as well as the sidewall of the N electrode 60 and the part of the area of the surface of the N electrode 60 away from the substrate 10, optionally, the second passivation
  • the value range of the partial width X of the surface of the P electrode and the N electrode is in the range of 2um to 4um, including the endpoint value, to prevent the contact area of the P electrode and the P electrode pad and the welding of the N electrode and the N electrode.
  • the contact area of the disk is oxidized, which affects the electrical contact performance of the P electrode and the P electrode pad and the electrical contact performance of the N electrode and the N electrode pad.
  • the composite conductive layer includes an ohmic contact layer and at least two transparent conductive layers, and the at least two transparent conductive layers are dense
  • the performance is gradually reduced along the preset direction, so that when at least two transparent conductive layers are etched, and the composite conductive layer is only located on the surface of the P-type gallium nitride layer, the composite conductive layer can be made close to the first
  • the distance between the side surface of a region and the first region gradually increases along the preset direction, thereby increasing the angle between the side surface of the composite conductive layer close to the first region and the first region, so that The value of the angle is within the range of 140 degrees to 160 degrees, so as to improve the coating of the first passivation layer on the side of the composite conductive layer after the subsequent formation of the first passivation layer, and reduce the The probability that the part of the first passivation layer located on the side surface of the composite conductive layer will break, improves the reliability of the

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Abstract

本申请提供了一种应用于显示屏的LED芯片及其制备方法，该LED芯片包括衬底、外延片、复合导电层、第一钝化层、P电极以及N电极，其中，复合导电层包括欧姆接触层和至少两层透明导电层，至少两层透明导电层的致密性沿预设方向逐渐降低，从而在对至少两层透明导电层进行刻蚀后，使得复合导电层靠近第一区域的侧面到第一区域之间的距离沿预设方向逐渐增大，进而增大复合导电层靠近第一区域的侧面与第一区域所成的角度，使其角度的取值位于140度～160度范围内，以提高后续第一钝化层形成后，第一钝化层在复合导电层该侧面的包覆性，降低第一钝化层位于复合导电层侧面的部分发生断裂的概率，提高所述LED的可靠性。

Description

一种应用于显示屏的LED芯片及其制备方法
本申请要求于2020年05月27日提交中国专利局、申请号为202010461643.1、发明名称为“一种应用于显示屏的LED芯片及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种应用于显示屏的LED芯片及其制备方法。
背景技术
LED显示屏是由LED点阵和LED PC面板组成，通过R(红色)、G(绿色)、B(蓝色)三种颜色的LED芯片的亮和灭来显示文字、图片、动画、视屏等，显示的内容可根据不同场合需要做出不同调节，其各部分组件都是模块化结构的显示器件。需要说明的是，应用于显示屏的LED芯片(即发光二极管)呈现低电流、常态反压的工作状态，当根据其反向截止特性，通过给其施加反向电压，使其处于截止状态时，具有该LED芯片的显示屏显示黑色，处于不工作的显示状态。
具体制作时，应用于显示屏的LED芯片的制作涉及MESA、ITO、PAD、PV四道工艺，而现有LED显示屏中的各LED芯片的ITO、MESA结构的倾斜角度较小，从而在对LED芯片施加常态逆向电压，使其属于反向截止状态时，容易导致LED芯片中的钝化层(即PV层)出现开裂现象，造成LED显示屏出现光线衰弱以及漏光等现象，因此，现有LED芯片的可靠性有待提高。
发明内容
有鉴于此，本申请实施例提供了一种应用于显示屏的LED芯片及其制备方法，以提高LED芯片的可靠性。
为实现上述目的，本申请提供如下技术方案：
一种应用于显示屏的LED芯片，包括：
衬底；
位于所述衬底表面的外延片，所述外延片包括层叠的N型氮化镓层、有源层和P型氮化镓层，且所述外延片的第一区域曝露所述N型氮化镓层部分表面；
位于所述P型氮化镓层表面的复合导电层，所述复合导电层包括层叠的欧姆接触层和至少两层透明导电层；
位于所述复合导电层一侧的第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面；
与所述P型氮化镓层电连接的P电极以及与所述N型氮化镓层裸露区域电连接的N电极；
其中，所述至少两层透明导电层中各透明导电层的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层；所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
可选的，所述复合导电层具有第一通孔，所述第一通孔曝露所述P型氮化镓层表面，所述P电极通过所述第一通孔与所述P型氮化镓层电连接；
所述第一通孔的侧壁与所述第一通孔底部所形成的角度的取值范围为140度～160度，包括端点值。
可选的，所述欧姆接触层的厚度取值范围为50埃～200埃，包括端点值。
可选的，所述N电极覆盖所述第一钝化层部分表面。
可选的，所述N电极覆盖所述第一钝化层表面的区域占所述N电极整体区域的比例取值范围为10％～50％，包括端点值。
可选的，所述第一钝化层的材料为SiO 2、SiN x或Al 2O 3。
可选的，如果所述第一钝化层为SiN x层，所述第一钝化层的折射率取值范围为1.46～1.48，包括端点值；
如果所述第一钝化层为SiO 2层，所述第一钝化层的折射率取值范围为1.9～2.0，包括端点值；
如果所述第一钝化层为Al 2O 3层，所述第一钝化层的折射率取值范围为1.7～1.8，包括端点值。
可选的，还包括：
位于所述复合导电层背离所述衬底一侧的第二钝化层，所述第二钝化层完全覆盖所述外延片和所述复合导电层，所述第二钝化层具有第二通孔和第三通孔，所述第二通孔曝露所述P电极部分表面，所述第三通孔曝露所述N电极部分表面；
通过所述第二通孔与所述P电极电连接的P电极焊盘；
通过所述第三通孔与所述N电极电连接的N电极焊盘。
一种应用于显示屏的LED芯片的制备方法，包括：
在衬底上形成外延片，所述外延片包括层叠的N型氮化镓层、有源层和P型氮化镓层，且所述外延片的第一区域曝露所述N型氮化镓层部分表面；
在所述P型氮化镓层表面形成复合导电层，所述复合导电层包括层叠的欧姆接触层和至少两层透明导电层；
在所述复合导电层背离所述外延片一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面；
在所述P型氮化镓层背离所述有源层一侧形成与所述P型氮化镓层电连接的P电极；
在所述第一区域形成与所述N型氮化镓层裸露区域电连接的N电极；
其中，所述至少两层透明导电层中各透明导电层的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层；所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
可选的，在所述P型氮化镓层表面形成复合导电层包括：
利用溅射沉积工艺，在所述P型氮化镓层表面形成欧姆接触层；
利用电子束蒸镀工艺，在所述欧姆接触层背离所述P型氮化镓层一侧表面形成至少两层透明导电层；
其中，所述至少两层透明导电层中各透明导电层形成时的蒸镀速率沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层。
可选的，所述至少两层透明导电层中各透明导电层形成时的蒸镀速率取值范围为0.5A/S～2.5A/S，包括端点值。
可选的，利用溅射沉积工艺，在所述P型氮化镓层表面形成欧姆接触层包括：
利用溅射沉积工艺在所述P型氮化镓层表面形成接触层；
对所述接触层进行快速退火再结晶，使得所述接触层与所述P型氮化镓层形成欧姆接触，以在所述P型氮化镓层表面形成欧姆接触层。
可选的，所述接触层形成过程中的射频功率取值范围为400W～800W，包括端点值；电压功率取值范围为50W～200W，包括端点值；
所述接触层的退火温度取值范围为400℃～600℃，包括端点值。
可选的，还包括：
对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，形成第一通孔，所述第一通孔曝露所述P型氮化镓层部分表面，所述P电极通过所述第一通孔与所述P型氮化镓层电连接；
所述第一通孔的侧壁与所述第一通孔底部所形成的角度的取值范围为140度～160度。
可选的，对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，形成第一通孔包括：
在所述至少两层透明导电层背离所述欧姆接触层一侧形成光刻胶图形；
以所述光刻胶图形为掩模，先利用第一浓度的刻蚀液对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，再利用第二浓度的刻蚀液所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，以形成第一通孔，且所述第一通孔的侧壁与所述第一通孔的底部形成的角度的取值范围为140度～160度；
所述第一浓度大于所述第二浓度。
可选的，在所述复合导电层背离所述外延片一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面包括：
在所述复合导电层背离所述P型氮化镓层一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面以及所述N型氮化镓层裸露表面；
对所述第一钝化层对应所述N型氮化镓层裸露表面部分区域进行刻蚀，使得所述第一钝化层覆盖所述N型氮化镓层裸露区域部分表面，裸露所述N型氮化镓层裸露区域部分表面。
可选的，所述第一钝化层的沉积温度为280℃～340℃，包括端点值，沉积气体包括SiH 4和N 2O，SiH 4和N 2O气体比例的取值范围为0.1～0.4，包括端点值。
可选的，在衬底上形成外延片包括：
在衬底上形成外延结构，所述外延结构包括层叠的N型氮化镓层、有源层和P型氮化镓层；
利用刻蚀气体对所述外延结构进行刻蚀，裸露所述N型氮化镓层第一区域的表面，形成外延片；
其中，所述刻蚀气体包括：Cl 2、Ar和O 2。
可选的，所述刻蚀气体中，O 2的比例取值范围为10％～30％，包括端 点值；所述刻蚀气体中，Cl 2的比例取值范围为60％～80％，包括端点值。
本申请实施例所提供的应用于显示屏的LED芯片中，所述LED芯片包括衬底、外延片、复合导电层、第一钝化层、P电极以及N电极，其中，所述复合导电层包括欧姆接触层和至少两层透明导电层，所述至少两层透明导电层的致密性沿预设方向逐渐降低，从而在对至少两层透明导电层进行刻蚀，所述复合导电层仅位于所述P型氮化镓层表面时，可以使得所述复合导电层靠近所述第一区域的侧面到所述第一区域之间的距离沿预设方向逐渐增大，进而增大所述复合导电层靠近所述第一区域的侧面与所述第一区域所成的角度，使其角度的取值位于140度～160度范围内，以提高后续所述第一钝化层形成后，所述第一钝化层在所述复合导电层该侧面的包覆性，降低所述第一钝化层位于所述复合导电层侧面的部分发生断裂的概率，提高所述LED的可靠性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一个实施例所提供的LED芯片的结构示意图；
图2为本申请另一个实施例所提供的LED芯片的结构示意图；
图3为本申请一个实施例所提供的LED芯片的制备方法的流程图；
图4-图16为本申请一个实施例所提供的LED芯片的制备方法中各工艺步骤完成后的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本 申请还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。
正如背景技术部分所述，现有LED芯片的可靠性有待提高。
而且，随着小间距显示屏技术的发展，LED显示屏中蓝绿芯片尺寸越来越小，P电极与N电极之间的间距越来越小，从而在给LED芯片施加逆向电压时，LED芯片中的逆向电场越来越大，造成LED芯片中的PV层(即钝化层)在ITO(透明导电层)及MESA的边缘陡坡处更容易出现开裂披覆性等问题，导致ITO出现浮起等现象，使得在户外应用场景时，LED显示屏工作在常态逆压的情况下，更容易出现光衰、漏电等现象。
有鉴于此，本申请实施例提供了一种应用于显示屏的LED芯片以及制备方法，以提高LED芯片的可靠性，下面结合附图对本申请实施例所提供的应用于显示屏的LED芯片以及制备方法进行描述。
如图1所示，本申请实施例提供的应用于显示屏的LED芯片，包括：
衬底10，可选的，所述衬底10为蓝宝石衬底；
位于所述衬底10表面的外延片20，所述外延片20包括层叠的N型氮化镓层21、有源层22和P型氮化镓层23，且所述外延片20的第一区域曝露所述N型氮化镓层21部分表面；
位于所述P型氮化镓层23表面的复合导电层30，所述复合导电层30包括层叠的欧姆接触层31和至少两层透明导电层32；
位于所述复合导电层30一侧的第一钝化层40，所述第一钝化层40覆盖所述复合导电层30表面且延伸至覆盖所述N型氮化镓层21裸露区域部分表面；
与所述P型氮化镓层23电连接的P电极50以及与所述N型氮化镓层21裸露区域电连接的N电极60；
其中，所述至少两层透明导电层32中各透明导电层的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层；所述复合导电层30中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
需要说明的是，在本申请实施例中，所述外延片靠近所述第一区域的侧壁与所述N型氮化镓层曝露的表面形成的角度的取值范围为135度～160度，包括端点值，以提高后续所述第一钝化层在所述外延层侧面的包覆性。
在本申请实施例中，所述复合导电层包括欧姆接触层和至少两层透明导电层，所述至少两层透明导电层的致密性沿预设方向逐渐降低，从而仅 在所述P型氮化镓层表面形成所述复合导电层时，可以使得所述复合导电层靠近所述第一区域的侧面到所述第一区域之间的距离沿预设方向逐渐增大，从而增大所述复合导电层靠近所述第一区域的侧面与所述第一区域所成的角度，使其角度的取值位于140度～160度范围内，以提高后续所述第一钝化层形成后，所述第一钝化层在所述复合导电层该侧面的包覆性，降低所述第一钝化层位于所述复合导电层侧面的部分发生断裂的概率，提高所述LED的可靠性。
在上述实施例的基础上，在本申请一个实施例中，所述复合导电层30包括：
位于所述P型氮化镓层23表面的欧姆接触层31；
位于所述欧姆接触层31背离所述P型氮化镓层23一侧的表面的至少两层透明导电层32，至少两层透明导电层32包括位于所述欧姆接触层31表面的第一透明导电层321以及位于第一透明导电层321表面的第二透明导电层322；
其中，所述至少两层透明导电层中各透明导电层形成时的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层，即所述第一透明导电层的致密性大于所述第二透明导电层的致密性。
具体的，在本申请的一个实施例中，所述欧姆接触层、所述第一透明导电层和所述第二透明导电层的材料为ITO，所述欧姆接触层的形成工艺为溅射沉积工艺，所述第一透明导电层和所述第二透明导电层的形成工艺为电子束蒸镀工艺，但本申请对此并不做限定，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述欧姆接触层的厚度取值范围为50埃～200埃，包括端点值，以使得所述复合导电层与所述外延片形成良好的欧姆接触。
需要说明的是，在本申请实施例中，所述第一透明导电层和所述第二透明导电层的致密性沿着预设方向逐渐降低，可以使得所述复合导电层靠近所述第一区域的侧面到所述第一区域之间的距离沿预设方向逐渐增大，有利于所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成较大的角度，提高后续所述第一钝化层形成后，所述第一钝化层在所述复合导电层该侧面的包覆性。
在本申请另一个实施例中，所述复合导电层还可以包括第三透明导电层、第四透明导电层等，使得所述复合导电层的侧面倾斜过渡更平缓，但本申请对此并不做限定，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述复合导电层30 具有第一通孔，所述第一通孔曝露所述P型氮化镓层23表面，所述P电极50通过所述第一通孔与所述P型氮化镓层23电连接。
需要说明的是，在上述实施例中，所述P电极通过所述第一通孔与所述P型氮化镓层23电连接，可以使得所述P电极直接与所述外延片的P型氮化镓层电连接，有利于在实际工作中，所述LED芯片中所述P电极的电流直接流入所述外延片。但本申请对此并不做限定，在本申请的其他实施例中，如图2所示，所述P电极还可以通过所述复合导电层与所述外延片的P型氮化镓层电连接，具体视情况而定。
可选的，在本申请的一个实施例中，所述第一通孔的侧壁与所述第一通孔底部所形成的角度的取值范围为140度～160度，包括端点值，以使得所述P电极在所述第一通孔侧壁的包覆性较好，降低所述P电极发生断裂的概率。
需要说明的是，在本申请实施例中，所述复合导电层与所述P电极之间具有第一钝化层，所述第一钝化层具有高致密性，以使得所述第一钝化层作为电流阻挡层，改变所述P电极与所述N电极之间的电流通路，增加P电极与N电极之间的间距，降低常态逆压下所述LED芯片中的逆压电场，提高所述LED芯片常态逆压下的可靠性。
可选的，在上述实施例的基础上，在本申请一个实施例中，所述第一钝化层的材料为SiO 2、SiN x或Al 2O 3，本申请对此并不做限定，在本申请其他的实施例中，所述第一钝化层的材料还可以为其他材料，具体视情况而定。
具体的，在上述实施例的基础上，在本申请的一个实施例中，如果所述第一钝化层为SiN x层，所述第一钝化层的折射率取值范围为1.46～1.48，包括端点值，以保证所述第一钝化层具有较高的致密性；如果所述第一钝化层为SiO 2层，所述第一钝化层的折射率取值范围为1.9～2.0，包括端点值，以保证所述第一钝化层具有较高的致密性；如果所述第一钝化层为Al 2O 3层，所述第一钝化层的折射率取值范围为1.7～1.8，包括端点值，以保证所述第一钝化层具有较高的致密性。
在上述实施例的基础上，在本申请一个实施例中，所述N电极覆盖所述第一钝化层部分表面，以进一步改变所述P电极和所述N电极之间的电流通路，增大了所述P电极和所述N电极之间的间距，降低常态逆压下所述LED芯片中的逆压电场，进而提高所述LED工作在常态逆压下时的可靠性。
具体的，在上述实施例的基础上，在本申请一个实施例中，所述N电 极60覆盖所述第一钝化层40表面的区域占所述N电极整体区域的比例取值范围为10％～50％，包括端点值，但本申请对此并不做限定，具体视情况而定。
可选的，在本申请一个实施例中，所述P电极和所述N电极为金属电极，以提高LED芯片中P电极和N电极的电性能，但本申请对此并不做限定，具体视情况而定。
继续参考图1，在上述实施例的基础上，在本申请一个实施例中，所述的LED芯片还包括：
位于所述第一钝化层40背离所述衬底10一侧的第二钝化层70，所述第二钝化层70完全覆盖所述外延片20和所述复合导电层30，所述第二钝化层70具有第二通孔和第三通孔，所述第二通孔曝露所述P电极50部分表面，所述第三通孔曝露所述N电极60部分表面；
通过所述第二通孔与所述P电极50电连接的P电极焊盘；
通过所述第三通孔与所述N电极60电连接的N电极焊盘。
在上述实施例的基础上，在本申请一个实施例中，所述第二钝化层的材料为SiO 2、SiN x或Al 2O 3，本申请对此并不做限定，在本申请其他的实施例中，所述第二钝化层的材料还可以为其他材料，具体视情况而定。
需要说明的是，继续参考图1，在上述实施例的基础上，在本申请一个实施例中，所述第二钝化层70包裹所述P电极50的侧壁和所述P电极50背离所述衬底10一侧表面的部分面积，以及所述N电极60的侧壁和所述N电极60背离所述衬底10一侧表面的部分面积，可选的，所述第二钝化层包裹所述P电极和所述N电极表面的部分宽度X的取值范围为2um～4um，包括端点值，以防止所述P电极和P电极焊盘的接触区域以及N电极和N电极焊盘的接触区域被氧化，影响P电极和P电极焊盘的电接触性能以及N电极和N电极焊盘的电接触性能。
综上所述，本申请实施例提供的应用于显示屏的LED芯片中，所述复合导电层包括欧姆接触层和至少两层透明导电层，所述至少两层透明导电层的致密性沿预设方向逐渐降低，从而仅在所述P型氮化镓层表面形成所述复合导电层时，可以使得所述复合导电层靠近所述第一区域的侧面到所述第一区域之间的距离沿预设方向逐渐增大，从而增大所述复合导电层靠近所述第一区域的侧面与所述第一区域所成的角度，使其角度的取值位于140度～160度范围内，以提高后续所述第一钝化层形成后，所述第一钝化层在所述复合导电层该侧面的包覆性，降低所述第一钝化层位于所述复合导电层侧面的部分发生断裂的概率，提高所述LED的可靠性。
相应的，本申请实施例还提供了一种应用于显示屏的LED芯片的制备方法，用于制作上述任一实施例所提供的应用于显示屏的LED芯片。
具体的，如图3所示，本申请实施例所提供的应用于显示屏的LED芯片的制备方法包括：
S301：如图4所示，在衬底10上形成外延片20，所述外延片20包括层叠的N型氮化镓层21、有源层22和P型氮化镓层23，且所述外延片20的第一区域曝露所述N型氮化镓层21部分表面。
在上述实施例的基础上，在本申请一个实施例中，所述衬底为蓝宝石衬底，但本申请对此并不做限定，在本申请其他实施例中，所述衬底还可以为其他材料的衬底，具体视情况而定。
需要说明的是，在本申请实施例中，所述外延片靠近所述第一区域的侧壁与所述N型氮化镓层曝露的表面形成的角度的取值范围为135度～160度，包括端点值，以提高后续所述第一钝化层在所述外延层侧面的包覆性。
在上述实施例的基础上，在本申请一个实施例中，在衬底上形成外延片包括：
如图5所示，在衬底10上形成外延结构2，所述外延结构2包括层叠的N型氮化镓层21、有源层22和P型氮化镓层23；
如图6所示，利用光刻工艺和干法刻蚀工艺，对所述外延结构2的第一区域进行刻蚀，使得所述外延结构2裸露所述N型氮化镓层21第一区域的表面，其中，所述外延结构2中裸露的所述N型氮化镓层21的第一区域用于后续形成与所述N型氮化镓层电连接的N电极。
可选的，在本申请的一个实施例中，对所述外延结构2的第一区域进行刻蚀包括：利用电感耦合等离子体(ICP)工艺，对所述外延结构2的第一区域进行刻蚀，所述刻蚀气体包括：Cl 2、Ar和O 2。但本申请对此并不做限定，具体视情况而定。
需要说明的是，在本申请实施例中，所述第一区域的刻蚀深度可以为所述P型氮化镓层与所述有源层的厚度之和，也可以大于所述P型氮化镓层与所述有源层的厚度之和，且小于所述P型氮化镓层、所述有源层和所述N型氮化镓层的厚度之和，本申请对此并不做限定，只要曝露所述N型氮化镓层位于所述第一区域的部分表面，以便于后续形成与所述N型氮化镓层电连接的N电极即可。
在上述实施例的基础上，在本申请一个实施例中，所述刻蚀气体中，O 2的比例取值范围为10％～30％，包括端点值；所述刻蚀气体中，Cl 2的比 例取值范围为60％～80％，包括端点值，本申请对此并不做限定，具体视情况而定。可选的，在本申请的一个具体实施例中，所述刻蚀气体Cl 2、Ar和O 2的比例为5:1:2，使得所述外延片靠近所述第一区域的侧壁的倾斜度较大。
在上述实施例的基础上，在本申请的一个实施例中，所述外延片靠近所述第一区域的侧壁与所述外延片裸露所述N型氮化镓层表面区域所成的角度取值范围为135度～160度，包括端点值，但本申请对此并不做限定，具体视情况而定。
S302：如图7所示，在所述P型氮化镓层23表面形成复合导电层30，所述复合导电层30包括层叠的欧姆接触层31和至少两层透明导电层32；其中，所述至少两层透明导电层32中各透明导电层的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层31指向所述透明导电层；所述复合导电层30中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
在上述实施例的基础上，在本申请一个实施例中，在所述P型氮化镓层表面形成复合导电层包括：
利用溅射沉积工艺，在所述P型氮化镓层23表面形成欧姆接触层31，可选的，所述欧姆接触层的厚度取值范围为50埃～200埃，包括端点值；
利用电子束蒸镀工艺，在所述欧姆接触层31背离所述P型氮化镓层23一侧表面形成至少两层透明导电层32；
其中，所述至少两层透明导电层中各透明导电层形成时的蒸镀速率沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层。
在上述实施例的基础上，在本申请一个实施例中，利用溅射沉积工艺，在所述P型氮化镓层表面形成欧姆接触层包括：
利用溅射沉积工艺在所述P型氮化镓层表面形成接触层；
对所述接触层进行快速退火再结晶，使得所述接触层与所述P型氮化镓层形成欧姆接触，以在所述P型氮化镓层表面形成欧姆接触层。
在上述实施例的基础上，在本申请一个实施例中，所述接触层形成过程中的射频功率取值范围为400W～800W，包括端点值；电压功率取值范围为50W～200W，包括端点值；所述接触层的退火温度取值范围为400℃～600℃，包括端点值，本申请对此并不做限定，具体视情况而定。
具体的，在上述任一实施例基础上，在本申请的一个实施例中，如图8所示，利用电子束蒸镀工艺，在所述欧姆接触层31背离所述P型氮化镓层23一侧表面形成至少两层透明导电层32包括：在所述欧姆接触层31 表面形成第一透明导电层321，在第一透明导电层321表面形成第二透明导电层322，所述第二透明导电层的蒸镀速率小于所述第一透明导电层的蒸镀速率。可选的，所述第一透明导电层的蒸镀速率为2A/S(即为每秒蒸镀2A厚度的第一透明导电层)，第二透明导电层的蒸镀速率为1A/S(即为每秒蒸镀1A厚度的第二透明导电层)，但本申请对此并不做限定，具体视情况而定。
在本申请另一个实施例中，所述复合导电层还可以包括第三透明导电层、第四透明导电层等，但本申请对此并不做限定，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述至少两层透明导电层中各透明导电层形成时的蒸镀速率取值范围为0.5A/S～2.5A/S，包括端点值，即所述至少两层透明导电层中与所述欧姆接触层直接接触的一层透明导电层的蒸镀速率不大于2.5A/S，所述至少两层透明导电层中距离所述欧姆接触层最远的一层透明导电层的蒸镀速率不小于0.5A/S。其中，A/S表示埃/秒(即为每秒蒸镀透明导电层的厚度)。
需要说明的是，在本申请实施例中，所述第一透明导电层和所述第二透明导电层的蒸镀速率沿着预设方向逐渐降低，可以使得后续对所述复合导电层刻蚀，使得所述复合导电层仅位于所述外延片的P型氮化镓层表面时，所述复合导电层靠近所述第一区域的侧面到所述第一区域之间的距离沿预设方向逐渐增大，有利于所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成较大的角度，提高后续所述第一钝化层形成后，所述第一钝化层在所述复合导电层该侧面的包覆性。
具体的，在本申请的一个实施例中，所述欧姆接触层、所述第一透明导电层和所述第二透明导电层的材料为ITO，本申请对此并不做限定，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，在所述P型氮化镓层23表面形成复合导电层30包括：
如图9所示，在所述外延片20背离所述衬底10一侧形成复合导电结构3，所述复合导电结构包括欧姆接触层和至少两层透明导电层，且完全覆盖所述外延片背离所述衬底一侧表面；
如图10所示，在所述复合导电结构3背离所述外延片20一侧表面涂抹一层光刻胶，形成第一光刻胶层，对所述第一光刻胶层进行曝光、显影以及坚膜后，形成第一光刻胶图形33；
如图11所示，以所述第一光刻胶图形为掩膜，对所述复合导电结构进行刻蚀，去除所述复合导电结构位于所述N型氮化镓层裸露表面的部分以 及所述复合导电结构位于所述外延片朝向所述第一区域侧面的部分，仅保留所述复合导电结构位于所述P型氮化镓层表面的部分，形成复合导电层，且所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
可选的，在本申请的一个实施例中，对所述第一光刻胶层坚膜温度的取值范围为80℃～100℃，包括端点值。
在上述实施例的基础上，在本申请一个实施例中，如图12所示，所述的制备方法还包括：
对所述欧姆接触层31和所述至少两层透明导电层32组成的结构进行刻蚀，形成第一通孔，所述第一通孔曝露所述P型氮化镓层23部分表面，所述P电极50通过所述第一通孔与所述P型氮化镓层23电连接；
其中，所述第一通孔的侧壁与所述第一通孔底部所形成的角度的取值范围为140度～160度，包括端点值，以使得后续形成的所述P电极在所述第一通孔侧壁的包覆性较好，降低所述P电极发生断裂的概率。
需要说明的是，在上述实施例中，所述P电极通过所述第一通孔与所述P型氮化镓层23电连接，可以使得所述P电极直接与所述外延片的P型氮化镓层电连接，有利于在实际工作中，所述LED芯片中所述P电极的电流直接流入所述外延片，但本申请对此并不做限定，在本申请的其他实施例中。
具体的，在上述实施例的基础上，在本申请一个实施例中，对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，形成第一通孔包括：
在所述至少两层透明导电层背离所述欧姆接触层一侧形成第二光刻胶层，对所述第二光刻胶层进行曝光、显影以及坚膜后，形成光刻胶图形；
以所述光刻胶图形为掩模，先利用第一浓度的刻蚀液对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，再利用第二浓度的刻蚀液所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，以形成第一通孔，且所述第一通孔的侧壁与所述第一通孔的底部形成的角度的取值范围为140度～160度，包括端点值；
其中，所述第一浓度大于所述第二浓度。
需要说明的是，在上述实施例中，先利用浓度较高的第一浓度的刻蚀液对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，以利用较快的刻蚀速率刻蚀所述欧姆接触层和所述至少两层透明导电层形成的结构，且确保将所述欧姆接触层和至少两层透明导电层形成的结构被刻 穿，以曝露所述P型氮化镓层部分表面，避免出现刻蚀残留，再利用浓度较低的第二浓度的刻蚀液对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，以使得所述第一通孔的侧壁具有较大的倾斜率，进而使得所述第一通孔的侧壁与所述第一通孔的底部形成较大的角度。
S303：如图13所示，在所述复合导电层30背离所述外延片20一侧形成第一钝化层40，所述第一钝化层40覆盖所述复合导电层30表面且延伸至覆盖所述N型氮化镓层21裸露区域部分表面。
在上述实施例的基础上，在本申请一个实施例中，在所述复合导电层背离所述外延片一侧形成第一钝化层包括：采用PECVD设备在所述复合导电层背离所述外延片一侧沉积第一钝化层，本申请对此并不做限定，在本申请其他实施例中，还可以采用其他方式在所述复合导电层背离所述外延片一侧形成第一钝化层，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述第一钝化层的材料为SiO 2、SiN x或Al 2O 3，本申请对此并不做限定，在本申请其他的实施例中，所述第一钝化层的材料还可以为其他材料，具体视情况而定。
具体的，在上述实施例的基础上，在本申请的一个实施例中，如果所述第一钝化层为SiN x层，所述第一钝化层的折射率取值范围为1.46～1.48，包括端点值，以保证所述第一钝化层具有较高的致密性；如果所述第一钝化层为SiO 2层，所述第一钝化层的折射率取值范围为1.9～2.0，包括端点值，以保证所述第一钝化层具有较高的致密性；如果所述第一钝化层为Al 2O 3层，所述第一钝化层的折射率取值范围为1.7～1.8，包括端点值，以保证所述第一钝化层具有较高的致密性。
在上述实施例的基础上，在本申请一个实施例中，在所述复合导电层背离所述外延片一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面包括：
在所述复合导电层背离所述P型氮化镓层一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面以及所述N型氮化镓层裸露表面；
在所述第一钝化层背离所述复合导电层一侧表面形成第三光刻胶层，对所述三光刻胶层进行曝光、显影以及坚膜后，形成第三光刻胶图形；
以所述第三光刻胶图形为掩膜版，对所述第一钝化层对应所述N型氮化镓层裸露表面部分区域进行刻蚀，使得所述第一钝化层覆盖所述N型氮化镓层裸露区域部分表面，裸露所述N型氮化镓层裸露区域部分表面。
在上述实施例的基础上，在本申请一个实施例中，所述第一钝化层的沉积温度取值范围为280℃～340℃，包括端点值，以利用高温沉积所述第 一钝化层，使得所述第一钝化层具有较高的致密性；沉积气体包括SiH 4和N 2O，沉积气体中SiH 4和N 2O气体比例的取值范围为0.1～0.4，包括端点值，但本申请对此并不做限定，具体视情况。
如图14所示，在上述实施例中，如果所述复合导电层30还包括所述第一通孔，在所述复合导电层背离所述外延片一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面包括：
在所述复合导电层背离所述P型氮化镓层一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面、所述第一通孔区域以及所述N型氮化镓层裸露表面；
对所述第一钝化层40对应所述第一通孔区域以及所述第一钝化层40对应所述N型氮化镓层裸露表面部分区域进行刻蚀，使得所述第一钝化层40对应所述第一通孔区域裸露所述P型氮化镓层23，且所述第一钝化层40覆盖所述N型氮化镓层21裸露区域部分表面，裸露所述N型氮化镓层21裸露区域部分表面包括：
在所述第一钝化层背离所述复合导电层一侧表面涂抹一层光刻胶，形成第四光刻胶层，对所述四光刻胶层进行曝光、显影以及坚膜后，形成第四光刻胶图形；以所述第四光刻胶图形为掩膜版，先采用第一浓度的BOE蚀刻液蚀刻，对所述第一钝化层对应所述第一通孔区域以及所述第一钝化层对应所述N型氮化镓层裸露表面部分区域进行刻蚀；再采用第二浓度的BOE蚀刻液蚀刻，对所述第一钝化层对应所述第一通孔区域以及所述第一钝化层对应所述N型氮化镓层裸露表面部分区域进行刻蚀，使得所述第一钝化层对应所述第一通孔区域裸露所述P型氮化镓层，且所述第一钝化层覆盖所述N型氮化镓层裸露区域部分表面，裸露所述N型氮化镓层裸露区域部分表面；其中，第一浓度高于所述第二浓度。
在上述实施例的基础上，在本申请一个实施例中，所述第一浓度的BOE蚀刻液和所述第二浓度的BOE蚀刻液由HF溶液以及NH 4F溶液混合而成，可选的，第一浓度的BOE蚀刻液的浓度取值范围为1:5～1:10，包括端点值，第二浓度的BOE蚀刻液的浓度取值范围为1:10～1:20，包括端点值。
可选的，在上述实施例中，所述第一浓度的BOE蚀刻液中HF溶液和NH 4F溶液的浓度比例为1:5，所述第二浓度的BOE蚀刻液中HF溶液和NH 4F溶液的浓度比例为1:20，但本申请对此并不做限定，具体视情况而定。
S304：如图15所示，在所述P型氮化镓层23背离所述有源层22一侧形成与所述P型氮化镓层23电连接的P电极50。
需要说明的是，在本申请实施例中，所述复合导电层与所述P电极之间具有第一钝化层，所述第一钝化层具有高致密性，以使得所述第一钝化层作为电流阻挡层，改变所述P电极与后续形成的所述N电极之间的电流通路，增加P电极与N电极之间的间距，降低常态逆压下所述LED芯片中的逆压电场，提高所述LED芯片常态逆压下的可靠性。
S305：继续参考图15，在所述第一区域形成与所述N型氮化镓层21裸露区域电连接的N电极60。
继续参考图15，在上述实施例的基础上，在本申请一个实施例中，所述N电极覆盖所述第一钝化层部分表面，以进一步改变所述P电极和所述N电极之间的电流通路，增大了所述P电极和所述N电极之间的间距，降低常态逆压下所述LED芯片中的逆压电场，进而提高所述LED工作在常态逆压下时的可靠性。
具体的，在上述实施例的基础上，在本申请一个实施例中，所述N电极60覆盖所述第一钝化层40表面的区域占所述N电极整体区域的比例取值范围为10％～50％，包括端点值，但本申请对此并不做限定，具体视情况而定。
可选的，在本申请一个实施例中，所述P电极和所述N电极为金属电极，以提高LED芯片中P电极和N电极的电性能，但本申请对此并不做限定，具体视情况而定。
具体的，在上述实施例的基础上，在本申请一个实施例中，在所述P型氮化镓层背离所述有源层一侧形成与所述P型氮化镓层电连接的P电极，在所述第一区域形成与所述N型氮化镓层裸露区域电连接的N电极包括：
在所述第一钝化层背离所述复合导电层一侧表面涂抹一层光刻胶，形成第五光刻胶层，所述第五光刻胶层覆盖所述外延片和所述复合导电层；
对所述第五光刻胶层进行曝光、后烘以及显影后，形成第五光刻胶图形；
以所述第五光刻胶图形为掩膜，在所述第一通孔处蒸镀所述P电极，使得所述P型氮化镓层电连接的P电极，在所述第一区域蒸镀所述N电极，使得在所述第一区域形成与所述N型氮化镓层裸露区域电连接的N电极。
如图16所示，在上述实施例的基础上，在本申请一个实施例中，所述的制备方法还包括：
在所述第一钝化层40背离所述衬底10一侧形成第二钝化层70，所述第二钝化层70完全覆盖所述外延片20和所述复合导电层30，所述第二钝化层70具有第二通孔和第三通孔，所述第二通孔曝露所述P电极50部分表面，所述第三通孔曝露所述N电极60部分表面；
通过所述第二通孔与所述P电极50电连接的P电极焊盘；
通过所述第三通孔与所述N电极60电连接的N电极焊盘。
在上述实施例的基础上，在本申请一个实施例中，在所述第一钝化层背离所述外延片一侧形成第二钝化层包括：采用PECVD设备在所述复合导电层背离所述外延片一侧沉积第二钝化层，本申请对此并不做限定，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述第二钝化层的材料为SiO 2、SiN x或Al 2O 3，本申请对此并不做限定，在本申请其他的实施例中，所述第二钝化层的材料还可以为其他材料，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述第二钝化层的沉积温度取值范围为200℃～275℃，包括端点值，沉积气体包括SiH 4和N 2O，沉积气体中SiH 4和N 2O气体比例的取值范围为0.1～0.4，包括端点值，本申请对此并不做限定，具体视情况。
具体的，在上述实施例的基础上，在本申请一个实施例中，所述第二钝化层具有第二通孔和第三通孔包括：
在所述第二钝化层背离所述复合导电层一侧形成第六光刻胶层，对所述第六光刻胶层进行曝光、显影以及坚膜后，形成第六光刻胶图形；
以所述第六光刻胶图形为掩膜，利用电感耦合等离子体(ICP)刻蚀工艺，对所述第二钝化层进行刻蚀，使得所述第二钝化层具有第二通孔和第三通孔。
需要说明的是，继续参考图16，在上述实施例的基础上，在本申请一个实施例中，所述第二钝化层70包裹所述P电极50的侧壁和所述P电极50背离所述衬底10一侧表面的部分面积，以及所述N电极60的侧壁和所述N电极60背离所述衬底10一侧表面的部分面积，可选的，所述第二钝化层包裹所述P电极和所述N电极表面的部分宽度X的取值范围为2um～4um，包括端点值，以防止所述P电极和P电极焊盘的接触区域以及N电极和N电极焊盘的接触区域被氧化，影响P电极和P电极焊盘的电接触性能以及N电极和N电极焊盘的电接触性能。
综上所述，本申请实施例提供的应用于显示屏的LED芯片的制备方法中，所述复合导电层包括欧姆接触层和至少两层透明导电层，所述至少两 层透明导电层的致密性沿预设方向逐渐降低，从而在对至少两层透明导电层进行刻蚀，所述复合导电层仅位于所述P型氮化镓层表面时，可以使得所述复合导电层靠近所述第一区域的侧面到所述第一区域之间的距离沿预设方向逐渐增大，从而增大所述复合导电层靠近所述第一区域的侧面与所述第一区域所成的角度，使其角度的取值位于140度～160度范围内，以提高后续所述第一钝化层形成后，所述第一钝化层在所述复合导电层该侧面的包覆性，降低所述第一钝化层位于所述复合导电层侧面的部分发生断裂的概率，提高所述LED的可靠性。
本说明书中各个部分采用并列和递进相结合的方式描述，每个部分重点说明的都是与其他部分的不同之处，各个部分之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (19)

  1. 一种应用于显示屏的LED芯片，其特征在于，包括：
    衬底；
    位于所述衬底表面的外延片，所述外延片包括层叠的N型氮化镓层、有源层和P型氮化镓层，且所述外延片的第一区域曝露所述N型氮化镓层部分表面；
    位于所述P型氮化镓层表面的复合导电层，所述复合导电层包括层叠的欧姆接触层和至少两层透明导电层；
    位于所述复合导电层一侧的第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面；
    与所述P型氮化镓层电连接的P电极以及与所述N型氮化镓层裸露区域电连接的N电极；
    其中，所述至少两层透明导电层中各透明导电层的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层；所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
  2. 根据权利要求1所述的LED芯片，其特征在于，所述复合导电层具有第一通孔，所述第一通孔曝露所述P型氮化镓层表面，所述P电极通过所述第一通孔与所述P型氮化镓层电连接；
    所述第一通孔的侧壁与所述第一通孔底部所形成的角度的取值范围为140度～160度，包括端点值。
  3. 根据权利要求1所述的LED芯片，其特征在于，所述欧姆接触层的厚度取值范围为50埃～200埃，包括端点值。
  4. 根据权利要求1所述的LED芯片，其特征在于，所述N电极覆盖所述第一钝化层部分表面。
  5. 根据权利要求4所述的LED芯片，其特征在于，所述N电极覆盖所述第一钝化层表面的区域占所述N电极整体区域的比例取值范围为10％～50％，包括端点值。
  6. 根据权利要求1所述的LED芯片，其特征在于，所述第一钝化层的材料为SiO 2、SiN x或Al 2O 3。
  7. 根据权利要求6所述的LED芯片，其特征在于，如果所述第一钝化层为SiN x层，所述第一钝化层的折射率取值范围为1.46～1.48，包括端点值；
    如果所述第一钝化层为SiO 2层，所述第一钝化层的折射率取值范围为 1.9～2.0，包括端点值；
    如果所述第一钝化层为Al 2O 3层，所述第一钝化层的折射率取值范围为1.7～1.8，包括端点值。
  8. 根据权利要求1所述的LED芯片，其特征在于，还包括：
    位于所述复合导电层背离所述衬底一侧的第二钝化层，所述第二钝化层完全覆盖所述外延片和所述复合导电层，所述第二钝化层具有第二通孔和第三通孔，所述第二通孔曝露所述P电极部分表面，所述第三通孔曝露所述N电极部分表面；
    通过所述第二通孔与所述P电极电连接的P电极焊盘；
    通过所述第三通孔与所述N电极电连接的N电极焊盘。
  9. 一种应用于显示屏的LED芯片的制备方法，其特征在于，包括：
    在衬底上形成外延片，所述外延片包括层叠的N型氮化镓层、有源层和P型氮化镓层，且所述外延片的第一区域曝露所述N型氮化镓层部分表面；
    在所述P型氮化镓层表面形成复合导电层，所述复合导电层包括层叠的欧姆接触层和至少两层透明导电层；
    在所述复合导电层背离所述外延片一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面；
    在所述P型氮化镓层背离所述有源层一侧形成与所述P型氮化镓层电连接的P电极；
    在所述第一区域形成与所述N型氮化镓层裸露区域电连接的N电极；
    其中，所述至少两层透明导电层中各透明导电层的致密性沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层；所述复合导电层中靠近所述第一区域的侧面与所述第一区域形成的角度的取值范围为140度～160度，包括端点值。
  10. 根据权利要求9所述的制备方法，其特征在于，在所述P型氮化镓层表面形成复合导电层包括：
    利用溅射沉积工艺，在所述P型氮化镓层表面形成欧姆接触层；
    利用电子束蒸镀工艺，在所述欧姆接触层背离所述P型氮化镓层一侧表面形成至少两层透明导电层；
    其中，所述至少两层透明导电层中各透明导电层形成时的蒸镀速率沿预设方向逐渐降低，所述预设方向由所述欧姆接触层指向所述透明导电层。
  11. 根据权利要求10所述的制备方法，其特征在于，所述至少两层透 明导电层中各透明导电层形成时的蒸镀速率取值范围为0.5A/S～2.5A/S，包括端点值。
  12. 根据权利要求10所述的制备方法，其特征在于，利用溅射沉积工艺，在所述P型氮化镓层表面形成欧姆接触层包括：
    利用溅射沉积工艺在所述P型氮化镓层表面形成接触层；
    对所述接触层进行快速退火再结晶，使得所述接触层与所述P型氮化镓层形成欧姆接触，以在所述P型氮化镓层表面形成欧姆接触层。
  13. 根据权利要求12所述的制备方法，其特征在于，所述接触层形成过程中的射频功率取值范围为400W～800W，包括端点值；电压功率取值范围为50W～200W，包括端点值；
    所述接触层的退火温度取值范围为400℃～600℃，包括端点值。
  14. 根据权利要求10所述的制备方法，其特征在于，还包括：
    对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，形成第一通孔，所述第一通孔曝露所述P型氮化镓层部分表面，所述P电极通过所述第一通孔与所述P型氮化镓层电连接；
    所述第一通孔的侧壁与所述第一通孔底部所形成的角度的取值范围为140度～160度。
  15. 根据权利要求14所述的制备方法，其特征在于，对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，形成第一通孔包括：
    在所述至少两层透明导电层背离所述欧姆接触层一侧形成光刻胶图形；
    以所述光刻胶图形为掩模，先利用第一浓度的刻蚀液对所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，再利用第二浓度的刻蚀液所述欧姆接触层和所述至少两层透明导电层组成的结构进行刻蚀，以形成第一通孔，且所述第一通孔的侧壁与所述第一通孔的底部形成的角度的取值范围为140度～160度；
    所述第一浓度大于所述第二浓度。
  16. 根据权利要求9所述的制备方法，其特征在于，在所述复合导电层背离所述外延片一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面且延伸至覆盖所述N型氮化镓层裸露区域部分表面包括：
    在所述复合导电层背离所述P型氮化镓层一侧形成第一钝化层，所述第一钝化层覆盖所述复合导电层表面以及所述N型氮化镓层裸露表面；
    对所述第一钝化层对应所述N型氮化镓层裸露表面部分区域进行刻蚀，使得所述第一钝化层覆盖所述N型氮化镓层裸露区域部分表面，裸露 所述N型氮化镓层裸露区域部分表面。
  17. 根据权利要求16所述的制备方法，其特征在于，所述第一钝化层的沉积温度为280℃～340℃，包括端点值，沉积气体包括SiH 4和N 2O，SiH 4和N 2O气体比例的取值范围为0.1～0.4，包括端点值。
  18. 根据权利要求9所述的制备方法，其特征在于，在衬底上形成外延片包括：
    在衬底上形成外延结构，所述外延结构包括层叠的N型氮化镓层、有源层和P型氮化镓层；
    利用刻蚀气体对所述外延结构进行刻蚀，裸露所述N型氮化镓层第一区域的表面，形成外延片；
    其中，所述刻蚀气体包括：Cl 2、Ar和O 2。
  19. 根据权利要求18所述的制备方法，其特征在于，所述刻蚀气体中，O 2的比例取值范围为10％～30％，包括端点值；所述刻蚀气体中，Cl 2的比例取值范围为60％～80％，包括端点值。
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CN114447174A (zh) * 2022-01-30 2022-05-06 京东方晶芯科技有限公司 一种发光芯片外延片、检测系统及检测方法
CN114447174B (zh) * 2022-01-30 2024-04-26 京东方晶芯科技有限公司 一种发光芯片外延片、检测系统及检测方法
CN116130576A (zh) * 2023-02-24 2023-05-16 江西兆驰半导体有限公司 一种mini LED芯片接触电极及制备方法
CN117410401A (zh) * 2023-12-15 2024-01-16 江西兆驰半导体有限公司 一种led芯片及其制备方法
CN117410401B (zh) * 2023-12-15 2024-02-23 江西兆驰半导体有限公司 一种led芯片及其制备方法
CN118198240A (zh) * 2024-05-16 2024-06-14 南昌凯捷半导体科技有限公司 一种Mini-LED芯片及其制作方法

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