WO2021237784A1 - 薄膜晶体管及其制备方法、显示面板 - Google Patents

薄膜晶体管及其制备方法、显示面板 Download PDF

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Publication number
WO2021237784A1
WO2021237784A1 PCT/CN2020/094656 CN2020094656W WO2021237784A1 WO 2021237784 A1 WO2021237784 A1 WO 2021237784A1 CN 2020094656 W CN2020094656 W CN 2020094656W WO 2021237784 A1 WO2021237784 A1 WO 2021237784A1
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Prior art keywords
layer
thin film
film transistor
interlayer dielectric
oxide layer
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French (fr)
Inventor
罗传宝
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/770,827 priority Critical patent/US11217698B2/en
Publication of WO2021237784A1 publication Critical patent/WO2021237784A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technology, in particular to a thin film transistor, a preparation method thereof, and a display panel.
  • AMLCD Matrix Liquid Crystal Display
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • AMLCD devices and AMOLED display devices using Oxide TFT have high resolution, large size, and high resolution. Refresh frequency and high transmittance in the visible light range and other significant advantages, have broad application prospects in the display field.
  • Indium gallium zinc oxide (IGZO) TFT is a representative Oxide TFT, which has a variety of typical structures.
  • top-gate IGZO TFT is widely used because of its small parasitic capacitance, small number of masks used in the manufacturing process, and the ability of the gate and gate insulating layer to protect the channel region from the atmospheric environment and the plasma in the subsequent process.
  • the existing top-gate IGZO The TFT cannot balance high mobility and high uniformity, resulting in poor performance of the existing top-gate IGZO TFT and the display panel containing the same.
  • the present invention provides a thin film transistor, a preparation method thereof, and a display panel, so as to solve the technical problem of poor performance of the existing top-gate IGZO TFT and the display panel containing the same.
  • the present invention provides a thin film transistor, the thin film transistor includes an active layer, the active layer includes a plurality of stacked structures, each of the stacked structures includes:
  • N-layer indium oxide layer where N is an integer greater than 1;
  • a gallium oxide layer, the gallium oxide layer is disposed on the Nth indium oxide layer;
  • a zinc oxide layer, the zinc oxide layer is disposed on the gallium oxide layer.
  • the thin film transistor further includes:
  • a light-shielding layer, the light-shielding layer is provided on the substrate;
  • a buffer layer is provided on the substrate and covers the light-shielding layer
  • the active layer is prepared on the buffer layer using an atomic layer deposition method.
  • the thin film transistor further includes:
  • a gate insulating layer, the gate insulating layer is provided on the active layer;
  • a gate layer, the gate layer is provided on the gate insulating layer
  • An interlayer dielectric layer, the interlayer dielectric layer is provided on the buffer layer and covers the gate layer, the gate insulating layer and the active layer;
  • a source-drain layer, the source-drain layer is provided on the interlayer dielectric layer, and the source-drain layer includes a source electrode and a drain electrode arranged at intervals;
  • a passivation layer, the passivation layer is provided on the interlayer dielectric layer and covers the source and drain layers;
  • the pixel electrode layer is provided on the passivation layer.
  • the thin film transistor further includes:
  • a first via hole, the first via hole is provided on the interlayer dielectric layer and the buffer layer, and is used to electrically connect the source electrode and the light shielding layer;
  • a second via hole, the second via hole is provided on the interlayer dielectric layer for electrically connecting the source electrode and the active layer;
  • a third via hole, the third via hole is provided on the interlayer dielectric layer for electrically connecting the drain electrode and the active layer;
  • the fourth via hole is provided on the passivation layer and is used to electrically connect the drain electrode and the pixel electrode layer.
  • the substrate is a glass substrate, and the material for preparing the light shielding layer is metal.
  • the buffer layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the present invention provides a method for manufacturing a thin film transistor, which includes the following steps:
  • Step S1 preparing an active layer; wherein, the active layer includes a plurality of laminated structures, and each of the laminated structures includes:
  • N-layer indium oxide layer where N is an integer greater than 1;
  • a gallium oxide layer, the gallium oxide layer is disposed on the Nth indium oxide layer;
  • a zinc oxide layer, the zinc oxide layer is disposed on the gallium oxide layer.
  • the manufacturing method of the thin film transistor further includes the following steps:
  • Step S01 providing a substrate
  • Step S02 preparing a light-shielding layer on the substrate
  • Step S03 preparing a buffer layer on the substrate, the buffer layer covering the light shielding layer;
  • the step S1 is specifically to prepare an active layer on the buffer layer using an atomic layer deposition method.
  • the step of "preparing an active layer on the buffer layer using an atomic layer deposition method” includes the following steps:
  • Step S11 using the buffer layer as the current layer
  • Step S12 using an atomic layer deposition method, sequentially deposit N layers of the indium oxide layer on the current layer, deposit the gallium oxide layer on the Nth layer of the indium oxide layer, and deposit on the gallium oxide layer The zinc oxide layer to form the laminated structure;
  • Step S13 using the zinc oxide layer in the currently formed laminated structure as the current layer, and repeating the step S12 until a plurality of the laminated structures are formed;
  • Step S14 patterning several of the stacked structures to obtain the active layer.
  • the manufacturing method of the thin film transistor further includes the following steps:
  • the method for manufacturing the thin film transistor further includes the following steps:
  • a fourth via hole is prepared on the passivation layer for electrically connecting the drain electrode and the pixel electrode layer.
  • the thickness of the indium oxide layer, the gallium oxide layer, and the zinc oxide layer ranges from 50-300A.
  • the deposition rate of the indium oxide layer, the gallium oxide layer, and the zinc oxide layer ranges from 0.8 to 2.2 A/cycle.
  • the deposition rate of the zinc oxide layer, the deposition rate of the gallium oxide layer and the indium oxide layer decrease sequentially.
  • the present invention provides a display panel, the display panel includes a thin film transistor, the thin film transistor includes an active layer, the active layer includes a plurality of stacked structures, each of the stacked structures includes:
  • N-layer indium oxide layer where N is an integer greater than 1;
  • a gallium oxide layer, the gallium oxide layer is disposed on the Nth indium oxide layer;
  • a zinc oxide layer, the zinc oxide layer is disposed on the gallium oxide layer.
  • the thin film transistor further includes:
  • a light-shielding layer, the light-shielding layer is provided on the substrate;
  • a buffer layer is provided on the substrate and covers the light-shielding layer
  • the active layer is prepared on the buffer layer using an atomic layer deposition method.
  • the thin film transistor further includes:
  • a gate insulating layer, the gate insulating layer is provided on the active layer;
  • a gate layer, the gate layer is provided on the gate insulating layer
  • An interlayer dielectric layer, the interlayer dielectric layer is provided on the buffer layer and covers the gate layer, the gate insulating layer and the active layer;
  • a source-drain layer, the source-drain layer is provided on the interlayer dielectric layer, and the source-drain layer includes a source electrode and a drain electrode arranged at intervals;
  • a passivation layer, the passivation layer is provided on the interlayer dielectric layer and covers the source and drain layers;
  • the pixel electrode layer is provided on the passivation layer.
  • the thin film transistor further includes:
  • a first via hole, the first via hole is provided on the interlayer dielectric layer and the buffer layer, and is used to electrically connect the source electrode and the light shielding layer;
  • a second via hole, the second via hole is provided on the interlayer dielectric layer for electrically connecting the source electrode and the active layer;
  • a third via hole, the third via hole is provided on the interlayer dielectric layer for electrically connecting the drain electrode and the active layer;
  • the fourth via hole is provided on the passivation layer and is used to electrically connect the drain electrode and the pixel electrode layer.
  • the substrate is a glass substrate, and the material for preparing the light shielding layer is metal.
  • the buffer layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the number of layers of the indium oxide layer in the active layer stack structure of the thin film transistor is set to at least two, which can effectively increase the electron concentration inside the active layer and improve the mobility of the thin film transistor.
  • the active layer adopts a stacked design of N-layer indium oxide layer, gallium oxide layer and zinc oxide layer. Since the above-mentioned layers have high uniformity, the uniformity of the active layer can be improved as a whole. Since the mobility of the thin film transistor and the uniformity of the active layer are improved, the performance of the thin film transistor can be greatly improved.
  • FIG. 1 is a schematic diagram of a film layer of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of preparing a light-shielding layer provided by an embodiment of the present invention.
  • Fig. 4 is a schematic diagram of preparing a buffer layer provided by an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for preparing an active layer provided by an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of preparing an active layer provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of preparing a gate insulating layer and a gate layer according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of preparing an interlayer dielectric layer and a plurality of via holes provided by an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of preparing a source and drain layer according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of preparing a passivation layer provided by an embodiment of the present invention.
  • an embodiment of the present invention provides a thin film transistor
  • the thin film transistor includes an active layer 104
  • the active layer 104 includes a plurality of stacked structures, each stacked structure includes: N-layer indium oxide (InOx ) Layer 1041, gallium oxide (GaOx) layer 1042, and zinc oxide (ZnOx) layer 1043.
  • N is an integer greater than 1
  • the gallium oxide layer 1042 is provided on the Nth indium oxide layer 1041
  • the zinc oxide layer 1043 is provided on the gallium oxide layer 1042.
  • the active layer 104 in FIG. 1 includes a laminated structure that includes two indium oxide layers 1041.
  • the two indium oxide layers 1041 are referred to as the first layer of oxide in the order from bottom to top.
  • the gallium oxide layer 1042 is disposed on the second indium oxide layer 1041.
  • the active layer 104 may also include multiple stacked structures.
  • the active layer 104 includes two stacked structures.
  • the two stacked structures are called the first stacked structure and the second stacked structure in the order from bottom to top. Laminated structure.
  • the first indium oxide layer 1041 in the second stacked structure is disposed on the zinc oxide layer 1043 in the first stacked structure.
  • the active layer 104 adopts a stacked design of an N-layer indium oxide layer 1041, a gallium oxide layer 1042, and a zinc oxide layer 1043. Due to the high uniformity of the above-mentioned layers, the uniformity of the active layer 104 can be improved as a whole. sex. It can be understood that, since the mobility of the thin film transistor and the uniformity of the active layer 104 are improved, the performance of the thin film transistor can be greatly improved.
  • the thin film transistor further includes: a substrate 101, a light shielding layer 102 and a buffer layer 103.
  • the substrate 101 is preferably a glass substrate; the light shielding layer 102 is provided on the substrate 101; the buffer layer 103 is provided on the substrate 101 and covers the light shielding layer 102.
  • the active layer 104 is prepared on the buffer layer 103 using an atomic layer deposition method.
  • the substrate 101 is preferably a glass substrate, the light shielding layer 102 is made of metal, and the buffer layer is a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • preparing the active layer 104 on the buffer layer 103 by the atomic layer deposition method can improve the oxygen content and oxygen vacancy defects in each film layer in the active layer 104, and reduce the shallow defects in each film layer.
  • the interface state density of the active layer 104 is reduced, and the uniformity of the active layer 104 is further improved.
  • the thin film transistor further includes: a gate insulating layer 105, a gate layer 106, an interlayer dielectric layer 107, a source and drain layer 108, a passivation layer 109, and a pixel electrode layer 110 .
  • the gate insulating layer 105 is arranged on the active layer 104; the gate layer 106 is arranged on the gate insulating layer 105; the interlayer dielectric layer 107 is arranged on the buffer layer 103 and covers the gate layer 106 and the gate insulating layer.
  • the layer 105 and the active layer 104; the source and drain layer 108 is provided on the interlayer dielectric layer 107, the source and drain layer 108 includes a source electrode 1081 and a drain electrode 1082 arranged at intervals; the passivation layer 109 is provided on the interlayer dielectric layer 107 And cover the source and drain layer 108; the pixel electrode layer 110 is provided on the passivation layer 109.
  • the thin film transistor further includes: a first via 201, a second via 202, a third via 203 and a fourth via 204.
  • the first via hole 201 is provided on the interlayer dielectric layer 107 and the buffer layer 103 for electrically connecting the source electrode 1081 and the light shielding layer 102;
  • the second via hole 202 is provided on the interlayer dielectric layer 107 for electrical connection
  • the source electrode 1081 and the active layer 104 are electrically connected;
  • the third via hole 203 is provided on the interlayer dielectric layer 107 for electrically connecting the drain electrode 1082 and the active layer 104;
  • the fourth via hole 204 is provided on the passivation layer 109 Above, it is used to electrically connect the drain 1082 and the pixel electrode layer 110.
  • the structure of the active layer 104 provided by the embodiment of the present invention is not only suitable for top-gate thin film transistors, but also suitable for bottom-gate thin film transistors and etch-stop thin film transistors.
  • the embodiment of the present invention also provides a method for manufacturing the above-mentioned thin film transistor. As shown in FIG. 2, the method for manufacturing the thin film transistor includes the following steps:
  • the active layer 104 is prepared.
  • the active layer 104 includes a plurality of laminated structures, and each laminated structure includes: an N-layer indium oxide layer 1041, a gallium oxide layer 1042, and a zinc oxide layer 1043.
  • N is an integer greater than 1; the gallium oxide layer 1042 is provided on the Nth indium oxide layer 1041; the zinc oxide layer 1043 is provided on the gallium oxide layer 1042.
  • the number of layers of the indium oxide layer 1041 in the prepared active layer 104 is at least two, which can effectively increase the electron concentration inside the active layer 104 and improve the mobility of the thin film transistor.
  • the active layer 104 adopts a stacked design of an N-layer indium oxide layer 1041, a gallium oxide layer 1042, and a zinc oxide layer 1043. Due to the high uniformity of the above-mentioned layers, the uniformity of the active layer 104 can be improved as a whole. sex. It can be understood that, since the mobility of the thin film transistor and the uniformity of the active layer 104 are improved, the performance of the thin film transistor can be greatly improved.
  • the method for manufacturing a thin film transistor further includes the following steps:
  • a substrate 101 is provided; wherein, the substrate 101 is preferably a glass substrate.
  • step S02 a light-shielding layer 102 is prepared on the substrate 101.
  • step S03 a buffer layer 103 is prepared on the substrate 101, and the buffer layer 103 covers the light-shielding layer 102.
  • Step S1 is specifically to prepare the active layer 104 on the buffer layer 103 using an atomic layer deposition method.
  • a substrate 101 is provided, a metal is deposited on the substrate 101 by a physical vapor sputtering method, and the metal is etched by a photolithography process to obtain a light-shielding layer 102.
  • the metal material may be molybdenum (Mo), copper (Cu), or an alloy material composed of molybdenum and copper, and hydrogen peroxide (H 2 O 2 )-based chemical solution may be used as an etchant in the photolithography process.
  • the buffer layer 103 is deposited on the substrate 101 by a chemical vapor method and high temperature thermal annealing is performed to complete the preparation of the buffer layer 103.
  • the material of the buffer layer 103 is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • an active layer 104 is prepared on the buffer layer 103 using an atomic layer deposition method.
  • preparing the active layer 104 on the buffer layer 103 by the atomic layer deposition method can improve the oxygen content and oxygen vacancy defects in each film layer in the active layer 104, and reduce the shallow defects in each film layer.
  • the interface state density of the active layer 104 is reduced, and the uniformity of the active layer 104 is further improved.
  • the step of "preparing the active layer 104 on the buffer layer 103 using an atomic layer deposition method” includes the following steps:
  • step S11 the buffer layer 103 is used as the current layer.
  • Step S12 using the atomic layer deposition method, sequentially deposit N layers of indium oxide layer 1041 on the current layer, depositing a gallium oxide layer 1042 on the Nth indium oxide layer 1041, depositing a zinc oxide layer 1043 on the gallium oxide layer 1042, to Form a laminated structure.
  • step S13 the zinc oxide layer 1043 in the currently formed laminated structure is used as the current layer, and step S12 is repeatedly performed until several laminated structures are formed.
  • Step S14 patterning the formed multiple layered structures to obtain the active layer 104.
  • the active layer 104 is prepared on the buffer layer 103 using the atomic layer deposition method, wherein the precursor used when depositing the indium oxide layer 1041 on the buffer layer 103 by the atomic layer deposition method is an indium source, and the indium source is specifically (3-Dimethylaminopropyl)-Dimethylindium.
  • the precursor used when depositing the gallium oxide layer 1042 on the Nth indium oxide layer 1041 by using the atomic layer deposition method is a gallium source, and the gallium source is specifically trimethylgallium.
  • the precursor used when depositing the zinc oxide layer 1043 on the gallium oxide layer 1043 by using the atomic layer deposition method is a zinc source, and the zinc source is specifically diethyl zinc.
  • the deposited N layers of indium oxide layer 1041, gallium oxide layer 1042, and zinc oxide layer 1043 are referred to as a laminated structure.
  • the active layer 104 contains only one laminated structure, the laminated structure For patterning, the patterned laminated structure is called the active layer 104; otherwise, step S12 is continued on the zinc oxide layer 1043 currently formed until multiple laminated structures are obtained, and then the multiple laminated structures The structure is patterned, and the active layer 104 is obtained.
  • a photolithography process is used to pattern the formed multiple layer structures, and an oxalic acid-based chemical solution can be used as an etchant in the photolithography process.
  • each film layer in the active layer 104 ranges from 50 to 300 A
  • the deposition rate of each film layer is controlled within the range of 0.8 to 2.2 A/cycle
  • the deposition rate of the zinc oxide layer 1043 The deposition rate of the gallium oxide layer 1042 and the indium oxide layer 1041 decrease sequentially.
  • step S1 the method for manufacturing a thin film transistor further includes the following steps:
  • the source and drain layer 108 includes a source electrode 1081 and a drain electrode 1082 arranged at intervals.
  • an insulating material is deposited on the active layer 104 using a chemical vapor method, a metal is deposited on the insulating material, and the insulating material and metal are etched by a photolithography process to obtain the gate insulating layer 105 and the gate respectively. ⁇ 106.
  • the metal material may be molybdenum (Mo), copper (Cu), or an alloy material composed of molybdenum and copper, and hydrogen peroxide (H 2 O 2 )-based chemical solution may be used as an etchant in the photolithography process.
  • the interlayer dielectric layer 107 is deposited on the buffer layer 103 using a chemical vapor method, and the interlayer dielectric layer 107 and the buffer layer 103 are dug respectively using a photolithography process to obtain first via holes 201 and The second via 202 and the third via 203.
  • an oxidizing gas such as fluorine (F)-based gas can be used as an etchant in the photolithography process.
  • first via 201 is provided on the interlayer dielectric layer 107 and the buffer layer 103, and the second via 202 and the third via 203 are provided on the interlayer dielectric layer 107.
  • the physical vapor method is used to deposit metal on the interlayer dielectric layer 107, and the metal is etched by a photolithography process to form the source electrode 1081 and the drain electrode 1082.
  • the source electrode 1081 and the drain electrode 1082 are collectively referred to as Source and drain layer 108.
  • the metal material may be molybdenum (Mo), copper (Cu), or an alloy material composed of molybdenum and copper, and hydrogen peroxide (H 2 O 2 )-based chemical solution may be used as an etchant in the photolithography process.
  • the source electrode 1081 is electrically connected to the light shielding layer 102 through the first via hole 201, the source electrode 1081 is electrically connected to the active layer 104 through the second via hole 202, and the drain electrode 1082 is electrically connected to the active layer through the third via hole 203.
  • the layer 104 is electrically connected.
  • a passivation layer 109 is deposited on the source and drain layers 108 by using a chemical vapor method, and the passivation layer 109 is dug through a photolithography process to obtain the fourth via 204.
  • the material of the passivation layer 109 is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • Fluorine (F) can be used in the photolithography process.
  • the oxidizing gas is used as an etchant.
  • indium tin oxide is deposited on the passivation layer 109 by using a physical vapor phase method, and the indium tin oxide is etched by a photolithography process to obtain a pixel electrode layer 110.
  • the photolithography process can use an oxalic acid-based chemical solution as an etchant.
  • An embodiment of the present invention also provides a display panel including the above-mentioned thin film transistor.
  • the structure of the thin film transistor has been described in detail in the above embodiments, and will not be repeated here. It is understandable that since the performance of the thin film transistor can be greatly improved, the performance of the display panel including the thin film transistor can be greatly improved.

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Abstract

一种薄膜晶体管，薄膜晶体管包括有源层（104），所述有源层（104）包括若干叠层结构，每个所述叠层结构包括：N层氧化铟层（1041）；氧化镓层（1042），所述氧化镓层（1042）设于第N层所述氧化铟层（1041）上；氧化锌层（1043），所述氧化锌层（1043）设于所述氧化镓层（1042）上，提高了薄膜晶体管的性能。还提供该薄膜晶体管的制备方法及包含该薄膜晶体管的显示面板。

Description

薄膜晶体管及其制备方法、显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、显示面板。
 背景技术
近年来，金属氧化物（Oxide）薄膜晶体管（Thin-Film Transistor，TFT）被普遍应用于有源矩阵液晶显示（Active Matrix Liquid Crystal Display，AMLCD）装置和有源矩阵有机发光二极管（Active-Matrix Organic Light-Emitting Diode，AMOLED）显示装置中，使用Oxide TFT的AMLCD装置和AMOLED显示装置具有高分辨率、大尺寸、高刷新频率和可见光范围内高穿透率等显著优点，在显示领域中具有广阔的应用前景。
铟镓锌氧化物（IGZO）TFT是一种代表性的Oxide TFT，其具有多种典型结构。其中，顶栅型IGZO TFT因其寄生电容小、制作工艺中使用的掩膜数量少、栅极和栅极绝缘层能够保护沟道区使其不被大气环境和后续制程中的电浆所影响等优点而被广泛使用。但是，现有的顶栅型IGZO TFT无法兼顾高迁移率和高均一性，导致现有的顶栅型IGZO TFT及包含其的显示面板的性能较差。
 技术问题
本发明提供一种薄膜晶体管及其制备方法、显示面板，以解决现有的顶栅型IGZO TFT及包含其的显示面板性能较差的技术问题。
 技术解决方案
第一方面，本发明提供一种薄膜晶体管，所述薄膜晶体管包括有源层，所述有源层包括若干叠层结构，每个所述叠层结构包括：
N层氧化铟层；其中，N为大于1的整数；
氧化镓层，所述氧化镓层设于第N层所述氧化铟层上；
氧化锌层，所述氧化锌层设于所述氧化镓层上。
在一些实施例中，所述薄膜晶体管还包括：
基板；
遮光层，所述遮光层设于所述基板上；
缓冲层，所述缓冲层设于所述基板上，且覆盖所述遮光层；
所述有源层使用原子层沉积法制备于所述缓冲层上。
在一些实施例中，所述薄膜晶体管还包括：
栅极绝缘层，所述栅极绝缘层设于所述有源层上；
栅极层，所述栅极层设于所述栅极绝缘层上；
层间介质层，所述层间介质层设于所述缓冲层上，且覆盖所述栅极层、所述栅极绝缘层和所述有源层；
源漏极层，所述源漏极层设于所述层间介质层上，所述源漏极层包括间隔设置的源极和漏极；
钝化层，所述钝化层设于所述层间介质层上，且覆盖所述源漏极层；
像素电极层，所述像素电极层设于所述钝化层上。
在一些实施例中，所述薄膜晶体管还包括：
第一过孔，所述第一过孔设于所述层间介质层和所述缓冲层上，用于电性连接所述源极和所述遮光层；
第二过孔，所述第二过孔设于所述层间介质层上，用于电性连接所述源极和所述有源层；
第三过孔，所述第三过孔设于所述层间介质层上，用于电性连接所述漏极和所述有源层；
第四过孔，所述第四过孔设于所述钝化层上，用于电性连接所述漏极和所述像素电极层。
在一些实施例中，所述基板为玻璃基板，所述遮光层的制备材料为金属。
在一些实施例中，所述缓冲层为氧化硅薄膜、氮化硅薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
第二方面，本发明提供一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法包括以下步骤：
步骤S1，制备有源层；其中，所述有源层包括若干叠层结构，每个所述叠层结构包括：
N层氧化铟层；其中，N为大于1的整数；
氧化镓层，所述氧化镓层设于第N层所述氧化铟层上；
氧化锌层，所述氧化锌层设于所述氧化镓层上。
在一些实施例中，在所述步骤S1之前，所述薄膜晶体管的制备方法还包括以下步骤：
步骤S01，提供基板；
步骤S02，在所述基板上制备遮光层；
步骤S03，在所述基板上制备缓冲层，所述缓冲层覆盖所述遮光层；
所述步骤S1具体为使用原子层沉积法在所述缓冲层上制备有源层。
在一些实施例中，所述步骤“使用原子层沉积法在所述缓冲层上制备有源层”包括以下步骤：
步骤S11，将所述缓冲层作为当前层；
步骤S12，使用原子层沉积法，依次在所述当前层上沉积N层所述氧化铟层、在第N层所述氧化铟层上沉积所述氧化镓层、在所述氧化镓层上沉积所述氧化锌层，以形成一个所述叠层结构；
步骤S13，将当前形成的所述叠层结构中的所述氧化锌层作为所述当前层，重复执行所述步骤S12直至形成若干所述叠层结构；
步骤S14，将若干所述叠层结构进行图案化，得到所述有源层。
在一些实施例中，在所述步骤S1之后，所述薄膜晶体管的制备方法还包括以下步骤：
S21，在所述有源层上制备栅极绝缘层；
S22，在所述栅极绝缘层上制备栅极层；
S23，在所述缓冲层上制备层间介质层，所述层间介质层覆盖所述栅极层、所述栅极绝缘层和所述有源层；
S24，在所述层间介质层上制备源漏极层，所述源漏极层包括间隔设置的源极和漏极；
S25，在所述层间介质层上制备钝化层，所述钝化层覆盖所述源漏极层；
S26，在所述钝化层上制备像素电极层。
在一些实施例中，所述薄膜晶体管的制备方法还包括以下步骤：
在所述层间介质层和所述缓冲层上制备第一过孔，用于电性连接所述源极和所述遮光层；
在所述层间介质层上制备第二过孔，用于电性连接所述源极和所述有源层；
在所述层间介质层上制备第三过孔，用于电性连接所述漏极和所述有源层；
在所述钝化层上制备第四过孔，用于电性连接所述漏极和所述像素电极层。
在一些实施例中，所述氧化铟层、所述氧化镓层和所述氧化锌层的厚度的取值范围为50-300A。
在一些实施例中，所述氧化铟层、氧化镓层和所述氧化锌层的沉积速率的取值范围为0.8-2.2 A/cycle。
在一些实施例中，所述氧化锌层的沉积速率、所述氧化镓层和所述氧化铟层的沉积速率依次降低。
第三方面，本发明提供一种显示面板，所述显示面板包括薄膜晶体管，所述薄膜晶体管包括有源层，所述有源层包括若干叠层结构，每个所述叠层结构包括：
N层氧化铟层；其中，N为大于1的整数；
氧化镓层，所述氧化镓层设于第N层所述氧化铟层上；
氧化锌层，所述氧化锌层设于所述氧化镓层上。
在一些实施例中，所述薄膜晶体管还包括：
基板；
遮光层，所述遮光层设于所述基板上；
缓冲层，所述缓冲层设于所述基板上，且覆盖所述遮光层；
所述有源层使用原子层沉积法制备于所述缓冲层上。
在一些实施例中，所述薄膜晶体管还包括：
栅极绝缘层，所述栅极绝缘层设于所述有源层上；
栅极层，所述栅极层设于所述栅极绝缘层上；
层间介质层，所述层间介质层设于所述缓冲层上，且覆盖所述栅极层、所述栅极绝缘层和所述有源层；
源漏极层，所述源漏极层设于所述层间介质层上，所述源漏极层包括间隔设置的源极和漏极；
钝化层，所述钝化层设于所述层间介质层上，且覆盖所述源漏极层；
像素电极层，所述像素电极层设于所述钝化层上。
在一些实施例中，所述薄膜晶体管还包括：
第一过孔，所述第一过孔设于所述层间介质层和所述缓冲层上，用于电性连接所述源极和所述遮光层；
第二过孔，所述第二过孔设于所述层间介质层上，用于电性连接所述源极和所述有源层；
第三过孔，所述第三过孔设于所述层间介质层上，用于电性连接所述漏极和所述有源层；
第四过孔，所述第四过孔设于所述钝化层上，用于电性连接所述漏极和所述像素电极层。
在一些实施例中，所述基板为玻璃基板，所述遮光层的制备材料为金属。
在一些实施例中，所述缓冲层为氧化硅薄膜、氮化硅薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
 有益效果
本发明通过将薄膜晶体管中的有源层的叠层结构中的氧化铟层的层数设置为至少为两层，能够有效增加有源层内部的电子浓度，提高薄膜晶体管的迁移率。同时，有源层采用N层氧化铟层、氧化镓层和氧化锌层的叠层设计，由于上述各膜层的均一性较高，因此总体上能够提高有源层的均一性。由于薄膜晶体管的迁移率和有源层的均一性得到了提高，因此薄膜晶体管的性能能够极大提高。
 附图说明
图1为本发明的实施例提供的薄膜晶体管的膜层示意图。
图2为本发明的实施例提供的薄膜晶体管的制备方法流程图。
图3为本发明的实施例提供的制备遮光层的示意图。
图4为本发明的实施例提供的制备缓冲层的示意图。
图5为本发明的实施例提供的制备有源层的方法流程图。
图6为本发明的实施例提供的制备有源层的示意图。
图7为本发明的实施例提供的制备栅极绝缘层和栅极层的示意图。
图8为本发明的实施例提供的制备层间介质层及多个过孔的示意图。
图9为本发明的实施例提供的制备源漏极层的示意图。
图10为本发明的实施例提供的制备钝化层的示意图。
 本发明的实施方式
为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
如图1所示，本发明的实施例提供一种薄膜晶体管，该薄膜晶体管包括有源层104，该有源层104包括若干叠层结构，每个叠层结构包括：N层氧化铟（InOx）层1041、氧化镓（GaOx）层1042和氧化锌（ZnOx）层1043。其中，N为大于1的整数；氧化镓层1042设于第N层氧化铟层1041上；氧化锌层1043设于氧化镓层1042上。
具体的，图1中的有源层104包括一个叠层结构，该叠层结构包括两层氧化铟层1041，按照从下到上的顺序依次将两层氧化铟层1041称为第一层氧化铟层1041和第二层氧化铟层1041。此时，氧化镓层1042设于第二层氧化铟层1041上。
有源层104还可以包括多个叠层结构，例如，有源层104包括两个叠层结构，按照从下到上的顺序依次将两个叠层结构称为第一叠层结构和第二叠层结构。此时，第二叠层结构中的第一层氧化铟层1041设于第一叠层结构中的氧化锌层1043上。
需要说明的是，由于氧化铟层1041的层数为至少为两层，因此能够有效增加有源层104内部的电子浓度，提高薄膜晶体管的迁移率。同时，有源层104采用N层氧化铟层1041、氧化镓层1042和氧化锌层1043的叠层设计，由于上述各膜层的均一性较高，因此总体上能够提高有源层104的均一性。可以理解的是，由于薄膜晶体管的迁移率和有源层104的均一性得到了提高，因此薄膜晶体管的性能能够极大提高。
基于上述实施例，如图1所示，薄膜晶体管还包括：基板101、遮光层102和缓冲层103。其中，基板101优选为玻璃基板；遮光层102设于基板101上；缓冲层103设于基板101上，且覆盖遮光层102。有源层104使用原子层沉积法制备于缓冲层103上。其中，基板101优选为玻璃基板，遮光层102的制备材料为金属，缓冲层为氧化硅薄膜、氮化硅薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
需要说明的是，通过原子层沉积法在缓冲层103上制备有源层104，可以改善有源层104中各膜层内的氧含量及氧空位缺陷，减少各膜层中的浅层缺陷，降低有源层104的界面态密度，进一步提高有源层104的均一性。
基于上述任一实施例，如图1所示，薄膜晶体管还包括：栅极绝缘层105、栅极层106、层间介质层107、源漏极层108、钝化层109和像素电极层110。其中，栅极绝缘层105设于有源层104上；栅极层106设于栅极绝缘层105上；层间介质层107设于缓冲层103上，且覆盖栅极层106、栅极绝缘层105和有源层104；源漏极层108设于层间介质层107上，源漏极层108包括间隔设置的源极1081和漏极1082；钝化层109设于层间介质层107上，且覆盖源漏极层108；像素电极层110设于钝化层109上。
基于上述任一实施例，如图1所示，薄膜晶体管还包括：第一过孔201、第二过孔202、第三过孔203和第四过孔204。其中，第一过孔201设于层间介质层107和缓冲层103上，用于电性连接源极1081和遮光层102；第二过孔202设于层间介质层107上，用于电性连接源极1081和有源层104；第三过孔203设于层间介质层107上，用于电性连接漏极1082和有源层104；第四过孔204设于钝化层109上，用于电性连接漏极1082和像素电极层110。
另外需要说明的是，本发明的实施例提供的有源层104的结构不仅适用于顶栅型薄膜晶体管，还适用于底栅型薄膜晶体管及刻蚀阻挡型薄膜晶体管。
本发明的实施例还提供上述薄膜晶体管的制备方法，如图2所示，该薄膜晶体管的制备方法包括以下步骤：
步骤S1，制备有源层104。其中，该有源层104包括若干叠层结构，每个叠层结构包括：N层氧化铟层1041、氧化镓层1042和氧化锌层1043。N为大于1的整数；氧化镓层1042设于第N层氧化铟层1041上；氧化锌层1043设于氧化镓层1042上。
其中，有源层104的结构已在上述实施例中详细说明，此处不再赘述。
需要说明的是，制备得到的有源层104中氧化铟层1041的层数为至少为两层，因此能够有效增加有源层104内部的电子浓度，提高薄膜晶体管的迁移率。同时，有源层104采用N层氧化铟层1041、氧化镓层1042和氧化锌层1043的叠层设计，由于上述各膜层的均一性较高，因此总体上能够提高有源层104的均一性。可以理解的是，由于薄膜晶体管的迁移率和有源层104的均一性得到了提高，因此薄膜晶体管的性能能够极大提高。
基于上述任一实施例，如图2所示，在步骤S1之前，薄膜晶体管的制备方法还包括以下步骤：
步骤S01，提供基板101；其中，基板101优选为玻璃基板。
步骤S02，在基板101上制备遮光层102。
步骤S03，在基板101上制备缓冲层103，缓冲层103覆盖遮光层102。
步骤S1具体为使用原子层沉积法在缓冲层103上制备有源层104。
具体的，如图3所示，提供基板101，利用物理气相溅射法在基板101上沉积金属，并采用光刻工艺刻蚀金属得到遮光层102。其中，金属的材料可以为钼（Mo）、铜（Cu）或者钼和铜组成的合金材料，光刻工艺中可使用过氧化氢（H 2O 2）系药液作为蚀刻剂。
如图4所示，遮光层102制备完成后，利用化学气相法在基板101上沉积缓冲层103并进行高温热退火以完成缓冲层103的制备。其中，缓冲层103的材料为氧化硅（SiOx）薄膜、氮化硅（SiNx）薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
缓冲层103制备完成后，使用原子层沉积法在缓冲层103上制备有源层104。
需要说明的是，通过原子层沉积法在缓冲层103上制备有源层104，可以改善有源层104中各膜层内的氧含量及氧空位缺陷，减少各膜层中的浅层缺陷，降低有源层104的界面态密度，进一步提高有源层104的均一性。
基于上述任一实施例，如图5所示，步骤“使用原子层沉积法在缓冲层103上制备有源层104”包括以下步骤：
步骤S11，将缓冲层103作为当前层。
步骤S12，使用原子层沉积法，依次在当前层上沉积N层氧化铟层1041、在第N层氧化铟层1041上沉积氧化镓层1042、在氧化镓层1042上沉积氧化锌层1043，以形成一个叠层结构。
步骤S13，将当前形成的叠层结构中的氧化锌层1043作为当前层，重复执行步骤S12直至形成若干叠层结构。
步骤S14，将形成的若干叠层结构进行图案化，得到有源层104。
具体的，使用原子层沉积法在缓冲层103上制备有源层104，其中，使用原子层沉积法在缓冲层103上沉积氧化铟层1041时使用到的前驱体为铟源，铟源具体为（3-二甲基氨基丙基）-二甲基铟。使用原子层沉积法在第N层氧化铟层1041上沉积氧化镓层1042时使用到的前驱体为镓源，镓源具体为三甲基镓。使用原子层沉积法在氧化镓层1043上沉积氧化锌层1043时使用到的前驱体为锌源，锌源具体为二乙基锌。
如图6所示，将沉积得到N层氧化铟层1041、氧化镓层1042和氧化锌层1043称为一个叠层结构，若有源层104仅包含一个叠层结构，则将该叠层结构进行图案化，将图案化后的叠层结构称为有源层104；否则，在当前形成的氧化锌层1043上继续执行步骤S12，直至得到多个叠层结构，然后将这多个叠层结构进行图案化，得到有源层104。其中，采用光刻工艺将形成的若干叠层结构进行图案化，光刻工艺中可使用草酸系药液作为蚀刻剂。
需要说明的是，有源层104中各膜层的厚度的取值范围为50-300A，各膜层的沉积速率控制在0.8~2.2 A/cycle的范围内，且氧化锌层1043的沉积速率、氧化镓层1042和氧化铟层1041的沉积速率依次降低。
基于上述任一实施例，如图2所示，在步骤S1之后，薄膜晶体管的制备方法还包括以下步骤：
S21，在有源层104上制备栅极绝缘层105。
S22，在栅极绝缘层105上制备栅极层106。
S23，在缓冲层103上制备层间介质层107，层间介质层107覆盖栅极层106、栅极绝缘层105和有源层104。
S24，在层间介质层107上制备源漏极层108，源漏极层108包括间隔设置的源极1081和漏极1082。
S25，在层间介质层107上制备钝化层109，钝化层109覆盖源漏极层108。
S26，在钝化层109上制备像素电极层110。
具体的，如图7所示，使用化学气相法在有源层104上沉积绝缘材料，在绝缘材料上沉积金属，并采用光刻工艺刻蚀绝缘材料和金属分别得到栅极绝缘层105和栅极层106。其中，金属的材料可以为钼（Mo）、铜（Cu）或者钼和铜组成的合金材料，光刻工艺中可使用过氧化氢（H 2O 2）系药液作为蚀刻剂。
如图8所示，使用化学气相法在缓冲层103上沉积层间介质层107，并采用光刻工艺分别对层间介质层107和缓冲层103进行挖孔，得到第一过孔201、第二过孔202和第三过孔203。其中，光刻工艺中可使用氟（F）系等氧化性气体作为蚀刻剂。
需要说明的是，第一过孔201设于层间介质层107和缓冲层103上，第二过孔202和第三过孔203设于层间介质层107上。
如图9所示，使用物理气相法在层间介质层107上沉积金属，并采用光刻工艺刻蚀金属形成源极1081和漏极1082，此时，将源极1081和漏极1082统称为源漏极层108。其中，金属的材料可以为钼（Mo）、铜（Cu）或者钼和铜组成的合金材料，光刻工艺中可使用过氧化氢（H 2O 2）系药液作为蚀刻剂。此时，源极1081通过第一过孔201与遮光层102电性连接，源极1081通过第二过孔202与有源层104电性连接，漏极1082通过第三过孔203与有源层104电性连接。
如图10所示，使用化学气相法在源漏极层108上沉积钝化层109，并采用光刻工艺分别对钝化层109进行挖孔，得到第四过孔204。其中，钝化层109的材料为氧化硅（SiOx）薄膜、氮化硅（SiNx）薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜，光刻工艺中可使用氟（F）系等氧化性气体作为蚀刻剂。
如图1所示，使用物理气相法在钝化层109上沉积氧化铟锡（ITO），并采用光刻工艺对氧化铟锡进行刻蚀，得到像素电极层110。其中，光刻工艺可使用草酸系药液作为蚀刻剂。
本发明的实施例还提供一种显示面板，该显示面板包括上述的薄膜晶体管。
需要说明的是，薄膜晶体管的结构已在上述实施例中详细说明，此处不再赘述。可以理解的是，由于薄膜晶体管的性能能够极大提高，因此包含薄膜晶体管的显示面板的性能能够极大提高。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (20)

  1. 一种薄膜晶体管，所述薄膜晶体管包括有源层，其中，所述有源层包括若干叠层结构，每个所述叠层结构包括：
    N层氧化铟层；其中，N为大于1的整数；
    氧化镓层，所述氧化镓层设于第N层所述氧化铟层上；
    氧化锌层，所述氧化锌层设于所述氧化镓层上。
  2. 如权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    基板；
    遮光层，所述遮光层设于所述基板上；
    缓冲层，所述缓冲层设于所述基板上，且覆盖所述遮光层；
    所述有源层使用原子层沉积法制备于所述缓冲层上。
  3. 如权利要求2所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    栅极绝缘层，所述栅极绝缘层设于所述有源层上；
    栅极层，所述栅极层设于所述栅极绝缘层上；
    层间介质层，所述层间介质层设于所述缓冲层上，且覆盖所述栅极层、所述栅极绝缘层和所述有源层；
    源漏极层，所述源漏极层设于所述层间介质层上，所述源漏极层包括间隔设置的源极和漏极；
    钝化层，所述钝化层设于所述层间介质层上，且覆盖所述源漏极层；
    像素电极层，所述像素电极层设于所述钝化层上。
  4. 如权利要求3所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    第一过孔，所述第一过孔设于所述层间介质层和所述缓冲层上，用于电性连接所述源极和所述遮光层；
    第二过孔，所述第二过孔设于所述层间介质层上，用于电性连接所述源极和所述有源层；
    第三过孔，所述第三过孔设于所述层间介质层上，用于电性连接所述漏极和所述有源层；
    第四过孔，所述第四过孔设于所述钝化层上，用于电性连接所述漏极和所述像素电极层。
  5. 如权利要求2所述的薄膜晶体管，其中，所述基板为玻璃基板，所述遮光层的制备材料为金属。
  6. 如权利要求2所述的薄膜晶体管，其中，所述缓冲层为氧化硅薄膜、氮化硅薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
  7. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括以下步骤：
    步骤S1，制备有源层；其中，所述有源层包括若干叠层结构，每个所述叠层结构包括：
    N层氧化铟层；其中，N为大于1的整数；
    氧化镓层，所述氧化镓层设于第N层所述氧化铟层上；
    氧化锌层，所述氧化锌层设于所述氧化镓层上。
  8. 如权利要求7所述的薄膜晶体管的制备方法，其中，在所述步骤S1之前，所述薄膜晶体管的制备方法还包括以下步骤：
    步骤S01，提供基板；
    步骤S02，在所述基板上制备遮光层；
    步骤S03，在所述基板上制备缓冲层，所述缓冲层覆盖所述遮光层；
    所述步骤S1具体为使用原子层沉积法在所述缓冲层上制备有源层。
  9. 如权利要求8所述的薄膜晶体管的制备方法，其中，所述步骤“使用原子层沉积法在所述缓冲层上制备有源层”包括以下步骤：
    步骤S11，将所述缓冲层作为当前层；
    步骤S12，使用原子层沉积法，依次在所述当前层上沉积N层所述氧化铟层、在第N层所述氧化铟层上沉积所述氧化镓层、在所述氧化镓层上沉积所述氧化锌层，以形成一个所述叠层结构；
    步骤S13，将当前形成的所述叠层结构中的所述氧化锌层作为所述当前层，重复执行所述步骤S12直至形成若干所述叠层结构；
    步骤S14，将若干所述叠层结构进行图案化，得到所述有源层。
  10. 如权利要求9所述的薄膜晶体管的制备方法，其中，在所述步骤S1之后，所述薄膜晶体管的制备方法还包括以下步骤：
    S21，在所述有源层上制备栅极绝缘层；
    S22，在所述栅极绝缘层上制备栅极层；
    S23，在所述缓冲层上制备层间介质层，所述层间介质层覆盖所述栅极层、所述栅极绝缘层和所述有源层；
    S24，在所述层间介质层上制备源漏极层，所述源漏极层包括间隔设置的源极和漏极；
    S25，在所述层间介质层上制备钝化层，所述钝化层覆盖所述源漏极层；
    S26，在所述钝化层上制备像素电极层。
  11. 如权利要求10所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括以下步骤：
    在所述层间介质层和所述缓冲层上制备第一过孔，用于电性连接所述源极和所述遮光层；
    在所述层间介质层上制备第二过孔，用于电性连接所述源极和所述有源层；
    在所述层间介质层上制备第三过孔，用于电性连接所述漏极和所述有源层；
    在所述钝化层上制备第四过孔，用于电性连接所述漏极和所述像素电极层。
  12. 如权利要求9所述的薄膜晶体管的制备方法，其中，所述氧化铟层、所述氧化镓层和所述氧化锌层的厚度的取值范围为50-300A。
  13. 如权利要求9所述的薄膜晶体管的制备方法，其中，所述氧化铟层、所述氧化镓层和所述氧化锌层的沉积速率的取值范围为0.8-2.2 A/cycle。
  14. 如权利要求13所述的薄膜晶体管的制备方法，其中，所述氧化锌层的沉积速率、所述氧化镓层和所述氧化铟层的沉积速率依次降低。
  15. 一种显示面板，其中，所述显示面板包括薄膜晶体管，所述薄膜晶体管包括有源层，所述有源层包括若干叠层结构，每个所述叠层结构包括：
    N层氧化铟层；其中，N为大于1的整数；
    氧化镓层，所述氧化镓层设于第N层所述氧化铟层上；
    氧化锌层，所述氧化锌层设于所述氧化镓层上。
  16. 如权利要求15所述的显示面板，其中，所述薄膜晶体管还包括：
    基板；
    遮光层，所述遮光层设于所述基板上；
    缓冲层，所述缓冲层设于所述基板上，且覆盖所述遮光层；
    所述有源层使用原子层沉积法制备于所述缓冲层上。
  17. 如权利要求16所述的显示面板，其中，所述薄膜晶体管还包括：
    栅极绝缘层，所述栅极绝缘层设于所述有源层上；
    栅极层，所述栅极层设于所述栅极绝缘层上；
    层间介质层，所述层间介质层设于所述缓冲层上，且覆盖所述栅极层、所述栅极绝缘层和所述有源层；
    源漏极层，所述源漏极层设于所述层间介质层上，所述源漏极层包括间隔设置的源极和漏极；
    钝化层，所述钝化层设于所述层间介质层上，且覆盖所述源漏极层；
    像素电极层，所述像素电极层设于所述钝化层上。
  18. 如权利要求17所述的显示面板，其中，所述薄膜晶体管还包括：
    第一过孔，所述第一过孔设于所述层间介质层和所述缓冲层上，用于电性连接所述源极和所述遮光层；
    第二过孔，所述第二过孔设于所述层间介质层上，用于电性连接所述源极和所述有源层；
    第三过孔，所述第三过孔设于所述层间介质层上，用于电性连接所述漏极和所述有源层；
    第四过孔，所述第四过孔设于所述钝化层上，用于电性连接所述漏极和所述像素电极层。
  19. 如权利要求16所述的显示面板，其中，所述基板为玻璃基板，所述遮光层的制备材料为金属。
  20. 如权利要求16所述的显示面板，其中，所述缓冲层为氧化硅薄膜、氮化硅薄膜或者氧化硅薄膜和氮化硅薄膜交替层叠设置形成的复合薄膜。
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