WO2021233203A1 - 相位检测方法及其装置、设备 - Google Patents

相位检测方法及其装置、设备 Download PDF

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Publication number
WO2021233203A1
WO2021233203A1 PCT/CN2021/093649 CN2021093649W WO2021233203A1 WO 2021233203 A1 WO2021233203 A1 WO 2021233203A1 CN 2021093649 W CN2021093649 W CN 2021093649W WO 2021233203 A1 WO2021233203 A1 WO 2021233203A1
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Prior art keywords
phase
signal
component
value
clock signal
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PCT/CN2021/093649
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English (en)
French (fr)
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赵亮
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中兴通讯股份有限公司
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Priority to KR1020227043460A priority Critical patent/KR20230008212A/ko
Priority to EP21809727.7A priority patent/EP4142156A4/en
Priority to JP2022570673A priority patent/JP7606538B2/ja
Publication of WO2021233203A1 publication Critical patent/WO2021233203A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • G01R25/04—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the embodiments of the present invention relate to, but are not limited to, the field of communication technology, and in particular, to a phase detection method and its device and equipment.
  • 5G communication requires higher and higher accuracy of the 1588 clock time, and the time synchronization accuracy of a single node has been required to be within a few nanoseconds. If you want to further improve the accuracy of the clock signal, you must either increase the frequency of the clock signal, or perform compensation after measuring the phase of the clock signal.
  • the former method has higher requirements on the chip and process, while the latter method has higher requirements on the chip and process. The requirements are lower, so the latter method is more cost-effective.
  • the first type uses a high-frequency clock signal to sample the clock signal to be measured to obtain phase information
  • the second type is to first shift a clock signal through phase And generate several clock signals with the same frequency but different phases, and then compare with the clock signal to be tested, find the clock signal with the closest phase to obtain the phase information
  • the third method is to take a clock signal in a small step The phase shift is long and the clock signal to be measured is sampled at the same time, and the phase information is obtained through the acquired sampling value after traversing one cycle.
  • the first type of method has higher requirements on the chip and process; the second type of method has a lower implementation cost, but the accuracy is not high; the third type of method has higher accuracy, but the measurement speed is slower, and the higher the accuracy, the higher the speed slow.
  • the embodiment of the present invention provides a phase detection method and its device and equipment.
  • an embodiment of the present invention provides a phase detection device, including: a signal processing component configured to obtain a reference clock signal and an initial phase value of the reference clock signal, and output the reference clock signal; phase discrimination The component is connected to the signal processing component and is configured to obtain a clock signal to be tested, and obtain and output a first phase difference signal according to the reference clock signal and the clock signal to be tested; the phase comparison component is respectively connected to the The phase discriminating component is connected to the signal processing component, and is configured to obtain and output a phase adjustment signal according to the first phase difference signal; the signal processing component is also configured to compare the reference clock signal according to the phase adjustment signal Perform phase adjustment to reduce the first phase difference signal, and accumulate the adjusted phase value to obtain a phase integration value, and obtain the phase value of the clock signal to be measured according to the phase integration value and the initial phase value .
  • the embodiments of the present invention also provide a phase detection method, which is applied to a phase detection device, the phase detection device includes a signal processing component, a phase discrimination component, and a phase comparison component connected end to end in sequence; the method includes: The signal processing component obtains the reference clock signal and the initial phase value of the reference clock signal, and outputs the reference clock signal to the phase discriminating part; the phase discriminating part obtains the clock signal to be measured, and performs the calculation according to the reference clock signal.
  • the clock signal and the clock signal to be measured obtain a first phase difference signal, and output the first phase difference signal to the phase comparison component;
  • the phase comparison component obtains a phase adjustment signal according to the first phase difference signal, And output the phase adjustment signal to the signal processing component;
  • the signal processing component adjusts the phase of the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, and accumulates the adjusted
  • the phase value is used to obtain a phase cumulative value, and the phase value of the clock signal to be measured is obtained according to the phase cumulative value and the initial phase value.
  • an embodiment of the present invention also provides a device including the phase detection device of the first aspect as described above.
  • FIG. 1 is a schematic diagram of a phase detection device provided by an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a phase detection device provided by another embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a phase detection device provided by another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a phase detection device provided by another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a phase detection device provided by another embodiment of the present invention.
  • FIG. 6 is a flowchart of a phase detection method provided by an embodiment of the present invention.
  • FIG. 7 is a flowchart of a phase detection method provided by another embodiment of the present invention.
  • FIG. 8 is a flowchart of a phase detection method provided by another embodiment of the present invention.
  • FIG. 9 is a flowchart of a phase detection method provided by another embodiment of the present invention.
  • FIG. 10 is a flowchart of a phase detection method provided by another embodiment of the present invention.
  • Fig. 11 is a schematic diagram of a device according to an embodiment of the present invention.
  • the embodiment of the present invention provides a phase detection method and device and equipment, wherein the phase detection device includes a signal processing component, a phase discrimination component and a phase comparison component which are connected end to end in sequence, and the phase comparison component is based on the first output from the phase discrimination component
  • a phase difference signal obtains a phase adjustment signal, where the first phase difference signal is obtained by the phase discriminating component according to the reference clock signal and the clock signal to be measured, and the signal processing component adjusts the phase of the reference clock signal according to the phase adjustment signal to Reduce the first phase difference signal, that is, gradually reduce the first phase difference signal output by the phase discrimination component according to the reference clock signal and the clock signal to be measured by adjusting the phase of the reference clock signal, so that the phase of the reference clock signal can be Approximate the phase of the clock signal to be measured, thereby gradually improving the accuracy of the first phase difference signal output by the phase discriminating component, thereby increasing the accuracy of the phase detection of the clock signal; in addition, because the phase difference signal is within the numerical range of the
  • phase detection speed can be better. Therefore, the phase detection accuracy and the phase detection speed of the clock signal can be improved.
  • Fig. 1 is a schematic diagram of a phase detection device provided by an embodiment of the present invention.
  • the phase detection device 100 includes a signal processing component 110, a phase discrimination component 120 and a phase comparison component 130 connected end to end in sequence.
  • the signal processing component 110 can be set to obtain the reference clock signal and the initial phase value of the reference clock signal, and to output the reference clock signal;
  • the phase discriminating component 120 can be set to obtain the clock signal to be measured, and according to the reference clock signal and the to-be-measured clock signal.
  • the first phase difference signal is obtained and output from the clock signal; the phase comparison component 130 can be configured to obtain and output the phase adjustment signal according to the first phase difference signal; in addition, the signal processing component 110 can also be configured to compare the reference signal according to the phase adjustment signal.
  • the clock signal undergoes phase adjustment to reduce the first phase difference signal, and the adjusted phase value is accumulated to obtain a phase accumulated value, and the phase value of the clock signal to be measured is obtained according to the phase accumulated value and the initial phase value. Therefore, the signal processing component 110, the phase discrimination component 120 and the phase comparison component 130 can cooperate with each other to realize the phase detection of the clock signal.
  • the clock signal to be measured is a clock signal that needs to be phase-detected
  • the reference clock signal is a known clock signal that is set to detect the phase of the clock signal to be measured.
  • the signal processing component 110 obtains the reference for the first time. In the case of a clock signal, the signal processing component 110 can obtain the initial phase value of the reference clock signal, thereby providing necessary basic conditions for obtaining the phase value of the clock signal to be measured in subsequent operations.
  • the first phase difference signal is a signal obtained by the phase detector 120 according to the reference clock signal and the clock signal to be measured. Due to the limitation of the manufacturing process or calculation accuracy of the phase detector 120, the phase detector 120 The first phase difference signal output by the component 120 is not accurate. Therefore, the signal processing component 110 and the phase comparison component 130 are arranged so that the signal processing component 110, the phase discrimination component 120 and the phase comparison component 130 are connected end to end in sequence, and the phase The comparison component 130 can obtain the phase adjustment signal according to the first phase difference signal output by the phase discrimination component 120, and the signal processing component 110 can perform phase adjustment on the reference clock signal according to the phase adjustment signal to reduce the first phase.
  • the value of the difference signal that is, the phase of the reference clock signal is adjusted by the mutual cooperation between the phase discrimination component 120, the phase comparison component 130, and the signal processing component 110 to gradually reduce the first output output by the phase discrimination component 120.
  • the phase difference signal enables the phase of the reference clock signal to gradually approach the phase of the clock signal to be measured, thereby improving the accuracy of the first phase difference signal obtained by the phase discriminating component 120 according to the reference clock signal and the clock signal to be measured.
  • the phase adjustment of the reference clock signal is performed within the value range of the first phase difference signal, and for the purpose of reducing the first phase difference signal, it only needs to be within the value range of the first phase difference signal.
  • the phase detection of the clock signal to be measured can be realized by performing a limited number of processing within. Compared with the way of traversing a clock cycle to obtain phase information in some cases, this embodiment can have a better phase detection speed. Therefore, this The embodiment can improve the phase detection accuracy and phase detection speed of the clock signal.
  • the signal processing component 110 may include a Field Programmable Gate Array (FPGA) chip configured with a phase shifter function, and may also include a digital signal processing (Digital Signal Process, DSP) chip. )
  • FPGA Field Programmable Gate Array
  • DSP Digital Signal Process
  • the digital phase shifter will obtain the reference clock signal
  • the DSP chip will obtain the reference clock signal and the initial phase value of the reference clock signal
  • the phase adjustment signal output by the phase comparison component 130 outputs a configuration signal to the digital phase shifter, so that the digital phase shifter adjusts the phase of the reference clock signal according to the configuration signal, so as to reduce the amount of time that the phase discriminating component 120 responds to the reference clock.
  • the first phase difference signal obtained from the signal and the clock signal to be measured.
  • the DSP chip will also accumulate the phase value when the reference clock signal is phase adjusted, and obtain the phase value of the reference clock signal according to the accumulated phase value and the initial phase value of the reference clock signal. Measure the phase value of the clock signal.
  • the phase discriminating component 120 can adopt a digital phase discriminator or an analog phase discriminator; and when the phase discriminating component 120 adopts a digital phase discriminator, the phase discriminating component 120 can be an independent digital phase discriminator. It may also be a digital phase detector integrated in the signal processing component 110.
  • the phase detector 120 may be a functional component in an FPGA chip. For the specific implementation of the phase-detection component 120, this embodiment does not specifically limit it.
  • the phase comparison component 130 may include a signal processing chip such as an FPGA chip or the like, and may also include a logic processing chip such as a comparator, which is not specifically limited in this embodiment.
  • the phase comparison component 130 when the phase comparison component 130 receives the first phase difference signal output by the phase discrimination component 120, the phase comparison component 130 may first determine the first phase difference signal. Whether the phase difference signal meets the preset condition, when the preset condition is satisfied, the phase comparison component 130 outputs the corresponding phase adjustment signal. For example, when the phase comparison component 130 determines that the first phase difference signal is within the first preset interval, the phase comparison component 130 may output a phase adjustment signal that is set to shift the reference clock signal into a positive phase; and when the phase comparison component 130 If it is determined that the first phase difference signal is within the second preset interval range, the phase comparison component 130 may output a phase adjustment signal that is set to negatively shift the reference clock signal.
  • a signal processing chip such as an FPGA chip
  • the preset conditions can be appropriately set according to actual application needs, and this embodiment is not specifically limited; in addition, the first preset interval range and the second preset interval range can also be set according to actual application requirements However, appropriate settings are not specifically limited in this embodiment.
  • the phase comparison component 130 includes a logic processing chip such as a comparator
  • the phase comparison component 130 can convert the first phase The difference signal is logically compared with a reference signal, and a corresponding phase adjustment signal is output according to the comparison result of the first phase difference signal and the reference signal. For example, when the first phase difference signal is greater than the reference signal, the phase comparison component 130 may output a phase adjustment signal that is set to negatively shift the reference clock signal; and when the first phase difference signal is less than the reference signal, the phase comparison The component 130 may output a phase adjustment signal configured to positively shift the reference clock signal.
  • the reference signal may be a signal set based on experience, or a signal related to a reference clock signal, and may be appropriately set according to actual application requirements, and this embodiment does not specifically limit it.
  • the phase comparison component 130 includes, but is not limited to, a first signal generation component 131 and a signal comparison component 132, wherein the first signal generation component 131 is connected to the phase discrimination component 120, and the signal comparison The component 132 is connected to the first signal generating component 131 and the signal processing component 110 respectively.
  • the first signal generating part 131 can be configured to obtain the first voltage signal according to the first phase difference signal;
  • the signal comparing part 132 can be configured to obtain the reference voltage signal and the first voltage signal, and according to the reference voltage signal and the first voltage signal.
  • the first voltage signal obtains a phase adjustment signal configured to perform phase adjustment on the reference clock signal.
  • the first signal generating component 131 may be a charge pump, and the charge pump is also a switched capacitor voltage converter, which can output a voltage value by charging and storing energy. After the first signal generating component 131 receives the first phase difference signal output by the phase discriminating component 120, the first signal generating component 131 can charge according to the duration indicated by the first phase difference signal, thereby obtaining the first voltage signal , So as to provide the necessary basic conditions for obtaining the phase adjustment signal in the subsequent steps.
  • the signal comparison component 132 may be a voltage comparator, where the reference voltage signal may be a voltage signal set based on experience, or a voltage signal related to the reference clock signal, which may be performed according to actual application requirements. Appropriate settings are not specifically limited in this embodiment. After the signal comparison component 132 obtains the reference voltage signal and the first voltage signal, the signal comparison component 132 can obtain a phase adjustment signal set to adjust the phase of the reference clock signal according to the reference voltage signal and the first voltage signal.
  • the signal comparison component 132 may output a phase adjustment signal with a high level value, and the phase adjustment signal with a high level value may be It is configured to enable the signal processing component 110 to perform a negative phase-shift phase adjustment on the reference clock signal; when the voltage value of the first voltage signal is less than the voltage value of the reference voltage signal, the signal comparison component 132 can output a level value of low level
  • the phase adjustment signal whose level value is a low level can be set to enable the signal processing component 110 to perform a positive phase-shift phase adjustment on the reference clock signal; when the voltage value of the first voltage signal is equal to the reference voltage signal
  • the signal comparison component 132 can output a phase adjustment signal with a level value of an intermediate level, and the phase adjustment signal with a level value of the intermediate level can be set to stop the signal processing component 110 from performing the reference clock signal Phase adjustment operation.
  • the intermediate level is a level between the high level and the low level. Therefore, through the cooperation of the first signal generating component 131 and the signal comparing component 132, it is possible to provide an accurate adjustment direction for the phase adjustment of the reference clock signal by the signal processing component 110, so that the phase of the reference clock signal can be close to the phase to be measured.
  • the phase of the clock signal can thereby gradually increase the accuracy of the first phase difference signal output by the phase discriminating component 120, and thereby the accuracy of the phase detection of the clock signal can be improved.
  • the phase comparison component 130 may further include a second signal generating component 133, wherein the second signal generating component 133 is connected to the signal comparing component 132.
  • the second signal generating component 133 may be configured to obtain a phase reference signal and obtain a reference voltage signal according to the phase reference signal, wherein the phase reference signal is obtained according to the reference clock signal.
  • the second signal generating component 133 may be a charge pump, and the charge pump is also a switched capacitor voltage converter, which can output a voltage value by charging and storing energy. After the second signal generating component 133 receives a phase reference signal, the second signal generating component 133 can charge according to the time period indicated by the phase reference signal to obtain a reference voltage signal, thereby providing a phase adjustment signal for subsequent steps. The necessary basic conditions.
  • the phase reference signal may be obtained according to the period of the reference clock signal.
  • the phase reference signal may be a half period of the reference clock signal or a quarter period of the reference clock signal. Appropriate selection is made according to the needs of use, and this embodiment does not specifically limit it.
  • the phase reference signal is a preset fixed value. Therefore, the reference voltage signal obtained by charging the second signal generating component 133 according to the time period indicated by the phase reference signal is also a fixed value, which can facilitate communication with The first voltage signal is compared to obtain a phase adjustment signal.
  • the signal processing component 110 includes but is not limited to a controller 111 and a phase shifting component 112, wherein the phase comparison component 130, the controller 111, the phase shifting component 112, and the phase discriminating component 120 Connect in order.
  • the controller 111 can be configured to obtain the initial phase value of the reference clock signal, and can be configured to obtain a phase shift signal according to the phase adjustment signal output by the phase comparison component 130, and can be configured to send the phase shift signal to the phase shift component 112.
  • phase shift component 112 can be set to obtain the reference clock signal and adjust the phase of the reference clock signal according to the phase shift signal, so as to reduce the output of the phase discrimination component 120 according to the reference clock signal and the clock signal to be measured
  • controller 111 can also be configured to accumulate the phase shift signal to obtain the phase integration value, and obtain the phase value of the clock signal to be measured according to the phase integration value and the initial phase value of the reference clock signal.
  • the controller 111 may have different implementations.
  • the controller 111 may be an FPGA chip, or a DSP chip, or a combination of a control chip and a frequency divider.
  • the controller 111 is a combination of a control chip and a two-frequency divider, the two-frequency divider can be responsible for generating two-division information (for example, the phase shift signal in this embodiment), and the control chip can be responsible for configuring the phase shift component 112
  • the dichotomy information enables the phase shifting component 112 to adjust the displacement of the phase of the reference clock signal according to the dichotomy information.
  • the phase shifting component 112 may also have different implementations.
  • the phase shifting component 112 may be a digital phase shifter or an analog phase shifter with configuration function, which is not specifically limited in this embodiment.
  • the controller 111 when the controller 111 cooperates with the phase shifting component 112 to adjust the phase of the reference clock signal, the controller 111 can also accumulate the phase shift signal to obtain the phase integration value. Therefore, when the detection is over, according to The phase integration value and the initial phase value of the reference clock signal can obtain the phase value of the clock signal to be measured, thereby realizing the detection processing of the phase of the clock signal to be measured.
  • the controller when the controller receives the phase adjustment signal, the controller can obtain the phase shift signal according to the phase adjustment signal Among them, k is the number of phase adjustments of the reference clock signal, and T is the period of the reference clock signal. Therefore, when the controller accumulates the phase shift signal, the accumulated phase value can be obtained
  • the controller 111 can adjust the signal according to the phase According to different types of configuration information, different types of configuration information are sent to the phase shifting component 112, so that the phase shifting component 112 can perform different phase adjustment processing on the reference clock signal according to the different types of configuration information. For example, when the level value of the phase adjustment signal is high, the controller 111 will send a configuration message indicating negative phase shifting to the phase shifting component 112, so that the phase shifting component 112 will perform negative phase shifting configuration according to the indication.
  • the information performs a negative phase shift phase adjustment on the reference clock signal; when the level value of the phase adjustment signal is low, the controller 111 will send a configuration message indicating the positive phase shift to the phase shift component 112 to make the phase shift
  • the component 112 performs a positive phase-shifting phase adjustment on the reference clock signal according to the configuration information indicating the positive phase shift; when the level of the phase adjustment signal is an intermediate level, the controller 111 will not send anything to the phase-shifting component 112.
  • the configuration information that is, the phase shifting unit 112 does not perform phase adjustment on the reference clock signal. It is worth noting that the intermediate level is a level between the high level and the low level.
  • the phase of the reference clock signal can be adjusted in an accurate adjustment direction, so that the phase of the reference clock signal can be close to the phase of the clock signal to be measured, which can gradually improve the accuracy of the reference clock signal.
  • the accuracy of the first phase difference signal output by the phase component 120 can further improve the accuracy of the phase detection of the clock signal.
  • the signal processing component 110 further includes a counter, where the counter may be built in the controller 111 or may be externally installed in the controller 111 and connected to the controller 111.
  • the count value of the counter may not only be set to indicate the number of phase adjustments of the reference clock signal by the signal processing component 110, but also may be set to obtain a phase shift signal used to adjust the phase of the reference clock signal.
  • the maximum count value can be set for the counter.
  • the controller 111 When the current count value of the counter is the maximum count value, that is, the number of phase adjustments of the reference clock signal by the signal processing component 110 reaches the preset maximum number of adjustments, or when the controller
  • the controller 111 When 111 receives a phase adjustment signal whose level value is an intermediate level, the controller 111 will reset the counter to zero. In the case where the controller 111 resets the counter, it is explained that the phase measurement is finished, so that the next phase detection can be performed. It is worth noting that the intermediate level is a level between the high level and the low level.
  • controller 111 is specifically configured to obtain the phase value of the clock signal to be measured according to the phase cumulative value and the initial phase value through the following formula:
  • T1 is the phase value of the clock signal to be tested
  • T2 is the initial phase value of the reference clock signal
  • T is the period of the reference clock signal
  • n is the number of phase adjustments performed on the reference clock signal, n ⁇ 1.
  • the accuracy of phase detection is determined, and a specific example is used to illustrate:
  • the detection device 100 performs phase detection on the stamped clock signal, when the maximum count value of the counter is set to 10, that is, the number of phase adjustments of the reference clock signal by the signal processing component 110 is set to 9 times (the first time is not Adjust the phase of the reference clock signal), then, in this case, according to the above formula, the final measurement accuracy is about 8ps.
  • this embodiment has a better phase detection speed; in addition, when the same number of phase shifts is performed, it can be seen from the above example that compared with some cases, this embodiment has better phase detection speed. Phase detection accuracy.
  • the phase detection device 200 includes a controller 211, a digital phase shifter 212, a digital phase detector 220, a first charge pump 231, and a voltage detector.
  • phase detection device 200 when the phase detection device 200 is used to perform phase detection of the clock signal to be measured, the various components in the phase detection device 200 cooperate with each other to perform the following detection principle:
  • the second charge pump 233 Before starting to perform the phase detection operation, the second charge pump 233 first performs for a duration of The charging process is to obtain a reference voltage signal with a voltage value of Vref, where T is the period of the reference clock signal, and the second charge pump 233 sends the reference voltage signal to the voltage comparator 232.
  • the controller 211 sets the maximum count value of the counter 213 to n, and causes the counter 213 to start counting from 0.
  • the digital phase shifter 212 outputs the initial reference clock signal to the digital phase detector 220.
  • the phase converter 220 obtains and outputs a first phase difference signal to the first charge pump 231 according to the initial reference clock signal and the clock signal to be measured.
  • the comparator 232 outputs the first voltage signal, and the voltage comparator 232 obtains and outputs a phase adjustment signal to the controller 211 according to the first voltage signal and the reference voltage signal.
  • the controller 211 When the controller 211 receives the phase adjustment signal, it starts to perform the phase detection operation of the clock signal to be measured. At this time, the count value of the counter 213 increases by one; when the level value of the phase adjustment signal is high, the controller 211 It will cooperate with the digital phase shifter 212 to make the reference clock signal take the displacement as Perform a negative phase shift so that the phase of the reference clock signal can approach the phase of the clock signal to be measured; when the level of the phase adjustment signal is low, the controller 211 will cooperate with the digital phase shifter 212 to shift the reference clock signal The amount is Perform a positive phase shift so that the phase of the reference clock signal can approach the phase of the clock signal to be measured.
  • the phase-adjusted reference clock signal will be input into the digital phase detector 220.
  • the digital phase detector 220 will The phase-adjusted reference clock signal and the clock signal to be measured are obtained and output a new first phase difference signal, and the first charge pump 231 and the voltage comparator 232 cooperate with each other to control the direction according to the new first phase difference signal
  • the device 211 outputs a new phase adjustment signal, and repeats the detection until the count value of the counter 213 reaches the preset maximum count value, and the phase detection operation of the clock signal to be measured is completed. At this point, the following results can be obtained:
  • T1 is the phase value of the clock signal to be tested
  • T2 is the initial phase value of the reference clock signal
  • T is the period of the reference clock signal
  • n is the number of phase adjustments performed on the reference clock signal, n ⁇ 1.
  • the level value of the phase adjustment signal is an intermediate level (that is, the level between the high level and the low level), it indicates the phase of the reference clock signal and the phase of the clock signal to be measured There is a difference of half a period between them. At this time, the phase adjustment operation of the reference clock signal is stopped, and the phase detection operation ends. In this case, the phase value of the clock signal to be measured can also be obtained according to the above formula, which will not be repeated here.
  • the device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • an embodiment of the present invention also provides a phase detection method, which can be applied to the phase detection device in the above device embodiment, and the phase detection method includes but is not limited to the following steps:
  • Step S100 the signal processing component obtains the reference clock signal and the initial phase value of the reference clock signal, and outputs the reference clock signal to the phase discrimination component;
  • Step S200 the phase discrimination component obtains the clock signal to be measured, obtains the first phase difference signal according to the reference clock signal and the clock signal to be measured, and outputs the first phase difference signal to the phase comparison component;
  • Step S300 The phase comparison component obtains a phase adjustment signal according to the first phase difference signal, and outputs the phase adjustment signal to the signal processing component;
  • step S400 the signal processing component performs phase adjustment on the reference clock signal according to the phase adjustment signal to reduce the first phase difference signal, and accumulates the adjusted phase value to obtain the phase accumulation value, and obtains the pending phase value according to the phase accumulation value and the initial phase value. Measure the phase value of the clock signal.
  • the clock signal to be measured is a clock signal that requires phase detection
  • the reference clock signal is a known clock signal that is set to detect the phase of the clock signal to be measured
  • the reference clock is first acquired by the signal processing component
  • the signal processing component can obtain the initial phase value of the reference clock signal, so as to provide the necessary basic conditions for obtaining the phase value of the clock signal to be measured in subsequent operations.
  • the first phase difference signal is a signal obtained by the phase discriminating component based on the reference clock signal and the clock signal to be measured. Due to the limitation of the manufacturing process or calculation accuracy of the phase discriminating component, the phase discriminating component is The output first phase difference signal is not accurate.
  • the phase comparison component can obtain the phase adjustment signal according to the first phase difference signal, and
  • the phase adjustment signal is transmitted to the signal processing component, and the signal processing component adjusts the phase of the reference clock signal according to the phase adjustment signal to reduce the value of the first phase difference signal, that is, through the phase discrimination component and the phase comparison
  • the coordination between the components and the signal processing components adjusts the phase of the reference clock signal to gradually reduce the first phase difference signal output by the phase discriminating component, so that the phase of the reference clock signal can gradually approach that of the clock signal under test. Therefore, the accuracy of the first phase difference signal obtained by the phase discrimination component based on the reference clock signal and the clock signal to be measured can be improved.
  • phase adjustment of the reference clock signal is performed within the value range of the first phase difference signal, and for the purpose of reducing the first phase difference signal, it only needs to be within the value range of the first phase difference signal.
  • the phase detection of the clock signal to be measured can be realized by performing a limited number of processing within. Compared with the way of traversing a clock cycle to obtain phase information in some cases, this embodiment can have a better phase detection speed. Therefore, this The embodiment can improve the phase detection accuracy and phase detection speed of the clock signal.
  • phase detection method in this embodiment can be applied to the phase detection device in the above device embodiment, the specific implementation of the signal processing component, phase discrimination component, and phase comparison component in this embodiment can be With reference to the relevant description in the foregoing device embodiment, details are not repeated here.
  • This step S300 may include but is not limited to the following steps:
  • Step S310 The first signal generating component obtains the first voltage signal according to the first phase difference signal, and outputs the first voltage signal to the signal comparing component;
  • step S320 the signal comparison component obtains the reference voltage signal and the first voltage signal, and obtains the phase adjustment signal according to the reference voltage signal and the first voltage signal, and the signal comparison component outputs the phase adjustment signal to the signal processing component.
  • the first signal generating component may be a charge pump, and the charge pump is also called a switched capacitor voltage converter, which can output a voltage value by charging and storing energy.
  • the first signal generating component After the first signal generating component receives the first phase difference signal output by the phase discriminating component, the first signal generating component can charge according to the duration indicated by the first phase difference signal, thereby obtaining the first voltage signal, which is The phase adjustment signal obtained in the subsequent steps provides the necessary basic conditions.
  • the reference voltage signal may be a voltage signal set based on experience, or a voltage signal related to the reference clock signal, which may be appropriately set according to actual application requirements, and this embodiment does not specifically limit it.
  • the signal comparison component can obtain the phase set to perform phase adjustment on the reference clock signal according to the reference voltage signal and the first voltage signal.
  • the adjustment signal for example, when the voltage value of the first voltage signal is greater than the voltage value of the reference voltage signal, the signal comparison component can output a phase adjustment signal with a high level value, and the level value is a high level phase adjustment signal
  • the signal can be set to enable the signal processing component to perform negative phase adjustment of the reference clock signal; another example, when the voltage value of the first voltage signal is less than the voltage value of the reference voltage signal, the signal comparison component can output a level value A low-level phase adjustment signal.
  • the phase adjustment signal with a low level value can be set to enable the signal processing component to perform a positive phase-shift phase adjustment on the reference clock signal; for example, when the voltage of the first voltage signal The value is equal to the voltage value of the reference voltage signal, and the signal comparison component can output a phase adjustment signal with a level value of an intermediate level (that is, a level between the high level and the low level), and the level value is the intermediate level.
  • the flat phase adjustment signal may be set to stop the signal processing component from performing phase adjustment operations on the reference clock signal. It is worth noting that, among the specific examples of the phase adjustment signal obtained by the signal comparison component according to the reference voltage signal and the first voltage signal, different combination examples can be formed according to actual conditions. In order to avoid repetition of content, we will not Go into details.
  • an accurate adjustment direction can be provided for the phase adjustment of the reference clock signal by the signal processing component, so that the phase of the reference clock signal can be close to the phase of the reference clock signal.
  • the phase of the clock signal is measured, so that the accuracy of the first phase difference signal output by the phase discriminating component can be gradually improved, and the accuracy of the phase detection of the clock signal can be improved.
  • phase detection method may further include the following steps:
  • Step S500 the second signal generating component obtains the phase reference signal, and obtains the reference voltage signal according to the phase reference signal, where the phase reference signal is obtained according to the reference clock signal;
  • step S600 the second signal generating component outputs a reference voltage signal to the signal comparing component.
  • the second signal generating component may be a charge pump, and the charge pump is also referred to as a switched capacitor voltage converter, which can output a voltage value by charging and storing energy.
  • the second signal generating component After the second signal generating component receives a phase reference signal, the second signal generating component can charge according to the duration indicated by the phase reference signal to obtain a reference voltage signal, thereby providing necessary information for obtaining the phase adjustment signal in the subsequent steps. basic condition.
  • the phase reference signal may be obtained according to the period of the reference clock signal.
  • the phase reference signal may be a half period of the reference clock signal or a quarter period of the reference clock signal. Appropriate selection is made according to the needs of use, and this embodiment does not specifically limit it.
  • the signal processing component in step S400 adjusts the phase of the reference clock signal according to the phase adjustment signal, and different specific steps may be included in different embodiments:
  • Step S401 When the level value of the phase adjustment signal is a high level, the signal processing component performs a negative phase shift phase adjustment on the reference clock signal.
  • Step S402 When the level value of the phase adjustment signal is low, the signal processing component performs a positive phase shift phase adjustment on the reference clock signal.
  • Step S403 When the level value of the phase adjustment signal is an intermediate level, the signal processing component does not perform phase adjustment on the reference clock signal, where the intermediate level is a level between a high level and a low level.
  • steps S401, S402, and S403 can be mutually parallel technical solutions, or can be combined with each other to form different technical solutions, and appropriate selections can be made according to the actual situation. There is no specific limitation.
  • the signal processing component can adjust the phase of the reference clock signal in different directions according to the different level values of the phase adjustment signal, so that the phase of the reference clock signal can be close to the phase of the clock signal to be measured, so that Gradually improve the accuracy of the first phase difference signal output by the phase discriminating component, thereby improving the phase detection accuracy of the clock signal.
  • the step S400 may include But not limited to the following steps:
  • Step S410 the controller obtains a phase shift signal according to the phase adjustment signal, and outputs the phase shift signal to the phase shift component;
  • Step S420 The phase shift component adjusts the phase of the reference clock signal according to the phase shift signal to reduce the first phase difference signal
  • step S430 the controller accumulates the phase shift signal to obtain a phase integration value, and obtains the phase value of the clock signal to be measured according to the phase integration value and the initial phase value.
  • the controller when the controller cooperates with the phase shift component to adjust the phase of the reference clock signal, the controller can also accumulate the phase shift signal to obtain the phase integration value. Therefore, when the detection is over, the phase accumulates according to the phase. Value and the initial phase value of the reference clock signal, the phase value of the clock signal to be measured can be obtained, thereby realizing the detection processing of the phase of the clock signal to be measured.
  • the controller when the controller receives the phase adjustment signal, the controller can obtain the phase shift signal according to the phase adjustment signal Among them, k is the number of phase adjustments of the reference clock signal, and T is the period of the reference clock signal. Therefore, when the controller accumulates the phase shift signal, the accumulated phase value can be obtained
  • the controller can send different types of configuration information to the phase shifting component according to different types of the phase adjustment signal, so that the phase shifting component can be configured according to different types of configuration information.
  • Perform different phase adjustment processing on the reference clock signal For example, when the level value of the phase adjustment signal is high, the controller will send a configuration information indicating negative phase shifting to the phase shifting component, so that the phase shifting component can compare the reference according to the configuration information indicating negative phase shifting.
  • the clock signal performs phase adjustment of negative phase shift; when the level value of the phase adjustment signal is low, the controller will send a configuration message indicating positive phase shift to the phase shift component, so that the phase shift component performs according to the indication
  • the configuration information of the positive phase shift adjusts the phase of the reference clock signal; when the level value of the phase adjustment signal is an intermediate level, the controller will not send any configuration information to the phase shift component, that is, the phase shift component No phase adjustment is made to the reference clock signal.
  • the intermediate level is a level between the high level and the low level.
  • the phase of the reference clock signal can be adjusted in an accurate adjustment direction, so that the phase of the reference clock signal can be close to the phase of the clock signal to be measured, so that the phase discrimination component can be gradually improved.
  • the accuracy of the output first phase difference signal can further improve the phase detection accuracy of the clock signal.
  • the controller in step S410 is based on the phase Adjusting the signal to obtain the phase-shifted signal may include the following specific steps:
  • Step S411 the controller obtains the count value in the counter
  • step S412 the controller obtains a phase shift signal according to the count value.
  • the count value of the counter may not only be set to indicate the number of phase adjustments of the reference clock signal by the signal processing component, but also may be set to obtain a phase shift signal used to adjust the phase of the reference clock signal. Therefore, by obtaining the count value in the counter, it is convenient to obtain the phase shift signal that is set to adjust the phase of the reference clock signal, and the accumulated phase shift signal can be counted according to the count value, so as to obtain the value of the clock signal to be measured. Phase value.
  • the maximum count value can be set for the counter.
  • the controller can make the counter Reset to 0.
  • the controller resets the counter, it indicates that the phase measurement is over to facilitate the next phase detection.
  • the controller in step S430 obtains the phase value of the clock signal to be measured according to the phase integration value and the initial phase value, which may include the following specific steps:
  • step S431 the controller obtains the phase value of the clock signal to be measured according to the accumulated phase value and the initial phase value through the following formula:
  • phase detection determines the accuracy of phase detection, that is, when the phase detection method of this embodiment is used to perform phase detection on the clock signal to be measured, only a limited number of phase shift processing is required on the reference clock signal to achieve relatively accurate measurement accuracy. For example, to perform phase detection on a stamping clock signal with a frequency of 125MHz, you only need to perform 9 phase adjustments on the reference clock signal to obtain a detection result with a measurement accuracy of about 8ps, and if you use some conditions to traverse a clock cycle to When the phase information is obtained for measurement, if the same measurement accuracy needs to be achieved, that is, when traversing a clock cycle at 8ps steps to obtain the phase information, it needs to perform phase shift operations 1000 times. Therefore, compared with some cases, this The embodiment has a better phase detection speed; in addition, when the same number of phase shifts are performed, it can be known from the above analysis that, compared with some cases, this embodiment has better phase detection accuracy.
  • an embodiment of the present invention also provides a device, which may include a phase detection device as in any of the above device embodiments.
  • the equipment in this embodiment includes the phase detection device in any of the above embodiments
  • the equipment in this embodiment has the hardware structure of the phase detection device in the above embodiment, and the various components in the phase detection device can communicate with each other. Cooperate with each other so that the device in this embodiment can execute the phase detection method in any of the above method embodiments. Therefore, the specific implementation of the device in this embodiment can refer to the above embodiment. In order to avoid redundancy, it will not be repeated here. .
  • the device in this embodiment has the phase detection device in any of the above embodiments, the device in this embodiment has the technical effect brought by the phase detection device in the above embodiment, that is, compared with some cases, this The device in the embodiment can improve the phase detection accuracy and phase detection speed of the clock signal.
  • the embodiment of the present invention provides a phase detection method and device and equipment, which can improve the phase detection accuracy and phase detection speed of a clock signal.
  • the phase of the reference clock signal can be close to the phase of the clock signal to be measured through a limited number of processing, so that the measurement of the clock phase can be completed with high precision and high speed.
  • computer storage medium includes volatile and non-volatile data implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data).
  • Information such as computer-readable instructions, data structures, program modules, or other data.
  • Computer storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or Any other medium used to store desired information and that can be accessed by a computer.
  • communication media usually contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as carrier waves or other transmission mechanisms, and may include any information delivery media. .

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Abstract

一种相位检测方法及其装置、设备。其中，相位检测装置包括信号处理组件、鉴相部件和相位比较组件，信号处理组件被设置成获取参考时钟信号及其初始相位值；鉴相部件被设置成获取待测时钟信号，并根据参考时钟信号和待测时钟信号得到第一相位差信号；相位比较组件被设置成根据第一相位差信号得到相位调整信号；此外，信号处理组件还被设置成根据相位调整信号对参考时钟信号进行相位调整，以减小第一相位差信号，并累计调整的相位值以得到相位累计值，且根据相位累计值和初始相位值得到待测时钟信号的相位值。

Description

相位检测方法及其装置、设备
相关申请的交叉引用
本申请基于申请号为202010428524.6、申请日为2020年05月20日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明实施例涉及但不限于通信技术领域，尤其涉及一种相位检测方法及其装置、设备。
背景技术
目前5G通讯对1588时钟时间的精度要求越来越高，单节点的对时精度已要求在几个纳秒之内。如果要进一步提高时钟信号的精度，要么提高时钟信号的频率，要么对时钟信号的相位进行测量后补偿，前一种方式对芯片、工艺等要求较高，后一种方式则对芯片、工艺等要求较低，因此后一种方式的性价比较高。
当前普遍采用的时钟相位测量方式主要有三类：第一类方式是用一个很高频率的时钟信号去对待测时钟信号进行采样而得到相位信息；第二类方式是先将一个时钟信号通过移相而产生若干个同频率但不同相位的时钟信号，然后和待测时钟信号进行比较，找到相位最接近的一个时钟信号而得到相位信息；第三类方式是将一个时钟信号以一个很小的步长来移相并同时对待测时钟信号进行采样，遍历一个周期后通过获取到的采样值而得到相位信息。第一类方式对芯片及工艺等要求较高；第二类方式的实现代价较小，但精度不高；第三类方式的精度较高，但测量速度较慢，而且精度越高，速度越慢。
因此，如何高精度、高速度的完成时钟相位的测量，是亟待解决的技术问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供了一种相位检测方法及其装置、设备。
第一方面，本发明实施例提供了一种相位检测装置，包括：信号处理组件，被设置成获取参考时钟信号和所述参考时钟信号的初始相位值，并输出所述参考时钟信号；鉴相部件，与所述信号处理组件连接，被设置成获取待测时钟信号，并根据所述参考时钟信号和所述待测时钟信号得到且输出第一相位差信号；相位比较组件，分别与所述鉴相部件和所述信号处理组件连接，被设置成根据所述第一相位差信号得到并输出相位调整信号；所述信号处理组件还被设置成根据所述相位调整信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号，并累计调整的相位值以得到相位累计值，且根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值。
第二方面，本发明实施例还提供了一种相位检测方法，应用于相位检测装置，所述相位检测装置包括依次首尾连接的信号处理组件、鉴相部件和相位比较组件；所述方法包括：所述信号处理组件获取参考时钟信号和所述参考时钟信号的初始相位值，并向所述鉴相部件输出所述参考时钟信号；所述鉴相部件获取待测时钟信号，并根据所述参考时钟信号和所述待测时钟信号得到第一相位差信号，且向所述相位比较组件输出所述第一相位差信号；所述相位比较组件根据所述第一相位差信号得到相位调整信号，并向所述信号处理组件输出所述相位调整信号；所述信号处理组件根据所述相位调整信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号，并累计调整的相位值以得到相位累计值，且根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值。
第三方面，本发明实施例还提供了一种设备，包括有如上所述第一方面的相位检测装置。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明技术方案的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明的技术方案，并不构成对本发明技术方案的限制。
图1是本发明一个实施例提供的相位检测装置的示意图；
图2是本发明另一实施例提供的相位检测装置的示意图；
图3是本发明另一实施例提供的相位检测装置的示意图；
图4是本发明另一实施例提供的相位检测装置的示意图；
图5是本发明另一实施例提供的相位检测装置的示意图；
图6是本发明一个实施例提供的相位检测方法的流程图；
图7是本发明另一实施例提供的相位检测方法的流程图；
图8是本发明另一实施例提供的相位检测方法的流程图；
图9是本发明另一实施例提供的相位检测方法的流程图；
图10是本发明另一实施例提供的相位检测方法的流程图；
图11是本发明一实施例的一种设备的示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
需要说明的是，虽然在装置示意图中进行了功能模块划分，在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于装置中的模块划分，或流程图中的顺序执行所示出或描述的步骤。说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本发明实施例提供了一种相位检测方法及其装置、设备，其中，相位检测装置包括依 次首尾连接的信号处理组件、鉴相部件和相位比较组件，相位比较组件根据由鉴相部件输出的第一相位差信号得到相位调整信号，其中第一相位差信号由鉴相部件根据参考时钟信号和待测时钟信号而得到，而信号处理组件则根据该相位调整信号对参考时钟信号进行相位调整，以减小第一相位差信号，即，通过调整参考时钟信号的相位而逐渐减小由鉴相部件根据参考时钟信号和待测时钟信号而输出的第一相位差信号，使得参考时钟信号的相位能够逼近待测时钟信号的相位，从而逐渐提高由鉴相部件输出的第一相位差信号的精度，进而提高对时钟信号的相位检测精度；此外，由于是在第一相位差信号的数值范围内对参考时钟信号进行相位调整，并且以减小第一相位差信号为目的，所以，仅需要在第一相位差信号的数值范围内进行有限次数的处理，即可实现对时钟信号的相位检测，相比于一些情况中遍历一个时钟周期以获取相位信息的方式，能够具有更优的相位检测速度，所以，能够提高对时钟信号的相位检测精度和相位检测速度。
下面结合附图，对本发明实施例作进一步阐述。
如图1所示，图1是本发明一个实施例提供的相位检测装置的示意图。在图1的示例中，该相位检测装置100包括依次首尾连接的信号处理组件110、鉴相部件120和相位比较组件130。其中，信号处理组件110能够被设置成获取参考时钟信号和参考时钟信号的初始相位值，并输出参考时钟信号；鉴相部件120能够被设置成获取待测时钟信号，并根据参考时钟信号和待测时钟信号得到且输出第一相位差信号；相位比较组件130能够被设置成根据第一相位差信号得到并输出相位调整信号；此外，信号处理组件110还能够被设置成根据相位调整信号对参考时钟信号进行相位调整，以减小第一相位差信号，并累计调整的相位值以得到相位累计值，且根据相位累计值和初始相位值得到待测时钟信号的相位值。因此，信号处理组件110、鉴相部件120和相位比较组件130能够相互配合以实现对时钟信号的相位检测。
在一实施例中，待测时钟信号为需要进行相位检测的时钟信号，参考时钟信号为已知的被设置成对待测时钟信号的相位进行检测的时钟信号，在信号处理组件110首次获取到参考时钟信号时，信号处理组件110可以获取到参考时钟信号的初始相位值，从而为后续操作中得到待测时钟信号的相位值提供必要的基础条件。
在一实施例中，第一相位差信号为由鉴相部件120根据参考时钟信号和待测时钟信号而得到的信号，由于受限于鉴相部件120的制作工艺或者计算精度等问题，鉴相部件120所输出的第一相位差信号并不准确，因此，通过设置信号处理组件110和相位比较组件130，使得信号处理组件110、鉴相部件120和相位比较组件130依次首尾连接，并且，相位比较组件130能够根据由鉴相部件120输出的第一相位差信号而得到相位调整信号，而信号处理组件110则能够根据该相位调整信号对参考时钟信号进行相位调整，以减小该第一相位差信号的数值，即，通过鉴相部件120、相位比较组件130及信号处理组件110之间的相互配合，对参考时钟信号的相位进行调整而逐渐减小由鉴相部件120所输出的第一相位差信号，使得参考时钟信号的相位能够逐渐逼近待测时钟信号的相位，从而可以提高鉴相部件120根据参考时钟信号和待测时钟信号而得到的第一相位差信号的精度。此外，由于对参考时钟信号进行的相位调整是在第一相位差信号的数值范围内执行的，并且以减小第一相位差信号为目的，所以，仅需要在第一相位差信号的数值范围内进行有限次数的处理，即可实现对待测时钟信号的相位检测，相比于一些情况中遍历一个时钟周期以获取相位信 息的方式，本实施例能够具有更优的相位检测速度，所以，本实施例能够提高对时钟信号的相位检测精度和相位检测速度。
在一实施例中，信号处理组件110可以包括有配置有移相器功能的现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)芯片，也可以包括有由数字信号处理(Digital Signal Process，DSP)芯片与数字移相器构成的组合，本实施例并不作具体限定。如果信号处理组件110包括有由DSP芯片与数字移相器构成的组合，则数字移相器会获取参考时钟信号，而DSP芯片则会获取参考时钟信号和参考时钟信号的初始相位值，并根据由相位比较组件130所输出的相位调整信号向数字移相器输出一个配置信号，以使数字移相器根据该配置信号对参考时钟信号进行相位调整，以减小由鉴相部件120根据参考时钟信号和待测时钟信号所得到的第一相位差信号，此外，DSP芯片还会累计对参考时钟信号进行相位调整时的相位值，并根据累计的相位值和参考时钟信号的初始相位值得到待测时钟信号的相位值。
在一实施例中，鉴相部件120可以采用数字鉴相器，也可以采用模拟鉴相器；而当鉴相部件120采用数字鉴相器时，鉴相部件120可以为独立的数字鉴相器，也可以为集成于信号处理组件110中的数字鉴相器，例如鉴相部件120可以为FPGA芯片中的一个功能部件。对于鉴相部件120的具体实施方式，本实施例并不作具体限定。
在一实施例中，相位比较组件130可以包括有如FPGA芯片等的信号处理芯片，也可以包括有如比较器等的逻辑处理芯片，本实施例并不作具体限定。
当相位比较组件130包括有如FPGA芯片等的信号处理芯片时，在相位比较组件130接收到由鉴相部件120所输出的第一相位差信号的情况下，相位比较组件130可以先判断该第一相位差信号是否满足预设条件，当满足预设条件时，相位比较组件130输出对应的相位调整信号。例如，当相位比较组件130判断第一相位差信号处于第一预设区间范围内，相位比较组件130可以输出被设置成使参考时钟信号进行正移相的相位调整信号；而当相位比较组件130判断第一相位差信号处于第二预设区间范围内，则相位比较组件130可以输出被设置成使参考时钟信号进行负移相的相位调整信号。值得注意的是，预设条件可以根据实际应用需要而进行适当的设定，本实施例并不作具体限定；另外，第一预设区间范围和第二预设区间范围，也可以根据实际应用需要而进行适当的设定，本实施例并不作具体限定。
当相位比较组件130包括有如比较器等的逻辑处理芯片时，在相位比较组件130接收到由鉴相部件120所输出的第一相位差信号的情况下，相位比较组件130可以把该第一相位差信号与一个基准信号进行逻辑比较，并且根据第一相位差信号与该基准信号的比较结果而输出对应的相位调整信号。例如，当第一相位差信号大于该基准信号，相位比较组件130可以输出被设置成使参考时钟信号进行负移相的相位调整信号；而当第一相位差信号小于该基准信号，则相位比较组件130可以输出被设置成使参考时钟信号进行正移相的相位调整信号。值得注意的是，基准信号可以为根据经验而设置的信号，也可以为与参考时钟信号相关的信号，可以根据实际应用需要而进行适当的设置，本实施例并不作具体限定。
另外，参照图2，在一实施例中，相位比较组件130包括但不限于有第一信号生成部件131和信号比较部件132，其中，第一信号生成部件131与鉴相部件120连接，信号比较部件132分别与第一信号生成部件131和信号处理组件110连接。第一信号生成部件131 能够被设置成根据第一相位差信号而得到第一电压信号；信号比较部件132则能够被设置成获取基准电压信号和该第一电压信号，并根据该基准电压信号和该第一电压信号得到被设置成对参考时钟信号进行相位调整的相位调整信号。
在一实施例中，第一信号生成部件131可以为电荷泵，电荷泵也被成为开关电容式电压变换器，能够通过充电储能而输出电压值。当第一信号生成部件131接收到由鉴相部件120所输出的第一相位差信号后，第一信号生成部件131可以根据第一相位差信号所表示的时长进行充电，从而得到第一电压信号，从而为后续步骤中得到相位调整信号提供必要的基础条件。
在一实施例中，信号比较部件132可以为电压比较器，其中，基准电压信号可以为根据经验而设置的电压信号，也可以为与参考时钟信号相关的电压信号，可以根据实际应用需要而进行适当的设置，本实施例并不作具体限定。当信号比较部件132获取到基准电压信号和第一电压信号后，信号比较部件132可以根据该基准电压信号和该第一电压信号得到被设置成对参考时钟信号进行相位调整的相位调整信号。例如，当第一电压信号的电压值大于基准电压信号的电压值，信号比较部件132可以输出一个电平值为高电平的相位调整信号，该电平值为高电平的相位调整信号可以被设置成使信号处理组件110对参考时钟信号进行负移相的相位调整；当第一电压信号的电压值小于基准电压信号的电压值，信号比较部件132可以输出一个电平值为低电平的相位调整信号，该电平值为低电平的相位调整信号可以被设置成使信号处理组件110对参考时钟信号进行正移相的相位调整；当第一电压信号的电压值等于基准电压信号的电压值，信号比较部件132可以输出一个电平值为中间电平的相位调整信号，该电平值为中间电平的相位调整信号可以被设置成使信号处理组件110停止对参考时钟信号进行相位调整操作。值得注意的是，中间电平为介于高电平和低电平之间的电平。因此，通过第一信号生成部件131和信号比较部件132的相互配合，能够为信号处理组件110对参考时钟信号进行的相位调整提供准确的调整方向，从而能够使得参考时钟信号的相位可以逼近待测时钟信号的相位，从而可以逐渐提高由鉴相部件120输出的第一相位差信号的精度，进而可以提高对时钟信号的相位检测精度。
另外，参照图3，在一实施例中，相位比较组件130还可以包括第二信号生成部件133，其中，第二信号生成部件133与信号比较部件132连接。第二信号生成部件133可以被设置成获取相位参考信号，并根据该相位参考信号得到基准电压信号，其中，该相位参考信号根据参考时钟信号而得到。
在一实施例中，第二信号生成部件133可以为电荷泵，电荷泵也被成为开关电容式电压变换器，能够通过充电储能而输出电压值。当第二信号生成部件133接收到一个相位参考信号后，第二信号生成部件133可以根据该相位参考信号所表示的时长进行充电，从而得到基准电压信号，从而为后续步骤中得到相位调整信号提供必要的基础条件。
在一实施例中，相位参考信号可以根据参考时钟信号的周期而得到，例如，相位参考信号可以为参考时钟信号的半个周期，也可以为参考时钟信号的四分之一周期，可以根据实际使用需要而进行适当的选择，本实施例并不作具体限定。
在一实施例中，相位参考信号为预先设置的固定值，因此，第二信号生成部件133根据相位参考信号所表示的时长进行充电而得到的基准电压信号，也是一个固定值，从而可以便于与第一电压信号进行比较而得到相位调整信号。
另外，参照图4，在一实施例中，信号处理组件110包括但不限于有控制器111和移相部件112，其中，相位比较组件130、控制器111、移相部件112和鉴相部件120依次连接。控制器111能够被设置成获取参考时钟信号的初始相位值，以及能够被设置成根据由相位比较组件130所输出的相位调整信号得到移相信号，并能够被设置成向移相部件112发送该移相信号；移相部件112则能够被设置成获取参考时钟信号并根据该移相信号对参考时钟信号进行相位调整，以减小由鉴相部件120根据参考时钟信号和待测时钟信号而输出的第一相位差信号；此外，控制器111还能够被设置成累计移相信号以得到相位累计值，并根据该相位累计值和参考时钟信号的初始相位值得到待测时钟信号的相位值。
在一实施例中，控制器111可以有不同的实施方式，例如，控制器111可以为FPGA芯片，也可以为DSP芯片，还可以为由控制芯片和二分频器构成的组合，本实施例并不作具体限定。当控制器111为由控制芯片和二分频器构成的组合，二分频器可以负责产生二分信息(例如本实施例中的移相信号)，而控制芯片则可以负责对移相部件112配置该二分信息，使得移相部件112能够根据该二分信息调整参考时钟信号的相位的位移量。另外，移相部件112也可以有不同的实施方式，例如，移相部件112可以为数字移相器，也可以为具备配置功能的模拟移相器，本实施例并不作具体限定。
在一实施例中，当控制器111与移相部件112相配合以对参考时钟信号进行相位调整时，控制器111还可以累计移相信号以得到相位累计值，因此，当检测结束时，根据该相位累计值和参考时钟信号的初始相位值，即可得到待测时钟信号的相位值，从而实现对待测时钟信号的相位的检测处理。以一个具体示例进行说明，当控制器接收到相位调整信号后，控制器可以根据该相位调整信号得到移相信号
Figure PCTCN2021093649-appb-000001
其中，k为对参考时钟信号的相位调整次数，T为参考时钟信号的周期，因此，当控制器对该移相信号进行累计时，可以得到相位累计值为
Figure PCTCN2021093649-appb-000002
在一实施例中，当相位比较组件130包括信号比较部件132，并且信号比较部件132向控制器111输出被设置成对参考时钟信号进行相位调整的相位调整信号，控制器111可以根据相位调整信号的不同类型而向移相部件112发送不同类型的配置信息，以使移相部件112能够根据不同类型的配置信息对参考时钟信号进行不同的相位调整处理。例如，当相位调整信号的电平值为高电平，控制器111会向移相部件112发送一个表示进行负移相的配置信息，以使移相部件112根据该表示进行负移相的配置信息对参考时钟信号进行负移相的相位调整；当相位调整信号的电平值为低电平，控制器111会向移相部件112发送一个表示进行正移相的配置信息，以使移相部件112根据该表示进行正移相的配置信息对参考时钟信号进行正移相的相位调整；当相位调整信号的电平值为中间电平，则控制器111不会向移相部件112发送任何配置信息，即，移相部件112不对参考时钟信号进行相位调整。值得注意的是，中间电平为介于高电平和低电平之间的电平。因此，通过控制器111和移相部件112的相互配合，能够往准确的调整方向对参考时钟信号进行相位调整，使得 参考时钟信号的相位可以逼近待测时钟信号的相位，从而可以逐渐提高由鉴相部件120输出的第一相位差信号的精度，进而可以提高对时钟信号的相位检测精度。
另外，在一实施例中，信号处理组件110还包括有计数器，其中，该计数器可以内置于控制器111，也可以外置于控制器111并与控制器111连接。
在一实施例中，计数器的计数值不仅可以被设置成表示信号处理组件110对参考时钟信号的相位调整次数，还可以被设置成获得用来调整参考时钟信号的相位的移相信号。
在一实施例中，可以对计数器设置最大计数值，当计数器当前的计数值为最大计数值，即信号处理组件110对参考时钟信号的相位调整次数达到预设的最大调整次数，或者当控制器111接收到电平值为中间电平的相位调整信号，控制器111都会使计数器复位为0。在控制器111使计数器复位的情况下，说明相位测量结束，以便于进行下一次的相位检测。值得注意的是，中间电平为介于高电平和低电平之间的电平。
另外，在一实施例中，控制器111具体被设置成通过如下公式根据相位累计值和初始相位值得到待测时钟信号的相位值：
Figure PCTCN2021093649-appb-000003
其中，T1为待测时钟信号的相位值；T2为参考时钟信号的初始相位值；
Figure PCTCN2021093649-appb-000004
为相位累计值；T为参考时钟信号的周期；n为对参考时钟信号进行的相位调整次数，n≥1。
在一实施例中，
Figure PCTCN2021093649-appb-000005
决定了相位检测的精度，以一个具体示例进行说明：
例如需要对频率为125MHz的打戳时钟信号进行相位检测，该打戳时钟信号的周期为8ns，那么，在利用一个与该打戳时钟信号具有相同频率的参考时钟信号，通过本实施例的相位检测装置100对该打戳时钟信号进行相位检测的情况下，当设定计数器的最大计数值为10，即设定信号处理组件110对参考时钟信号的相位调整次数为9次(最初一次并不调整参考时钟信号的相位)，那么，在这个情况下，根据上述公式可知，最终得到的测量精度约为8ps。而如果利用一些情况中遍历一个时钟周期以获取相位信息的方式进行测量时，如果需要达到同样的测量精度，即以8ps为步进遍历一个时钟周期以获取相位信息时，需要进行1000次移相操作，因此，与一些情况相比，本实施例具有更优的相位检测速度；另外，当执行相同的移相次数时，由上述示例可知，与一些情况相比，本实施例具有更优的相位检测精度。
另外，参照图5，本发明另一个实施例还提供了一种相位检测装置，该相位检测装置200包括控制器211、数字移相器212、数字鉴相器220、第一电荷泵231、电压比较器232、第二电荷泵233和计数器213，其中，控制器211、数字移相器212、数字鉴相器220、第一电荷泵231和电压比较器232依次首尾连接，控制器211还与计数器213连接，电压比较器232还与第二电荷泵233连接。
参照图5，当利用该相位检测装置200对待测时钟信号进行相位检测时，该相位检测 装置200中的各个器件相互配合以执行如下的检测原理：
在开始执行相位检测操作之前，第二电荷泵233先进行时长为
Figure PCTCN2021093649-appb-000006
的充电处理以得到电压值为Vref的基准电压信号，其中，T为参考时钟信号的周期，并且，第二电荷泵233把该基准电压信号发送给电压比较器232。
控制器211设置计数器213的最大计数值为n，并使计数器213从0开始进行计数。
在开始执行相位检测操作之前，由于计数器213当前的计数值为0，因此不对参考时钟信号进行相位调整，此时，数字移相器212向数字鉴相器220输出初始的参考时钟信号，数字鉴相器220根据初始的参考时钟信号和待测时钟信号得到并向第一电荷泵231输出第一相位差信号，第一电荷泵231根据第一相位差信号所表示的时长进行充电，并向电压比较器232输出第一电压信号，电压比较器232根据第一电压信号和基准电压信号得到并向控制器211输出相位调整信号。
当控制器211接收到该相位调整信号时，开始执行对待测时钟信号的相位检测操作，此时，计数器213的计数值增加1；当相位调整信号的电平值为高电平时，控制器211会配合数字移相器212使得参考时钟信号以位移量为
Figure PCTCN2021093649-appb-000007
进行负移相，以使参考时钟信号的相位能够逼近待测时钟信号的相位；当相位调整信号的电平值为低电平时，控制器211会配合数字移相器212使得参考时钟信号以位移量为
Figure PCTCN2021093649-appb-000008
进行正移相，以使参考时钟信号的相位能够逼近待测时钟信号的相位。
当控制器211和数字移相器212配合以调整参考时钟信号的相位后，经过相位调整的参考时钟信号会被输入到数字鉴相器220之中，此时，数字鉴相器220会根据经过相位调整的参考时钟信号和待测时钟信号而得到并输出一个新的第一相位差信号，而第一电荷泵231和电压比较器232则相互配合以根据该新的第一相位差信号向控制器211输出一个新的相位调整信号，如此循环检测，直到计数器213的计数值达到预设的最大计数值，完成对待测时钟信号的相位检测操作。此时，可以得到如下结果：
Figure PCTCN2021093649-appb-000009
其中，T1为待测时钟信号的相位值；T2为参考时钟信号的初始相位值；
Figure PCTCN2021093649-appb-000010
为相位累计值；T为参考时钟信号的周期；n为对参考时钟信号进行的相位调整次数，n≥1。
此外，值得注意的是，当相位调整信号的电平值为中间电平(即介于高电平和低电平之间的电平)时，说明参考时钟信号的相位和待测时钟信号的相位之间相差半个周期，此时，停止对参考时钟信号的相位调整操作，相位检测操作结束。在这种情况下，同样可以根据上述公式而得到待测时钟信号的相位值，此处不再赘述。
以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，参照图6，本发明的一个实施例还提供了一种相位检测方法，该相位检测方法可以应用于如上装置实施例中的相位检测装置，该相位检测方法包括但不限于以下步骤：
步骤S100，信号处理组件获取参考时钟信号和参考时钟信号的初始相位值，并向鉴相部件输出参考时钟信号；
步骤S200，鉴相部件获取待测时钟信号，并根据参考时钟信号和待测时钟信号得到第一相位差信号，且向相位比较组件输出第一相位差信号；
步骤S300，相位比较组件根据第一相位差信号得到相位调整信号，并向信号处理组件输出相位调整信号；
步骤S400，信号处理组件根据相位调整信号对参考时钟信号进行相位调整，以减小第一相位差信号，并累计调整的相位值以得到相位累计值，且根据相位累计值和初始相位值得到待测时钟信号的相位值。
在一实施例中，待测时钟信号为需要进行相位检测的时钟信号，参考时钟信号为已知的被设置成对待测时钟信号的相位进行检测的时钟信号，在信号处理组件首次获取到参考时钟信号时，信号处理组件可以获取到参考时钟信号的初始相位值，从而为后续操作中得到待测时钟信号的相位值提供必要的基础条件。
在一实施例中，第一相位差信号为由鉴相部件根据参考时钟信号和待测时钟信号而得到的信号，由于受限于鉴相部件的制作工艺或者计算精度等问题，鉴相部件所输出的第一相位差信号并不准确，因此，通过把由鉴相部件输出的第一相位差信号传输到相位比较组件，使得相位比较组件能够根据该第一相位差信号得到相位调整信号，并把该相位调整信号传输给信号处理组件，而信号处理组件则根据该相位调整信号对参考时钟信号进行相位调整，以减小该第一相位差信号的数值，即，通过鉴相部件、相位比较组件及信号处理组件之间的相互配合，对参考时钟信号的相位进行调整而逐渐减小由鉴相部件所输出的第一相位差信号，使得参考时钟信号的相位能够逐渐逼近待测时钟信号的相位，从而可以提高鉴相部件根据参考时钟信号和待测时钟信号而得到的第一相位差信号的精度。此外，由于对参考时钟信号进行的相位调整是在第一相位差信号的数值范围内执行的，并且以减小第一相位差信号为目的，所以，仅需要在第一相位差信号的数值范围内进行有限次数的处理，即可实现对待测时钟信号的相位检测，相比于一些情况中遍历一个时钟周期以获取相位信息的方式，本实施例能够具有更优的相位检测速度，所以，本实施例能够提高对时钟信号的相位检测精度和相位检测速度。
值得注意的是，由于本实施例的相位检测方法可以应用于上述装置实施例中的相位检测装置，因此，本实施例中的信号处理组件、鉴相部件和相位比较组件的具体实现方式，可以参照上述装置实施例中的相关描述，此处不再赘述。
另外，在一实施例中，当相位比较组件包括第一信号生成部件和信号比较部件，并且信号处理组件、鉴相部件、第一信号生成部件和信号比较部件依次首尾连接，那么，参照图7，该步骤S300可以包括但不限于以下步骤：
步骤S310，第一信号生成部件根据第一相位差信号得到第一电压信号，并向信号比较 部件输出第一电压信号；
步骤S320，信号比较部件获取基准电压信号和第一电压信号，并根据基准电压信号和第一电压信号得到相位调整信号，信号比较部件向信号处理组件输出相位调整信号。
在一实施例中，第一信号生成部件可以为电荷泵，电荷泵也被成为开关电容式电压变换器，能够通过充电储能而输出电压值。当第一信号生成部件接收到由鉴相部件所输出的第一相位差信号后，第一信号生成部件可以根据第一相位差信号所表示的时长进行充电，从而得到第一电压信号，从而为后续步骤中得到相位调整信号提供必要的基础条件。
在一实施例中，基准电压信号可以为根据经验而设置的电压信号，也可以为与参考时钟信号相关的电压信号，可以根据实际应用需要而进行适当的设置，本实施例并不作具体限定。
在一实施例中，当信号比较部件获取到基准电压信号和第一电压信号后，信号比较部件可以根据该基准电压信号和该第一电压信号得到被设置成对参考时钟信号进行相位调整的相位调整信号，例如，当第一电压信号的电压值大于基准电压信号的电压值，信号比较部件可以输出一个电平值为高电平的相位调整信号，该电平值为高电平的相位调整信号可以被设置成使信号处理组件对参考时钟信号进行负移相的相位调整；又如，当第一电压信号的电压值小于基准电压信号的电压值，信号比较部件可以输出一个电平值为低电平的相位调整信号，该电平值为低电平的相位调整信号可以被设置成使信号处理组件对参考时钟信号进行正移相的相位调整；再如，当第一电压信号的电压值等于基准电压信号的电压值，信号比较部件可以输出一个电平值为中间电平(即介于高电平和低电平之间的电平)的相位调整信号，该电平值为中间电平的相位调整信号可以被设置成使信号处理组件停止对参考时钟信号进行相位调整操作。值得注意的是，上述的信号比较部件根据基准电压信号和第一电压信号得到相位调整信号的各个具体示例之间，可以根据实际情况而形成不同的组合示例，为了避免内容重复，此处不再赘述。
在一实施例中，通过第一信号生成部件和信号比较部件的相互配合，能够为信号处理组件对参考时钟信号进行的相位调整提供准确的调整方向，从而能够使得参考时钟信号的相位可以逼近待测时钟信号的相位，从而可以逐渐提高由鉴相部件输出的第一相位差信号的精度，进而可以提高对时钟信号的相位检测精度。
另外，在一实施例中，当相位比较组件还包括第二信号生成部件，并且第二信号生成部件和信号比较部件连接，那么，参照图8，该相位检测方法还可以包括有以下步骤：
步骤S500，第二信号生成部件获取相位参考信号，并根据相位参考信号得到基准电压信号，其中，相位参考信号为根据参考时钟信号而得到；
步骤S600，第二信号生成部件向信号比较部件输出基准电压信号。
在一实施例中，第二信号生成部件可以为电荷泵，电荷泵也被成为开关电容式电压变换器，能够通过充电储能而输出电压值。当第二信号生成部件接收到一个相位参考信号后，第二信号生成部件可以根据该相位参考信号所表示的时长进行充电，从而得到基准电压信号，从而为后续步骤中得到相位调整信号提供必要的基础条件。
在一实施例中，相位参考信号可以根据参考时钟信号的周期而得到，例如，相位参考信号可以为参考时钟信号的半个周期，也可以为参考时钟信号的四分之一周期，可以根据实际使用需要而进行适当的选择，本实施例并不作具体限定。
另外，在一实施例中，步骤S400中的信号处理组件根据相位调整信号对参考时钟信号进行相位调整，在不同实施例中可以包括有不同的具体步骤：
步骤S401，当相位调整信号的电平值为高电平，信号处理组件对参考时钟信号进行负移相的相位调整。
步骤S402，当相位调整信号的电平值为低电平，信号处理组件对参考时钟信号进行正移相的相位调整。
步骤S403，当相位调整信号的电平值为中间电平，信号处理组件不对参考时钟信号进行相位调整，其中，中间电平为介于高电平和低电平之间的电平。
值得注意的是，上述步骤S401、步骤S402和步骤S403之间可以互为并列的技术方案，也可以相互组合而形成不同的技术方案，可以根据实际情况而进行适当的选择，本实施例对此并不作具体限定。
在一实施例中，根据相位调整信号的不同电平值，信号处理组件可以对参考时钟信号进行不同方向的相位调整，从而能够使得参考时钟信号的相位可以逼近待测时钟信号的相位，从而可以逐渐提高由鉴相部件输出的第一相位差信号的精度，进而可以提高对时钟信号的相位检测精度。
另外，在一实施例中，当信号处理组件包括控制器和移相部件，并且相位比较组件、控制器、移相部件和鉴相部件依次首尾连接，那么，参照图9，该步骤S400可以包括但不限于以下步骤：
步骤S410，控制器根据相位调整信号得到移相信号，并向移相部件输出移相信号；
步骤S420，移相部件根据移相信号对参考时钟信号进行相位调整，以减小第一相位差信号；
步骤S430，控制器累计移相信号以得到相位累计值，并根据相位累计值和初始相位值得到待测时钟信号的相位值。
在一实施例中，当控制器与移相部件相配合以对参考时钟信号进行相位调整时，控制器还可以累计移相信号以得到相位累计值，因此，当检测结束时，根据该相位累计值和参考时钟信号的初始相位值，即可得到待测时钟信号的相位值，从而实现对待测时钟信号的相位的检测处理。以一个具体示例进行说明，当控制器接收到相位调整信号后，控制器可以根据该相位调整信号得到移相信号
Figure PCTCN2021093649-appb-000011
其中，k为对参考时钟信号的相位调整次数，T为参考时钟信号的周期，因此，当控制器对该移相信号进行累计时，可以得到相位累计值为
Figure PCTCN2021093649-appb-000012
在一实施例中，当控制器接收到相位调整信号后，控制器可以根据相位调整信号的不同类型而向移相部件发送不同类型的配置信息，以使移相部件能够根据不同类型的配置信息对参考时钟信号进行不同的相位调整处理。例如，当相位调整信号的电平值为高电平，控制器会向移相部件发送一个表示进行负移相的配置信息，以使移相部件根据该表示进行 负移相的配置信息对参考时钟信号进行负移相的相位调整；当相位调整信号的电平值为低电平，控制器会向移相部件发送一个表示进行正移相的配置信息，以使移相部件根据该表示进行正移相的配置信息对参考时钟信号进行正移相的相位调整；当相位调整信号的电平值为中间电平，则控制器不会向移相部件发送任何配置信息，即，移相部件不对参考时钟信号进行相位调整。值得注意的是，中间电平为介于高电平和低电平之间的电平。因此，通过控制器和移相部件的相互配合，能够往准确的调整方向对参考时钟信号进行相位调整，使得参考时钟信号的相位可以逼近待测时钟信号的相位，从而可以逐渐提高由鉴相部件输出的第一相位差信号的精度，进而可以提高对时钟信号的相位检测精度。
另外，在一实施例中，当信号处理组件还包括计数器，并且计数器内置于控制器，或者计数器外置于控制器并与控制器连接，那么，参照图10，步骤S410中的控制器根据相位调整信号得到移相信号，可以包括有以下具体步骤：
步骤S411，控制器获取计数器中的计数值；
步骤S412，控制器根据计数值得到移相信号。
在一实施例中，计数器的计数值不仅可以被设置成表示信号处理组件对参考时钟信号的相位调整次数，还可以被设置成获得用来调整参考时钟信号的相位的移相信号。因此，通过获取计数器中的计数值，能够便于获得被设置成对参考时钟信号进行相位调整的移相信号，并且能够根据该计数值而统计累计的移相信号，以便于得到待测时钟信号的相位值。
在一实施例中，可以对计数器设置最大计数值，当计数器当前的计数值为最大计数值，即信号处理组件对参考时钟信号的相位调整次数达到预设的最大调整次数，控制器可以使计数器复位为0，在控制器使计数器复位的情况下，说明相位测量结束，以便于进行下一次的相位检测。
另外，在一实施例中，步骤S430中的控制器根据相位累计值和初始相位值得到待测时钟信号的相位值，可以包括有以下具体步骤：
步骤S431，控制器通过如下公式根据相位累计值和初始相位值得到待测时钟信号的相位值：
Figure PCTCN2021093649-appb-000013
其中，T1为待测时钟信号的相位值；T2为初始相位值；
Figure PCTCN2021093649-appb-000014
为相位累计值；T为参考时钟信号的周期；n为对参考时钟信号进行的相位调整次数，n≥1。
在一实施例中，根据上述公式可知，
Figure PCTCN2021093649-appb-000015
决定了相位检测的精度，即，当利用本实施例的相位检测方法对待测时钟信号进行相位检测时，只需对参考时钟信号进行有限次数的移相处理，即可达到较为精确的测量精度，例如对频率为125MHz的打戳时钟信号进行相位检测，只需对参考时钟信号进行9次相位调整，即可得到测量精度约为8ps的检测结果，而如果利用一些情况术中遍历一个时钟周期以获取相位信息的方式进行测量时，如果 需要达到同样的测量精度，即以8ps为步进遍历一个时钟周期以获取相位信息时，需要进行移相操作1000次，因此，与一些情况相比，本实施例具有更优的相位检测速度；另外，当执行相同的移相次数时，由上述分析可知，与一些情况相比，本实施例具有更优的相位检测精度。
此外，参照图11，本发明的一个实施例还提供了一种设备，该设备可以包括有如上任一装置实施例中的相位检测装置。
由于本实施例中的设备包括有如上任一实施例中的相位检测装置，因此本实施例中的设备具有上述实施例中相位检测装置的硬件结构，并且，相位检测装置中的各个部件之间能够相互配合以使本实施例的设备能够执行上述任一方法实施例中的相位检测方法，因此，本实施例的设备的具体实施方式可参照上述实施例，为避免冗余，在此不再赘述。
由于本实施例中的设备具有如上任一实施例中的相位检测装置，因此本实施例中的设备具有上述实施例中相位检测装置所带来的技术效果，即，与一些情况相比，本实施例中的设备能够提高对时钟信号的相位检测精度和相位检测速度。
本发明实施例提供了一种相位检测方法及其装置、设备，能够提高对时钟信号的相位检测精度和相位检测速度。
本发明实施例中，能够通过有限次数的处理使得参考时钟信号的相位逼近待测时钟信号的相位，从而能够高精度、高速度的完成对时钟相位的测量。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统可以被实施为软件、固件、硬件及其适当的组合。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上是对本发明的一些实施进行了具体说明，但本发明并不局限于上述实施方式，熟悉本领域的技术人员在不违背本发明范围的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本发明权利要求所限定的范围内。

Claims (15)

  1. 一种相位检测装置，包括：
    信号处理组件，被设置成获取参考时钟信号和所述参考时钟信号的初始相位值，并输出所述参考时钟信号；
    鉴相部件，与所述信号处理组件连接，被设置成获取待测时钟信号，并根据所述参考时钟信号和所述待测时钟信号得到且输出第一相位差信号；
    相位比较组件，分别与所述鉴相部件和所述信号处理组件连接，被设置成根据所述第一相位差信号得到并输出相位调整信号；
    所述信号处理组件还被设置成根据所述相位调整信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号，并累计调整的相位值以得到相位累计值，且根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值。
  2. 根据权利要求1所述的相位检测装置，其中，所述相位比较组件包括：
    第一信号生成部件，与所述鉴相部件连接，被设置成根据所述第一相位差信号得到并输出第一电压信号；
    信号比较部件，分别与所述第一信号生成部件和所述信号处理组件连接，被设置成获取基准电压信号和所述第一电压信号，并根据所述基准电压信号和所述第一电压信号得到且输出所述相位调整信号。
  3. 根据权利要求2所述的相位检测装置，其中，所述相位比较组件还包括：
    第二信号生成部件，与所述信号比较部件连接，被设置成获取相位参考信号，并根据所述相位参考信号得到且输出所述基准电压信号，其中，所述相位参考信号为根据所述参考时钟信号而得到。
  4. 根据权利要求1至3任一项所述的相位检测装置，其中，所述信号处理组件包括：
    控制器，与所述相位比较组件连接，被设置成获取所述参考时钟信号的初始相位值以及根据所述相位调整信号得到并输出移相信号；
    移相部件，分别与所述控制器和所述鉴相部件连接，被设置成获取所述参考时钟信号并根据所述移相信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号；
    所述控制器还被设置成累计所述移相信号以得到相位累计值，并根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值。
  5. 根据权利要求4所述的相位检测装置，其中，所述信号处理组件还包括：
    计数器，内置于所述控制器，或者外置于所述控制器并与所述控制器连接。
  6. 根据权利要求4所述的相位检测装置，其中，所述控制器被设置成通过如下公式根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值：
    Figure PCTCN2021093649-appb-100001
    其中，T1为所述待测时钟信号的相位值；T2为所述初始相位值；
    Figure PCTCN2021093649-appb-100002
    为所述相位累计值；T为所述参考时钟信号的周期；n为对所述参考时钟信号进行的相位调整次 数，n≥1。
  7. 一种相位检测方法，应用于相位检测装置，所述相位检测装置包括依次首尾连接的信号处理组件、鉴相部件和相位比较组件；
    所述方法包括：
    所述信号处理组件获取参考时钟信号和所述参考时钟信号的初始相位值，并向所述鉴相部件输出所述参考时钟信号；
    所述鉴相部件获取待测时钟信号，并根据所述参考时钟信号和所述待测时钟信号得到第一相位差信号，且向所述相位比较组件输出所述第一相位差信号；
    所述相位比较组件根据所述第一相位差信号得到相位调整信号，并向所述信号处理组件输出所述相位调整信号；
    所述信号处理组件根据所述相位调整信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号，并累计调整的相位值以得到相位累计值，且根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值。
  8. 根据权利要求7所述的方法，其中，所述相位比较组件包括第一信号生成部件和信号比较部件，所述信号处理组件、所述鉴相部件、所述第一信号生成部件和所述信号比较部件依次首尾连接；
    所述相位比较组件根据所述第一相位差信号得到相位调整信号，并向所述信号处理组件输出所述相位调整信号，包括：
    所述第一信号生成部件根据所述第一相位差信号得到第一电压信号，并向所述信号比较部件输出所述第一电压信号；
    所述信号比较部件获取基准电压信号和所述第一电压信号，并根据所述基准电压信号和所述第一电压信号得到相位调整信号，所述信号比较部件向所述信号处理组件输出所述相位调整信号。
  9. 根据权利要求8所述的方法，其中，所述信号比较部件根据所述基准电压信号和所述第一电压信号得到相位调整信号，包括如下至少之一：
    当所述第一电压信号大于所述基准电压信号，所述信号比较部件输出电平值为高电平的相位调整信号；
    当所述第一电压信号等于所述基准电压信号，所述信号比较部件输出电平值为中间电平的相位调整信号，其中，中间电平为介于高电平和低电平之间的电平；
    当所述第一电压信号小于所述基准电压信号，所述信号比较部件输出电平值为低电平的相位调整信号。
  10. 根据权利要求8所述的方法，其中，所述相位比较组件还包括第二信号生成部件，所述第二信号生成部件和所述信号比较部件连接；
    所述方法还包括：
    所述第二信号生成部件获取相位参考信号，并根据所述相位参考信号得到基准电压信号，其中，所述相位参考信号为根据所述参考时钟信号而得到；
    所述第二信号生成部件向所述信号比较部件输出所述基准电压信号。
  11. 根据权利要求7所述的方法，其中，所述信号处理组件根据所述相位调整信号对所述参考时钟信号进行相位调整，包括如下至少之一：
    当所述相位调整信号的电平值为高电平，所述信号处理组件对所述参考时钟信号进行负移相的相位调整；
    当所述相位调整信号的电平值为低电平，所述信号处理组件对所述参考时钟信号进行正移相的相位调整；
    当所述相位调整信号的电平值为中间电平，所述信号处理组件不对所述参考时钟信号进行相位调整，其中，中间电平为介于高电平和低电平之间的电平。
  12. 根据权利要求7至11任一项所述的方法，其中，所述信号处理组件包括控制器和移相部件，所述相位比较组件、所述控制器、所述移相部件和所述鉴相部件依次首尾连接；
    所述信号处理组件根据所述相位调整信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号，并累计调整的相位值以得到相位累计值，且根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值，包括：
    所述控制器根据所述相位调整信号得到移相信号，并向所述移相部件输出所述移相信号；
    所述移相部件根据所述移相信号对所述参考时钟信号进行相位调整，以减小所述第一相位差信号；
    所述控制器累计所述移相信号以得到相位累计值，并根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值。
  13. 根据权利要求12所述的方法，其中，所述信号处理组件还包括计数器，所述计数器内置于所述控制器，或者外置于所述控制器并与所述控制器连接；
    所述控制器根据所述相位调整信号得到移相信号，包括：
    所述控制器获取所述计数器中的计数值；
    所述控制器根据所述计数值得到移相信号。
  14. 根据权利要求12所述的方法，其中，所述控制器根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值，包括，
    所述控制器通过如下公式根据所述相位累计值和所述初始相位值得到所述待测时钟信号的相位值：
    Figure PCTCN2021093649-appb-100003
    其中，T1为所述待测时钟信号的相位值；T2为所述初始相位值；
    Figure PCTCN2021093649-appb-100004
    为所述相位累计值；T为所述参考时钟信号的周期；n为对所述参考时钟信号进行的相位调整次数，n≥1。
  15. 一种设备，包括有如权利要求1至6任一项所述的相位检测装置。
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