WO2021226920A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

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Publication number
WO2021226920A1
WO2021226920A1 PCT/CN2020/090192 CN2020090192W WO2021226920A1 WO 2021226920 A1 WO2021226920 A1 WO 2021226920A1 CN 2020090192 W CN2020090192 W CN 2020090192W WO 2021226920 A1 WO2021226920 A1 WO 2021226920A1
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WO
WIPO (PCT)
Prior art keywords
detection
trace
wiring
traces
display
Prior art date
Application number
PCT/CN2020/090192
Other languages
English (en)
French (fr)
Inventor
石领
黄建邦
张�浩
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/270,966 priority Critical patent/US20220123088A1/en
Priority to CN202080000732.4A priority patent/CN113939864A/zh
Priority to PCT/CN2020/090192 priority patent/WO2021226920A1/zh
Priority to EP20904263.9A priority patent/EP3998599A4/en
Publication of WO2021226920A1 publication Critical patent/WO2021226920A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the embodiment of the present disclosure relates to a display panel and a manufacturing method thereof.
  • OLED Organic Light Emitting Diode
  • TFT thin film transistor
  • At least one embodiment of the present disclosure provides a display panel having a display side and a non-display side, including a display area and a bending area located on one side of the display area, the bending area including at least one first Wiring, the bending area can be operatively bent from the display side to the non-display side, the display area includes a second wiring, and the first end of the at least one first wiring is electrically connected In the second wiring, the second end of the at least one first wiring is bent to the non-display side through the bending area;
  • the detection trace and the bending area are only located on the side of the side away from the display area.
  • the at least one first wiring includes a plurality of first wirings
  • the plurality of first wirings includes a first group of wirings and a second group of wirings
  • the first group of wires and the second group of wires are insulated from each other and are suitable for transmitting different electrical signals respectively, and the detection wires are arranged between the first group of wires and the second group of wires. between.
  • the first group of wires are power wires
  • the second group of wires are data wires
  • the traces are power lines that transmit different potentials.
  • the shape and size of the first trace per unit length and the detection trace per unit length are substantially the same.
  • the first wiring and the detection wiring both extend in a bent shape or have a hollow structure.
  • the detection traces are arranged in a plurality of rows electrically connected end to end, and the first end and the second end of the detection trace are divided into the plurality of rows.
  • the first end and the second end of the detection trace are both located on the non-display side.
  • the sum of the number of the first wiring and the number of the detection wiring is less than or equal to 500, and the two adjacent rows
  • the first spacing of the detection traces is 10-12 microns, and the sum of the line width of the detection traces and the first spacing is 60-80 microns; or the number of the first traces and the detection traces
  • the sum of the number of rows is greater than 500 and less than or equal to 2000, the first spacing of two adjacent rows of detection traces is 6-10 microns, and the sum of the line width of the detection traces and the first spacing is 25-60 Micrometers; or the sum of the number of the first traces and the number of rows of detection traces is greater than 2000, the first distance between two adjacent rows of detection traces is 5-6 microns, and the line width of the detection traces is equal to
  • the sum of the first pitch is 15-25 microns.
  • the second pitch between two adjacent first traces is the same as the first pitch, and the line width of the first trace is equal to that of the first trace.
  • the sum of the second pitch is the same as the sum of the line width of the detection trace and the sum of the first pitch.
  • the thickness of the first trace and the detection trace are the same, and the thickness is 700nm-850nm .
  • the detection wiring and at least part of the plurality of first wirings are provided in the same layer.
  • the display area includes a plurality of sub-pixels arranged in an array, and each of the plurality of sub-pixels includes a light-emitting device and a pixel driver electrically connected to the light-emitting device.
  • a circuit, the pixel driving circuit includes a thin film transistor, the thin film transistor includes a gate and a source and drain, and the detection trace is arranged on the same layer as the gate or on the same layer as the source and drain.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display panel, the display panel having a display side and a non-display side, and the method includes: forming a display area and a bending area located on one side of the display area, Wherein, at least one first wiring and a detection wiring arranged in parallel with the at least one first wiring are formed in the bending area, and the detection wiring includes a first end and a second end for detecting Connected to an external detection circuit, the detection trace and the bending area are only formed on the side of the side away from the display area; a second trace is formed in the display area, and the at least one first The first end of the trace is electrically connected to the second trace; the bending area is bent so that the second end of the at least one first trace is bent to the non-display through the bending area Side, and at least part of the detection trace is bent along with the bending area.
  • the method for manufacturing a display panel provided by at least one embodiment of the present disclosure further includes: after bending the bending area, connecting the first end and the second end of the detection trace to an external detection circuit, the The external detection circuit detects the resistance of the detection wiring and compares the resistance with a reference resistance to determine the state of the detection wiring.
  • the detection trace when the difference between the resistance and the reference resistance is greater than ten percent of the reference resistance, it is determined that the detection trace is in a damaged state; When the difference between the resistance and the reference resistance is less than or equal to ten percent of the reference resistance, it is determined that the detection trace is in a normal state.
  • the at least one first wiring includes a plurality of first wirings
  • the plurality of first wirings includes a first group of wirings and a second wiring.
  • the first group of wires and the second group of wires are insulated from each other and are suitable for transmitting different electrical signals respectively, and the detection wires are formed in the first group of wires and the second group of wires Between the lines.
  • the detection wiring is formed in the same layer as at least part of the plurality of first wirings.
  • forming the display area further includes forming a plurality of sub-pixels arranged in an array, and each of the plurality of sub-pixels includes a light-emitting device and interacts with the light-emitting device.
  • FIG. 1 is a schematic partial plan view of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a display panel provided by at least one embodiment of the present disclosure
  • 3A is a schematic plan view of a bending area of a display panel provided by at least one embodiment of the present disclosure
  • 3B is a schematic plan view of the wiring arrangement of the bending area of the display panel provided by at least one embodiment of the present disclosure
  • FIG. 4 is a schematic plan view of a bending area of another display panel provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic plan view of detecting traces in a bending area of a display panel provided by at least one embodiment of the present disclosure
  • 6A-6D are schematic diagrams of detecting traces per unit length in the bending area of the display panel provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of the first wiring and the detection wiring in the bending area of the display panel provided by at least one embodiment of the present disclosure
  • FIG. 8 is a schematic cross-sectional view of a display area of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic cross-sectional view of a bending area of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a manufacturing method of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a flowchart of another method of manufacturing a display panel provided by at least one embodiment of the present disclosure.
  • the non-display area of the display panel can be bent to the non-display side of the display panel through the bendable area to increase the display area.
  • the bendable area includes multiple wires that electrically connect the display area and the display panel driving chip. These wires may break during the bending of the bendable area. If the wires are broken, the display panel Unable to work normally.
  • At least one embodiment of the present disclosure provides a display panel and a manufacturing method thereof.
  • the display panel has a display side and a non-display side, and includes a display area and a bending area located on one side of the display area. Wiring, the bending area can be operatively bent from the display side to the non-display side, the display area includes a second wiring, the first end of at least one first wiring is electrically connected to the second wiring, at least one first wiring The second end of the line is bent to the non-display side through the bending area.
  • the bending area also includes a detection trace arranged side by side with at least one first trace. At least part of the detection trace is bent with the bending area.
  • the detection trace includes a first end and a second end for connecting to an external detection line. Circuit; the detection trace and the bending area are only located on the side of the aforementioned side away from the display area. After the bending area is bent, by detecting the detection trace in the bending area of the display panel, the status of the detection trace can be obtained, and it can be judged whether the detection trace remains normal after bending, so that The state of the traces used to transmit the display signal to the display area in the bending area is inferred, which in turn provides help for the structural design and manufacturing process of the bending area.
  • Fig. 1 shows a schematic partial plan view of a display panel provided by at least one embodiment of the present disclosure
  • Fig. 2 shows a schematic cross-sectional view of the display panel after bending.
  • the display panel has a display side (that is, the upper side of the display panel shown in Figure 2) and a non-display side (that is, the lower side of the display panel shown in Figure 2), including a display
  • the bending area B can be operatively bent from the display side to the non-display side, that is, after the bending area B is bent, the structure in the bending area B can be bent and deformed adaptively and remains Workable state, such as realizing the required electrical connection or signal transmission.
  • the display area AA includes one or more second traces 102 (one second trace 102 is shown as an example in FIG. 1), and the first end 1011 of at least one first trace 101 is electrically connected to the corresponding second trace. Line 102, the second end 1012 of at least one first trace 101 is folded to the non-display side through the bending area B.
  • the bending area B includes detection wires 103 arranged side by side with at least one first wire 101, for example, at least one first wire 101 and detection wires 103 are along the bending axis of the bending area B (the bending axis in the figure).
  • the length direction of the area B is arranged side by side, at least part of the detection wiring 103 is bent with the bending area B, the detection wiring 103 includes a first end 1031 and a second end 1032, which are used to connect an external detection circuit .
  • the detection trace 103 and the bending area B are only located on the side of the aforementioned side away from the display area AA.
  • the detection wiring 103 and the bending area B are only located on one side of the display area AA, for example, the detection wiring 103 does not surround the display area AA.
  • the display area AA includes a plurality of second traces 102
  • the bending area B includes a plurality of first traces 101
  • the first ends of the plurality of first traces 101 are connected to the plurality of second traces.
  • the wiring 102 is electrically connected, and the second ends of the multiple first wirings 101 are folded to the non-display side through the bending area B, so that the multiple first wirings 101 can go to multiple display areas AA in the non-display side direction.
  • the second trace 102 provides electrical signals.
  • the state of the detection wire 103 can be obtained, and then it can be judged whether the detection wire 103 is normal after bending, and thus It can be inferred that the state of the first wiring 101 arranged in parallel with the detection wiring 103 in the bending area B and used for transmitting electrical signals for the display area AA.
  • resistance detection can be performed on the detection trace 103. When the detected resistance value of the detection trace 103 is greater than a reference resistance, it can be determined that the detection trace 103 is abnormal, such as a significant crack or break.
  • the structure of the bending area B needs to be optimized. Design and manufacturing process; for example, when the detected resistance value of the detection trace 103 is less than the reference resistance, it can be judged that the detection trace 103 is normal, and then it can be inferred that the detection trace 103 and the detection trace 103 are arranged side by side in the bending area B.
  • the first wiring 101 used to transmit electrical signals for the display area AA can also work normally.
  • the structure of the bending area B is reasonably designed and qualified.
  • the aforementioned reference resistance is the average resistance measured when the detection trace 103 is in a normal state.
  • the display panel further includes a driver chip IC (Integrated Circuit) for driving the display area AA for display operations, and the second end 1012 of the first wiring 101 is electrically connected to the driver.
  • the chip IC electrically connects the second wiring 102 in the display area AA with the driving chip IC, and then provides electrical signals for the display area AA through the first wiring 101, such as display signals, control signals, and timing signals.
  • the driving chip IC is bent to the non-display side of the display panel.
  • the display panel may further include a flexible printed circuit board (FPC), and the second end 1012 of the first wiring 101 may also be electrically connected to the flexible printed circuit board FPC, for example, by bonding.
  • the flexible circuit board FPC may further include a driving circuit, the second end 1012 of the first wiring 101 is electrically connected to the driving circuit, and the driving circuit transmits electrical signals to the display area AA through the first wiring 101 , Such as touch signal or clock signal.
  • the flexible circuit board FPC is bent to the non-display side of the display panel and overlaps with the display area, thereby helping to achieve a narrow frame design.
  • the driver chip IC or the flexible circuit board FPC is arranged on the non-display side of the display panel, and the plurality of first wires 101 are bent to electrically connect the plurality of second wires 102 located in the display area AA to the display panel.
  • Driver chip IC or flexible circuit board FPC on the non-display side.
  • the display panel may further include a first fan-shaped wiring area 10 located between the display area AA and the bending area B, and the first fan-shaped wiring area 10 includes a plurality of first A lead 1013 (one is shown as an example) is used to electrically connect the plurality of second wires 102 in the display area AA to the first ends 1011 of the plurality of first wires 101 in the bending area B.
  • the display panel may further include a second fan-shaped wiring area 20 located between the bending area B and the driving chip IC or the flexible circuit board FPC.
  • the second fan-shaped wiring area 20 includes a plurality of second leads 1014 (shown in the figure). Take one as an example) for electrically connecting the second ends 1012 of the plurality of first wires 101 in the bending area B to the driving chip IC or the flexible circuit board FPC.
  • the non-display side of the display panel may also include a structure such as a back film 104.
  • a structure such as a back film 104.
  • an adhesive 105 may be used to bond the back film 104 of the bent portion of the display panel.
  • the back film 104 can protect the display panel.
  • the plurality of first traces 101 in the bending area B include multiple sets of traces for transmitting different electrical signals.
  • the multiple first traces 101 include a first group of traces 101A and a second group of traces 101B, and the first group of traces 101A and a second group of traces 101B
  • the insulation from each other is suitable for transmitting different electrical signals respectively
  • the detection wiring 103 is arranged between the first group of wiring 101A and the second group of wiring 101B.
  • the detection wiring 103 separates the first group of wiring 101A and the second group of wiring 101B for transmitting different electrical signals, thereby avoiding the occurrence between the first group of wiring 101A and the second group of wiring 101B.
  • the signal crosstalk can also prevent the multiple first wires 101 from causing heat concentration due to excessive currents transmitted.
  • the first group of traces 101A are power lines, for example, the power line VDD for transmitting high level or the power line VSS for transmitting low level
  • the second group of traces 101B is The data line DATA used to transmit data signals for the display area AA
  • the first set of wires 101A and the second set of wires 101B are power lines that transmit different potentials, for example, the first set of wires 101A
  • the second group of traces 101B is the low-level power supply line VSS.
  • the first group of wires 101A and the second group of wires 101B may also be wires that transmit other signals, such as scan lines that transmit scan signals.
  • the multiple first traces 101 in the bending area B include a first group of traces 101A, a second group of traces 101B, and a third group of traces 101C.
  • the group of traces 101A is the power supply line VDD used to transmit high level
  • the second group of traces 101B is the data line DATA used to transmit data signals for the display area AA
  • the third group of traces 101C is used to transmit low level
  • the power line VSS and the detection line 103 are arranged between the first group of lines 101A and the second group of lines 101B to prevent signal crosstalk between the power line VDD and the data line DATA.
  • the detection wiring 103 may also be arranged between the second group of wiring 101B and the third group of wiring 101C to prevent signal crosstalk between the power line VDD and the power line VSS; or Detecting traces 103 are set between one set of traces 101A and the second set of traces 101B, and between the second set of traces 101B and the third set of traces 101C, to prevent signal crosstalk between different traces, and Prevent heat concentration due to excessive current being transmitted.
  • the different gray areas in FIG. 3A respectively represent the areas where multiple sets of traces are arranged in the bending area B, and each gray area includes multiple traces (two are shown as an example in the figure), for example , These traces are arranged side by side.
  • the first group of wires 101A is used to transmit a high-level power supply line VDD
  • multiple wires of the first group of wires 101A are arranged side by side in the above-mentioned area, and are electrically connected to each other at at least one end.
  • the light gray area above and/or below the gray area in FIG. 3A is electrically connected, for example, connected as a whole), so as to transmit electrical signals of the same potential.
  • the power line VSS can also be arranged similarly.
  • FIG. 3B shows a schematic diagram of the arrangement of the detection wiring 103 and the first group of wiring 101A and the second group of wiring 101B on both sides of the detection wiring.
  • the first set of traces 101A are power lines, and the multiple traces of the first set of traces 101A are connected at the upper end of Figure 3B as a whole (the light gray part in the figure), which is used to transmit the same potential Electrical signal.
  • the second group of wiring lines 101B are data lines DATA, and the plurality of data lines DATA are respectively connected to the driving circuit of the display area AA through the plurality of first leads 1013 in the first sector-shaped wiring area 10.
  • the first group of wires 101A, the second group of wires 101B, and the plurality of first wires 1013 in the first fan-shaped wire area 10 define a space, and the detection wires 103 can be arranged in the space.
  • the multiple sets of traces included in the multiple first traces 101 in the bending area B are symmetrically distributed, for example, along the length direction of the bending area B (for example, the horizontal direction in FIG. 1)
  • the center line of B is distributed axially symmetrically. At this time, the center line extends from the side of the bending area B close to the display area AA to the side of the bending area B away from the display area AA, and is connected to a plurality of first lines
  • the extension direction of 101 is the same.
  • the multiple first traces 101 in the bending area B include a second group of traces 101B located at the center, and two lines located on both sides of the second group of traces 101B.
  • the center line C of the bending area B is located in the middle of the second set of wiring lines 101B, and the multiple sets of wiring lines included in the plurality of first wiring lines 101 are distributed along the center line C in an axisymmetric manner.
  • the second set of traces 101B at the center position is the power line VDD for transmitting high level
  • the two sets of second set of traces 101B are the data lines DATA for transmitting data signals for the display area AA
  • the two sets of second The three sets of wirings 101C are power lines VSS for transmitting low levels
  • a detection wiring 103 is provided between the first set of wirings 101A and each second set of wirings 101B.
  • the detection wiring 103 may be provided between each second group of wiring 101B and the third group of wiring 101C adjacent to it; or, the first group of wiring 101A and each of the Detecting wires 103 are set between the two sets of wires 101B and between each second set of wires 101B and the third group of wires 101C adjacent thereto.
  • the plurality of first traces 101 in the bending area B may also include two groups of fourth traces located on the side of the third group of traces 101C that are away from the second group of traces 101B. Traces (not shown), etc., for example, the fourth group of traces are clock signal lines.
  • the embodiment of the present disclosure does not specifically limit the type and quantity of the transmission signal of each wire in the bending area B.
  • the detection wiring can also be arranged on one side of the clock signal line, for example, between the third group of wiring 101C and the fourth group of wiring, or arranged on the fourth group of wiring away from the third group of wiring 101C. On the side.
  • the data line DATA, clock line, or power line in the bent area B has a thinner line width, so that the detection line is designed to be compatible with the material, line width, and structure of these lines. Etc. are the same, and set on one side of these traces, which can effectively detect the status of these traces, such as whether they are broken or not.
  • the data lines DATA, clock lines, or power lines in the bending area B may also have different line widths.
  • the detection lines may be set as lines with finer line widths. It is designed to have the same material, line width, and structure as the wire with the thinner line width, so as to accurately detect the state of the wire with the thinner line width.
  • the first end 1031 and the second end 1032 of the detection trace 103 are both located on the non-display side of the display panel.
  • the first end 1031 and the second end 1032 of the detection trace 103 are both located on the side of the bending area B that is bent to the non-display side (that is, in the figure The lower side shown).
  • the detection wiring 103 can be electrically connected to an external detection circuit on the non-display side of the display panel for detection, thereby avoiding the effect of detection on the display side on the structure and circuit of the display panel.
  • the detection wiring 103 is arranged in multiple rows electrically connected first and last, and the first end 1031 and the second end 1032 of the detection wiring 103 are divided into the first row and the last row of the multiple rows.
  • FIG. 5 shows a schematic diagram of the arrangement of the detection wiring 103.
  • the detection trace 103 includes multiple rows electrically connected end to end (shown as ten rows in the figure as an example), and the first end 1031 and the second end 1032 of the detection trace 103 are divided from the multiple rows Lead out from the first row (the leftmost row in the figure) and the last row (the rightmost row in the figure).
  • the detection trace 103 when the detection trace 103 is detected through the first end 1031 and the second end 1032, if any one of the multiple rows is abnormal after bending, such as a break, the detection result of the detection trace 103 will be An abnormality occurs, for example, the detected resistance value of the detection wiring 103 becomes larger, and it can be inferred that the first wiring 101 arranged in parallel with the detection wiring 103 is likely to be abnormal; and the detection wiring 103 is arranged Multiple rows electrically connected first and last can improve the accuracy of detection and reduce the chance of detection.
  • the shape and size of the first trace 101 per unit length and the detection trace 103 per unit length are substantially the same.
  • the first trace 101 and the detection trace 103 both extend from one side of the bending area B (for example, the side close to the display area AA) in the same direction to the other side of the bending area B.
  • Side for example, the side close to the driver chip IC. Therefore, the structure and arrangement of the first wiring 101 and the detection wiring 103 are basically the same, thereby improving the accuracy of inferring the state of the first wiring 101 based on the detection result of the detection wiring 103.
  • the first wiring 101 and the detection wiring 103 both extend in a bent shape or have a hollow structure.
  • the first trace 101 and the detection trace 103 can be bent in a bend shape, bend in an arc, or have a hollow structure, thereby bending in the bending area B
  • the first wiring 101 and the detection wiring 103 can adapt to the shape change of the bending area B by changing the shape of the wiring (for example, elongated), so as to prevent the first wiring 101 and the detection wiring 103 from being in the bending area B Fracture occurs after bending.
  • the size and arrangement of the first wiring 101 and the detection wiring 103 may be designed according to the size of the bending area B, the number of the first wiring 101 and the number of rows of the detection wiring 103.
  • the length L of the bending area B can be 1.3mm-2.0mm
  • the width W of the bending area B can be designed according to the type of product.
  • the width W of the bending area B can be 15mm-20mm.
  • the width W of the bending area B can be 45mm-60mm; for larger products such as tablet computers, bending
  • the width W of the area B may be 130mm-160mm.
  • the bending radius of the bending area B (that is, the radius of the arc formed by the bending area B) may be 0.2 mm-0.5 mm.
  • the first pitch D1 may be 10-12 microns
  • the sum of the line width W1 of the detection trace 103 and the first pitch (that is, the arrangement pitch P1 of the detection trace 103) may be 60-80 ⁇ m; or, the first route
  • the first distance D1 between two adjacent rows of detection traces 103 can be 6-10 microns
  • the sum of the line width W1 and the first pitch D1 (ie P1) can be 25-60 microns; or,
  • the second distance D2 between two adjacent first traces 101 is the same as the first distance D1
  • the line width W2 of the first trace 101 is the same as the line width W1 of the detection trace 103.
  • the sum of the line width W2 and the second spacing D2 of the first trace 101 that is, the arrangement pitch P2 of the first trace 101
  • the sum of the line width W1 and the first spacing D1 of the detection trace 103 That is, P1
  • the thickness of the first trace 101 and the detection trace 103 are the same, and the thickness is 700 nm-850 nm, such as 750 nm or 800 nm.
  • the display panel has a multi-layer structure, including at least one insulating layer, a conductive pattern layer, etc., and the detection trace 101 is arranged in the same layer as at least part of the plurality of first traces 101, for example, the detection trace
  • the wires 101 and the multiple first wires 101 are arranged in the same layer.
  • the structure and arrangement of the multiple first wires 101 and the detection wires 103 are basically the same, so as to improve the accuracy of inferring the state of the first wires 101 based on the detection results of the detection wires 103.
  • “same layer arrangement” means that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display panel, that is, in the manufacturing process, the two functional layers
  • the layer or the structure layer can be formed of the same material layer, and the required pattern and structure can be formed through the same patterning process.
  • the display area AA includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device, and the pixel driving circuit includes a thin film transistor.
  • the gate electrode and the source and drain electrodes, and the detection traces are arranged on the same layer as the gate electrode or on the same layer as the source and drain electrodes.
  • FIG. 8 shows a schematic cross-sectional view of a display area AA of a display panel
  • FIG. 9 shows a schematic cross-sectional view of a bending area B of the display panel
  • the display area AA includes a plurality of sub-pixels arranged on the base substrate 110.
  • Each sub-pixel includes a light-emitting device 203 and a pixel drive circuit electrically connected to the light-emitting device 203.
  • the pixel drive circuit includes a thin film transistor 201 and a storage device. Capacitor 202 and other structures.
  • the thin film transistor 201 includes a semiconductor layer 121, a gate 122, a source and drain (including a source 123 and a drain 124), and the like.
  • the storage capacitor 202 includes a first capacitor plate 202A and a second capacitor plate 202B.
  • the first capacitor plate 202A and the gate 122 are arranged in the same layer.
  • the light emitting device 203 includes an anode 127, a light emitting layer 128, and a cathode 129.
  • the display panel further includes a planarization layer 112 for planarizing the thin film transistor 201 and the storage capacitor 202, the planarization layer 112 has a first via hole, and the anode 127 of the light emitting device 203 passes through the first via in the planarization layer 112.
  • the hole is electrically connected to the drain 124 of the thin film transistor 201.
  • the display area AA further includes an insulating layer 130 disposed between different conductive layers.
  • the insulating layer 130 includes, for example, a barrier layer 131, a buffer layer 132, a gate insulating layer 133, a first interlayer insulating layer 134, and a second interlayer insulating layer 135.
  • the barrier layer 131 and the buffer layer 132 are sequentially disposed on the base substrate 110 to block impurities in the base substrate 110 to prevent the impurities from entering the inside of the display panel.
  • the semiconductor layer 121 is disposed on the buffer layer 132, the gate insulating layer 133 is disposed on the semiconductor layer 121, the gate 122 and the first capacitor plate 202A are disposed on the gate insulating layer 133, and the first interlayer insulating layer 134 is disposed on the gate.
  • the second capacitor plate 202B is disposed on the first interlayer insulating layer 134
  • the second capacitor plate 202B is disposed on the first interlayer insulating layer 134
  • the second interlayer insulating layer 135 is disposed on the second capacitor plate 202B
  • the source and drain are disposed on the second interlayer insulating layer 135.
  • the semiconductor layer 121 includes a source region and a drain region
  • the gate insulating layer 133, the first interlayer insulating layer 134, and the second interlayer insulating layer 135 have second via holes exposing the source region and the drain region
  • the source 123 and the drain 124 are electrically connected to the source region and the drain region through a second via hole, respectively.
  • the display area AA of the display panel further includes a pixel defining layer 113, an encapsulation layer 190 (including a three-layer structure composed of a first inorganic material layer 191, an organic material layer 192, and a second inorganic material layer 193) and other structures.
  • a pixel defining layer 113 the display area AA of the display panel further includes a pixel defining layer 113, an encapsulation layer 190 (including a three-layer structure composed of a first inorganic material layer 191, an organic material layer 192, and a second inorganic material layer 193) and other structures.
  • an encapsulation layer 190 including a three-layer structure composed of a first inorganic material layer 191, an organic material layer 192, and a second inorganic material layer 193
  • the bending area B includes an insulating layer 130 disposed on the base substrate 110, and the insulating layer 130 in the bending area B is disposed in the same layer as at least part of the insulating layer 130 in the display area AA. That is, the insulating layer 130 in the bending region B may include one or more of the barrier layer 131, the buffer layer 132, the gate insulating layer 133, the first interlayer insulating layer 134, and the second interlayer insulating layer 135.
  • the insulating layer 130 has a groove 130A and a flexible insulating material 140 filled in the groove 130A, and the first wiring 101 and the detection wiring 103 are disposed on the insulating layer 130.
  • the flexible insulating material filled in the groove 130A is provided in the same layer as the flat layer 112 in the display area AA.
  • the flexible insulating material may be a flexible insulating material such as polyimide, resin (for example, acrylic resin, epoxy resin, etc.). Since part or all of the insulating layer 130 is formed of inorganic insulating materials, such as silicon nitride, silicon oxide, or silicon oxynitride and other inorganic insulating materials, inorganic insulating materials are usually brittle and are not easy to bend or break easily after bending.
  • removing the material of part of the insulating layer 130 in the bending area B and filling the flexible insulating material 140 can make the bending area B easy to bend, and the flexible insulating material 140 can buffer when the bending area B is bent. Function to reduce or prevent the occurrence of fracture due to bending stress.
  • the detection wiring 103 may be provided on the same layer as the source and drain of the thin film transistor 201 or on the same layer as the gate 122 of the thin film transistor 201.
  • the first wiring 101 when the first wiring 101 is a power line or a data line, the first wiring 101 may be arranged in the same layer as the source and drain of the thin film transistor.
  • the first wiring 101 and the gate 122 of the thin film transistor when the first wiring 101 is a scan line, the first wiring 101 and the gate 122 of the thin film transistor may be provided in the same layer.
  • the first wiring 101 and the detection wiring 103 are arranged on the same layer, that is, the first wiring 101 and the detection wiring 103 are arranged on the same layer as the source and drain of the thin film transistor 201 or on the same layer as the gate 122 of the thin film transistor 201. It is set so that the structure and arrangement of the detection wiring 103 and the first wiring 101 are basically the same.
  • the first wiring 101 and the detection wiring 103 may be made of metal materials such as copper, aluminum, molybdenum, titanium, or alloy materials, such as single-layer metal structures or multi-layer metal structures, such as Titanium/aluminum/titanium three-layer metal structure or molybdenum/aluminum/molybdenum three-layer metal structure, etc. These materials have good ductility and are not easy to break after bending.
  • the second trace 102, the gate 122, and the source and drain electrodes may also be made of metal materials or alloy materials such as copper, aluminum, molybdenum, titanium, etc., for example, including a single-layer metal structure or a multi-layer metal structure.
  • the base substrate 110 may be a flexible substrate to have bending performance.
  • the material of the flexible substrate may be, for example, polyimide, polyester (PET), polymethyl methacrylate (PMMA), and the like.
  • the semiconductor layer 121 may be an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
  • the polysilicon may be high temperature polysilicon or low temperature polysilicon, and the oxide semiconductor may be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO), or the like.
  • one or more of the insulating layers 130 can be made of inorganic insulating materials, such as inorganic insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, or organic insulating materials, such as organic insulating materials such as resin.
  • the pixel defining layer 113 can be made of organic insulating materials such as resin. The embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display panel having a display side and a non-display side. As shown in FIG. 10, the manufacturing method includes step S101 and step S102.
  • Step S101 forming a display area and a bending area located on one side of the display area, forming at least one first trace and a detection trace arranged in parallel with the at least one first trace in the bending area, and the detection trace includes the first trace.
  • One end and the second end are used to detect the connection to the external detection circuit.
  • the detection trace and the bending area are only formed on the side of the side far away from the display area AA; a second trace is formed in the display area, at least one first The first end of the trace is electrically connected to the second trace.
  • the at least one first trace includes a plurality of first traces
  • the plurality of first traces include a first group of traces and a second group of traces
  • the first group of traces and the second group of traces The wires are insulated from each other and are suitable for transmitting different electrical signals respectively, and the detection wires are formed between the first group of wires and the second group of wires.
  • the detection of the wiring can avoid signal crosstalk between the first group of wiring and the second group of wiring, and prevent multiple first wirings from causing heat concentration due to excessive current transmitted.
  • the specific settings of the first group of wiring and the second group of wiring can refer to the above-mentioned embodiment, and will not be repeated here.
  • the detection trace and at least part of the first trace are formed in the same layer, for example, the detection trace and the multiple first traces are formed in the same layer, that is, the detection trace and the multiple first traces are formed in the same layer.
  • the lines are formed using the same material layer and using the same patterning process.
  • forming the display area further includes forming a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device,
  • the pixel driving circuit includes a thin film transistor.
  • the thin film transistor includes a gate electrode and a source and drain electrode. The detection trace is formed on the same layer as the gate electrode or the same layer as the source and drain electrodes. Therefore, the manufacturing process of the display panel can be simplified.
  • each structural layer or functional layer on the display panel can be formed one by one using a patterning process.
  • One patterning process includes, for example, photoresist coating, exposure, development, and etching.
  • photoresist coating for example, photoresist coating, exposure, development, and etching.
  • etching for details, reference may be made to related technologies, which are not specifically limited in the embodiments of the present disclosure.
  • Step S102 Bending the bending area, so that the second end of the at least one first wire is bent to the non-display side through the bending area, and detecting that at least part of the wire is bent with the bending area.
  • the first wiring and the detection wiring have basically the same structure and arrangement.
  • the first wire and the detection wire have substantially the same bending shape after being bent along the bending area.
  • the manufacturing method of the display panel may further include step S103.
  • Step S103 After bending the bending area, connect the first end and the second end of the detection trace to an external detection circuit.
  • the external detection circuit detects the resistance of the detection trace and compares the resistance with the reference resistance to determine the detection The status of the wiring.
  • a resistance detection device may be used to detect the resistance of the detection trace. For example, when the difference between the resistance of the detected detection trace and the reference resistance is greater than ten percent of the reference resistance, it is determined that the detection trace is in a damaged state, and it can be inferred that the structure and arrangement of the detection trace are basically the same.
  • the first trace is also in a damaged state and cannot perform normal operation; for example, when the difference between the resistance and the reference resistance is less than or equal to 10% of the reference resistance, the detection trace is determined to be in a normal state, which can be inferred and detected.
  • the first wire with basically the same wire structure and arrangement is also in a normal state and can work normally.
  • the above-mentioned reference resistance is the average resistance measured when the detection trace is in a normal state.
  • the detected traces in the bending area can be used to determine the status of each trace in the bending area, and then the structural design and manufacturing process of the bending area can be evaluated, which provides a basis for optimizing the structure design and manufacturing process of the bending area.
  • the detection traces can also avoid the first group of traces and the second group of traces for transmitting different electrical signals. Signal crosstalk occurs between the two sets of wires, and prevents heat concentration due to excessive current being transmitted, so as to further improve the display effect of the display panel.
  • the subsequent manufacturing process may be performed on the display panel.
  • the packaging process, etc. the embodiments of the present disclosure do not limit the subsequent manufacturing process of the display panel.

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Abstract

一种显示面板及其制造方法。该显示面板具有显示侧和非显示侧，包括显示区域(AA)和位于显示区域(AA)一侧边的弯折区域(B)，弯折区域(B)包括至少一条第一走线(101)，弯折区域(B)能够可工作地从显示侧弯折到非显示侧，显示区域(AA)包括第二走线(102)，第一走线(101)的第一端(1011)电连接第二走线(102)，第一走线(101)的第二端(1012)通过弯折区域(B)弯折到非显示侧。弯折区域(B)还包括与第一走线(101)并列排布的检测走线(103)，检测走线(103)的至少部分随弯折区域(B)弯折，检测走线(103)包括第一端(1031)和第二端(1032)，用于连接外部检测电路，检测走线(103)和弯折区域(B)仅位于该侧边的远离显示区域(AA)的一侧。通过外部检测电路对检测走线(103)进行检测，可以判断弯折区域(B)中与检测走线(103)并列排布的第一走线(101)的状态。

Description

显示面板及其制造方法 技术领域
本公开的实施例涉及一种显示面板及其制造方法。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造工艺与薄膜晶体管(TFT)工艺兼容等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。目前，OLED显示面板正往大屏化、全屏化方向发展，以提升用户体验。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板具有显示侧和非显示侧，包括显示区域和位于所述显示区域一侧边的弯折区域，所述弯折区域包括至少一条第一走线，所述弯折区域能可工作地从所述显示侧弯折到所述非显示侧，所述显示区域包括第二走线，所述至少一条第一走线的第一端电连接所述第二走线，所述至少一条第一走线的第二端通过所述弯折区域弯折到所述非显示侧；其中，所述弯折区域还包括与所述至少一条第一走线并列排布的检测走线，所述检测走线的至少部分随所述弯折区域弯折，所述检测走线包括第一端和第二端，用于连接外部检测电路；所述检测走线和所述弯折区域仅位于所述侧边的远离所述显示区域的一侧。
例如，本公开至少一实施例提供的显示面板中，所述至少一条第一走线包括多条第一走线，所述多条第一走线包括第一组走线和第二组走线，所述第一组走线和所述第二组走线彼此绝缘适用于分别传输不同的电信号，所述检测走线设置在所述第一组走线和所述第二组走线之间。
例如，本公开至少一实施例提供的显示面板中，所述第一组走线为电源线，所述第二组走线为数据线；或者所述第一组走线和所述第二组走线为传输不同电位的电源线。
例如，本公开至少一实施例提供的显示面板中，单位长度的所述第一 走线与单位长度的所述检测走线的形状和尺寸大致相同。
例如，本公开至少一实施例提供的显示面板中，所述第一走线与所述检测走线均呈弯折状延伸或者具有镂空结构。
例如，本公开至少一实施例提供的显示面板中，所述检测走线排布为首尾依次电连接的多行，所述检测走线的第一端和第二端分为位于所述多行的首行和尾行。
例如，本公开至少一实施例提供的显示面板中，在所述弯折区域弯折之后，所述检测走线的第一端和第二端均位于所述非显示侧。
例如，本公开至少一实施例提供的显示面板中，在所述弯折区域中，所述第一走线的数量和所述检测走线的行数之和小于等于500，相邻的两行检测走线的第一间距为10-12微米，所述检测走线的线宽与所述第一间距之和为60-80微米；或者所述第一走线的数量和所述检测走线的行数之和大于500且小于等于2000，相邻的两行检测走线的第一间距为6-10微米，所述检测走线的线宽与所述第一间距之和为25-60微米；或者所述第一走线的数量和检测走线的行数之和大于2000，相邻的两行检测走线的第一间距为5-6微米，所述检测走线的线宽与所述第一间距之和为15-25微米。
例如，本公开至少一实施例提供的显示面板中，相邻的两条所述第一走线之间的第二间距与所述第一间距相同，所述第一走线的线宽与所述第二间距之和与所述检测走线的线宽与所述第一间距之和相同。
例如，本公开至少一实施例提供的显示面板中，在垂直于所述显示面板的板面方向上，所述第一走线和所述检测走线的厚度相同，所述厚度为700nm-850nm。
例如，本公开至少一实施例提供的显示面板中，所述检测走线与所述多条第一走线中的至少部分同层设置。
例如，本公开至少一实施例提供的显示面板中，所述显示区域包括阵列排布的多个子像素，所述多个子像素中的每个包括发光器件以及与所述发光器件电连接的像素驱动电路，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极和源漏极，所述检测走线与所述栅极同层设置或者与所述源漏极同层设置。
本公开至少一实施例提供还一种显示面板的制造方法，所述显示面板具有显示侧和非显示侧，所述方法包括：形成显示区域和位于所述显示区域 一侧边的弯折区域，其中，在所述弯折区域形成至少一条第一走线以及与所述至少一条第一走线并列排布的检测走线，所述检测走线包括第一端和第二端，用于检测连接外部检测电路，所述检测走线和所述弯折区域仅形成于所述侧边的远离所述显示区域的一侧；在所述显示区域形成第二走线，所述至少一条第一走线的第一端电连接所述第二走线；弯折所述弯折区域，以使所述至少一条第一走线的第二端通过所述弯折区域弯折到所述非显示侧，并且所述检测走线的至少部分随所述弯折区域弯折。
例如，本公开至少一实施例提供的显示面板的制造方法还包括：在弯折所述弯折区域后，将所述检测走线的第一端和第二端连接于外部检测电路，所述外部检测电路检测所述检测走线的电阻，并将所述电阻与基准电阻比较，以确定所述检测走线的状态。
例如，本公开至少一实施例提供的显示面板的制造方法中，当所述电阻与所述基准电阻的差大于所述基准电阻的百分之十时，确定所述检测走线处于损坏状态；当所述电阻与所述基准电阻的差小于等于所述基准电阻的百分之十时，确定所述检测走线处于正常状态。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述至少一条第一走线包括多条第一走线，所述多条第一走线包括第一组走线和第二组走线，所述第一组走线和所述第二组走线彼此绝缘适用于分别传输不同的电信号，所述检测走线形成在所述第一组走线和所述第二组走线之间。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述检测走线与所述多条第一走线中的至少部分同层形成。
例如，本公开至少一实施例提供的显示面板的制造方法中，形成所述显示区域还包括形成阵列排布的多个子像素，所述多个子像素中的每个包括发光器件以及与所述发光器件电连接的像素驱动电路，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极和源漏极，所述检测走线与所述栅极同层形成或者与所述源漏极同层形成。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示面板的部分平面示意图；
图2为本公开至少一实施例提供的显示面板的截面示意图；
图3A为本公开至少一实施例提供的显示面板的弯折区域的平面示意图；
图3B为本公开至少一实施例提供的显示面板的弯折区域走线排布的平面示意图；
图4为本公开至少一实施例提供的另一显示面板的弯折区域的平面示意图；
图5为本公开至少一实施例提供的显示面板的弯折区域中检测走线的平面示意图；
图6A-图6D为本公开至少一实施例提供的显示面板的弯折区域中单位长度的检测走线的示意图；
图7为本公开至少一实施例提供的显示面板的弯折区域中第一走线和检测走线的示意图；
图8为本公开至少一实施例提供的显示面板的显示区域的截面示意图；
图9为本公开至少一实施例提供的显示面板的弯折区域的截面示意图；
图10为本公开至少一实施例提供的显示面板的制造方法的流程图；
图11为本公开至少一实施例提供的另一显示面板的制造方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板往大屏化、全屏化方向发展的过程中，如何进一步提高显示面板的屏占比(即显示区域在显示面板显示侧的比例)是本领域技术人员主要研究的问题。在一些实施方式中，可以通过在显示面板的显示区域的一侧边设置可弯折区，通过可弯折区将显示面板的非显示区域弯折到显示面板的非显示侧，以提高显示区域在显示面板显示侧的比例。通常来说，可弯折区域包括多条电连接显示区域与显示面板驱动芯片的走线，这些走线在可弯折区域弯折的过程中存在断裂的风险，若走线断裂，则显示面板无法进行正常工作。
本公开至少一实施例提供一种显示面板及其制造方法，该显示面板具有显示侧和非显示侧，包括显示区域和位于显示区域一侧边的弯折区域，弯折区域包括至少一条第一走线，弯折区域能可工作地从显示侧弯折到非显示侧，显示区域包括第二走线，至少一条第一走线的第一端电连接第二走线，至少一条第一走线的第二端通过弯折区域弯折到非显示侧。弯折区域还包括与至少一条第一走线并列排布的检测走线，检测走线的至少部分随弯折区域弯折，检测走线包括第一端和第二端，用于连接外部检测电路；检测走线和弯折区域仅位于上述侧边的远离显示区域的一侧。在弯折区域被弯折后，通过对该显示面板的弯折区域中的检测走线进行检测，可以得到检测走线的状态，判断该检测走线在弯折后是否保持正常状态，从而可推测出弯折区域中用于为显示区域传输显示信号的走线的状态，进而为弯折区域的结构设计以及制造工艺提供帮助。
下面，通过几个具体的实施例来详细且非限制性地介绍本公开实施例提供的显示面板及其制造方法。
图1示出了本公开至少一实施例提供的显示面板的部分平面示意图；图2示出了该显示面板在弯折后的截面示意图。
如图1和图2所示，该显示面板具有显示侧(即图2中示出的显示面板的上侧)和非显示侧(即图2中示出的显示面板的下侧)，包括显示区域AA和位于显示区域AA一侧边(例如图2中的下侧边)的弯折区域B，弯折区域B包括至少一条第一走线101(图1中示出一条作为示例)，如图2所示，弯折区域B能可工作地从显示侧弯折到非显示侧，即在弯折区域B弯折后，弯折区域B中的结构能适应性地产生弯曲变形，并保持可工作状态，例如实现所需要的电连接或信号传输。显示区域AA包括一条或多条第二走线102(图1中示出一条第二走线102作为示例)，至少一条第一走线101的第一端1011电连接与之对应的第二走线102，至少一条第一走线101的第二端1012通过弯折区域B折到非显示侧。弯折区域B包括与至少一条第一走线101并列排布的检测走线103，例如至少一条第一走线101和检测走线103沿弯折区域B的弯折轴(图中的弯折区域B的长度方向，即水平方向)并列排布，检测走线103的至少部分随弯折区域B弯折，检测走线103包括第一端1031和第二端1032，用于连接外部检测电路。例如，检测走线103和弯折区域B仅位于上述侧边的远离显示区域AA的一侧。
需要说明的是，本公开的实施例中，检测走线103和弯折区域B仅位于显示区域AA的一侧，例如，检测走线103不会围绕显示区域AA。
例如，在一些实施例中，显示区域AA包括多条第二走线102，弯折区域B包括多条第一走线101，多条第一走线101的第一端分别与多条第二走线102电连接，多条第一走线101的第二端通过弯折区域B折到非显示侧，从而可以在非显示侧向通过多条第一走线101向显示区域AA的多条第二走线102提供电信号。
在本公开的实施例中，通过对显示面板的弯折区域B中的检测走线103进行检测，可以得到检测走线103的状态，进而判断该检测走线103在弯折后是否正常，从而可推测出弯折区域B中与检测走线103并列排布的且用于为显示区域AA传输电信号的第一走线101的状态。例如，在一些示例中，可以对检测走线103进行电阻检测，当检测到的检测走线103的电阻值大于一个基准电阻时，可判断该检测走线103出现异常，例如出现显著裂纹或断裂，进而推断出弯折区域B中与检测走线103并列排布的且用于为显示区域AA传输电信号的第一走线101很可能也出现异常，此时需要优化弯折区域B的结构设计以及制作工艺；例如，当检测到的检测走线103的电阻值小于 基准电阻时，可判断该检测走线103正常，进而推断出弯折区域B中与检测走线103并列排布的且用于为显示区域AA传输电信号的第一走线101也可以正常工作，此时弯折区域B的结构设计合理以及制作合格。例如，上述基准电阻为检测走线103处于正常状态时所测得的平均电阻。
例如，在一些实施例中，如图1所示，显示面板还包括用于驱动显示区域AA进行显示操作的驱动芯片IC(Integrated Circuit)，第一走线101的第二端1012电连接该驱动芯片IC，以将显示区域AA中的第二走线102与驱动芯片IC电连接，进而通过第一走线101为显示区域AA提供电信号，例如显示信号、控制信号、时序信号等。例如，在弯折区域B弯折后，驱动芯片IC即被弯折到显示面板的非显示侧。
例如，在一些实施例中，显示面板还可以包括柔性电路板FPC(Flexible Printed Circuit)，第一走线101的第二端1012也可以例如通过邦定的方式电连接该柔性电路板FPC。例如，在一些示例中，柔性电路板FPC还可以包括驱动电路，第一走线101的第二端1012电连接到该驱动电路，该驱动电路通过第一走线101向显示区域AA传输电信号，例如触控信号或者时钟信号等。例如，在弯折区域B弯折后，柔性电路板FPC即被弯折到显示面板的非显示侧，与显示区与层叠，由此有助于实现窄边框设计。
由此，驱动芯片IC或者柔性电路板FPC设置在显示面板的非显示侧，多条第一走线101通过弯折将位于显示区域AA中的多条第二走线102电连接到位于显示面板非显示侧的驱动芯片IC或者柔性电路板FPC。
例如，在一些实施例中，如图1所示，显示面板还可以包括位于显示区域AA和弯折区域B之间的第一扇形走线区10，第一扇形走线区10包括多条第一引线1013(图中示出一条作为示例)，用于将显示区域AA中的多条第二走线102电连接到弯折区域B中的多条第一走线101的第一端1011。例如，显示面板还可以包括位于弯折区域B和驱动芯片IC或者柔性电路板FPC之间的第二扇形走线区20，第二扇形走线区20包括多条第二引线1014(图中示出一条作为示例)，用于弯折区域B中多条第一走线101的第二端1012电连接到驱动芯片IC或者柔性电路板FPC。
例如，如图2所示，显示面板的非显示侧还可以包括背膜104等结构，在弯折区域B弯折后，可以利用粘结剂105将显示面板弯折部分的背膜104粘结，以固定弯折区域B的弯折状态。背膜104可以起到保护显示面板的作 用。
例如，在一些实施例中，弯折区域B中的多条第一走线101包括多组用于传输不同的电信号的走线。例如，如图3A所示，在弯折区域B中，多条第一走线101包括第一组走线101A和第二组走线101B，第一组走线101A和第二组走线101B彼此绝缘适用于分别传输不同的电信号，检测走线103设置在第一组走线101A和第二组走线101B之间。由此，检测走线103将用于传输不同电信号的第一组走线101A和第二组走线101B间隔开，进而可以避免第一组走线101A和第二组走线101B之间发生信号串扰，还能防止多条第一走线101由于传输的电流过大而造成热量集中。
例如，在一些实施例中，第一组走线101A为电源线，例如为用于传输高电平的电源线VDD或者为用于传输低电平的电源线VSS，第二组走线101B为用于为显示区域AA传输数据信号的数据线DATA；或者，在一些实施例中，第一组走线101A和第二组走线101B为传输不同电位的电源线，例如第一组走线101A为用于传输高电平的电源线VDD，第二组走线101B为用于传输低电平的电源线VSS。在其他实施例中，第一组走线101A和第二组走线101B也可以为传输其他信号的走线，例如为传输扫描信号的扫描线等。
例如，在一个示例中，如图3A所示，弯折区域B中的多条第一走线101包括第一组走线101A、第二组走线101B以及第三组走线101C，第一组走线101A为用于传输高电平的电源线VDD，第二组走线101B为用于为显示区域AA传输数据信号的数据线DATA，第三组走线101C为用于传输低电平的电源线VSS，检测走线103设置在第一组走线101A和第二组走线101B之间，以防止电源线VDD和数据线DATA之间发生信号串扰。例如，在另一个示例中，检测走线103也可以设置在第二组走线101B和第三组走线101C之间，以防止电源线VDD和电源线VSS之间发生信号串扰；或者，第一组走线101A和第二组走线101B之间以及第二组走线101B和第三组走线101C之间均设置检测走线103，以防止不同的走线之间发生信号串扰，并防止由于传输的电流过大而造成热量集中。
需要说明的是，图3A中的不同灰色区域分别表示多组走线在弯折区B中排布的区域，每个灰色区域包括多条走线(图中示出两条作为示例)，例如，这些走线并列排布。例如，当第一组走线101A为用于传输高电平的电 源线VDD时，第一组走线101A的多条走线在上述区域中并列排布，并在至少一个端部相互电连接(例如在图3A中灰色区域上方和/或下方的浅灰色区域进行电连接，例如连接成一个整体)，从而用于传输同一电位的电信号。同理，对于电源线VSS，也可以进行类似的排布。
例如，在一个示例中，图3B示出了检测走线103和检测走线两侧的第一组走线101A和第二组走线101B的排布示意图。如图3B所示，第一组走线101A为电源线，第一组走线101A的多条走线在图3B中的上端连接为一体(图中的浅灰色部分)，用于传输同一电位的电信号。第二组走线101B为数据线DATA，多条数据线DATA分别通过第一扇形走线区10中的多条第一引线1013连接到显示区域AA的驱动电路。例如，第一组走线101A、第二组走线101B和第一扇形走线区10中的多条第一引线1013限定了一个空间，检测走线103可排布在该空间内。
例如，在一些实施例中，弯折区域B中的多条第一走线101所包括的多组走线呈对称分布，例如沿弯折区域B的长度方向(例如图1中的水平方向)的中心线呈轴对称分布，此时，该中心线从弯折区域B的靠近显示区域AA的一侧延伸至弯折区域B的远离显示区域AA的一侧，并且与多条第一走线101的延伸方向相同。
例如，在一个示例中，如图4所示，弯折区域B中的多条第一走线101包括位于中心位置的第二组走线101B、分别位于第二组走线101B两侧的两组第一组走线101A以及分别位于两组第一组走线101A的远离第二组走线101B一侧的两组第三组走线101C。该弯折区域B的中心线C位于第二组走线101B的中部，多条第一走线101所包括的多组走线沿该中心线C呈轴对称分布。例如，位于中心位置的第二组走线101B为用于传输高电平的电源线VDD，两组第二组走线101B为用于为显示区域AA传输数据信号的数据线DATA，两组第三组走线101C为用于传输低电平的电源线VSS，第一组走线101A和每条第二组走线101B之间均设置检测走线103。例如，在另一些示例中，也可以每条第二组走线101B和与其相邻的第三组走线101C之间均设置检测走线103；或者，第一组走线101A和每条第二组走线101B之间以及每条第二组走线101B和与其相邻的第三组走线101C之间均设置检测走线103。
例如，在一些实施例中，弯折区域B中的多条第一走线101还可以包括 两组分别位于两组第三组走线101C的远离第二组走线101B一侧的第四组走线(未示出)等，例如第四组走线为时钟信号线。本公开的实施例对弯折区域B中各走线的传输信号的种类以及数量不作具体限定。例如，检测走线也可以设置在时钟信号线的一侧，例如设置在第三组走线101C和第四组走线之间，或者设置在第四组走线的远离第三组走线101C的一侧。
例如，在一些实施例中，弯折区域B中的数据线DATA、时钟走线或者电源线等具有较细的线宽，从而将检测走线设计为与这些走线的材料、线宽和结构等均相同，且设置在这些走线的一侧，可以有效检测这些走线的状态，例如是否发生断裂等。例如，在一些实施例中，弯折区域B中的数据线DATA、时钟走线或者电源线等也可以具有不同的线宽，此时，检测走线可以设置为具有较细线宽的走线旁，并设计为与该具有较细线宽的走线的材料、线宽和结构等均相同，以准确检测该具有较细线宽的走线的状态。
例如，在一些实施例中，在弯折区域B弯折之后，检测走线103的第一端1031和第二端1032均位于显示面板的非显示侧。例如，在图3A和图4示出的实施例中，检测走线103的第一端1031和第二端1032均位于弯折区域B的被弯折到非显示侧的一侧(即图中示出的下侧)。由此，可以在显示面板的非显示侧将检测走线103电连接到外部检测电路，以进行检测，从而避免在显示侧进行检测而对显示面板的结构以及电路产生影响。
例如，在一些实施例中，检测走线103排布为首尾依次电连接的多行，检测走线103的第一端1031和第二端1032分为位于该多行的首行和尾行。例如，图5示出了一种检测走线103的排布示意图。如图5所示，检测走线103包括首尾依次电连接的多行(图中示出为十行作为示例)，检测走线103的第一端1031和第二端1032分为从该多行的首行(图中最左侧的一行)和尾行(图中最右侧的一行)中引出。此时，通过第一端1031和第二端1032对检测走线103进行检测时，若多行中的任意一处在弯折后出现异常，例如断裂，则检测走线103的检测结果即会出现异常，例如检测出的检测走线103的电阻值变大，由此可推断出与检测走线103并列排布的第一走线101很可能也出现异常；并且，检测走线103排布为首尾依次电连接的多行可以提高检测的准确性，降低检测偶然性。
例如，在一些实施例中，单位长度的第一走线101与单位长度的检测走线103的形状和尺寸大致相同。例如，在一些实施例中，第一走线101和检 测走线103均从弯折区域B的一侧(例如靠近显示区域AA的一侧)沿相同的方向延伸到弯折区域B的另一侧(例如靠近驱动芯片IC的一侧)。由此，第一走线101和检测走线103的结构和设置基本相同，从而提高根据检测走线103的检测结果推测第一走线101状态的准确性。
例如，在一些实施例中，第一走线101与检测走线103均呈弯折状延伸或者具有镂空结构。例如，如图6A-图6D所示，第一走线101与检测走线103可以呈折线形弯折状延、呈弧线弯折状延或者具有镂空结构，从而在弯折区域B弯折后，第一走线101与检测走线103可以通过走线形状的改变(例如拉长)来适应弯折区域B的形状改变，避免第一走线101与检测走线103在弯折区域B弯折后出现断裂现象。
例如，在一些实施例中，第一走线101和检测走线103的尺寸和排布可以根据弯折区域B的尺寸以及第一走线101的数量和检测走线103的行数来设计。例如，在一些示例中，如图4所示，弯折区域B的长度L可以为1.3mm-2.0mm，弯折区域B的宽度W可以根据产品的种类进行设计，例如，对于手表等尺寸较小的产品，弯折区域B的宽度W可以为15mm-20mm，对于手机等尺寸中等的产品，弯折区域B的宽度W可以为45mm-60mm；对于平板电脑等尺寸较大的产品，弯折区域B的宽度W可以为130mm-160mm。例如，弯折区域B的弯曲半径(即弯折区域B弯折后形成的圆弧的半径)为可以为0.2mm-0.5mm。此时，在弯折区域B中，如图7所示，第一走线101的数量和检测走线103的行数之和小于等于500的情况下，相邻的两行检测走线103的第一间距D1可以为10-12微米，检测走线103的线宽W1与第一间距之和(即检测走线103的排布节距P1)可以为60-80微米；或者，第一走线101的数量和检测走线103的行数之和大于500且小于等于2000的情况下，相邻的两行检测走线103的第一间距D1可以为6-10微米，检测走线103的线宽W1与第一间距D1之和(即P1)可以为25-60微米；或者，在第一走线101的数量和检测走线103的行数之和大于2000的情况下，相邻的两行检测走线103的第一间距D1可以为5-6微米，检测走线103的线宽W1与第一间距D1之和(即P1)可以为15-25微米。
例如，在一些实施例中，相邻的两条第一走线101之间的第二间距D2与第一间距D1相同，第一走线101的线宽W2与检测走线103的线宽W1相同，从而第一走线101的线宽W2与第二间距D2之和(即第一走线101 的排布节距P2)与检测走线103的线宽W1与第一间距D1之和(即P1)相同。
例如，在一些实施例中，在垂直于显示面板的板面方向上，第一走线101和检测走线103的厚度相同，该厚度为700nm-850nm，例如750nm或者800nm等。
例如，在一些实施例中，显示面板为多层结构，包括至少一个绝缘层、导电图案层等，检测走线101与多条第一走线101中的至少部分同层设置，例如，检测走线101与多条第一走线101均同层设置。
由此，多条第一走线101与检测走线103的结构和排布基本相同，以提高根据检测走线103的检测结果推测第一走线101状态的准确性。
需要注意的是，在本公开的实施例中，“同层设置”为两个功能层或结构层在显示面板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，在一些实施例中，显示区域AA包括阵列排布的多个子像素，多个子像素中的每个包括发光器件以及与发光器件电连接的像素驱动电路，像素驱动电路包括薄膜晶体管，薄膜晶体管包括栅极和源漏极，检测走线与栅极同层设置或者与源漏极同层设置。
例如，图8示出了一种显示面板的显示区域AA的截面示意图，图9示出了显示面板的弯折区域B的截面示意图。如图8所示，显示区域AA包括设置于衬底基板110上的多个子像素，每个子像素包括发光器件203以及与发光器件203电连接的像素驱动电路，像素驱动电路包括薄膜晶体管201和存储电容202等结构。例如，薄膜晶体管201包括半导体层121、栅极122以及源漏极(包括源极123和漏极124)等。存储电容202包括第一电容极板202A和第二电容极板202B。例如，第一电容极板202A与栅极122同层设置。发光器件203包括阳极127、发光层128以及阴极129。例如，显示面板还包括用于平坦化薄膜晶体管201和存储电容202的平坦化层112，平坦化层112中具有第一过孔，发光器件203的阳极127通过平坦化层112中的第一过孔与薄膜晶体管201的漏极124电连接。
例如，显示区域AA还包括设置在不同导电层之间的绝缘层130。如图8所示，绝缘层130例如包括阻挡层131、缓冲层132、栅绝缘层133、第一 层间绝缘层134以及第二层间绝缘层135。阻挡层131和缓冲层132依次设置在衬底基板110上，用于阻挡衬底基板110中的杂质，以避免该杂质进入到显示面板内部。半导体层121设置在缓冲层132上，栅绝缘层133设置在半导体层121上，栅极122以及第一电容极板202A设置在栅绝缘层133上，第一层间绝缘层134设置在栅极122以及第一电容极板202A上，第二电容极板202B设置在第一层间绝缘层134上，第二电容极板202B设置在第一层间绝缘层134上，第二层间绝缘层135设置在第二电容极板202B上，源漏极设置在第二层间绝缘层135上。例如，半导体层121包括源极区和漏极区，栅绝缘层133、第一层间绝缘层134和第二层间绝缘层135中具有暴露源极区和漏极区的第二过孔，源极123和漏极124分别通过第二过孔与源极区和漏极区电连接。
例如，显示面板的显示区域AA还包括像素界定层113、封装层190(包括第一无机材料层191、有机材料层192以及第二无机材料层193组成的三层结构)等其他结构，本公开的实施例对此不做限定。
例如，如图3A所示，弯折区域B包括设置在衬底基板110上的绝缘层130，弯折区域B中的绝缘层130与显示区域AA中的绝缘层130的至少部分同层设置，即弯折区域B中的绝缘层130可以包括阻挡层131、缓冲层132、栅绝缘层133、第一层间绝缘层134以及第二层间绝缘层135中的一种或多种。例如，绝缘层130中均具有凹槽130A以及填充在凹槽130A中的柔性绝缘材料140，第一走线101和检测走线103设置在绝缘层130上。
例如，填充在凹槽130A中的柔性绝缘材料与显示区域AA中的平坦层112同层设置。例如，该柔性绝缘材料可以为聚酰亚胺、树脂(例如丙烯酸树脂、环氧树脂等)等柔性的绝缘材料。由于绝缘层130中的部分或者全部采用无机绝缘材料形成，例如采用氮化硅、氧化硅或者氮氧化硅等无机绝缘材料形成，由于无机绝缘材料通常具有脆性，不易弯折或者弯折后容易断裂，因此将弯折区域B中的部分绝缘层130的材料去除并填充柔性绝缘材料140可以使弯折区域B易于弯折，并且该柔性绝缘材料140可以在弯折区域B弯折时起到缓冲作用，减少或防止由于弯曲应力导致的断裂现象发生。
例如，在一些示例中，检测走线103可以与薄膜晶体管201的源漏极同层设置或者与薄膜晶体管201的栅极122同层设置。例如，在图3A和图4示出的实施例中，当第一走线101为电源线或者数据线时，第一走线101可 与薄膜晶体管的源漏极同层设置。在其他实施例中，当第一走线101为扫描线时，第一走线101可与薄膜晶体管的栅极122同层设置。
例如，第一走线101与检测走线103同层设置，即第一走线101与检测走线103均与薄膜晶体管201的源漏极同层设置或者与薄膜晶体管201的栅极122同层设置，以使检测走线103与第一走线101的结构和排布基本相同。
例如，在本公开的实施例中，第一走线101和检测走线103可以采用铜、铝、钼、钛等金属材料或者合金材料，例如包括单层金属结构或者多层金属结构，例如包括钛/铝/钛三层金属结构或者钼/铝/钼三层金属结构等。这些材料具有良好的延展性，在弯曲后不易断裂。例如，第二走线102、栅极122以及源漏极也可以采用铜、铝、钼、钛等金属材料或者合金材料，例如包括单层金属结构或者多层金属结构。衬底基板110可以为柔性基板，以使其具有弯折性能，柔性基板的材料例如可以为聚酰亚胺、聚酯(PET)、聚甲基丙烯酸甲酯(PMMA)等。例如，半导体层121可以为非晶硅层、多晶硅层或金属氧化物半导体层。例如，多晶硅可以为高温多晶硅或低温多晶硅，氧化物半导体可以为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化镓锌(GZO)等。例如，绝缘层130中的一种或多种可以采用无机绝缘材料，例如氮化硅、氧化硅或者氮氧化硅等无机绝缘材料，或者采用有机绝缘材料，例如树脂等有机绝缘材料。像素界定层113可以采用树脂等有机绝缘材料。本公开的实施例对各功能层的材料不做具体限定。
本公开至少一实施例提供还一种显示面板的制造方法，该显示面板具有显示侧和非显示侧，如图10所示，该制造方法包括步骤S101和步骤S102。
步骤S101：形成显示区域和位于显示区域一侧边的弯折区域，在弯折区域形成至少一条第一走线以及与至少一条第一走线并列排布的检测走线，检测走线包括第一端和第二端，用于检测连接外部检测电路，检测走线和弯折区域仅形成于上述侧边的远离显示区域AA的一侧；在显示区域形成第二走线，至少一条第一走线的第一端电连接第二走线。
例如，在一些实施例中，至少一条第一走线包括多条第一走线，多条第一走线包括第一组走线和第二组走线，第一组走线和第二组走线彼此绝缘适用于分别传输不同的电信号，检测走线形成在第一组走线和第二组走线之间。由此检测走线可以避免第一组走线和第二组走线之间发生信号串扰，并防止多条第一走线由于传输的电流过大而造成热量集中。第一组走线和第二 组走线的具体设置可以参见上述实施例，在此不再赘述。
例如，在一些实施例中，检测走线与第一走线中的至少部分同层形成，例如检测走线与多条第一走线均同层形成，即检测走线与多条第一走线采用相同的材料层并采用相同的构图工艺形成。
例如，在一些实施例中，参见图8和图9，形成显示区域还包括形成阵列排布的多个子像素，多个子像素中的每个包括发光器件以及与发光器件电连接的像素驱动电路，像素驱动电路包括薄膜晶体管，薄膜晶体管包括栅极和源漏极，检测走线与栅极同层形成或者与源漏极同层形成。由此可以简化显示面板的制造工艺。
例如，显示面板上的各结构层或功能层可以采用构图工艺一一形成。一次构图工艺例如包括光刻胶的涂覆、曝光、显影以及刻蚀等工序，具体可以参见相关技术，本公开的实施例对此不作具体限定。
步骤S102：弯折弯折区域，以使至少一条第一走线的第二端通过弯折区域弯折到非显示侧，并且检测走线的至少部分随弯折区域弯折。
例如，第一走线和检测走线具有基本相同的结构和排布，具体可以参见上述实施例。由此，第一走线和检测走线随弯折区域弯折后具有基本相同的弯折形态。
例如，在一些实施例中，如图11所示，显示面板的制造方法还可以包括步骤S103。
步骤S103：在弯折弯折区域后，将检测走线的第一端和第二端连接于外部检测电路，外部检测电路检测检测走线的电阻，并将电阻与基准电阻比较，以确定检测走线的状态。
例如，在一些实施例中，可以采用电阻检测装置检测检测走线的电阻。例如，当检测到的检测走线的电阻与基准电阻的差大于基准电阻的百分之十时，确定检测走线处于损坏状态，由此可以推断与检测走线的结构和排布基本相同的第一走线也处于损坏状态，而无法进行正常工作；例如，当电阻与基准电阻的差小于等于基准电阻的百分之十时，确定检测走线处于正常状态，由此可以推断与检测走线的结构和排布基本相同的第一走线也处于正常状态，可进行正常工作。例如，上述基准电阻为检测走线处于正常状态时所测得的平均电阻。
由此，可以利用弯折区域中的检测走线判断弯折区域中各走线的状态， 进而评估弯折区域的结构设计以及制造工艺，为优化弯折区域的结构设计以及制造工艺提供依据。并且，当检测走线形成在用于传输不同电信号的第一组走线和第二组走线之间时，检测走线还可以避免用于传输不同电信号的第一组走线和第二组走线之间发生信号串扰，并防止由于传输的电流过大而造成热量集中，以进一步提高显示面板的显示效果。
例如，在一些实施例中，当检测到检测走线处于正常状态，并推断与检测走线的结构和排布基本相同的第一走线也处于正常状态后，可以对显示面板进行后续制备工艺，例如封装工艺等，本公开的实施例对显示面板的后续制备工艺不作限定。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (18)

  1. 一种显示面板，具有显示侧和非显示侧，包括显示区域和位于所述显示区域一侧边的弯折区域，
    所述弯折区域包括至少一条第一走线，所述弯折区域能可工作地从所述显示侧弯折到所述非显示侧，
    所述显示区域包括第二走线，所述至少一条第一走线的第一端电连接所述第二走线，所述至少一条第一走线的第二端通过所述弯折区域弯折到所述非显示侧；
    其中，所述弯折区域还包括与所述至少一条第一走线并列排布的检测走线，所述检测走线的至少部分随所述弯折区域弯折，所述检测走线包括第一端和第二端，用于连接外部检测电路；所述检测走线和所述弯折区域仅位于所述侧边的远离所述显示区域的一侧。
  2. 根据权利要求1所述的显示面板，其中，所述至少一条第一走线包括多条第一走线，所述多条第一走线包括第一组走线和第二组走线，所述第一组走线和所述第二组走线彼此绝缘适用于分别传输不同的电信号，
    所述检测走线设置在所述第一组走线和所述第二组走线之间。
  3. 根据权利要求2所述的显示面板，其中，所述第一组走线为电源线，所述第二组走线为数据线；或者
    所述第一组走线和所述第二组走线为传输不同电位的电源线。
  4. 根据权利要求1-3任一所述的显示面板，其中，单位长度的所述第一走线与单位长度的所述检测走线的形状和尺寸大致相同。
  5. 根据权利要求4所述的显示面板，其中，所述第一走线与所述检测走线均呈弯折状延伸或者具有镂空结构。
  6. 根据权利要求1-5任一所述的显示面板，其中，所述检测走线排布为首尾依次电连接的多行，所述检测走线的第一端和第二端分为位于所述多行的首行和尾行。
  7. 根据权利要求1-6任一所述的显示面板，其中，在所述弯折区域弯折之后，所述检测走线的第一端和第二端均位于所述非显示侧。
  8. 根据权利要求6或7所述的显示面板，其中，在所述弯折区域中，
    所述第一走线的数量和所述检测走线的行数之和小于等于500，相邻的 两行检测走线的第一间距为10-12微米，所述检测走线的线宽与所述第一间距之和为60-80微米；或者
    所述第一走线的数量和所述检测走线的行数之和大于500且小于等于2000，相邻的两行检测走线的第一间距为6-10微米，所述检测走线的线宽与所述第一间距之和为25-60微米；或者
    所述第一走线的数量和检测走线的行数之和大于2000，相邻的两行检测走线的第一间距为5-6微米，所述检测走线的线宽与所述第一间距之和为15-25微米。
  9. 根据权利要求8所述的显示面板，其中，相邻的两条所述第一走线之间的第二间距与所述第一间距相同，所述第一走线的线宽与所述第二间距之和与所述检测走线的线宽与所述第一间距之和相同。
  10. 根据权利要求1-9任一所述的显示面板，其中，在垂直于所述显示面板的板面方向上，所述第一走线和所述检测走线的厚度相同，所述厚度为700nm-850nm。
  11. 根据权利要求2或3所述的显示面板，其中，所述检测走线与所述多条第一走线中的至少部分同层设置。
  12. 根据权利要求11所述的显示面板，其中，所述显示区域包括阵列排布的多个子像素，所述多个子像素中的每个包括发光器件以及与所述发光器件电连接的像素驱动电路，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极和源漏极，
    所述检测走线与所述栅极同层设置或者与所述源漏极同层设置。
  13. 一种显示面板的制造方法，所述显示面板具有显示侧和非显示侧，所述方法包括：
    形成显示区域和位于所述显示区域一侧边的弯折区域，其中，在所述弯折区域形成至少一条第一走线以及与所述至少一条第一走线并列排布的检测走线，所述检测走线包括第一端和第二端，用于检测连接外部检测电路，所述检测走线和所述弯折区域仅形成于所述侧边的远离所述显示区域的一侧；在所述显示区域形成第二走线，所述至少一条第一走线的第一端电连接所述第二走线；
    弯折所述弯折区域，以使所述至少一条第一走线的第二端通过所述弯折区域弯折到所述非显示侧，并且所述检测走线的至少部分随所述弯折区域弯 折。
  14. 根据权利要求13所述的制造方法，还包括：在弯折所述弯折区域后，将所述检测走线的第一端和第二端连接于外部检测电路，所述外部检测电路检测所述检测走线的电阻，并将所述电阻与基准电阻比较，以确定所述检测走线的状态。
  15. 根据权利要求14所述的制造方法，其中，当所述电阻与所述基准电阻的差大于所述基准电阻的百分之十时，确定所述检测走线处于损坏状态；
    当所述电阻与所述基准电阻的差小于等于所述基准电阻的百分之十时，确定所述检测走线处于正常状态。
  16. 根据权利要求13-15任一所述的制造方法，其中，所述至少一条第一走线包括多条第一走线，所述多条第一走线包括第一组走线和第二组走线，所述第一组走线和所述第二组走线彼此绝缘适用于分别传输不同的电信号，
    所述检测走线形成在所述第一组走线和所述第二组走线之间。
  17. 根据权利要求16所述的制造方法，其中，所述检测走线与所述多条第一走线中的至少部分同层形成。
  18. 根据权利要求17所述的制造方法，其中，形成所述显示区域还包括形成阵列排布的多个子像素，所述多个子像素中的每个包括发光器件以及与所述发光器件电连接的像素驱动电路，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极和源漏极，
    所述检测走线与所述栅极同层形成或者与所述源漏极同层形成。
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