WO2021207924A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021207924A1
WO2021207924A1 PCT/CN2020/084678 CN2020084678W WO2021207924A1 WO 2021207924 A1 WO2021207924 A1 WO 2021207924A1 CN 2020084678 W CN2020084678 W CN 2020084678W WO 2021207924 A1 WO2021207924 A1 WO 2021207924A1
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WO
WIPO (PCT)
Prior art keywords
pin
substrate
display
lead
display area
Prior art date
Application number
PCT/CN2020/084678
Other languages
English (en)
French (fr)
Inventor
韩林宏
尚庭华
于鹏飞
张顺
周洋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000527.8A priority Critical patent/CN113939861A/zh
Priority to PCT/CN2020/084678 priority patent/WO2021207924A1/zh
Priority to US17/265,293 priority patent/US12016217B2/en
Priority to DE112020005544.2T priority patent/DE112020005544T5/de
Publication of WO2021207924A1 publication Critical patent/WO2021207924A1/zh
Priority to US18/488,449 priority patent/US20240049538A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • Organic light-emitting display devices are listed as a promising next-generation display technology due to their advantages of lightness, thinness, flexibility, low power consumption, wide color gamut, and high contrast.
  • the production yield of organic light-emitting display panels is a key issue that restricts the large-scale application of organic light-emitting display devices.
  • providing a display panel includes:
  • the display substrate includes a display area and a non-display area surrounding the display area.
  • the display substrate includes a substrate, and a first bonding portion and a second bonding portion located on one side of the substrate and located in the non-display area. Bonding Department, the first connection line and the second connection line, of which:
  • the first bonding part includes a plurality of first pins, and the plurality of first pins includes a first detection pin and a second detection pin;
  • the second bonding part is located on a side of the first bonding part away from the display area and connected to the first bonding part, and the second bonding part includes a plurality of second pins, so The multiple second pins include a first connection pin and a second connection pin;
  • the first connection line connects the first detection pin and the first connection pin, and includes a first crack detection line arranged around at least a part of the edge of the display area;
  • the second connection line connects the second detection pin and the second connection pin
  • the integrated circuit chip is bonded to the first bonding part, and is used to drive the display substrate to display according to the motherboard signal, and to determine the Show whether there are cracks on the edge of the substrate;
  • the circuit board is bonded to the second bonding part and is used to transmit the main board signal to the integrated circuit chip.
  • the circuit board includes a connecting wire that connects the first connecting pin and the The second connection pin is connected.
  • the second connection line includes a second crack detection line arranged around at least a part of the edge of the display area.
  • the first crack detection line is arranged around a first part of the edge of the display area
  • the second crack detection line is arranged around a second part of the edge of the display area
  • the first part of the edge is connected to the edge of the display area. There is no overlap or partial overlap of the edges of the second part.
  • the first connection line includes a first lead connecting one end of the first crack detection line and the first detection pin, and a first lead connecting the other end of the first crack detection line and the first lead.
  • the second lead of the first connecting pin, the second lead and the orthographic projection of the first bonding portion on the substrate have no overlap;
  • the second connecting line includes connecting the second crack One end of the detection line is connected to the third lead of the second detection pin, and the other end of the second crack detection line is connected to the fourth lead of the second connection pin.
  • the fourth lead is connected to the The orthographic projection of the first bonding part on the substrate has no overlap.
  • the display substrate includes: a semiconductor layer, a first insulating layer, a first gate metal layer, a second An insulating layer, a second gate metal layer, a third insulating layer, and a data metal layer;
  • the first pin includes: a first transmission sublayer located on the first gate metal layer, and a first transmission sublayer located on the data metal layer and passing through A second transmission sublayer connected to the first transmission sublayer via a via;
  • the second pin includes a single-layer transmission part located on the data metal layer.
  • the first lead and the third lead are located on the first gate metal layer; the second lead and the fourth lead are located on the second gate metal layer, and the second lead
  • the lead wire is connected to the first connection pin through a via hole, and the fourth lead wire is connected to the second connection pin through a via hole.
  • the substrate is a flexible substrate, the display area is approximately polygonal, and the first bonding portion is adjacent to one side of the display area; the display substrate further includes The bending portion on the one side of the substrate and located between the display area and the first bonding portion, the bending portion includes a plurality of false lines arranged at intervals and substantially perpendicular to the side, so The plurality of dummy wires are located on the data metal layer; the orthographic projection of any one of the first lead, the second lead, the third lead, and the fourth lead on the substrate is located at the same The two adjacent false lines are between the orthographic projections on the substrate.
  • the first crack detection line and the second crack detection line each include a plurality of first detection segments and a plurality of second detection segments that are alternately connected, and the first detection segment is located in the first detection segment.
  • the second gate metal layer, the second detection section is located in the data metal layer, and the first detection section and the second detection section are connected by a via hole.
  • the display area is approximately polygonal, the first bonding portion is adjacent to one side of the display area, and at least one of the second detection segments is adjacent to a corner of the display area.
  • the second bonding part and the first bonding part are connected by a plurality of inner pins, and the plurality of inner pins are located on the data metal layer; the plurality of second leads
  • the pin also includes a first outer test pin and a second outer test pin.
  • the first outer test pin is connected to the first test pin through an inner pin
  • the second outer test pin is connected to the first test pin through an inner pin.
  • the inner pin is connected to the second detection pin.
  • the first crack detection line is winding around the edge of the first part of the display area; and/or, the second crack detection line is winding around the edge of the second part of the display area. Coiled.
  • At least a part of the first crack detection line extends in a waveform; and/or, at least a part of the second crack detection line extends in a waveform.
  • the lengths of the first crack detection line and the second crack detection line are approximately the same.
  • the material of the connecting wire includes copper.
  • the display panel is an organic light-emitting display panel; the display substrate further includes an encapsulation layer, and the encapsulation layer exposes the plurality of first pins of the first bonding portion and the The plurality of second pins of the second bonding part.
  • a display device including the display panel described in any of the foregoing embodiments.
  • Fig. 1 is a front view of a display panel according to an embodiment of the present disclosure
  • Fig. 2a is a schematic cross-sectional view taken along the A-A direction of the display panel shown in Fig. 1;
  • Fig. 2b is a partial enlarged schematic diagram of B of the display panel shown in Fig. 1;
  • Fig. 2c is a partial enlarged schematic diagram of the position C of the display panel shown in Fig. 1;
  • Figure 2d is a schematic cross-sectional view taken along the line D-D in Figure 2c;
  • FIG. 3 is a front view of a display panel according to another embodiment of the present disclosure.
  • FIG. 4 is a front view of a display panel according to another embodiment of the present disclosure.
  • Fig. 5 is a front view of a display panel according to still another embodiment of the present disclosure.
  • Fig. 6 is a front view of a display panel according to still another embodiment of the present disclosure.
  • FIG. 7 is a front view of a display panel according to still another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • a specific component when it is described that a specific component is located between the first component and the second component, there may or may not be an intermediate component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to another component, the specific component may be directly connected to the other component without an intervening component, or may not be directly connected to the other component but with an intervening component.
  • Organic light-emitting display panels are widely used in flexible display device products due to their light, thin, and bendable characteristics. Water and oxygen in the air are the main factors affecting the service life of organic light-emitting display panels.
  • a related technology uses Thin Film Encapsulation (TFE) technology to encapsulate and protect the substrate containing organic light-emitting devices and their driving circuits to prevent water Oxygen intrusion.
  • TFE Thin Film Encapsulation
  • connection refers to electrical connection.
  • the display panel 1 provided by an embodiment of the present disclosure includes:
  • the display substrate 10 includes a display area 10P and a non-display area 10Q surrounding the display area 10P.
  • the display substrate 10 includes a substrate 120, and a first bonding portion 10a, a second bonding portion 10b, a first connection line, and a second connection line located on one side of the substrate 120 and in the non-display area 10Q, wherein:
  • the first bonding portion 10a includes a plurality of first pins 01, and the plurality of first pins 01 includes a first detection pin 101a and a second detection pin 102a;
  • the second bonding portion 10b is located in the first bonding portion 10a is away from the side of the display area 10P and is connected to the first bonding portion 10a.
  • the second bonding portion 10b includes a plurality of second pins 02, and the plurality of second pins 02 includes a first connecting pin 101b and a first connecting pin 101b.
  • the second connection pin 102b; the first connection line connects the first detection pin 101a and the first connection pin 101b, and includes a first crack detection line 111 arranged around at least a part of the edge of the display area 10P; the second connection line will The second detection pin 102a is connected to the second connection pin 102b;
  • the integrated circuit chip 20 (Integrated Circuit Chip, IC), bonded to the first bonding part 10a, is used to drive the display substrate 10 to display according to the main board signal, and according to the electrical connection of the first detection pin 101a and the second detection pin 102a.
  • the signal judgment shows whether there is a crack on the edge of the substrate 10;
  • the circuit board 30 is bonded to the second bonding part 10b for transmitting main board signals to the IC 20.
  • the circuit board 30 includes a connecting wire 105b, and the connecting wire 105b connects the first connecting pin 101b and the second connecting pin 102b.
  • the display area 10P of the display substrate 10 is used to display images, and the non-display area 10Q of the display substrate 10 is used to arrange related circuits and related electronic components to support the display of the display area 10P.
  • the first bonding portion 10a of the display substrate 10 includes a plurality of first pins 01, and the plurality of first pins 01 are bonded in a one-to-one correspondence with the plurality of pins of the IC 20, that is, the key Together, the transmission of electrical signals between the first bonding part 10a and the IC 20 is realized.
  • the second bonding portion 10b of the display substrate 10 includes a plurality of second pins 02, and the plurality of second pins 02 are bonded in a one-to-one correspondence with the plurality of pins of the circuit board 30, thereby realizing the second bonding. Transmission of electrical signals between the fixed portion 10b and the circuit board 30.
  • Some second pins 02 of the second bonding part 10b may be connected to some first pins 01 of the first bonding part 10a through internal pins 106 (ILB), thereby realizing the second bonding part 10b Transmission of electrical signals with the first bonding part 10a.
  • ILB internal pins 106
  • the circuit board 30 is connected to the main board (not shown in the figure) of the display device, so that the main board signal can be transmitted to the IC 20 through the second bonding portion 10b and the first bonding portion 10a.
  • the circuit board 30 is, for example, a flexible printed circuit board (Flexible Printed Circuit, FPC).
  • the main function of the IC 20 is to provide a driving signal, a data signal, a clock signal, etc. to the display area 10P according to the motherboard signal, so as to drive the display substrate 10 to display. As shown in FIGS.
  • the second pins 02 of the fixed portion 10b are bonded by a conductive adhesive film 001.
  • the conductive adhesive film 001 is, for example, an anisotropic conductive film (ACF).
  • the specific shape of the display area 10P of the display substrate 10 is not limited, such as circular, elliptical, polygonal, or the like.
  • the display area 10P is approximately polygonal, for example, approximately rectangular as shown in FIG. 1.
  • the first bonding portion 10a is adjacent to one of the sides of the display area 10P.
  • the second bonding portion 10b is located on the side of the first bonding portion 10a away from the display area 10P.
  • the display area is roughly polygonal, which can be understood as: the shape of the display area is a polygon after ignoring the round chamfering, oblique chamfering, or process error of the display area.
  • the display substrate 10 is an Active Matrix Organic Light-Emitting Diode (AMOLED) display substrate.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • the pixel structure of the display area 10P of the AMOLED display substrate includes an organic light emitting device 121, a thin film transistor device 122, and a capacitive device 123.
  • Each organic light emitting device 121 is controlled by the thin film transistor device 122 and can be independently and continuously Glow.
  • the display substrate may also be a Passive Matrix Organic Light-Emitting Diode (PMOLED) display substrate.
  • PMOLED Passive Matrix Organic Light-Emitting Diode
  • the display principle of the PMOLED display substrate is to light up the organic light-emitting devices arranged in an array in the display area in a scanning manner, and each organic light-emitting device instantly emits light under a short pulse.
  • the display substrate 10 is an AMOLED display substrate, and the substrate 120 may be a flexible substrate or a rigid substrate, and the specific material type of the substrate 120 is not limited.
  • the substrate 120 is a flexible substrate, and the material of the substrate includes polyimide.
  • the substrate 120 is a hard substrate, and the material includes glass or resin.
  • the structure of the AMOLED display substrate includes: a barrier layer 41 and a buffer layer 42 located on one side of the substrate 120 and arranged in a direction away from the substrate 120. , Semiconductor layer 43, first insulating layer 44, first gate metal layer 115a, second insulating layer 45, second gate metal layer 115b, third insulating layer 46, data metal layer 116, flat layer 47, anode layer 48, The pixel defining layer 49, the organic functional layer 50, the cathode layer 51, and the encapsulation layer 117.
  • the encapsulation layer 117 exposes a plurality of first pins 01 of the first bonding portion 10a and a plurality of second pins 02 of the second bonding portion 10b.
  • the display panel is a touch display panel
  • the display substrate further includes a touch structure layer located on a side of the packaging layer away from the substrate.
  • the IC 20 is not only used to provide display-related signals to the display area 10P, but also used to determine according to the electrical signals of the first detection pin 101a and the second detection pin 102a, such as the potential difference It shows whether there are cracks on the edge of the substrate 10.
  • the first detection pin 101a, the first connection line, the first connection pin 101b, the connection line 105b, the second connection pin 102b, the second connection line, and the second detection pin 102a are connected in sequence to form A crack detection circuit, wherein the first crack detection line 111 included in the first connection line is arranged around at least a part of the edge of the display area 10P.
  • the first crack detection line 111 is likely to have cracks or even break under the action of the crack stress.
  • the resistance value of the first crack detection line 111 will increase greatly after a crack occurs, and the crack detection circuit will be broken after the first crack detection line 111 is broken. Therefore, by detecting the electrical signals of the first detection pin 101a and the second detection pin 102a, it can be roughly determined whether there is a crack on the edge of the display substrate 10. In the production stage of the display panel, timely screening out defective products with cracks can improve the product quality of the display device and avoid a large amount of waste of human resources.
  • the first connection line includes a first crack detection line 111 surrounding a first part of the edge of the display area 10P
  • the second connection line includes a second part of the edge surrounding the display area 10P.
  • the second crack detection line 131 of the display area 10P has no overlap between the edge of the first part and the edge of the second part of the display area 10P.
  • the first connection line includes a first lead 11a connecting one end of the first crack detection line 111 and the first detection pin 101a, and a first lead 11a connecting the other end of the first crack detection line 111 and the first connection pin.
  • the second lead 11b of 101b, the second lead 11b and the orthographic projection of the first bonding portion 10a on the substrate 120 do not overlap; similarly, the second connection line includes one end of the second crack detection line 131 and the second
  • the third lead 13a of the detection pin 102a, and the fourth lead 13b connecting the other end of the second crack detection line 131 and the second connection pin 102b, the fourth lead 13b and the first bonding portion 10a are on the substrate 120
  • the orthographic projection has no overlap.
  • the structural design of the first bonding part 10a is more complicated than that of the second bonding part 10b.
  • the external force that needs to be applied is relatively large when the IC 20 is connected to the first bonding part 10a.
  • the inventor of the present disclosure discovered that if a part of the trace of the crack detection circuit of the display panel passes through the IC bonding part along the length of the IC bonding part, then this part of the trace also needs to be skipped.
  • the wire design avoids the pins on the IC bonding part, which doubles the structure complexity and manufacturing difficulty of the IC bonding part. Not only the process cost is high, the process is easy to produce, but also the bonding stress is increased. The possibility of damage to the circuit structure.
  • the crack detection circuit except that the first detection pin 101a and the second detection pin 102a are arranged in the first bonding part 10a, and the wiring structure is basically arranged in the first bonding part 10a.
  • the connecting line 105b which is a part of the crack detection circuit, is also provided on the circuit board 30.
  • the first detection pin 101a and the second detection pin 102a have similar structures to other first pins. Therefore, compared with the above-mentioned related technologies, the embodiments of the present disclosure can reduce the structural complexity and manufacturing difficulty of the first bonding portion 10a, thereby reducing the occurrence of process defects, reducing process costs, and reducing the damage to the circuit structure due to bonding stress. possible.
  • the wiring structure of the crack detection circuit is basically arranged outside the area where the first bonding portion 10a is located, which greatly increases the freedom of wiring design, and the wiring is on the substrate 120.
  • the projection position, the material of the wiring, and the layer position of the wiring can be flexibly selected, so it is more conducive to optimizing the electrical performance of the display substrate.
  • connection line 105b on the circuit board 30 and the orthographic projection of the second bonding portion 10b on the substrate 120 also do not overlap, that is, the circuit board 30 is bonded to the second bonding portion 10b.
  • the connecting wire 105b is located outside the area where the second bonding portion 10b is located, and the connecting wire 105b is basically not affected by the bonding force, which makes the connection between the circuit board 30 and the second bonding portion 10b more reliable.
  • the layer position and material selection flexibility of the connecting wire 105b on the circuit board 30 is also higher.
  • the material of the connection line 105b includes copper.
  • the first pin 01 includes: a first transmission sublayer 01a located on the first gate metal layer 115a, and a first transmission sublayer 01a located on the data metal layer 116 through a via hole.
  • the second transmission sublayer 01b is connected to the transmission sublayer 01a
  • the second pin 02 is a single-layer transmission part located on the data metal layer 116.
  • the inner pin 106 connecting the first bonding portion 10a and the second bonding portion 10b is also located on the data metal layer 116.
  • the first lead 11a and the third lead 13a are arranged on the first gate metal layer 115a, and are manufactured and connected in the same layer as the first transmission sublayer of each first pin 01.
  • the structure of the second lead 11b and the fourth lead 13b can be flexibly selected.
  • the second lead 11b and the fourth lead 13b are located on the first gate metal layer 115a, or the second lead 11b and the fourth lead 13b are located on the second gate metal layer 115b, or both the second lead 11b and the fourth lead 13b It includes two stacked sub-layers, the two sub-layers are respectively located in the first gate metal layer 115a and the second gate metal layer 115b, and so on.
  • the second lead 11b and the fourth lead 13b are located on the second gate metal layer 115b, the second lead 11b is connected to the first connection pin 101b through a via hole, and the fourth lead 13b is connected to the second lead via a via hole. Pin 102b is connected.
  • the substrate 120 is a flexible substrate, the display area 10P is approximately polygonal, and the first bonding portion 10a is adjacent to one side of the display area 10P; the display substrate 10 is also It includes a bending portion 61 located on one side of the substrate 120 and between the display area 10P and the first bonding portion 10a.
  • the bending portion 61 includes a plurality of false lines 610 arranged at intervals and substantially perpendicular to the side.
  • the line 610 is located in the aforementioned data metal layer 116; the orthographic projection of any one of the first lead 11a, the second lead 11b, the third lead 13a, and the fourth lead 13b on the substrate is located between two adjacent dummy lines 610 on the substrate.
  • At least one of the first lead, the second lead, the third lead, and the fourth lead may also be located outside the region where the aforementioned plurality of dummy wires are located.
  • the first bonding portion 10a and the second bonding portion 10b need to be folded toward the back side of the display substrate 10 by means of the bending portion 61, so that the IC 20 and the circuit board 30 are fixed.
  • the plurality of false wires 610 arranged at intervals and substantially perpendicular to the side can improve the flexibility of bending, so that the layer structure is not prone to breakage.
  • a plurality of false wires 610 are located on the aforementioned data metal layer 116.
  • the material of the data metal layer 116 can be titanium aluminum titanium or molybdenum aluminum molybdenum, etc., which has good ductility, which makes bending The bending flexibility of the part 61 is better.
  • the orthographic projection of any one of the first lead 11a, the second lead 11b, the third lead 13a, and the fourth lead 13b on the substrate 120 is located between the orthographic projections of two adjacent dummy wires 610 on the substrate 120, In this way, the first lead 11a, the second lead 11b, the third lead 13a, and the fourth lead 13b can be protected by the false wire 610, and are not easily broken due to bending, which improves the reliability of the crack detection circuit.
  • the first crack detection line 111 and the second crack detection line 131 each include a plurality of first detection sections 1110 and a plurality of second detection sections that are alternately connected. 1111, wherein the first detection section 1110 is located on the second gate metal layer 115b, the second detection section 1111 is located on the data metal layer 116, and the first detection section 1110 and the second detection section 1111 are connected by a via hole.
  • the inventor of the present disclosure has noticed that during the production and transportation of the display panel or the display device, if the wires extend continuously in the same metal layer for too long, electrostatic breakdown is likely to occur.
  • the first crack detection line 111 and the second crack detection line 131 each include a plurality of first detection sections 1110 and a plurality of second detection sections 1111 that are alternately connected and in different layers, and adjacent first The detection section 1110 and the second detection section 1111 are connected by a via hole, so that the possibility of electrostatic breakdown of the crack detection line can be effectively reduced.
  • the inventor of the present disclosure also noticed that, due to its shape characteristics, the corner area of the display panel is more prone to tip discharge due to the accumulated electrostatic charge, causing the wiring to be electrostatically broken down.
  • at least one second detection section 1111 is adjacent to the corner of the display area 10P. In this way, it is possible to effectively reduce or even prevent the crack detection line from being electrostatically broken in the corner area.
  • the structural design of this embodiment also makes the structure of the first crack detection line 111 and the second crack detection line 131 in the corner area more sensitive to the crack stress, and is more likely to be damaged or destroyed by the crack stress. Therefore, the crack can be further improved. Sensitivity and accuracy of detection.
  • the first detection section 1110 is located on the second gate metal layer 115b, and the second detection section 1111 is located on the data metal layer 116.
  • the total thickness of the insulating layers on both sides of the second gate metal layer 115b is basically the same.
  • the first detection section 1110 with a relatively large length is arranged on the second gate metal layer 115b.
  • the section 1110 is basically the same in sensitivity to the stress caused by the insulation layer fracture on either side. Therefore, it can reflect the crack situation more accurately, which is more conducive to improving the accuracy of crack detection.
  • the first crack detection line 111 surrounds the first part of the edge of the display area 10P and has a winding shape
  • the second crack detection line 131 surrounds the second part of the edge of the display area 10P. And it is winding.
  • This design can significantly increase the total length of the crack detection line in the limited wiring area. Near the same position, as long as any one of them has a crack or break, the IC 20 can determine that there is a crack on the edge of the display substrate 10. Therefore, the detection Sensitivity and accuracy are further improved.
  • the length of the first crack detection line 111 and the second crack detection line 131 and the adopted winding design form are not limited, and can be designed according to the size of the frame of the display device.
  • the first crack detection line 111 includes two first detection sections 111a and a first connection section 111b, and two first detection sections 111a
  • the orthographic projection on the substrate 120 is arranged at intervals
  • the second crack detection line 131 includes two second detection sections 131a and a second connecting section 131b.
  • the orthographic projections of the two second detection sections 131a on the substrate 120 are arranged at intervals .
  • the first connection line includes a first crack detection line 111 that surrounds at least a part of the edge of the display area 10P, and the second connection line connects the second detection pin 102a and The second connecting pin 102b is connected to the inner pin 106.
  • the first connection line includes a first crack detection line 111 surrounding the edge of the first part of the display area 10P
  • the second connection line includes a second part surrounding the display area 10P.
  • This embodiment further increases the length of the edge of the display area 10P surrounded by the crack detection line, thereby further improving the accuracy of the IC 20 for crack detection on the edge of the display substrate 10.
  • At least a part of the first crack detection line 111 extends in a wave shape, for example, in a zigzag wave or a curved wave shape.
  • At least a part of the second crack detection line 131 extends in a wave shape, for example, in a zigzag wave or a curved wave shape.
  • the lengths of the first crack detection line 111 and the second crack detection line 131 are approximately equal. In this way, the probability that the crack or fracture of the first crack detection line 111 shows that there is a crack on the edge of the substrate 10 is approximately equal to the probability that the crack or fracture of the second crack detection line 131 shows that there is a crack on the edge of the substrate 10. In addition, it is also convenient to design and manufacture the routing of the first crack detection line 111 and the second crack detection line 131. Wherein, the lengths of the first crack detection line 111 and the second crack detection line 131 are approximately equal, which can be understood as: the difference between the lengths of the first crack detection line 111 and the second crack detection line 131 is within a certain error range.
  • the plurality of second pins 02 of the second bonding portion 10b further includes a first outer test pin 103b and a second outer test pin 104b.
  • the test pin 103b is connected to the first test pin 101a through an inner pin 106
  • the second outer test pin 104b is connected to the second test pin 102a through an inner pin 106.
  • the first outer test pin 103b and the second outer test pin 104b are used for the probes of the external contact voltmeter. By detecting the voltages of the first external test pin 103b and the second external test pin 104b, it can be determined whether the IC 20 is working normally in the crack detection circuit.
  • an embodiment of the present disclosure also provides a display device 100 including the display panel 1 of any of the foregoing embodiments.
  • the display device is a display device including a bendable flexible display panel.
  • the display device may also be a display device including a flat display panel, or a display device including a curved display panel.
  • the specific product type of the display device is not limited, for example, it can be a display, a computer, a TV, a mobile phone, a wearable device, an electronic paper, or a display screen, and so on.
  • the product quality of the display device is relatively high.

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Abstract

一种显示面板（1）及显示装置（100）。显示面板（1）包括：显示基板（10），包括衬底（120）及位于衬底（120）一侧且位于非显示区域（10Q）的第一邦定部（10a）、第二邦定部（10b）、第一连接线路和第二连接线路，第一邦定部（10a）包括第一检测引脚（101a）和第二检测引脚（102a）；第二邦定部（10b）位于第一邦定部（10a）远离显示区域（10P）的一侧并与第一邦定部（10a）连接，包括第一连接引脚（101b）和第二连接引脚（102b）；第一连接线路将第一检测引脚（101a）和第一连接引脚（101b）连接且包括围绕显示区域（10P）的至少部分边缘的第一裂纹检测线（111）；第二连接线路将第二检测引脚（102a）和第二连接引脚（102b）连接；集成电路芯片（20），邦定于第一邦定部（10a），根据第一检测引脚（101a）和第二检测引脚（102a）的电信号判断显示基板（10）的边缘是否存在裂纹；电路板（30），邦定于第二邦定部（10b），包括将第一连接引脚（101b）和第二连接引脚（102b）连接的连接线（105b）。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
有机发光显示装置由于其轻薄、可弯曲、功耗低、色域广、对比度高等优点，被列为极具发展前景的下一代显示技术。有机发光显示面板的生产良率，是制约有机发光显示装置走向大规模应用的一个关键问题。
发明内容
根据本公开实施例的一方面，提供一种显示面板包括：
显示基板，包括显示区域和围绕所述显示区域的非显示区域，所述显示基板包括衬底，以及位于所述衬底的一侧且位于所述非显示区域的第一邦定部、第二邦定部、第一连接线路和第二连接线路，其中：
所述第一邦定部包括多个第一引脚，所述多个第一引脚包括第一检测引脚和第二检测引脚；
所述第二邦定部位于所述第一邦定部远离所述显示区域的一侧并与所述第一邦定部连接，所述第二邦定部包括多个第二引脚，所述多个第二引脚包括第一连接引脚和第二连接引脚；
所述第一连接线路将所述第一检测引脚和所述第一连接引脚连接，且包括围绕所述显示区域的至少一部分边缘设置的第一裂纹检测线；
所述第二连接线路将所述第二检测引脚和所述第二连接引脚连接；
集成电路芯片，邦定于所述第一邦定部，用于根据主板信号驱动所述显示基板显示，及根据所述第一检测引脚和所述第二检测引脚的电信号判断所述显示基板的边缘是否存在裂纹；
电路板，邦定于所述第二邦定部，用于向所述集成电路芯片传输所述主板信号，所述电路板包括连接线，所述连接线将所述第一连接引脚和所述第二连接引脚连接。
在一些实施例中，所述第二连接线路包括围绕所述显示区域的至少一部分边缘设置的第二裂纹检测线。
在一些实施例中，所述第一裂纹检测线围绕所述显示区域的第一部分边缘设置，所述第二裂纹检测线围绕所述显示区域的第二部分边缘设置，所述第一部分边缘和所述第二部分边缘无重合或部分重合。
在一些实施例中，所述第一连接线路包括连接所述第一裂纹检测线的一端与所述第一检测引脚的第一引线，以及连接所述第一裂纹检测线的另一端与所述第一连接引脚的第二引线，所述第二引线与所述第一邦定部在所述衬底上的正投影无交叠；所述第二连接线路包括连接所述第二裂纹检测线的一端与所述第二检测引脚的第三引线，以及连接所述第二裂纹检测线的另一端与所述第二连接引脚的第四引线，所述第四引线与所述第一邦定部在所述衬底上的正投影无交叠。
在一些实施例中，所述连接线与所述第二邦定部在所述衬底上的正投影无交叠。
在一些实施例中，所述显示基板包括：位于所述衬底的所述一侧且沿远离所述衬底的方向依次设置的半导体层、第一绝缘层、第一栅金属层、第二绝缘层、第二栅金属层、第三绝缘层和数据金属层；所述第一引脚包括：位于所述第一栅金属层的第一传输子层，以及位于所述数据金属层并通过过孔与所述第一传输子层连接的第二传输子层；所述第二引脚包括位于所述数据金属层的单层传输部。
在一些实施例中，所述第一引线和所述第三引线位于所述第一栅金属层；所述第二引线和所述第四引线位于所述第二栅金属层，所述第二引线通过过孔与所述第一连接引脚连接，所述第四引线通过过孔与所述第二连接引脚连接。
在一些实施例中，所述衬底为柔性衬底，所述显示区域大致呈多边形，所述第一邦定部与所述显示区域的一个边相邻；所述显示基板还包括位于所述衬底的所述一侧且位于所述显示区域与所述第一邦定部之间的折弯部，所述折弯部包括间隔设置且与所述边大致垂直的多根假线，所述多根假线位于所述数据金属层；所述第一引线、所述第二引线、所述第三引线和所述第四引线中的任意一个在所述衬底上的正投影位于相邻两根所述假线在所述衬底上的正投影之间。
在一些实施例中，所述第一裂纹检测线和所述第二裂纹检测线均包括交替连接的多个第一检测段和多个第二检测段，所述第一检测段位于所述第二栅金属层，所述第二检测段位于所述数据金属层，所述第一检测段和所述第二检测段通过过孔连接。
在一些实施例中，所述显示区域大致呈多边形，所述第一邦定部与所述显示区域的一个边相邻，至少一个所述第二检测段与所述显示区域的角相邻。
在一些实施例中，所述第二邦定部与所述第一邦定部通过多个内引脚连接，所述 多个内引脚位于所述数据金属层；所述多个第二引脚还包括第一外测试引脚和第二外测试引脚，所述第一外测试引脚通过一个内引脚与所述第一检测引脚连接，所述第二外测试引脚通过一个内引脚与所述第二检测引脚连接。
在一些实施例中，所述第一裂纹检测线围绕所述显示区域的第一部分边缘呈迂绕状；和/或，所述第二裂纹检测线围绕所述显示区域的第二部分边缘呈迂绕状。
在一些实施例中，所述第一裂纹检测线的至少一部分呈波形延伸；和/或，所述第二裂纹检测线的至少一部分呈波形延伸。
在一些实施例中，所述第一裂纹检测线和所述第二裂纹检测线的长度大致相等。
在一些实施例中，所述连接线的材料包括铜。
在一些实施例中，所述显示面板为有机发光显示面板；所述显示基板还包括封装层，所述封装层曝露出所述第一邦定部的所述多个第一引脚和所述第二邦定部的所述多个第二引脚。
根据本公开实施例的另一方面，提供一种显示装置，包括前述任一实施例所述的显示面板。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是本公开一实施例的显示面板的主视图；
图2a是图1中所示显示面板的A-A向截面示意图；
图2b是图1中所示显示面板的B处局部放大示意图；
图2c是图1中所示显示面板的C处局部放大示意图；
图2d是图2c中的D-D向截面示意图；
图3是本公开另一实施例的显示面板的主视图；
图4是本公开又一实施例的显示面板的主视图；
图5是本公开再一实施例的显示面板的主视图；
图6是本公开再一实施例的显示面板的主视图；
图7是本公开再一实施例的显示面板的主视图；
图8是本公开一实施例的显示装置的示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
有机发光显示面板由于其轻薄、可弯曲的特点，被广泛用于柔性显示装置产品中。空气中的水氧是影响有机发光显示面板使用寿命的主要因素，一种相关技术采用薄膜封装(Thin Film Encapsulation，TFE)技术对包含有机发光器件及其驱动电路的基板进行封装保护，以防止水氧侵入。
本公开的发明人在实现本公开实施例的过程中注意到，有机发光显示面板在生产过程中，边缘处可能已产生裂纹，若不及时检出，直接后果就是导致水氧侵入显示区域，致使有机发光器件失效。为解决该技术问题，本公开实施例提供了一种显示面板及显示装置。在本公开以下各实施例中，连接指电性连接。
如图1所示，本公开一实施例提供的显示面板1，包括：
显示基板10，包括显示区域10P和围绕显示区域10P的非显示区域10Q。该显示基板10包括衬底120，以及位于衬底120的一侧且位于非显示区域10Q的第一邦定部10a、第二邦定部10b、第一连接线路和第二连接线路，其中：第一邦定部10a包括多个第一引脚01，该多个第一引脚01包括第一检测引脚101a和第二检测引脚102a；第二邦定部10b位于第一邦定部10a远离显示区域10P的一侧并与第一邦定部10a连接，第二邦定部10b包括多个第二引脚02，该多个第二引脚02包括第一连接引脚101b和第二连接引脚102b；第一连接线路将第一检测引脚101a和第一连接引脚101b连接，且包括围绕显示区域10P的至少一部分边缘设置的第一裂纹检测线111；第二连接线路将第二检测引脚102a和第二连接引脚102b连接；
集成电路芯片20(Integrated Circuit Chip，IC)，邦定于第一邦定部10a，用于根据主板信号驱动显示基板10显示，及根据第一检测引脚101a和第二检测引脚102a的电信号判断显示基板10的边缘是否存在裂纹；
电路板30，邦定于第二邦定部10b，用于向IC 20传输主板信号，电路板30包括连接线105b，连接线105b将第一连接引脚101b和第二连接引脚102b连接。
显示基板10的显示区域10P用于显示图像，显示基板10的非显示区域10Q用于布置相关电路和相关电子元件，以支持显示区域10P的显示。在本公开实施例中，显示基板10的第一邦定部10a包括多个第一引脚01，该多个第一引脚01与IC 20的多个引脚一一对应邦定，即键合，从而实现第一邦定部10a与IC 20之间电信号的传输。类似的，显示基板10的第二邦定部10b包括多个第二引脚02，该多个第二引脚02与电路板30的多个引脚一一对应邦定，从而实现第二邦定部10b与电路板30之间电信号的传输。第二邦定部10b的一些第二引脚02可以通过内引脚106(Internal pin bonding，ILB)与第一邦定部10a的一些第一引脚01连接，从而实现第二邦定部10b与第一邦定部10a之间电信号的传输。电路板30与显示装置的主板(图中未示出)连接，从而可以通过第二邦定部10b和第一邦定部10a向IC 20传输主板信号。电路板 30例如为柔性印刷电路板(Flexible Printed Circuit，FPC)。IC 20的主要作用是根据主板信号向显示区域10P提供驱动信号、数据信号和时钟信号等，从而驱动显示基板10显示。如图1和图2a所示，在本公开的一些实施例中，IC 20的引脚与第一邦定部10a的第一引脚01之间，以及电路板30的引脚与第二邦定部10b的第二引脚02之间通过导电胶膜001邦定。导电胶膜001例如为异方性导电胶膜(Anisotropic Conductive Film，ACF)。
在本公开实施例中，显示基板10的显示区域10P的具体形状不限，例如呈圆形、椭圆形或者多边形等等。在本公开的一些实施例中，显示区域10P大致呈多边形，例如，大致呈图1所示的矩形。第一邦定部10a与显示区域10P的其中一个边相邻，例如，第一邦定部10a与大致呈矩形的显示区域10P的其中一个长边相邻。第二邦定部10b位于第一邦定部10a的远离显示区域10P的一侧。显示区域大致呈多边形，可以理解为：在忽略显示区域的圆倒角、斜倒角或者工艺误差后，显示区域的形状为多边形。
在本公开的一些实施例中，显示基板10为主动矩阵有机发光二极管(Active Matrix Organic Light-Emitting Diode，AMOLED)显示基板。如图2d所示，AMOLED显示基板的显示区域10P的像素结构包括有机发光器件121、薄膜晶体管器件122和电容器件123，每个有机发光器件121受薄膜晶体管器件122的控制，可以独立且连续的发光。在本公开的另一些实施例中，显示基板也可以为被动矩阵有机发光二极管(Passive Matrix Organic Light-Emitting Diode，PMOLED)显示基板。PMOLED显示基板的显示原理为，以扫描方式点亮显示区域呈阵列排布的有机发光器件，每个有机发光器件在短脉冲下瞬间发光。
在本公开一些实施例中，显示基板10为AMOLED显示基板，其衬底120可以为柔性衬底或者硬质衬底，衬底120的具体材料类型不限。例如，在一些实施例中，衬底120为柔性衬底，衬底的材料包括聚酰亚胺。在另一些实施例中，衬底120为硬质衬底，材料包括玻璃或者树脂等。
如图2a和图2d所示，在本公开的一些实施例中，AMOLED显示基板的结构包括：位于衬底120的一侧且沿远离衬底120的方向依次设置的阻挡层41、缓冲层42、半导体层43、第一绝缘层44、第一栅金属层115a、第二绝缘层45、第二栅金属层115b、第三绝缘层46、数据金属层116、平坦层47、阳极层48、像素界定层49、有机功能层50、阴极层51和封装层117。封装层117曝露出第一邦定部10a的多个第一引脚 01和第二邦定部10b的多个第二引脚02。在本公开的一些实施例中，显示面板为触控显示面板，显示基板还包括位于封装层的远离衬底的一侧的触控结构层。
在本公开实施例中，IC 20除了用于向显示区域10P提供与显示相关的信号外，还用于根据第一检测引脚101a和第二检测引脚102a的电信号，例如电位差，判断显示基板10的边缘是否存在裂纹。如图1所示，第一检测引脚101a、第一连接线路、第一连接引脚101b、连接线105b、第二连接引脚102b、第二连接线路和第二检测引脚102a依次连接形成裂纹检测电路，其中，第一连接线路所包含的第一裂纹检测线111围绕显示区域10P的至少一部分边缘设置。如果显示基板10的边缘存在裂纹，那么，第一裂纹检测线111在裂纹应力的作用下，很有可能也会产生裂纹，甚至断裂。第一裂纹检测线111出现裂纹后阻值会大幅增加，第一裂纹检测线111断裂后会导致裂纹检测电路断路。因此，通过检测第一检测引脚101a和第二检测引脚102a的电信号，可以大致判断出显示基板10的边缘是否存在裂纹。在显示面板的生产阶段，及时将存在裂纹的不良品筛出，可以提高显示装置的产品品质，避免人力资材的大量浪费。
如图1所示，在本公开的一些实施例中，第一连接线路包括围绕显示区域10P的第一部分边缘的第一裂纹检测线111，第二连接线路包括围绕显示区域10P的第二部分边缘的第二裂纹检测线131，其中，显示区域10P的第一部分边缘和第二部分边缘无重合。显示区域10P被裂纹检测线所围绕的边缘的长度越大，即显示区域10P的上述第一部分边缘和第二部分边缘的长度之和越大，IC 20对显示基板10的边缘进行裂纹检测的准确性越高。
如图1所示，第一连接线路包括连接第一裂纹检测线111的一端与第一检测引脚101a的第一引线11a，以及连接第一裂纹检测线111的另一端与第一连接引脚101b的第二引线11b，第二引线11b与第一邦定部10a在衬底120上的正投影无交叠；类似的，第二连接线路包括连接第二裂纹检测线131的一端与第二检测引脚102a的第三引线13a，以及连接第二裂纹检测线131的另一端与第二连接引脚102b的第四引线13b，第四引线13b与第一邦定部10a在衬底120上的正投影无交叠。
由于IC 20需要向显示区域10P提供驱动信号、数据信号和时钟信号等诸多信号，因此，第一邦定部10a的结构设计相对第二邦定部10b更为复杂。此外，为使IC 20与第一邦定部10a可靠连接，在将IC 20与第一邦定部10a邦定时，所需施加的外力也相对较大。本公开的发明人在实现本公开实施例的过程中发现，如果显示面板的裂纹检测电路的一部分走线沿IC邦定部的长度方向经过IC邦定部，那么该部分走线还 需要通过跳线设计避开IC邦定部上的引脚，这使得IC邦定部的结构复杂度和制作难度成倍增加，不但工艺成本较高，易产生工艺不良，而且也加大了因邦定应力导致电路结构被破坏的可能性。
在本公开实施例中，裂纹检测电路除第一检测引脚101a和第二检测引脚102a设置在了第一邦定部10a，其走线结构基本都设置在了第一邦定部10a所在区域之外，作为裂纹检测电路一部分的连接线105b，还设置在了电路板30上，第一检测引脚101a和第二检测引脚102a与其它第一引脚的结构相类似。因此，对比上述相关技术，本公开实施例可以减小第一邦定部10a的结构复杂度和制作难度，从而减少工艺不良发生，降低工艺成本，减小因邦定应力导致电路结构被破坏的可能。
此外，本公开实施例中，裂纹检测电路的走线结构基本都设置在第一邦定部10a所在区域之外，这使得走线设计的自由度也大大增加，走线在衬底120上的投影位置、走线的材料、走线的层位置均可以灵活选择，因此，更有利于优化显示基板的电学性能。
如图1所示，电路板30上的连接线105b与第二邦定部10b在衬底120上的正投影也无交叠，也就是说，电路板30与第二邦定部10b邦定后，连接线105b位于第二邦定部10b所在区域之外，连接线105b基本不受邦定力的影响，这使得电路板30与第二邦定部10b连接的可靠性更高。并且，连接线105b在电路板30上的层位置和材料选择的灵活性也更高。在一些实施例中，连接线105b的材料包括铜。
第一引脚01和第二引脚02的具体结构不限。如图2a和图2b所示，在一些实施例中，第一引脚01包括：位于第一栅金属层115a的第一传输子层01a，以及位于数据金属层116并通过过孔与第一传输子层01a连接的第二传输子层01b，第二引脚02为位于数据金属层116的单层传输部。此外，连接第一邦定部10a和第二邦定部10b的内引脚106也位于数据金属层116。为简化制作工艺，第一引线11a和第三引线13a设置在第一栅金属层115a，与各个第一引脚01的第一传输子层同层制作并连接。
如前所述，由于第二引线11b和第四引线13b设置在第一邦定部10a所在区域之外，因此，第二引线11b和第四引线13b的结构形式可以灵活选择。例如，第二引线11b和第四引线13b位于第一栅金属层115a，或者，第二引线11b和第四引线13b位于第二栅金属层115b，或者，第二引线11b和第四引线13b均包括层叠的两个子层，两个子层分别位于第一栅金属层115a和第二栅金属层115b，等等。在一些实施例中，第二引线11b和第四引线13b位于第二栅金属层115b，第二引线11b通过过孔与第 一连接引脚101b连接，第四引线13b通过过孔与第二连接引脚102b连接。
如图3所示，在本公开的一些实施例中，衬底120为柔性衬底，显示区域10P大致呈多边形，第一邦定部10a与显示区域10P的一个边相邻；显示基板10还包括位于衬底120的一侧且位于显示区域10P与第一邦定部10a之间的折弯部61，折弯部61包括间隔设置且与边大致垂直的多根假线610，多根假线610位于前述的数据金属层116；第一引线11a、第二引线11b、第三引线13a和第四引线13b中的任意一个在衬底上的正投影位于相邻两根假线610在衬底120上的正投影之间。此外，在本公开的其它实施例中，第一引线、第二引线、第三引线和第四引线中的至少一个也可以位于前述多根假线所在的区域之外。
该实施例显示面板1应用于显示装置时，需要凭借折弯部61将第一邦定部10a和第二邦定部10b折向显示基板10的背侧，从而使IC 20和电路板30固定在显示基板10的背侧。间隔设置且与边大致垂直的多根假线610可以提高弯折的柔韧性，使其层结构不易发生断裂。在本公开的一些实施例中，多根假线610位于前述的数据金属层116，数据金属层116的材料可以采用钛铝钛或钼铝钼等，具有较好的延展性，这使得折弯部61的弯折柔韧性更佳。
第一引线11a、第二引线11b、第三引线13a和第四引线13b中的任意一个在衬底120上的正投影位于相邻两根假线610在衬底120上的正投影之间，这样，第一引线11a、第二引线11b、第三引线13a和第四引线13b可以受到假线610的保护，不易因弯折而发生断裂，提高了裂纹检测电路的可靠性。
如图2c和图2d所示，在本公开的一些实施例中，第一裂纹检测线111和第二裂纹检测线131均包括交替连接的多个第一检测段1110和多个第二检测段1111，其中，第一检测段1110位于第二栅金属层115b，第二检测段1111位于数据金属层116，第一检测段1110和第二检测段1111通过过孔连接。
本公开的发明人注意到，显示面板或显示装置在生产和运输过程中，如果走线在同一金属层中连续延伸长度过长，很容易发生静电击穿。在本公开上述实施例中，第一裂纹检测线111和第二裂纹检测线131均包括交替连接且不同层的多个第一检测段1110和多个第二检测段1111，相邻的第一检测段1110和第二检测段1111通过过孔连接，这样，可以有效减少裂纹检测线被静电击穿的可能。
本公开的发明人还注意到，显示面板的角部区域由于其形状特点，更容易因积聚的静电电荷发生尖端放电，导致走线被静电击穿。在本公开的一些实施例中，至少一 个第二检测段1111与显示区域10P的角相邻，这样，可以有效减少、甚至避免裂纹检测线在角部区域被静电击穿。此外，该实施例结构设计，还使得第一裂纹检测线111和第二裂纹检测线131在角部区域的结构对裂纹应力更加敏感，更容易被裂纹应力损伤或破坏，因此，能够进一步提高裂纹检测的灵敏性和准确性。
在图2c和图2d所示的实施例中，第一检测段1110位于第二栅金属层115b，第二检测段1111位于数据金属层116。显示基板10的结构中，第二栅金属层115b两侧的绝缘层总厚度基本相当，将长度占比相对较大的第一检测段1110设置在第二栅金属层115b，这样，第一检测段1110对于任意一侧绝缘层断裂所带来应力的敏感性基本相当，因此，能够更准确的反映裂纹情况，从而更有利于提高裂纹检测的准确性。
如图1所示，在本公开的一些实施例中，第一裂纹检测线111围绕显示区域10P的第一部分边缘并且呈迂绕状，第二裂纹检测线131围绕显示区域10P的第二部分边缘并且呈迂绕状。这样设计可以显著增加裂纹检测线在有限的布线区域内的总长度，在同一位置附近，只要其中任意一段产生裂纹或者断裂，IC 20便可以判断出显示基板10的边缘存在裂纹，因此，检测的灵敏性和准确性进一步提高。
第一裂纹检测线111和第二裂纹检测线131的长度和所采用的迂绕设计形式不限，可以根据显示装置的边框尺寸情况来设计。例如，图1所示的实施例中，为例兼顾显示装置的窄边框效果，第一裂纹检测线111包括两个第一检测段111a和一个第一连接段111b，两个第一检测段111a在衬底120上的正投影间隔设置，第二裂纹检测线131包括两个第二检测段131a和一个第二连接段131b，两个第二检测段131a在衬底120上的正投影间隔设置。
如图4所示，在本公开的另一些实施例中，第一连接线路包括围绕显示区域10P的至少一部分边缘的第一裂纹检测线111，第二连接线路为将第二检测引脚102a和第二连接引脚102b连接的内引脚106。显示区域10P被第一裂纹检测线111所围绕的边缘的长度越大，IC 20对显示基板10的边缘进行裂纹检测的准确性越高。
如图5所示，在本公开的又一些实施例中，第一连接线路包括围绕显示区域10P的第一部分边缘的第一裂纹检测线111，第二连接线路包括围绕显示区域10P的第二部分边缘的第二裂纹检测线131，其中，显示区域10P的第一部分边缘和第二部分边缘部分重合。该实施例进一步增加了显示区域10P被裂纹检测线所围绕的边缘的长度，从而进一步提高了IC 20对显示基板10的边缘进行裂纹检测的准确性。
如图6所示，在本公开的一些实施例中，第一裂纹检测线111的至少一部分呈波 形延伸，例如呈折线波或曲线波形状延伸。第二裂纹检测线131的至少一部分呈波形延伸，例如呈折线波或曲线波形状延伸。采用该设计，也可以增加第一裂纹检测线111和第二裂纹检测线131在各自有限的布线区域内的长度，从而进一步提高IC 20对显示基板10的边缘进行裂纹检测的灵敏性和准确性。
在本公开的一些实施例中，第一裂纹检测线111和第二裂纹检测线131的长度大致相等。这样，通过第一裂纹检测线111的裂纹或断裂检测出显示基板10的边缘存在裂纹的概率，大致等于通过第二裂纹检测线131的裂纹或断裂检测出显示基板10的边缘存在裂纹的概率，并且，也便于第一裂纹检测线111和第二裂纹检测线131的走线设计和制作。其中，第一裂纹检测线111和第二裂纹检测线131的长度大致相等，可以理解为：第一裂纹检测线111和第二裂纹检测线131的长度之差在一定的误差范围内。
如图7所示，在本公开的一些实施例中，第二邦定部10b的多个第二引脚02还包括第一外测试引脚103b和第二外测试引脚104b，第一外测试引脚103b通过一个内引脚106与第一检测引脚101a连接，第二外测试引脚104b通过一个内引脚106与第二检测引脚102a连接。显示基板10在制作过程中，需要对裂纹检测电路是否合格进行测试，第一外测试引脚103b和第二外测试引脚104b用于外接触电压计的探针。通过检测第一外测试引脚103b和第二外测试引脚104b的电压，可以判断IC 20在裂纹检测电路中是否正常工作。
如图8所示，本公开实施例还提供了一种显示装置100，包括前述任一实施例的显示面板1。图8所示的实施例中，显示装置为包含可弯折柔性显示面板的显示装置。在本公开的其它实施例中，显示装置也可以为包含平面显示面板的显示装置，或者为包含曲面显示面板的显示装置。显示装置的具体产品类型不限，例如可以为显示器、电脑、电视机、手机、可穿戴设备、电子纸或者展示屏等等。
如前面的描述，由于在显示面板的生产阶段便可以将边缘存在裂纹的不良品筛出，因此，显示装置的产品品质较高。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (17)

  1. 一种显示面板，包括：
    显示基板，包括显示区域和围绕所述显示区域的非显示区域，所述显示基板包括衬底，以及位于所述衬底的一侧且位于所述非显示区域的第一邦定部、第二邦定部、第一连接线路和第二连接线路，其中：
    所述第一邦定部包括多个第一引脚，所述多个第一引脚包括第一检测引脚和第二检测引脚；
    所述第二邦定部位于所述第一邦定部远离所述显示区域的一侧并与所述第一邦定部连接，所述第二邦定部包括多个第二引脚，所述多个第二引脚包括第一连接引脚和第二连接引脚；
    所述第一连接线路将所述第一检测引脚和所述第一连接引脚连接，且包括围绕所述显示区域的至少一部分边缘设置的第一裂纹检测线；
    所述第二连接线路将所述第二检测引脚和所述第二连接引脚连接；
    集成电路芯片，邦定于所述第一邦定部，用于根据主板信号驱动所述显示基板显示，及根据所述第一检测引脚和所述第二检测引脚的电信号判断所述显示基板的边缘是否存在裂纹；
    电路板，邦定于所述第二邦定部，用于向所述集成电路芯片传输所述主板信号，所述电路板包括连接线，所述连接线将所述第一连接引脚和所述第二连接引脚连接。
  2. 根据权利要求1所述的显示面板，其中：
    所述第二连接线路包括围绕所述显示区域的至少一部分边缘设置的第二裂纹检测线。
  3. 根据权利要求2所述的显示面板，其中：
    所述第一裂纹检测线围绕所述显示区域的第一部分边缘设置，所述第二裂纹检测线围绕所述显示区域的第二部分边缘设置，所述第一部分边缘和所述第二部分边缘无重合或部分重合。
  4. 根据权利要求3所述的显示面板，其中：
    所述第一连接线路包括连接所述第一裂纹检测线的一端与所述第一检测引脚的第一引线，以及连接所述第一裂纹检测线的另一端与所述第一连接引脚的第二引线，所述第二引线与所述第一邦定部在所述衬底上的正投影无交叠；
    所述第二连接线路包括连接所述第二裂纹检测线的一端与所述第二检测引脚的第三引线，以及连接所述第二裂纹检测线的另一端与所述第二连接引脚的第四引线，所述第四引线与所述第一邦定部在所述衬底上的正投影无交叠。
  5. 根据权利要求4所述的显示面板，其中：所述连接线与所述第二邦定部在所述衬底上的正投影无交叠。
  6. 根据权利要求4所述的显示面板，其中：
    所述显示基板包括：位于所述衬底的所述一侧且沿远离所述衬底的方向依次设置的半导体层、第一绝缘层、第一栅金属层、第二绝缘层、第二栅金属层、第三绝缘层和数据金属层；
    所述第一引脚包括：位于所述第一栅金属层的第一传输子层，以及位于所述数据金属层并通过过孔与所述第一传输子层连接的第二传输子层；
    所述第二引脚包括位于所述数据金属层的单层传输部。
  7. 根据权利要求6所述的显示面板，其中：
    所述第一引线和所述第三引线位于所述第一栅金属层；
    所述第二引线和所述第四引线位于所述第二栅金属层，所述第二引线通过过孔与所述第一连接引脚连接，所述第四引线通过过孔与所述第二连接引脚连接。
  8. 根据权利要求6所述的显示面板，其中：
    所述衬底为柔性衬底，所述显示区域大致呈多边形，所述第一邦定部与所述显示区域的一个边相邻；
    所述显示基板还包括位于所述衬底的所述一侧且位于所述显示区域与所述第一邦定部之间的折弯部，所述折弯部包括间隔设置且与所述边大致垂直的多根假线，所述多根假线位于所述数据金属层；
    所述第一引线、所述第二引线、所述第三引线和所述第四引线中的任意一个在所 述衬底上的正投影位于相邻两根所述假线在所述衬底上的正投影之间。
  9. 根据权利要求6所述的显示面板，其中：
    所述第一裂纹检测线和所述第二裂纹检测线均包括交替连接的多个第一检测段和多个第二检测段，所述第一检测段位于所述第二栅金属层，所述第二检测段位于所述数据金属层，所述第一检测段和所述第二检测段通过过孔连接。
  10. 根据权利要求9所述的显示面板，其中：
    所述显示区域大致呈多边形，所述第一邦定部与所述显示区域的一个边相邻，至少一个所述第二检测段与所述显示区域的角相邻。
  11. 根据权利要求6所述的显示面板，其中：
    所述第二邦定部与所述第一邦定部通过多个内引脚连接，所述多个内引脚位于所述数据金属层；
    所述多个第二引脚还包括第一外测试引脚和第二外测试引脚，所述第一外测试引脚通过一个内引脚与所述第一检测引脚连接，所述第二外测试引脚通过一个内引脚与所述第二检测引脚连接。
  12. 根据权利要求3所述的显示面板，其中：
    所述第一裂纹检测线围绕所述显示区域的第一部分边缘呈迂绕状；和/或，所述第二裂纹检测线围绕所述显示区域的第二部分边缘呈迂绕状。
  13. 根据权利要求12所述的显示面板，其中：
    所述第一裂纹检测线的至少一部分呈波形延伸；和/或，所述第二裂纹检测线的至少一部分呈波形延伸。
  14. 根据权利要求12所述的显示面板，其中：
    所述第一裂纹检测线和所述第二裂纹检测线的长度大致相等。
  15. 根据权利要求1所述的显示面板，其中：所述连接线的材料包括铜。
  16. 根据权利要求1-15任一项所述的显示面板，其中：
    所述显示面板为有机发光显示面板；
    所述显示基板还包括封装层，所述封装层曝露出所述第一邦定部的所述多个第一引脚和所述第二邦定部的所述多个第二引脚。
  17. 一种显示装置，包括根据权利要求1-16任一项所述的显示面板。
PCT/CN2020/084678 2020-04-14 2020-04-14 显示面板及显示装置 WO2021207924A1 (zh)

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US17/265,293 US12016217B2 (en) 2020-04-14 2020-04-14 Display panel and display device including crack detection line electrically connecting first and second pins
DE112020005544.2T DE112020005544T5 (de) 2020-04-14 2020-04-14 Anzeigefeld und Anzeigegerät
US18/488,449 US20240049538A1 (en) 2020-04-14 2023-10-17 Display panel and display device

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102601650B1 (ko) * 2016-07-26 2023-11-13 삼성디스플레이 주식회사 표시 장치
KR20220075071A (ko) * 2020-11-27 2022-06-07 삼성디스플레이 주식회사 표시 장치 및 이의 불량 검사 방법
CN115023030A (zh) * 2022-07-21 2022-09-06 珠海格力智能装备有限公司 印制电路板、印制电路板的检测方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203324610U (zh) * 2013-07-25 2013-12-04 京东方科技集团股份有限公司 显示装置
CN108154800A (zh) * 2016-12-05 2018-06-12 三星显示有限公司 显示装置
CN108922909A (zh) * 2018-07-26 2018-11-30 京东方科技集团股份有限公司 一种阵列基板、显示面板以及显示装置
CN109256045A (zh) * 2017-07-12 2019-01-22 三星显示有限公司 显示装置
CN109375399A (zh) * 2014-08-30 2019-02-22 乐金显示有限公司 显示装置
CN109427273A (zh) * 2017-08-21 2019-03-05 三星显示有限公司 显示装置
WO2019235823A1 (ko) * 2018-06-07 2019-12-12 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN110634411A (zh) * 2019-11-07 2019-12-31 京东方科技集团股份有限公司 一种显示模组及其封装检测方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070111717A (ko) 2006-05-18 2007-11-22 삼성전자주식회사 전도성 라인을 포함하는 평판 표시 장치 모기판 및 이의제조방법
US9252375B2 (en) * 2013-03-15 2016-02-02 LuxVue Technology Corporation Method of fabricating a light emitting diode display with integrated defect detection test
KR102402084B1 (ko) 2017-08-24 2022-05-25 삼성디스플레이 주식회사 표시 장치
KR102328314B1 (ko) * 2017-09-15 2021-11-17 엘지디스플레이 주식회사 전계 발광 표시 장치 및 전계 발광 표시 장치용 드라이버 ic 필름부
CN107742477B (zh) * 2017-11-29 2021-06-08 上海天马微电子有限公司 一种柔性显示基板、柔性显示面板和柔性显示装置
CN108762562B (zh) 2018-05-25 2020-12-01 京东方科技集团股份有限公司 一种显示基板、显示面板、触控显示装置及其制作方法
CN109739386B (zh) 2019-01-08 2021-10-15 京东方科技集团股份有限公司 触控传感器、触控模组及触控传感器裂纹检测方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203324610U (zh) * 2013-07-25 2013-12-04 京东方科技集团股份有限公司 显示装置
CN109375399A (zh) * 2014-08-30 2019-02-22 乐金显示有限公司 显示装置
CN108154800A (zh) * 2016-12-05 2018-06-12 三星显示有限公司 显示装置
CN109256045A (zh) * 2017-07-12 2019-01-22 三星显示有限公司 显示装置
CN109427273A (zh) * 2017-08-21 2019-03-05 三星显示有限公司 显示装置
WO2019235823A1 (ko) * 2018-06-07 2019-12-12 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN108922909A (zh) * 2018-07-26 2018-11-30 京东方科技集团股份有限公司 一种阵列基板、显示面板以及显示装置
CN110634411A (zh) * 2019-11-07 2019-12-31 京东方科技集团股份有限公司 一种显示模组及其封装检测方法

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