WO2021219254A1 - Composant électronique à surfaces de contact - Google Patents

Composant électronique à surfaces de contact Download PDF

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Publication number
WO2021219254A1
WO2021219254A1 PCT/EP2021/050837 EP2021050837W WO2021219254A1 WO 2021219254 A1 WO2021219254 A1 WO 2021219254A1 EP 2021050837 W EP2021050837 W EP 2021050837W WO 2021219254 A1 WO2021219254 A1 WO 2021219254A1
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WO
WIPO (PCT)
Prior art keywords
electronic
component
contact
electronic component
contact surfaces
Prior art date
Application number
PCT/EP2021/050837
Other languages
German (de)
English (en)
Inventor
Thomas Feichtinger
Original Assignee
Tdk Electronics Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Electronics Ag filed Critical Tdk Electronics Ag
Publication of WO2021219254A1 publication Critical patent/WO2021219254A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Definitions

  • the invention relates to an electronic component with a base body, a top surface and at least one side surface.
  • the base body comprises a semiconductor material and an electronic structure is applied to the top surface.
  • a reduction in the size of electrical contact areas is inevitably associated with a decrease in contact reliability.
  • a denser arrangement of conductive structures leads to undesired voltage flashovers and an increase in parasitic capacitances.
  • the object of the present invention is therefore to provide an electronic component which enables further miniaturization without the problems mentioned occurring.
  • An electronic component which has a base body, a top surface and at least one side surface.
  • the main body of the electronic Component comprises a semiconductor material.
  • An electronic structure is applied to the top surface.
  • a contact surface that is adjacent to the electronic structure extends over a section of the top surface and an adjacent side surface.
  • the electronic structure here comprises two electrical conductors that are separated from one another by a resistance component.
  • the electrical conductors are designed in the form of two intermeshing electrode combs.
  • Two contact surfaces each of which adjoins one of the electrical conductors of the electronic structure, each extend over a section of the top surface and a respective adjacent side surface.
  • the contact surfaces are connected to the electronic structure in an electrically conductive manner.
  • the respective contact surface By extending any of the contact surfaces to an adjacent side surface, the respective contact surface can be made so large that reliable contact can be ensured. With the same size of the electronic component, the respective contact surface can be enlarged. With a further miniaturization of the electronic component, the size of the respective contact surface can nevertheless be maintained.
  • the coverage of the top surface by the contact surfaces can be reduced. Even with a reduction in the coverage of the top surface by the contact surfaces each of the contact areas can be enlarged compared to the mere arrangement on the top surface.
  • the contact surfaces On a top surface, on which the contact surfaces cover a smaller proportion by extending to the side surfaces, there is more space for electronic structures. With the same size of the electronic component, the area occupied by the electronic structure on the upper side surface can be increased. In the case of a further miniaturization of the electronic component, the surface of the electronic structure can be retained by the arrangement described in that the contact surfaces are partially shifted onto the side surfaces.
  • the main body of the electronic component comprises a semiconductor material.
  • the semi-material can be one or more of the elements silicon (Si), germanium (Ge), gallium (Ga), boron (B), indium (In), selenium (Se), tellurium (Te) and their compounds such as gallium arsenide, indium antimonide , Gallium nitride, indium nitride, silicon germanium, etc. include.
  • the electronic component has a cuboid shape.
  • the electronic component thus comprises the top surface, four side surfaces adjoining the top surface and oriented normally with respect to this, and a bottom surface opposite the top surface.
  • an exemplary contact surface extends over a section of the rectangular top surface that extends as far as a first of the four edges of the top surface.
  • the exemplary contact surface also extends over a section of this side surface, which adjoins the top surface at the first edge and is normal to this.
  • the exemplary contact surface here forms a cohesive surface that is continued over the first edge without interruption.
  • At least one of the contact surfaces extends over a portion of the top surface, an adjacent side surface and the bottom surface.
  • the contact surface can be further enlarged by the additional extension of the contact surface onto the underside surface.
  • a contact surface that extends over several sides of the component enables flexible contacting of the component in different directions.
  • the electronic component comprises two contact surfaces which are arranged on opposite sides of the electronic structure, adjoin them and each extend over a section of the upper side surface and the respectively adjoining side surface.
  • Such an arrangement enables the electronic component or the electronic structure to be contacted from two opposite sides.
  • the electronic structure therefore lies between the two contact surfaces, the two contact surfaces not being in direct contact with one another.
  • the electronic component can thus be integrated into a circuit.
  • the component can represent a functional element within the circuit.
  • the electronic structure includes the resistance component.
  • the resistive component comprises a dielectric material.
  • Resistance components can be electrically conductive structures.
  • the resistance component is arranged such that during normal operation or with normal voltage applied to the contact surfaces, no electrical current flow occurs from a first contact surface to an opposite, second contact surface.
  • a sufficiently large area for the electronic structure is available on the upper side surface of the electronic component according to the invention, so that the shape and dimensions of the resistance component can be designed flexibly in accordance with the technical requirements.
  • the first contact area, the second contact area and the electronic structure lying in between, including the resistance component form a protective element against electrostatic discharge (English: Electro-static discharge, ESD protective element).
  • the resistance component can comprise a semiconductor diode, a thyristor or a transistor.
  • the electronic structure also includes two electrical conductors that are in contact with the contact surfaces and through the resistance components are separated from each other.
  • a semiconductor diode, a transistor or a thyristor is arranged as part of the resistance component between the electrical conductors.
  • the resistance component can also comprise an integrated circuit which has a plurality of diodes, transistors and / or thyristors.
  • the electrical conductors can have complex structures and, in at least one embodiment, are designed in the form of two intermeshing electrode combs.
  • the electrical resistance between the electrical conductors can be increased.
  • the relationship between the mutual distance between the electrical conductors and the electrical resistance is approximately linear.
  • the electronic structure If, according to the invention, a sufficiently large area is available for the electronic structure, this enables electrical conductors with opposite polarity, such as, for example, interlocking electrode combs, to be arranged with a greater mutual spacing.
  • the maximum voltage level absorbed by the ESD protective element can thus be increased or, in the case of further miniaturization of the components, maintained.
  • the value of the voltage level increases approximately linearly to increase the distance between the electrode combs.
  • a sufficiently large area of the electronic structure also offers further advantages.
  • a sufficiently large area is available for the electronic structure, so that desired or technical required complex structures of the electrical conductor and the resistance component, for example in the form of an integrated circuit of several transistors, thyristors and / or diodes, can be realized.
  • an electrical conductor of the electronic structure has, for example, a fine structure.
  • the individual conductor tracks of the fine structuring can then be arranged on a comparatively large area, so that there are sufficiently large distances between the individual conductor tracks. This leads, among other things, to a decrease in parasitic capacitances and to the avoidance of unwanted voltage flashovers.
  • a sufficiently large area of the electronic structure enables flexible design of the conductor tracks, which can thus be adapted as advantageously as possible to the technical conditions.
  • the electronic component is a TVS (Transient Voltage Suppressor) protection component.
  • a TVS protective component can comprise the ESD protective element described.
  • the TVS protective component can also include further elements and electronic components such as electronic filters, capacitors, resonant circuits, electrical resistors, diodes, thyristors, etc.
  • the electronic component comprises a plurality of electronic structures, each with adjacent contact areas.
  • Each of the electronic structures can be contacted, for example, with two contact surfaces on opposite sides of the respective electronic Adjacent structure.
  • the component can, for example, comprise several electronic structures connected in parallel, which are arranged next to one another on the component and are not in contact.
  • the electronic component comprises four contact surfaces which adjoin the electronic structure on four different sides and each extend over the top surface and the respective adjoining side surface.
  • each of the four contact surfaces extends onto a different one of the four side surfaces of the cuboid. Two of the four contact surfaces are therefore opposite each other. In one embodiment, all four contact surfaces are shaped identically and have the same size.
  • the four contact surfaces extend from the top surface over the respective side surface to the bottom surface. In this way, the available contact surface can be further enlarged and the electronic component can be contacted from different sides.
  • the component can furthermore comprise several electronic structures, each of the four contact surfaces also being able to be in contact with several of the electronic structures.
  • the component can comprise any number of electronic structures and adjacent contact areas.
  • a polymer layer is applied between at least a section of a contact area and a surface of the base body.
  • the section of the contact surface comprises at least one edge between the top surface and the side surface within the contact surface.
  • the polymer layer can be applied between the entire surface of a contact surface and the corresponding surface of the base body.
  • the polymer layer can be applied between all contact areas on the corresponding surfaces of the base body.
  • the polymer layer comprises a polyimide plastic.
  • the described polymer layer has the advantage that the stress on the contact surfaces, in particular on the edges between the top surface and the side surface, can be alleviated during a later soldering process for making electrical contact with the contact surfaces.
  • the invention further comprises a method for producing an electronic component with the following steps:
  • Provision of a wafer comprising a semiconductor material and a multiplicity of electronic structures arranged in a checkerboard grid.
  • a main body of the wafer comprises a semiconductor material.
  • the semi-material can be one or more of the elements silicon (Si), germanium (Ge), gallium (Ga), boron (B), indium (In), Selenium (Se), Tellurium (Te) and their compounds such as gallium arsenide, indium antimonide,
  • Gallium nitride, indium nitride, silicon germanium, etc. include.
  • the electronic structures are arranged on a first surface of the wafer.
  • the structures can include electronic components such as electrical resistors, diodes, thyristors, electronic filters, capacitors, resonant circuits, etc.
  • the checkerboard-like arrangement of the electronic structures on the first surface of the wafer simplifies later separation of the wafer into dies.
  • the main body of the wafer thus has a greater thickness than the isolated dies. In this way, the side surfaces of the later dies can already be completely exposed without the wafer being separated into the dies. This enables simple parallel processing of the dies in the following.
  • contact areas adjacent to the electronic structures so that the contact areas each extend over a section of the first surface and the respectively adjacent side area.
  • a sufficiently large surface for the contacting of the dies to the outside can be ensured. Since some of the contact areas are applied to the side surface, the extent of the contact areas on the first surface can furthermore be reduced, so that more space remains for the electronic structures.
  • the wafer Due to the cohesive substrate layer, the wafer has a greater thickness than the isolated dies. In addition, this substrate layer connects the dies. After the contiguous substrate layer has been removed by the described grinding, the dies are thus isolated. Each die comprises at least one electronic structure and a contact area adjacent to the structure.
  • each die comprises at least one electronic structure and at least two contact surfaces adjoining the structure, so that the die can be integrated into an electrical circuit.
  • a further section of the contact surface which is related to the section of the contact surface on the side surface of a die, is formed on an underside surface of the die.
  • the bottom surface is opposite to the first surface, which corresponds to a top surface of the die.
  • a seed layer which covers at least one portion of the first surface adjoining the respective electronic structure and a portion of the respective adjoining side surface.
  • the seed layer covers at least the area in which the contact area is to be formed later.
  • the seed layer can be applied over the entire area, that is to say, for example, cover an area of any size on the first surface and the adjoining side surfaces.
  • Several contact surfaces can be formed from a coherent seed layer.
  • a photo mask can then be applied and structured.
  • the photomask is structured in such a way that it covers sections of the first surface on which no contact areas are applied. After the photomask has been applied, only that part of the seed layer is exposed on which the contact surfaces will be applied in a later process step.
  • the pre-structured photomask allows the conductive metal to be easily applied to the desired exposed portion of the seed layer so that the contact areas are formed.
  • the contact surfaces can extend at least over the first surface and the side surfaces and additionally over the underside surface.
  • contact layers can be applied analogously to the steps above the underside surface are applied, which are in contact with contact layers on the side surfaces.
  • FIG. 1 shows a perspective view of a first embodiment of an electronic component according to the invention.
  • Figure 2 shows a detailed view of a top surface of the first embodiment of the component.
  • Figure 3 shows a perspective view of a
  • FIG. 4 shows a perspective view of a second embodiment of the electronic component with a plurality of electronic structures.
  • FIG. 5 shows a perspective view of a third embodiment of the electronic component with contact surfaces on four side surfaces.
  • FIGS. 6A, 6B, 6C, 6D, 6E and 6F schematically show different method stages of a method for producing an embodiment of the electronic component.
  • FIG. 1 shows a first embodiment of an electronic component 10 according to the invention.
  • the component 10 of the first embodiment is a die that was separated from a wafer.
  • the component 10 has a cuboid shape with a rectangular base area.
  • the component 10 comprises a base body 1 which comprises a semiconductor material.
  • the semiconductor material is silicon, for example.
  • the cuboid component 10 further comprises an upper side surface 2, a lower side surface 3 and four side surfaces 4, which are arranged between the upper side surface and the lower side surface and are normal to these.
  • the component 10 is a miniaturized component, the top surface 2 of which in the present embodiment has dimensions of a maximum of 400 ⁇ m ⁇ 200 ⁇ m.
  • the thickness of the component normal to the top surface is a maximum of 150 ⁇ m.
  • An electronic structure 5 is applied to the top surface 2.
  • the electronic structure 5 occupies a delimited section of the top surface 2.
  • the electronic structure 5 adjoins contact surfaces 6 on two opposite sides Contact surfaces 6 enable contact to be made between the electronic structure 5 and an external circuit, not shown.
  • the first contact surface 6A which adjoins and is contacted with a first side of the electronic structure 5, extends over a section on the top surface 2 of the electronic component and a section connected therewith on a first side surface 4A of the electronic component.
  • the second contact surface 6B which adjoins a second side of the electronic structure 5, which is opposite the first side, and is contacted with this, extends over a second section on the upper side surface 2 of the electronic component. Furthermore, the contact surface 6B extends over a side surface 4C which lies opposite the first side surface 4A.
  • the distance between the side surfaces 4A and 4C is a maximum of 400 ⁇ m in the present embodiment.
  • the distance between the side surfaces 4B and 4D aligned normal to the side surfaces 4A and 4C is a maximum of 200 ⁇ m in the present embodiment.
  • the contact surfaces 6 each form a continuous surface which extends over the top surface 2 and side surface 4.
  • a contact surface 6 comprises two contact layers which are at right angles to one another so that they form an L-shape.
  • the contact surface consists of a conductive metal such as nickel, copper, silver or gold or an alloy of the elements mentioned.
  • the present electronic component 10 functions as a TVS protective component.
  • the component 10 can be designed like the ESD protection assembly shown in FIG. This here comprises the two contact surfaces 6A and 6B and the electronic structure 5.
  • the electronic structure 5 comprises a resistance component 51 which is arranged between two electrical conductor structures 52A and 52B.
  • a first electrical conductor structure 52A is in electrical contact with the first contact area 6A and a second electrical conductor structure 52B is in electrical contact with the second contact area 6B.
  • the electrical conductor structures 52 are designed as interlocking electrode combs.
  • the resistance component 51 forms an electronic functional element with the two electrical conductor structures 52.
  • the resistance component 51 is, for example, a thyristor, a transistor or a semiconductor diode or an integrated circuit which combines one or more of the components mentioned.
  • the resistance component 51 comprises a semiconducting material.
  • the protective assembly can, however, also take the form of a semiconductor component, e.g. a diode or transistor, in another form.
  • a semiconductor junction can serve as a blocking element.
  • FIG. 3 shows an embodiment of an electronic component 20 according to the prior art.
  • the base body of the component 20 has the same geometry and the same dimensions as the component 10 according to the invention.
  • the two contact surfaces 6 on the component 20 are applied exclusively to the top surface 2 of the component.
  • the contact surfaces 6 do not extend onto one of the side surfaces 4 of the component 20.
  • the contact areas 6 on the component 20 take up a larger proportion of the top surface 2 than in the case of the component 10. Therefore, less space remains for the electronic structure 5.
  • the electronic structure comprises the same elements as the electronic structure on the component 10. Accordingly, the advantages that can be achieved with the proposed component can already be clearly seen from a direct optical comparison of FIGS. 1 and 3.
  • the area of the electronic structure 5 on a component with the specified masses can be increased by more than 30% compared to a component 20 according to the prior art.
  • the area of the electronic structure 5 on the top surface 2 of the electronic component 10 is thus at least 0.064 mm 2 in the present embodiment.
  • Resistance component can be increased.
  • the relationship between the maximum voltage level and the distance between the opposing polarity conductors is approximately linear.
  • a component 10 has the advantage over a component 20 that external contact is also possible via the side surfaces 4A and 4C.
  • FIG. 4 shows a further embodiment of an electronic component 30.
  • the electronic component 30 has a cuboid shape with a rectangular outline.
  • Component 30 essentially corresponds to component 10. The differences between the components are explained below.
  • the surface side 2 of the component 30 has the shape of a rectangle with a long side and a short side.
  • the electronic component 30 has four electronic structures 5A to 5D.
  • the electronic structures are arranged parallel to one another along the long side on the upper side surface 2 of the electronic component 30.
  • the electronic structures 5 are not in direct contact with one another.
  • Each of the electronic structures 5A to 5D is contacted on two opposite sides by two contact surfaces 6 in each case.
  • the contact surfaces 6 are each on one side of the electronic structures 5, which is directed in the direction of the long side of the top surface 2, applied.
  • Each of the contact surfaces 6 extends over a portion of the top surface 2 and a portion of the side surface 4A or 4C adjoining it.
  • the side surfaces 4A and 4C are the long side surfaces of the component 30 which adjoin the long side of the top surface 2.
  • Each of the four electronic structures 5 includes the same electronic functional elements.
  • the contact surfaces 6 are not in direct contact with one another.
  • FIG. 5 shows a third embodiment of the electronic component 40.
  • the third embodiment is essentially the same as the second embodiment of the component 30.
  • the component 40 has three electronic structures 5 which, just as with the component 30, are arranged parallel to one another along a long side of the top surface 2.
  • the number of electronic structures 5 can be varied as desired in different embodiments.
  • Each of the electronic structures is in turn contacted to the outside with two opposite contact surfaces 6, which each extend over a section on the top surface 2 and one of the side surfaces 4A or 4C.
  • the side surfaces 4A and 4C are the long side surfaces of the component 30, which adjoin the long side of the top surface 2.
  • component 40 also includes a ground electrode 7, which electrically connects electronic structures 5A to 5C to one another.
  • the ground electrode 7 is applied centrally on the top surface 2 over its entire length.
  • the ground electrode 7 runs parallel to the long side of the top surface 2.
  • the ground electrode 7 comprises an electrically conductive material such as nickel, copper, silver, gold or an alloy of these elements.
  • the selected electrically conductive material is applied to the upper side surface 2, or to the electronic structures 5 located thereon, in order to enable continuous contacting from a first short edge 2A of the upper side surface 2 to a second short edge 2B of the upper side surface 2.
  • the short edges of the upper side surface 2 correspond to edges along the short side of the rectangular upper side surface 2.
  • the contact surfaces 6C and 6D thereof are applied to both ends of the ground electrode 7.
  • the contact surfaces 6C and 6D each extend over a section on the top surface 2 and one of the short side surfaces 4B or 4D.
  • the short side surfaces 4B and 4C are the side surfaces of the component 40 that adjoin the short side of the upper side surface 2.
  • FIGS. 6A, 6B, 6C, 6D, 6E and 6F schematically show an exemplary method for producing the electronic component 10.
  • a silicon wafer 100 is provided.
  • the wafer can alternatively also comprise another semiconductor material.
  • the silicon wafer 100 comprises electronic structures 5 arranged in a checkerboard grid on the top surface 2.
  • the electronic structures 5 are applied to the top surface 2, for example, using a Complementary Metal Oxide Semiconductor (CMOS) process.
  • CMOS Complementary Metal Oxide Semiconductor
  • step A The wafer is then sawed in step A along the dividing lines between the later individual dies, so that the side surfaces 4 of the individual dies 10 are completely exposed. However, these are still connected via the substrate layer 110.
  • the lower side 8 of the substrate layer 110 of the wafer 100 rests on a carrier film 9A.
  • step B or C a seed layer 60 is applied to the top surface 2 of the wafer 100 in a photolithographic process.
  • the seed layer 60 covers the entire top surface 2 including the surfaces of the trenches 20 created by the sawing, which encompass the side surfaces 4 of the individual dies 10.
  • step C a photo mask 61 is applied and structured, the desired sections of the Top surface 2, on which no contact surfaces will be formed later, covers.
  • the exposed part of the seed layer 60 now exclusively comprises sections which correspond to the later contact surfaces 6.
  • the sections directly adjoin the electronic structures 5 and each extend over a section that extends from the top surface 2 to the later side surfaces 4 of the dies 10.
  • an electrically conductive material such as nickel, copper, silver or gold or an alloy of these elements can now be applied to the exposed part of the seed layer 60 in order to form the contact surfaces 6.
  • step D the photomask 61 and the underlying seed layer 60 are then removed from the top surface 2 of the component.
  • the electrically conductive material can be applied using another suitable method such as CVD or sputtering.
  • each electronic structure 5 is contacted with two contact surfaces 6 each, which adjoin the electronic structure 5 on opposite sides and each extend over a section on the top surface 2 and an adjoining side surface 4.
  • a subsequent step E the carrier film 9A is detached from the underside 8 of the substrate layer 110 and instead, a new carrier film 9B is applied to the surface side 2 of the wafer.
  • the substrate layer 110 is then ground down to the lower surface side 3 of the dies in order to separate the individual dies 10 of the wafer 100.
  • the carrier film 9B can be removed in step F.
  • the dies 10 produced can be subjected to an optical and electrical quality control.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un composant électronique (10) ayant un corps principal (1), une surface supérieure (2) et au moins une surface latérale (4), le corps principal (1) comprenant un matériau semi-conducteur, - une structure électronique (5) étant montée sur la surface supérieure (2), la structure électronique comprenant deux conducteurs électriques, qui sont séparés les uns des autres par un composant de résistance et les conducteurs électriques étant conçus sous la forme de deux peignes d'électrodes s'engrenant l'un dans l'autre, - deux surfaces de contact (6) s'étendant chacun à proximité de l'un des conducteurs électriques de la structure électronique (5) et sur une partie de la surface supérieure (2) et d'une surface latérale adjacente (4) dans chaque cas.
PCT/EP2021/050837 2020-04-27 2021-01-15 Composant électronique à surfaces de contact WO2021219254A1 (fr)

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DE102020111424.9 2020-04-27
DE102020111424 2020-04-27

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502329A (en) * 1992-01-31 1996-03-26 Sgs-Thomson Microelectronics S.A. Protection component for automobile circuit
DE19707887A1 (de) 1997-02-27 1998-09-10 Micronas Semiconductor Holding Verfahren zum Herstellen von elektronischen Elementen
DE102005004160A1 (de) 2005-01-28 2006-08-10 Infineon Technologies Ag Halbleiterbaustein und Verfahren zum Herstellen desselben
US20110089557A1 (en) 2009-10-19 2011-04-21 Jeng-Jye Shau Area reduction for die-scale surface mount package chips
US20150243612A1 (en) * 2014-01-08 2015-08-27 Rohm Co., Ltd. Chip parts and method for manufacturing the same, circuit assembly having the chip parts and electronic device
DE112017004775T5 (de) * 2016-09-23 2019-06-19 Tdk Corporation Elektronisches bauelement und elektronische bauelementevorrichtung

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502329A (en) * 1992-01-31 1996-03-26 Sgs-Thomson Microelectronics S.A. Protection component for automobile circuit
DE19707887A1 (de) 1997-02-27 1998-09-10 Micronas Semiconductor Holding Verfahren zum Herstellen von elektronischen Elementen
DE102005004160A1 (de) 2005-01-28 2006-08-10 Infineon Technologies Ag Halbleiterbaustein und Verfahren zum Herstellen desselben
US20110089557A1 (en) 2009-10-19 2011-04-21 Jeng-Jye Shau Area reduction for die-scale surface mount package chips
US20150243612A1 (en) * 2014-01-08 2015-08-27 Rohm Co., Ltd. Chip parts and method for manufacturing the same, circuit assembly having the chip parts and electronic device
DE112017004775T5 (de) * 2016-09-23 2019-06-19 Tdk Corporation Elektronisches bauelement und elektronische bauelementevorrichtung

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