WO2021217302A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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WO2021217302A1
WO2021217302A1 PCT/CN2020/087040 CN2020087040W WO2021217302A1 WO 2021217302 A1 WO2021217302 A1 WO 2021217302A1 CN 2020087040 W CN2020087040 W CN 2020087040W WO 2021217302 A1 WO2021217302 A1 WO 2021217302A1
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substrate
layer
semiconductor structure
metal nitride
manufacturing
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PCT/CN2020/087040
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English (en)
French (fr)
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程凯
张丽旸
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苏州晶湛半导体有限公司
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Priority to US17/616,170 priority Critical patent/US20220246424A1/en
Priority to CN202080092801.9A priority patent/CN115428120A/zh
Priority to PCT/CN2020/087040 priority patent/WO2021217302A1/zh
Priority to TW110112470A priority patent/TWI832042B/zh
Publication of WO2021217302A1 publication Critical patent/WO2021217302A1/zh

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Definitions

  • the present invention relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure and a semiconductor structure.
  • GaN As a wide bandgap semiconductor material, GaN has a wide range of application prospects, but the preparation of high-quality GaN epitaxial layers is quite difficult.
  • a GaN epitaxial layer is prepared on a commonly used Si substrate. Since Ga and Si substrates have a melting reaction at high temperatures and destroy the epitaxial layer, it is necessary to prepare a metal nitride layer of a certain thickness, such as an AlN layer, but the AlN layer and the There is a huge lattice mismatch between Si substrates, and the surface mobility of Al atoms is low. How to achieve a high-quality AlN epitaxial layer on the Si substrate is very important for the crystal quality of the subsequent epitaxial layer.
  • the invention provides a method for manufacturing a high-quality semiconductor structure and a semiconductor structure.
  • the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming an amorphous layer on the substrate, the amorphous layer including a plurality of patterns, so that part of the substrate is exposed; Forming a metal nitride layer on top; removing the amorphous layer, forming a plurality of cavities between the substrate and the metal nitride layer; removing the substrate.
  • the step of forming a metal nitride layer on the amorphous layer includes: forming a metal nitride film layer on the amorphous layer; and converting the polycrystalline film layer of the metal nitride film layer into a single crystal The film layer forms the metal nitride layer; wherein the metal nitride film layer includes a single crystal film layer in contact with the substrate and a polycrystalline film layer in contact with the amorphous layer.
  • the polycrystalline film layer is converted into a single crystal film layer through an annealing process.
  • the amorphous layer is removed by an etching process.
  • the amorphous layer is separated from the substrate and the metal nitride layer in a lateral direction after etching, and the lateral direction is perpendicular to the arrangement direction of the substrate and the metal nitride layer.
  • the graphic is a convex graphic
  • the orthographic projection of the graphic on the substrate is a rectangle, a triangle, a polygon, or a circle.
  • the material of the amorphous layer includes SiO2.
  • the substrate is a single crystal substrate
  • the single crystal substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate.
  • the material of the metal nitride layer includes AlN-based material.
  • the present invention also provides a semiconductor structure, including a plurality of main body parts and a plurality of supporting parts, the supporting parts connect two adjacent main body parts, and the main body part and the two adjacent supporting parts enclose a cavity.
  • the amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer , Improve the performance of the semiconductor structure.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a semiconductor structure of the present invention.
  • Fig. 2 is a schematic diagram of forming an amorphous layer on a substrate in the manufacturing method shown in Fig. 1.
  • FIG. 3 is a schematic diagram of forming a metal nitride layer on an amorphous layer in the manufacturing method shown in FIG. 1.
  • FIG. 4 is a schematic diagram of the structure of the manufacturing method shown in FIG. 1 with the amorphous layer removed.
  • FIG. 5 is a schematic structural diagram of a semiconductor structure manufactured by the manufacturing method shown in FIG. 1.
  • the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming an amorphous layer on the substrate, the amorphous layer including a plurality of patterns; and forming a metal nitride layer on the amorphous layer ; Remove the amorphous layer, a plurality of cavities are formed between the substrate and the metal nitride layer.
  • this embodiment provides a manufacturing method of a semiconductor structure, the manufacturing method includes:
  • Step S10 Provide the substrate 1.
  • Step S20 forming an amorphous layer 2 on the substrate 1, the amorphous layer 2 including a plurality of patterns 21, so that part of the substrate is exposed;
  • Step S30 forming a metal nitride layer 3 on the amorphous layer 2.
  • Step S40 Remove the amorphous layer 2, a plurality of cavities 30 are formed between the substrate 1 and the metal nitride layer 3, and the cavities 30 correspond to those occupied by the pattern 21 in step S20 Space.
  • Step S50 Remove the substrate 1.
  • the step S20 includes: first forming an amorphous film layer on the substrate 1, and then patterning the amorphous film layer to form the pattern 21, and forming a recess 22 between adjacent patterns 21.
  • the patterning process is, for example, a photolithography process.
  • the projection of the pattern 21 on the substrate 1 may be a rectangle, a triangle, a polygon (which can be understood as a pentagon and a closed pattern with more sides) or a circle.
  • the pattern 21 can suppress slippage or dislocations of the metal nitride layer 3 during growth, thereby reducing the dislocation density, thereby improving the quality of the metal nitride layer 3.
  • the pattern 21 is a convex pattern, that is, the pattern 21 is formed by extending upward; in other embodiments, a plurality of upward notches are formed on the substrate 1, and the pattern 21 is formed in the notch. At this time, the pattern 21 Corresponds to a concave pattern.
  • the step S30 includes: forming a metal nitride film layer on the amorphous layer 2, and the metal nitride film layer has a portion directly in contact with the substrate 1 (that is, located in the recess 22). ) Is a single crystal film layer, and the one directly in contact with the amorphous layer 2 is a polycrystalline film layer; the polycrystalline film layer of the metal nitride film layer is converted into a single crystal film layer to form the metal nitride layer.
  • the single crystal structure can be conducted to the polycrystalline structure part through the annealing process, so that the polycrystalline structure gradually becomes a single crystal structure, that is to say, the metal nitride film layer is finally all It becomes a single crystal structure.
  • the patterned amorphous layer 2 combined with the annealing process, a high-quality single crystal metal nitride film can be obtained.
  • the amorphous layer 2 is removed by an etching process, and the amorphous layer 2 is detached from the substrate 1 and the metal nitride layer 3 in the lateral direction after etching, thus The metal nitride layer will not be damaged during the etching process.
  • the lateral direction is perpendicular to the arrangement direction of the substrate 1 and the metal nitride layer 3.
  • step S50 the substrate 1 is removed by a lift-off technology. Since the step of removing the substrate 1 is after the step of removing the amorphous layer 2, when the substrate 1 removes the amorphous layer 2, it can still support the metal nitride layer 3 well, and prevent the metal nitride layer 3 from being Deformation occurs during this step.
  • the substrate 1 is a single crystal substrate, and the single crystal substrate may be a sapphire substrate, a silicon substrate or a silicon carbide substrate; the material of the amorphous layer 2 includes silicon oxide such as SiO2.
  • the material of the metal nitride layer 3 includes an AlN-based material. In this embodiment, an AlN-based material is selected.
  • the AlN-based material can be AlN, AlGaN, InAlN, ScAlN, and other materials.
  • the semiconductor structure (actually, the metal nitride layer 3) manufactured by the manufacturing method described in any one of the foregoing embodiments, the semiconductor structure 3 includes a plurality of body portions 31 and a plurality of support portions 32, so The supporting portion 32 connects two adjacent main body portions 31, and the main body portion 31 and the supporting portion 32 are at least partially staggered, so that the main body portion 31 and the two adjacent supporting portions 32 enclose a cavity 30.
  • one side of the cavity 30 is open.
  • the figure only illustrates a part of the semiconductor structure, which results in the cavities on both sides being different from the cavity in the middle, and the actual structure is the same.
  • the semiconductor structure 3 can be self-supporting.
  • Self-supporting can be understood as: being able to maintain its own shape without causing defects during processing.
  • the metal nitride layer of the semiconductor structure has a low dislocation density and a high quality, which is conducive to further production of a high-quality GaN structure.
  • the present invention also provides a resonator, which includes the semiconductor structure described in any one of the foregoing embodiments.
  • the resonator needs to form a cavity structure on its substrate, and the semiconductor structure manufactured by the aforementioned manufacturing method has a plurality of cavities 30.
  • the cavities 30 can replace the cavity structure of the substrate, so the semiconductor structure can be directly used.
  • To manufacture the resonator there is no need to form a cavity on the substrate of the resonator through other processes, which is beneficial to simplify the manufacturing process and reduce the manufacturing cost.
  • the semiconductor structure can also be used to make LED chips.
  • the amorphous layer can suppress slip or dislocations during epitaxial growth, thereby improving the quality of the metal nitride layer.
  • the performance of the semiconductor structure is improved, and the metal nitride layer can be self-supporting.
  • the semiconductor structure can be directly used to fabricate the resonator, which is beneficial to simplify the fabrication process of the resonator.

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Abstract

一种半导体结构的制作方法及半导体结构，所述制作方法包括：提供衬底（1）；在所述衬底（1）上形成无定形层（2），所述无定形层（2）包括多个图形（21），使部分衬底（1）暴露；在所述无定形层（2）上形成金属氮化物层（3）；去除所述无定形层（2），所述衬底（1）与所述金属氮化物层（3）之间形成多个空腔（30）；去除所述衬底（1）。在衬底（1）上形成无定形层（2），并在无定形层（2）上形成金属氮化物层（3），无定形层（2）可抑制外延生长时产生滑移或位错，从而提高金属氮化物层（3）的质量，改善半导体结构的性能，同时金属氮化物层（3）实现自支撑。

Description

半导体结构的制作方法及半导体结构 技术领域
本发明涉及半导体领域，尤其涉及一种半导体结构的制作方法及半导体结构。
背景技术
GaN作为宽禁带半导体材料，具有广泛的应用前景，但是高质量的GaN外延层的制备有相当难度。例如在常用的Si衬底上制备GaN外延层，由于Ga和Si衬底在高温下存在回熔反应，破坏外延层，需要先制备一定厚度的金属氮化物层，例如AlN层，但是AlN层与Si衬底之间存在巨大的晶格失配，并且Al原子的表面迁移率低，如何在Si衬底上实现高质量的AlN外延层对后续外延层的晶体质量至关重要。
发明内容
本发明提供一种高质量的半导体结构的制作方法及半导体结构。
本发明提供一种半导体结构的制作方法，包括：提供衬底；在所述衬底上形成无定形层，所述无定形层包括多个图形，使部分衬底暴露；在所述无定形层上形成金属氮化物层；去除所述无定形层，所述衬底与所述金属氮化物层之间形成多个空腔；去除所述衬底。
进一步的，在所述无定形层上形成金属氮化物层的步骤包括：在所述无定形层上形成金属氮化物膜层；将所述金属氮化物膜层的多晶膜层转化为单晶膜层，形成所述金属氮化物层；其中，所述金属氮化物膜层包括与所述 衬底接触的单晶膜层及与无定形层接触的多晶膜层。
进一步的，通过退火工艺将所述多晶膜层转化为单晶膜层。
进一步的，所述无定形层通过刻蚀工艺去除。
进一步的，所述无定形层在刻蚀后沿横向与衬底及所述金属氮化物层脱离，所述横向垂直于所述衬底与所述金属氮化物层的排列方向。
进一步的，所述图形为凸起图形，所述图形在所述衬底上的正投影为矩形、三角形、多边形或圆形。
进一步的，所述无定形层的材质包括SiO2。
进一步的，所述衬底为单晶衬底，所述单晶衬底为蓝宝石衬底、硅衬底或碳化硅衬底。
进一步的，所述金属氮化物层的材质包括AlN基材料。
本发明还提供一种半导体结构，包括多个主体部及多个支撑部，所述支撑部连接相邻的两个主体部，所述主体部与相邻的两个支撑部围成空腔。
本发明中，通过在衬底上形成无定形层，并在无定形层上形成金属氮化物层层，无定形层可抑制外延生长时产生滑移或位错，从而提高金属氮化物层的质量，改善半导体结构的性能。
附图说明
图1是本发明半导体结构的制作方法的一个实施方式的流程示意图。
图2是图1所示的制作方法中在衬底上形成无定形层的示意图。
图3是图1所示的制作方法中在无定形层上形成金属氮化物层的示意图。
图4是图1所示的制作方法中去除对无定形层的结构示意图。
图5是通过图1所示的制作方法制作的半导体结构的结构示意图。
具体实施方式
这里将详细地对示例性实施方式进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置的例子。
在本发明使用的术语是仅仅出于描述特定实施方式的目的，而非旨在限制本发明。除非另作定义，本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明说明书以及权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。除非另行指出，“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本发明说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本发明提供一种半导体结构的制作方法，包括：提供衬底；在所述衬底上形成无定形层，所述无定形层包括多个图形；在所述无定形层上形成金 属氮化物层；去除所述无定形层，所述衬底与所述金属氮化物层之间形成多个空腔。
请结合图1至图5，本实施方式提供一种半导体结构的制作方法，所述制作方法包括：
步骤S10：提供衬底1。
步骤S20：在所述衬底1上形成无定形层2，所述无定形层2包括多个图形21，使部分衬底暴露；
步骤S30：在所述无定形层2上形成金属氮化物层3。
步骤S40：去除所述无定形层2，所述衬底1与所述金属氮化物层3之间形成多个空腔30，所述空腔30对应的即是步骤S20中的图形21所占的空间。
步骤S50：去除所述衬底1。
可选的，所述步骤S20包括：首先在衬底1上形成无定形膜层，再对无定形膜层进行图形化处理以形成所述图形21，相邻的图形21之间形成凹陷22。所述图形化处理工艺例如为光刻工艺。所述图形21在所述衬底1上投影可以为矩形、三角形、多边形(可理解为五边形及具有更多边的封闭图形)或圆形。所述图形21可以抑制金属氮化物层3在生长时产生滑移或位错，从而减小位错密度，进而提高金属氮化物层3的质量。本实施方式中，所述图形21为凸起图形，即图形21向上延伸形成；在其他实施方式中，衬底1上形成朝上的多个缺口，图形21形成于缺口内，此时图形21对应为凹陷图形。
可选的，所述步骤S30包括：在所述无定形层2上形成金属氮化物膜层，所述金属氮化物膜层，与所述衬底1直接接触的部分(即位于凹陷部22内的)为单晶膜层，与无定形层2直接接触的为多晶膜层；将所述金属氮化物膜层的多晶膜层转化为单晶膜层，形成所述金属氮化物层。由于金属氮化物膜层有部分为单晶，通过退火工艺可将所述单晶结构传导至多晶结构部分， 从而使多晶结构逐渐变为单晶结构，也就是说金属氮化物膜层最终全部变为单晶结构。通过图形化的无定形层2，并结合退火工艺就可以得到高质量的单晶金属氮化物薄膜。
可选的，在所述步骤S40中，所述无定形层2通过刻蚀工艺去除，且无定形层2在刻蚀后沿横向与衬底1及所述金属氮化物层3脱离，因而在蚀刻过程中不会损害金属氮化物层。所述横向垂直于所述衬底1与所述金属氮化物层3的排列方向。
可选的，在步骤S50中，通过剥离工艺(lift-off technology)去除所述衬底1。由于去除衬底1的步骤在去除无定形层2的步骤之后，因此衬底1在去除无定形层2时，仍能对金属氮化物层3进行很好的支撑，避免金属氮化物层3在该步骤中发生变形。
可选的，所述衬底1为单晶衬底，所述单晶衬底可以是蓝宝石衬底、硅衬底或碳化硅衬底；所述无定形层2的材质包括SiO2等硅氧化物；所述金属氮化物层3的材质包括AlN基材料，本实施方式中选择AlN基材料，AlN基材料可以是AlN、AlGaN、InAlN、ScAlN等材料。
请结合图5，通过前述任一实施方式所述的制作方法制作而成的半导体结构(实际即是金属氮化物层3)，半导体结构3包括多个主体部31及多个支撑部32，所述支撑部32连接相邻的两个主体部31，所述主体部31与所述支撑部32至少部分错开，以使主体部31与相邻的两个支撑部32围成空腔30。本实施方式中，所述空腔30一侧开放。图中仅示意出半导体结构的一部分，因而导致两侧的空腔与中间的空腔有所不同，实际结构均是相同的。所述半导体结构3能够实现自支撑，自支撑可理解为：能够保持自身的形状，在处理中不会产生不良。同时，所述半导体结构的金属氮化物层的位错密度较小，具有较高的质量，有利于进一步制作高质量的GaN结构。
另一方面，本发明还提供一种谐振器，其包括前述任一实施方式所述 的半导体结构。通常谐振器需要在其基底上形成空腔结构，而利用前述制作方法制作而成的半导体结构具有多个空腔30，空腔30可代替基底的空腔结构，因此所述半导体结构可直接用来制作谐振器，无需再通过其他工艺在谐振器的基底上形成空腔，从而有利于简化制作工艺，降低制作成本。
在其他实施方式中，所述半导体结构还可以用于制作LED芯片。
本发明中，通过在衬底上形成无定形层，并在无定形层上形成金属氮化物层，无定形层可抑制外延生长时产生滑移或位错，从而提高金属氮化物层的质量，改善半导体结构的性能，同时金属氮化物层能够实现自支撑。半导体结构可以直接用于制作谐振器，有利于简化谐振器的制作工艺。
以上所述仅是本发明的较佳实施方式而已，并非对本发明做任何形式上的限制，虽然本发明已以较佳实施方式揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施方式所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

  1. 一种半导体结构的制作方法，其特征在于，包括：
    提供衬底(1)；
    在所述衬底上形成无定形层(2)，所述无定形层(2)包括多个图形(21)，使部分衬底暴露；
    在所述无定形层(2)上形成金属氮化物层(3)；
    去除所述无定形层，所述衬底(1)与所述金属氮化物层(3)之间形成多个空腔；
    去除所述衬底(1)，形成半导体结构。
  2. 根据权利要求1所述的半导体结构的制作方法，其特征在于，在所述无定形层(2)上形成金属氮化物层(3)的步骤包括：
    在所述无定形层(2)上形成金属氮化物膜层，所述金属氮化物膜层包括与所述衬底(1)接触的单晶膜层及与无定形层(2)接触的多晶膜层；
    将所述多晶膜层转化为单晶膜层，形成所述金属氮化物层(3)。
  3. 根据权利要求2所述的半导体结构的制作方法，其特征在于，通过退火工艺将所述金属氮化物膜层的多晶膜层转化为单晶膜层。
  4. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述无定形层(2)通过刻蚀工艺去除。
  5. 根据权利要求4所述的半导体结构的制作方法，其特征在于，所述无定形层(2)在刻蚀后沿横向与衬底(1)及所述金属氮化物层(3)脱离，所述横向垂直于所述衬底(1)与所述金属氮化物层(3)的排列方向。
  6. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述图形(21)为凸起图形，所述图形(21)在所述衬底(1)上的正投影为矩形、三角形、多边形或圆形。
  7. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述无定形层(2)的材质包括SiO2。
  8. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述衬底(1)为单晶衬底，所述单晶衬底为蓝宝石衬底、硅衬底或碳化硅衬底。
  9. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述金属氮化物层(3)的材质包括AlN基材料。
  10. 一种半导体结构，其特征在于，所述半导体结构包括多个主体部(31)及多个支撑部(32)，所述支撑部(32)连接相邻的两个主体部(31)，所述主体部(31)与相邻的两个支撑部(32)围成空腔(30)。
PCT/CN2020/087040 2020-04-26 2020-04-26 半导体结构的制作方法及半导体结构 WO2021217302A1 (zh)

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