WO2022151045A1 - 半导体器件及其制作方法、终端设备 - Google Patents

半导体器件及其制作方法、终端设备 Download PDF

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WO2022151045A1
WO2022151045A1 PCT/CN2021/071483 CN2021071483W WO2022151045A1 WO 2022151045 A1 WO2022151045 A1 WO 2022151045A1 CN 2021071483 W CN2021071483 W CN 2021071483W WO 2022151045 A1 WO2022151045 A1 WO 2022151045A1
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nano
semiconductor device
layer
frustum
protrusion
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PCT/CN2021/071483
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English (en)
French (fr)
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申健
张浩东
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华为技术有限公司
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Priority to PCT/CN2021/071483 priority Critical patent/WO2022151045A1/zh
Priority to CN202180089289.7A priority patent/CN116745889A/zh
Publication of WO2022151045A1 publication Critical patent/WO2022151045A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor device, a method for manufacturing the same, and a terminal device.
  • Silicon (Si) substrates are widely used in current semiconductor devices due to their advantages such as low price, mature preparation process, and realization of large-scale wafer preparation.
  • nitride-based semiconductor devices such as GaN or AlN crystal devices
  • Si silicon
  • nitride-based semiconductor devices such as GaN or AlN crystal devices
  • Si silicon
  • nitride-based semiconductor devices such as GaN or AlN crystal devices
  • Si silicon
  • nitride film is grown on the bottom surface, a series of problems such as surface cracking of the nitride film, high dislocation density, wafer warpage, uneven thickness, and uneven doping in the active area of semiconductor devices are prone to occur, which will seriously affect the semiconductor The process and performance of the device.
  • Embodiments of the present application provide a semiconductor device, a method for manufacturing the same, and a terminal device, which can improve the quality of a nitride film layer formed on a surface of a silicon substrate in the semiconductor device.
  • the application provides a semiconductor device, the semiconductor device includes a silicon substrate, the silicon substrate includes a base and a plurality of nano-protrusion structures scattered on the surface of the base, wherein the sidewalls of the nano-protrusion structures have a variety of different
  • the semiconductor device further includes a nucleation layer and an epitaxial layer; and the nucleation layer and the epitaxial layer are sequentially stacked on the surface of the silicon substrate on the side with the nano-protrusion structure, and the nucleation layer and the epitaxial layer are formed.
  • the material of the epitaxial layer includes a nitride material.
  • nano-protrusion structures with nano-scale dimensions are arranged on the surface of the silicon substrate, that is, the three-dimensional dimensions of the nano-protrusion structures (i.e. length, width, etc.) , high) are in the nanoscale size range; thus avoiding the thickness limitation of epitaxially grown nitride films (such as nucleation layers and epitaxial layers), the use of nanometer-thick nitride films can meet the needs, and then The improved epitaxial growth efficiency of the nitride film layer is low, and the cost of the semiconductor device is reduced.
  • the sidewalls of the nanoprotrusion structure with different inclination angles (that is, the crystal plane index), that is, the sidewall angles of the nanoprotrusion structure are variable, so that the dislocation of the subsequently grown nitride film can be made. Bending helps to release the stress of the nitride film layer, thereby reducing the dislocation density of the epitaxial layer, improving the quality of the nitride crystal in the epitaxial layer, and inhibiting the surface cracking phenomenon, wafer warpage, and uneven thickness of the epitaxial layer. equality issues.
  • the sidewalls of the nanoprotrusion structure are divided into multiple layers, and the inclination angles of the sidewalls of each layer are different.
  • the base and the nano-protrusion structure are integrated; in this case, the base and the nano-protrusion structure (ie, silicon substrate) are fabricated and processed through the same silicon wafer, so as to simplify the manufacturing process , the purpose of reducing production costs.
  • the base and the nano-protrusion structure ie, silicon substrate
  • the plurality of nano-protrusion structures dispersedly arranged on the surface of the substrate are arranged in an array, so as to significantly reduce the dislocation density of the nitride film layer epitaxially grown on the surface of the silicon substrate and improve the crystal quality.
  • the nanoprotrusion structure includes a nanopyramid frustum and a nanopyramid on top of the nanopyramid frustum; the nanopyramid frustum is connected to the substrate; the sidewall inclination angle of the nanopyramid frustum is greater than the sidewall inclination angle of the nanopyramid frustum.
  • the inclination angle of the sidewall of the nanopyramid is 60° ⁇ 85°; in this case, by arranging a nanopyramid with a larger inclination angle on the top of the nanopyramid frustum, the nanoconvex can be enlarged.
  • the side area of the starting structure (which can be increased by more than 30%) further reduces the dislocation density of the epitaxially grown nitride film layer and improves the quality of the nitride crystal.
  • the nano-protrusion structure includes: a first nano-pyramid frustum, a second nano-pyramid frustum, and a third nano-pyramid frustum arranged in layers; wherein the first nano-pyramid frustum is connected to the substrate; the second nano-pyramid frustum is connected to the substrate; The inclination angle of the side wall of the pyramid truncated is greater than the inclination angle of the side wall of the first nano pyramid truncated, the third nano pyramid truncated is a chamfered pyramid truncated structure; the projection of the third nano pyramid truncated on the base is located at the projection of the first nano pyramid truncated on the base. Projection inside.
  • the nucleation layer may use at least one of AlN and GaN; for example, the nucleation layer may use AlN.
  • the epitaxial layer may use at least one of AlN, GaN, and AlGaN; for example, the epitaxial layer may use GaN.
  • Embodiments of the present application also provide a method for fabricating a semiconductor device, including:
  • Step 01 forming a mask pattern layer on the surface of the silicon wafer; the mask pattern layer includes a plurality of dispersed mask patterns.
  • Step 02 using tetramethylammonium hydroxide solution to etch the surface of the silicon wafer formed with the mask pattern layer to obtain a silicon substrate with nano-protrusion structures formed at positions corresponding to the plurality of mask patterns respectively; Wherein, the nano-protrusion structure has sidewalls with various inclination angles.
  • Step 03 using nitride to form a nucleation layer and an epitaxial layer on the surface of the silicon substrate formed with the nano-protrusion structure in sequence.
  • a nano-protrusion structure is formed by a mask combined with wet etching, and the sidewalls of the nano-protrusion structure have a variety of different inclination angles, so that As a result, the traditional dry etching (etching), nano-imprinting, electron beam lithography (EBL) and other expensive nano-fabrication processes are avoided, that is, the process is simple, the price is low, and the nanometer
  • etching dry etching
  • EBL electron beam lithography
  • the sidewall angle of the raised structure is variable, which can bend the dislocation of the subsequently grown nitride film layer, which helps to release the stress of the nitride film layer, thereby reducing the dislocation density of the epitaxial layer and improving the thickness of the epitaxial layer.
  • the quality of nitride crystals prevents surface cracking, wafer warpage, and uneven thickness of the epitaxial layer.
  • the thickness of the nitride film layer can cover the nano-protrusion structure by the nitride film layer of nanometer thickness, thereby improving the low epitaxial growth efficiency of the nitride film layer and reducing the cost of the semiconductor device.
  • using a tetramethyl ammonium hydroxide solution to etch the surface of the silicon wafer on which the mask pattern layer is formed includes: using a tetramethyl ammonium hydroxide solution with a mass concentration of 1% to 20% , under the condition of temperature of 40°C to 100°C, etching the surface of the silicon wafer on which the mask pattern is formed for 2 min to 20 min.
  • nucleation can be sequentially formed on the surface of the silicon substrate on which the nano-protrusion structure is formed by using nitride. Before the layer and the epitaxial layer, the mask pattern on the top of the nano-protrusion structure is removed; so as to facilitate the subsequent epitaxial growth of the nucleation layer and the epitaxial layer on the surface of the silicon substrate.
  • Embodiments of the present application further provide a terminal device, including a printed circuit board and a semiconductor device provided in any of the foregoing possible implementation manners, and the semiconductor device is connected to the printed circuit board.
  • FIG. 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a nano-protrusion structure on the surface of a silicon substrate provided by an embodiment of the present application;
  • FIG. 3 is a scanning electron microscope photo of a silicon substrate provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the distribution of nano-protrusion structures on the surface of a silicon substrate according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of the distribution of nano-protrusion structures on the surface of a silicon substrate according to an embodiment of the present application
  • FIG. 7 is a flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a semiconductor device in a manufacturing process according to an embodiment of the present application.
  • a method, system, product or device is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to the process, method, product or device.
  • “Top”, “bottom”, “left”, “right”, etc. are only used relative to the orientation of components in the drawings, these directional terms are relative concepts, and they are used for relative description and clarification , which may vary according to the orientation in which the components in the figures are placed.
  • the embodiment of the present application provides a terminal device, and the terminal device may be an electronic product such as a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, etc.
  • the specific form of the terminal device is not particularly limited in the embodiment of the present application .
  • the above-mentioned terminal equipment is provided with a printed circuit board (printed circuit board, PCB) and a semiconductor device connected with the printed circuit board;
  • the semiconductor device is a nitride (such as GaN, AlN) based semiconductor device using a silicon (Si) substrate, and also That is, the semiconductor device includes a nitride film layer disposed on a silicon (Si) substrate;
  • the application does not limit the type of the semiconductor device, for example, the semiconductor device may be a power device, a radio frequency device, an optoelectronic device, and the like.
  • the above-mentioned semiconductor device may be a GaN HEMT (high electron mobility transistor, high electron mobility transistor), or a device including a GaN HEMT.
  • the nano-protrusion structure is arranged on the surface of the silicon substrate, and the nitride film layer is formed on the surface of the side where the nano-bump structure is arranged on the surface of the silicon substrate, so that the nitride film layer can be reduced.
  • the dislocation density can inhibit the cracking phenomenon on the surface of the nitride film, the warpage of the wafer, and the uneven thickness; at the same time, the growth efficiency of the epitaxial growth of the nitride film can be improved, and the production cost can be reduced.
  • a silicon substrate 1 includes a base 11 and a plurality of nano-protrusion structures 12 distributed on the surface of the base 11 ; wherein, the nano-protrusion structures 12 have sides with various inclination angles. wall.
  • the above-mentioned nano-protrusion structure 12 refers to that the nano-protrusion structure 12 is in the nano-scale range (that is, the size range of 1000 nm), that is, the three-dimensional size (that is, the length, width, height) of the nano-protrusion structure 12 is all within 1000 nm.
  • the dimensions of the above-mentioned nano-protrusion structures 12 in the length, width, and height directions may all be within a size range of 200 nm to 800 nm.
  • the nano-protrusion structure 12 includes at least two sidewalls with different inclination angles, that is, the nano-protrusion structure 12 includes sidewalls with different inclination angles.
  • the protruding structure 12 contains at least two crystal planes with different crystal plane indices; wherein, the crystal plane index is one of the constants of the crystal, and the plane passing through any three nodes in the spatial lattice is called a crystal plane, and generally through the crystal plane
  • the crystal plane is characterized by an index (ie, the M.H. Miller index).
  • an index ie, the M.H. Miller index
  • various inclination angles of the sidewalls of the nano-protrusion structures 12 may be in the range of 20° ⁇ 85°.
  • the semiconductor device further includes: a nucleation layer 2 (also referred to as a buffer layer, a nucleation layer, a nucleation layer, and a layer), epitaxial layer 3; the nucleation layer 2 and epitaxial layer 3 are film layers including nitride materials; in actual production, the surface on the side of the silicon substrate 1 with the nano-protrusion structure 12 can be used, and the epitaxial obtained by growing.
  • a nucleation layer 2 also referred to as a buffer layer, a nucleation layer, a nucleation layer, and a layer
  • the nucleation layer 2 and epitaxial layer 3 are film layers including nitride materials
  • the semiconductor device due to the lattice mismatch and thermal expansion coefficient difference between the nitride film layer used in the nitride-based semiconductor device (that is, the above-mentioned epitaxial layer 3) and the silicon substrate 1, the semiconductor device will be The quality of the nitride film layer in the silicon substrate is poor (or the crystal quality is poor). Therefore, in order to improve the quality of the epitaxial layer 3, it is necessary to use nitride on the surface of the silicon substrate to make larger crystal particles before the epitaxial layer 3 is fabricated.
  • the nucleation layer 2 is formed, and then the epitaxial layer 3 is epitaxially grown on the surface of the nucleation layer 2; that is, the epitaxial layer 3 serves as the functional layer in the nitride-based semiconductor device, and the nucleation layer 2 is used to improve the nitrogen in the epitaxial layer 3.
  • the crystal quality of the compound is set as a buffer layer.
  • the epitaxial layer 3 may be a voltage-resistant layer (also referred to as a buffer layer of a GaN HEMT) in the GaN HEMT, or may include a voltage-resistant layer and a voltage-resistant layer located on its surface. Multiple nitride film layers.
  • the nitride materials used in the nucleation layer 2 and the epitaxial layer 3 can also be different. This application does not limit this too much. In practice, suitable nitride materials can be selected according to needs. That's it.
  • the material for forming the nucleation layer 2 may be at least one of AlN and GaN; the material for forming the epitaxial layer 3 may include at least one of AlN, GaN, and AlGaN; for example,
  • the nucleation layer 2 can be made of AlN, and the epitaxial layer 3 (such as the withstand voltage layer in GaN HEMT) can be made of GaN.
  • the present application does not limit the method of forming the nucleation layer 2 and the epitaxial layer 3, for example, a metal organic vapor phase epitaxy method (metal organic vapor phase epitaxy, MOVPE), a magnetic sputtering method, etc. can be used.
  • a metal organic vapor phase epitaxy method metal organic vapor phase epitaxy, MOVPE
  • MOVPE metal organic vapor phase epitaxy
  • magnetic sputtering method etc.
  • the three-dimensional dimensions (ie length, width, height) of the nano-protrusion structures 12 are all within the nano-scale size range, thereby avoiding
  • the thickness of the epitaxially grown nitride film (such as 2 and 3) is limited, and the nanometer-thick nitride film can meet the requirements, thereby improving the low epitaxial growth efficiency of the nitride film and reducing the semiconductor device. cost.
  • the sidewall angles of the nano-protrusion structures 12 are variable, so that the subsequent growth of the nitride film can be achieved.
  • Dislocation bending helps to release the stress of the nitride film layer, thereby reducing the dislocation density of the epitaxial layer, improving the quality of the nitride crystal in the epitaxial layer, and inhibiting the surface cracking phenomenon, wafer warpage, etc. of the epitaxial layer. The problem of uneven thickness.
  • the base 11 and the nano-protrusion structure 12 may be an integral structure, that is, the base 11 and the nano-protrusion structure 12 (ie, the silicon substrate 1) is obtained by manufacturing and processing the same silicon wafer, so that the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • the substrate 11 and the nano-protrusion structure 12 may also be composed of two connected parts.
  • the silicon substrate 1 can be obtained by manufacturing and processing two laminated wafers; this application
  • the substrate 11 and the nano-protrusion structure 12 are integrated as an example for schematic illustration.
  • the present application does not make any reference to the shape of the sidewalls of the nano-protrusion structures 12 and the size of the inclination angles of the sidewalls (including acute angles, obtuse angles, right angles, etc.). Restriction, as long as it is ensured that the nano-protrusion structures 12 pass through variable sidewall angles, so that dislocations in the subsequently epitaxially grown nitride film can be bent, and the quality of the nitride film can be improved.
  • the nano-protrusion structure 12 is a pyramid structure, and the inclination angle of the sidewall of the pyramid structure gradually increases from bottom to top.
  • the nano-protrusion structure 12 is a pyramidal frustum structure, and the inclination angle of the sidewall of the pyramidal frustum structure gradually increases from bottom to top; or, the sidewall of the pyramidal frustum structure is in the middle area. It has a larger angle of inclination and a smaller angle of inclination at both ends.
  • the nano-protrusion structures 12 may be approximately circular protrusion structures, and the circular protrusion structures have various inclined surfaces randomly distributed.
  • the nano-protrusion structure 12 may be formed by wet etching in this application;
  • the etching is to gradually etch from the surface layer to the deep layer through the etching solution, so as to obtain the actual required structure; therefore, for the present application, when the nano-protrusion structure 12 is formed by wet etching, the etching conditions are controlled. , can make the nano-protrusion structure 12 present multiple layers of sidewall appearances with different inclination angles in the thickness direction (ie from top to bottom).
  • the fabrication of the above nano-protrusion structures 12 with multiple layers of different sidewall inclination angles is not limited to wet etching, and other fabrication methods can also be used.
  • the multi-layered sidewalls with different inclination angles of the nano-protrusion structure 12 it is only for the appearance (or outline) structure presented by the sidewall of the nano-protrusion structure 12 that is a stacked structure, It does not necessarily mean a physical inter-layer structure, and the embodiments of the present application are all described by taking an integrated structure in which the nano-protrusion structure 12 itself is a single layer as an example.
  • the present application does not limit the number of sidewall layers of the nano-protrusion structures 12 provided in the above-mentioned stacks.
  • the nano-protrusion structure 12 may have two layers of sidewalls with different inclination angles.
  • the nano-protrusion structure 12 may also have three layers of sidewalls with different inclination angles.
  • the nano-protrusion structure 12 may also have four layers of sidewalls with different inclination angles.
  • the shapes of the pyramids located in different layers in the above-mentioned stacked nano-protrusion structures 12 may be the same (for example, they may all be octagonal pyramids), or they may be different (for example, one is an octagonal pyramid, and the other is a quadrangular pyramid); This application does not limit this.
  • the first method of stacking the nano-protrusion structures 12 is the first method of stacking the nano-protrusion structures 12:
  • the nano-protrusion structure 12 may include a nano-pyramid frustum a1 and a The nano-pyramid a2 at the top of the structure a1; the nano-protrusion structure 12 is connected to the substrate 11 through the bottom of the nano-pyramid frustum a1.
  • the nanopyramid frustum a1 may be an octagonal frustum structure, and the nanopyramid frustum a2 may be a quadrangular pyramid; wherein, the nanopyramid frustum a1 and the nanopyramid frustum a2 may both have quadruple symmetry features.
  • the sidewall inclination angle ⁇ 1 of the nanopyramid a2 is greater than the sidewall inclination angle ⁇ 2 of the nanopyramid frustum a1;
  • the top of the mesa a1 is provided with a nano-pyramid a2 with a larger inclination angle, so that the lateral area of the nano-protrusion structure 12 can be increased (can be increased by more than 30%), thereby further reducing the dislocation density of the epitaxially grown nitride film layer, Improves nitride crystal quality.
  • the sidewall inclination angle ⁇ 1 of the nanopyramid a2 may be 60° ⁇ 85°, and the sidewall inclination angle ⁇ 2 of the nanopyramid frustum a1 may be 20° ⁇ 50°.
  • the sidewall inclination angle ⁇ 1 of the nanopyramid a2 may be 60°, 70°, 80°, 85°, and the sidewall inclination angle ⁇ 2 of the nanopyramid frustum a1 may be 20°, 30°, 40° °, 50 °.
  • the second method of stacking the nano-protrusion structures 12 is the second method of stacking the nano-protrusion structures 12:
  • the nano-protrusion structure 12 may include: a first nano-pyramid frustum b1 , a second nano-pyramid frustum b2 , and a third nano-pyramid frustum b3 arranged in layers; the nano-convex frustum b1 ;
  • the lift-up structure 12 is connected to the substrate 11 through the bottom of the first nano-pyramid frustum b1.
  • the sidewall inclination angle of the second nanopyramid frustum b2 is greater than the sidewall inclination angle of the first nanopyramid frustum b2, and the third nanopyramid frustum b3 is an inverted pyramid frustum structure; and the projection of the third nanopyramid frustum b3 on the substrate It is located inside the projection of the first nanopyramid frustum b1 on the substrate 11 (refer to FIG. 4( a )).
  • the first truncated nanopyramid b1 , the second truncated nanopyramid b2 , and the third truncated nanopyramid b3 may be octagonal truncated pyramid structures, and all have quadruple symmetry.
  • the sidewalls of the nano-protrusion structure 12 have three different inclination angles (crystal plane indices), so that the dislocation density of the epitaxially grown nitride film layers (2, 3) can be further reduced, and the nitrogen the quality of the compound crystals.
  • pyramid frustum eg a1, b1, b2, b3
  • a frustum e.g. a1, b1, b2, b3
  • truncated pyramid truncated pyramid
  • a plurality of nano-protrusion structures 12 can be arranged in an array; of course, the present application does not limit the specific array arrangement of the plurality of nano-protrusion structures 12 .
  • the plurality of nano-protrusion structures 12 scattered on the surface of the substrate 11 may be arranged in a tetragonal symmetrical array; that is, each nano-protrusion structure located in two adjacent rows 12. Align distribution along the column direction; schematically, the distances between two adjacent nano-protrusion structures 12 located in a row and two adjacent nano-protrusion structures 12 located in the same column may be the same.
  • the plurality of nano-protrusion structures 12 scattered on the surface of the substrate 11 may be arranged in a hexagonal symmetrical array; that is, the nano-protrusion structures 12 located in two adjacent rows Among them, each nano-protrusion structure 12 in one row is opposite to the middle position of two adjacent nano-protrusion structures 12 in another row, that is, the nano-protrusion structures 12 in two adjacent rows are dislocated.
  • the nano-protrusion structures 12 dispersedly arranged on the surface of the silicon substrate 1 can induce the internal tensile and compressive stress of the epitaxially grown nitride to be distributed in an array (for example, an array distribution), and the stresses are mutually neutralized and fully released, thereby inhibiting the Surface cracking and severe wafer warpage problems.
  • the topography of the nano-protrusions 12 dispersedly arranged on the surface of the silicon substrate 1 is undulating, which can induce the surface tension of the nucleation islands of the epitaxially grown nitrides during the merging process. In addition, the occurrence of surface cracking is suppressed.
  • the nano-protrusion structures 12 dispersedly arranged on the surface of the silicon substrate 1 can induce the lateral merging of the nitride nucleation islands grown by epitaxial growth, bend the dislocations, reduce the dislocation density, and further improve the crystal quality.
  • using the silicon substrate of the nano-protrusion structure 12 provided by some embodiments of the present application can reduce the dislocation density of the subsequently epitaxially grown nitride film layer by 2 to 3 orders of magnitude, It can be reduced to 10 7 cm -2 to 10 8 cm -2 .
  • the crystal quality of the epitaxial nitride on the surface of the silicon substrate is significantly improved by the arrangement of the nano-protrusion structure 12 , thereby solving the surface cracks, high dislocation density, wafer surface cracks and high dislocation density of the epitaxial nitride on the silicon substrate 1 .
  • problems such as warpage, uneven thickness, and uneven doping in the active area of semiconductor devices; furthermore, it helps to improve the performance of nitride-based semiconductor devices on silicon substrates, especially for the preparation of high-performance optoelectronic, power, and radio frequency devices. It can improve the internal quantum efficiency and life of the optoelectronic device, reduce the leakage current of the power device, increase the breakdown voltage, and further improve the reliability of the device.
  • an embodiment of the present application also provides a method for fabricating a semiconductor device, as shown in FIG. 7 , the fabrication method includes:
  • Step 01 as shown in FIG. 8( a ), a mask pattern layer 20 is formed on the surface of the silicon wafer 10 ; wherein the mask pattern layer 20 includes a plurality of dispersed mask patterns 21 .
  • the above step 01 may include: first depositing a silicon dioxide film (ie, a SiO 2 film) with a thickness of 10 nm to 300 nm on the surface of the silicon wafer 10 ; and then performing photolithography on the SiO 2 film , forming a mask pattern layer 20 .
  • the mask pattern layer 20 includes a plurality of cylindrical SiO 2 mask patterns ( 21 ) distributed in an array (such as a tetragonal symmetrical array); the diameter of the cylindrical SiO 2 mask patterns ( 21 ) may be 1 ⁇ m ⁇ 2 ⁇ m , the distance between two adjacent cylindrical SiO 2 mask patterns may be 1 ⁇ m ⁇ 3 ⁇ m.
  • step 01 the silicon wafer 10 whose surface is covered with a plurality of mask patterns 21 can be obtained.
  • Step 02. use tetramethylammonium hydroxide (TMAH) solution to etch the surface of the silicon wafer 10 on which the mask pattern layer 20 is formed, so as to obtain the corresponding mask pattern layer 20.
  • TMAH tetramethylammonium hydroxide
  • the position of the film pattern 21 is formed with the silicon substrate 1 of the nano-protrusion structure 12, and the nano-protrusion structure 12 has sidewalls with various inclination angles.
  • the above step 02 may include: using a TMAH solution with a mass concentration of 1% to 20%, under the condition of a temperature of 40° C. to 100° C., on the silicon on which the mask pattern 21 is formed.
  • the surface of the sheet 10 is etched for 2 to 20 minutes, so as to obtain the silicon substrate 1 with the nano-protrusion structures 12 formed at the positions corresponding to the mask patterns 21 .
  • the concentration of the TMAH solution can be 1wt%, 3wt%, 5wt%, 8wt%, 15wt%, 20wt%;
  • the etching temperature can be 40°C, 50°C, 60°C, 80°C, 100°C;
  • the etching time can be 2min, 10min, 15min, 20min, so that the three-dimensional size (that is, the size in the length, width, and height directions) formed on the surface of the silicon substrate 1 is in the range of 200nm ⁇ 800nm
  • the nano-protrusion structure 12 can be 1wt%, 3wt%, 5wt%, 8wt%, 15wt%, 20wt%;
  • the etching temperature can be 40°C, 50°C, 60°C, 80°C, 100°C;
  • the etching time can be 2min, 10min, 15min, 20min, so that the three-dimensional size (that is, the size in the length, width, and height directions) formed on the surface of
  • the above step 02 may include: placing the silicon wafer 10 formed in the foregoing step 01 with the surface covered with a plurality of mask patterns 21 in a polytetrafluoroethylene flower basket, and then immersing the silicon wafer 10 in 1wt% In an aqueous solution of ⁇ 20wt% TMAH, and adjusting the temperature to 40°C to 100°C, etching is performed for 2min to 20min to obtain a silicon substrate 1 with a nano-protrusion structure 12 formed on the surface; and the side of the nano-protrusion structure 12 is obtained.
  • the walls are divided into multiple layers, and the inclination angles of the side walls of each layer are different. Of course, the inclination angles of the side walls of the same layer can be the same or approximately the same.
  • nano-protrusion structures 12 with different shapes and structures can be obtained.
  • the etching time may be set to 20 minutes, thereby forming the nanoprotrusion structure 12 shown in FIG.
  • the etching time may be set to 10 min, thereby forming the three-layer nano-pyramid frustum structure shown in FIG. 4 .
  • the fabrication method of the semiconductor device may be appropriately adjusted according to the different structures of the nano-protrusion structures 12 to be formed.
  • the mask pattern 21 formed in step 01 will automatically fall off during the process of forming the nano-protrusion structure 12, Therefore, there is no need to separately provide a process for removing the mask pattern 21 .
  • the mask pattern 21 on the top of the nano-protrusion structure 12 may be removed through a process.
  • the above-mentioned process of removing the mask pattern 21 located on the top of the nano-protrusion structure 12 may include: retaining the aforementioned mask pattern 21 (such as the aforementioned cylindrical SiO 2 mask The silicon substrate 1 of the pattern) is placed in an HF (hydrofluoric acid) solution, and the mask pattern 21 is etched by the HF solution (for example, the etching time can be 0.5min-10min), and then rinsed with deionized water and nitrogen Blow dry to obtain the silicon substrate 1 with only the nano-protrusion structures 12 remaining on the surface.
  • HF hydrofluoric acid
  • Step 03 Referring to FIG. 8(b), nitride is used to form a nucleation layer 2 and an epitaxial layer 3 on the surface of the silicon substrate 1 on which the nano-protrusion structures 12 are formed in sequence.
  • the above step 03 may include: using a metal organic vapor phase epitaxy method (MOVPE) or a sputtering method to form a thickness of 5 nm ⁇ 200nm low temperature nitride nucleation layer 2 (such as AlN thin film layer); then, using metal organic vapor phase epitaxy (MOVPE) high temperature epitaxy to grow nitride epitaxial layer 3 (such as GaN thin film layer) with a thickness of 0.3 ⁇ m to 10 ⁇ m;
  • MOVPE metal organic vapor phase epitaxy
  • the relevant growth parameters of high temperature epitaxial growth of GaN crystal can be: substrate temperature is 1000-1140 °C, trimethylgallium flow rate: 5-100sccm; NH 3 gas flow rate is 1000-8000sccm; carrier gas is N 2 /H 2 /Ar.
  • a nano-protrusion structure is formed by a mask combined with wet etching, and the sidewalls of the nano-protrusion structure have various different In this way, the traditional dry etching, nano-imprinting, electron beam lithography (EBL) and other expensive nano-fabrication processes are avoided, that is, the process is simple and the price is low;
  • the sidewall angle of the nano-protrusion structure is variable, which can bend the dislocation of the subsequently grown nitride film layer, which helps to release the stress of the nitride film layer, thereby reducing the dislocation density of the epitaxial layer and improving the epitaxial layer.
  • the quality of nitride crystals in the layer suppresses the surface cracking phenomenon, wafer warpage, and uneven thickness of the epitaxial layer;
  • the nano-protrusion structure can be covered by a nanometer-thick nitride film layer without epitaxial growth of a micron-thickness nitride film layer, thereby improving the epitaxial growth efficiency of the nitride film layer and reducing the cost of semiconductor devices. .
  • step 03 according to the needs of the actual semiconductor device, other film layer structures can be correspondingly fabricated; taking a GaN transistor (ie GaN HEMT) as an example, after step 03, it may include fabricating source and drain layers, gate layers, The film layers such as the surface passivation layer can be manufactured with reference to the related art for details, which will not be repeated here.
  • GaN transistor ie GaN HEMT
  • step 03 it may include fabricating source and drain layers, gate layers, The film layers such as the surface passivation layer can be manufactured with reference to the related art for details, which will not be repeated here.

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Abstract

本申请提供了一种半导体器件及其制作方法、终端设备，能够提高半导体器件中在硅衬底表面形成的氮化物膜层的质量；该半导体器件包括硅衬底，该硅衬底包括基底以及位于基底表面分散设置的多个纳米凸起结构，其中该纳米凸起结构的侧壁具有多种不同的倾斜角；在此基础上，该半导体器件还包括形核层和外延层；且形核层和外延层依次层叠设置于硅衬底具有纳米凸起结构一侧的表面，并且形成形核层和外延层的材料包括氮化物材料。

Description

半导体器件及其制作方法、终端设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法、终端设备。
背景技术
硅(Si)衬底由于价格低廉、制备工艺成熟、可实现大尺寸晶圆制备等优点，广泛的应用在目前的半导体器件中。
然而，对于采用氮化物基的半导体器件(如GaN或AlN晶体器件)而言，通常会因为硅(Si)和氮化物晶体存在着严重的晶格失配和热膨胀系数差异，会导致在硅衬底表面生长氮化物膜层时，容易出现氮化物膜层表面龟裂、位错密度高、晶圆翘曲、厚度不均、半导体器件有源区掺杂不均等一系列问题，进而严重影响半导体器件的工艺制程及性能。
发明内容
本申请实施例提供一种半导体器件及其制作方法、终端设备，能够提高半导体器件中在硅衬底表面形成的氮化物膜层的质量。
本申请提供一种半导体器件，该半导体器件包括硅衬底，该硅衬底包括基底以及位于基底表面分散设置的多个纳米凸起结构，其中该纳米凸起结构的侧壁具有多种不同的倾斜角；在此基础上，该半导体器件还包括形核层和外延层；且形核层和外延层依次层叠设置于硅衬底具有纳米凸起结构一侧的表面，并且形成形核层和外延层的材料包括氮化物材料。
综上所述，对于本申请实施例提供的半导体器件而言，一方面，通过在硅衬底表面设置纳米级尺寸的纳米凸起结构，也即纳米凸起结构的三维尺寸(即长、宽、高)均处于纳米级尺寸范围内；从而避免了对外延生长的氮化物膜层(如形核层和外延层)的厚度限制，采用纳米级厚度的氮化物膜层即可满足需求，进而提高了氮化物膜层的外延生长效率低，降低了半导体器件的成本。另一方面，通过设置纳米凸起结构具有不同倾斜角(也即晶面指数)的侧壁，即纳米凸起结构的侧壁角度多变，从而能够使得后续生长的氮化物膜层的位错弯曲，有助于氮化物膜层应力的释放，进而降低了外延层的位错密度，提升了外延层中氮化物晶体质量，抑制了外延层出现表面龟裂现象、晶圆翘曲、厚度不均等问题。
在一些可能实现的方式中，纳米凸起结构的侧壁分为多层，且每一层侧壁的倾斜角不同。
在一些可能实现的方式中，基底与纳米凸起结构为一体结构；在此情况下，基底与纳米凸起结构(即硅衬底)通过同一片硅晶圆制作加工得到，以达到简化制作工艺，降低制作成本的目的。
在一些可能实现的方式中，基底表面分散设置的多个纳米凸起结构呈阵列排布；以显著降低在硅衬底表面外延生长的氮化物膜层的位错密度，提升晶体质量。
在一些可能实现的方式中，纳米凸起结构包括纳米棱锥台以及位于纳米棱锥台顶部的 纳米棱锥；纳米棱锥台与基底连接；纳米棱锥的侧壁倾斜角大于纳米棱锥台的侧壁倾斜角。
在一些可能实现的方式中，纳米棱锥的侧壁倾斜角为60°～85°；在此情况下，通过在纳米棱锥台的顶部设置具有较大倾斜角度的纳米棱锥，从而能够增大纳米凸起结构的侧面积(可以提升30％以上)，进一步降低外延生长的氮化物膜层的位错密度，提升氮化物晶体质量。
在一些可能实现的方式中，纳米凸起结构包括：叠层设置的第一纳米棱锥台、第二纳米棱锥台、第三纳米棱锥台；其中，第一纳米棱锥台与基底连接；第二纳米棱锥台的侧壁倾斜角大于第一纳米棱锥台的侧壁倾斜角，第三纳米棱锥台为倒棱锥台结构；第三纳米棱锥台在基底上的投影位于第一纳米棱锥台在基底上的投影内部。
在一些可能实现的方式中，形核层可以采用AlN、GaN中的至少一种；例如，形核层可以采用AlN。
在一些可能实现的方式中，外延层可以采用AlN、GaN、AlGaN中的至少一种；例如外延层可以采用GaN。
本申请实施例还提供一种半导体器件的制作方法，包括：
步骤01、在硅片的表面形成掩膜图案层；该掩膜图案层中包括多个分散的掩膜图案。
步骤02、采用四甲基氢氧化铵溶液，对形成有掩膜图案层的硅片表面进行刻蚀，以得到在对应多个掩膜图案的位置分别形成有纳米凸起结构的硅衬底；其中，纳米凸起结构具有多种不同倾斜角的侧壁。
步骤03、采用氮化物在形成有纳米凸起结构的硅衬底表面依次形成形核层和外延层。
采用本申请实施例提供的半导体器件的制作方法，一方面，通过掩膜结合湿法刻蚀的方式形成纳米凸起结构，并该纳米凸起结构的侧壁具有多种不同的倾斜角，这样一来，避免了采用传统的干法刻蚀(蚀刻)、纳米压印、电子束刻蚀(electron beam lithography，EBL)等昂贵的纳米制程工艺，也即工艺简单，价格低廉，同时形成的纳米凸起结构的侧壁角度多变，能够使得后续生长的氮化物膜层的位错弯曲，有助于氮化物膜层应力的释放，进而降低了外延层的位错密度，提升了外延层中氮化物晶体质量，抑制了外延层出现表面龟裂现象、晶圆翘曲、厚度不均等问题；另一方面，直接在纳米凸起结构的表面进行外延生长氮化物膜层，无需外延生长微米级厚度氮化物膜层，通过纳米级厚度的氮化物膜层即可覆盖纳米凸起结构，进而提高了氮化物膜层的外延生长效率低，降低了半导体器件的成本。
在一些可能实现的方式中，采用四甲基氢氧化铵溶液，对形成有掩膜图案层的硅片表面进行刻蚀包括：采用质量浓度为1％～20％的四甲基氢氧化铵溶液，在温度40℃～100℃的条件下，对形成有掩膜图案的硅片表面进行2min～20min刻蚀。
在一些可能实现的方式中，在步骤01中形成的掩膜图案保留在纳米凸起结构的顶部的情况下，可以在采用氮化物在形成有纳米凸起结构的硅衬底表面依次形成形核层和外延层之前，去除位于纳米凸起结构顶部的掩膜图案；以便于后续硅衬底表面的形核层和外延层的外延生长。
本申请实施例还提供一种终端设备，包括印刷线路板以及如前述任一种可能实现的方式中提供的半导体器件，并且该半导体器件与印刷线路板连接。
附图说明
图1为本申请实施例提供的一种半导体器件的结构示意图；
图2为本申请实施例提供的一种硅衬底表面的纳米凸起结构示意图；
图3为本申请实施例提供的一种硅衬底的扫描电镜照片；
图4为本申请实施例提供的一种硅衬底的扫描电镜照片；
图5为本申请实施例提供的一种硅衬底表面的纳米凸起结构分布示意图；
图6为本申请实施例提供的一种硅衬底表面的纳米凸起结构分布示意图；
图7为本申请实施例提供的一种半导体器件的制作方法流程图；
图8为本申请实施例提供的一种半导体器件的制作过程中的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“连接”、“相连”等类似的词语，用于表达不同组件之间的互通或互相作用，可以包括直接相连或通过其他组件间接相连。“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种终端设备，该终端设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环等电子产品；本申请实施例对该终端设备的具体形式不做特殊限制。
上述终端设备中设置印刷线路板(printed circuit board，PCB)以及与印刷线路板连接的半导体器件；该半导体器件为采用硅(Si)衬底的氮化物(如GaN、AlN)基半导体器件，也即该半导体器件中包括设置在硅(Si)衬底上的氮化物膜层；本申请对于该半导体器件的类型不作限制，例如，该半导体器件可以为功率器件、射频器件、光电器件等。
示意的，在一些可能实现的方式中，上述半导体器件可以为GaN HEMT(high electron mobility transistor，高电子迁移率晶体管)，或者包括GaN HEMT的器件。
本申请实施例提供的半导体器件中，采用在硅衬底表面设置纳米凸起结构，通过在硅衬底表面设置纳米凸起结构一侧的表面形成氮化物膜层，能够降低氮化物膜层的位错密度，抑制氮化物膜层表面龟裂现象、晶圆翘曲、厚度不均等问题；同时还能够提高外延生长氮化物膜层时的生长效率，降低生产成本。以下对本申请实施例提供的半导体器件进行具体说明。
如图1所示，在该半导体器件中，硅衬底1包括基底11以及位于基底11表面分散设 置的多个纳米凸起结构12；其中，纳米凸起结构12具有多种不同倾斜角的侧壁。
上述纳米凸起结构12是指，该纳米凸起结构12处于纳米级范围(即1000nm的尺寸范围内)，也即纳米凸起结构12的三维尺寸(即长、宽、高)均处于1000nm的尺寸范围内；示意的，在一些可能实现的方式中，上述纳米凸起结构12在长、宽、高方向上的尺寸可以均处于200nm～800nm的尺寸范围内。
另外，对于上述纳米凸起结构12具有多种不同倾斜角的侧壁而言，可以理解的是，该纳米凸起结构12至少包含了两种不同倾斜角的侧壁，也就是说，该纳米凸起结构12至少包含了两种具有不同晶面指数的晶面；其中，晶面指数是晶体的常数之一，通过空间点阵中任意三结点的平面称为晶面，一般通过晶面指数(也即米勒(M.H.Miller)指数)来表征晶面，关于晶面指数的具体计算方法可以参考相关技术，此处不作赘述。
示意的，在一些可能实现的方式中，上述纳米凸起结构12侧壁的多种不同倾斜角可以在20°～85°的范围内。
在此基础上，如图1所示，该半导体器件还包括：在硅衬底1具有纳米凸起结构12一侧的表面依次层叠设置的形核层2(也可以称为缓冲层、成核层)、外延层3；该形核层2和外延层3为包括氮化物材料的膜层；在实际的制作时可以采用在硅衬底1具有纳米凸起结构12一侧的表面，通过外延生长的方式获得。
此处应当理解的是，由于氮化物基半导体器件中采用的氮化物膜层(也即上述外延层3)与硅衬底1之间会存在晶格失配和热膨胀系数差异，会使得半导体器件中的氮化物膜层的质量差(或者说晶体质量差)，因此，为了提高外延层3的质量，需要在制作该外延层3之前，先在硅衬底表面采用氮化物制作晶体颗粒较大的形核层2，然后在形核层2的表面外延生长外延层3；也就是说，外延层3作为氮化物基半导体器件中的功能层，而形核层2为了提高外延层3中氮化物的晶体质量设置的缓冲层。
示意的，以氮化物基半导体器件为GaN HEMT为例，外延层3可以为GaN HEMT中的耐压层(也可以称为GaN HEMT的缓冲层)，或者是包括耐压层以及位于其表面的多个氮化物膜层。
当然，根据氮化物基半导体器件的类型不同，形核层2和外延层3采用的氮化物材料也可以不同，本申请对此不作过多的限制，实际中可以根据需要选择合适的氮化物材料即可。
示意的，在一些可能实现的方式中，形成形核层2的材料可以采用AlN、GaN中的至少一种；形成外延层3的材料可以包括AlN、GaN、AlGaN中的至少一种；例如，形核层2可以采用AlN，外延层3(如GaN HEMT中的耐压层)可以采用GaN。
另外，本申请对于形成形核层2和外延层3的方式不作限制，例如可以采用金属有机气相外延方法(metal organic vapor phase epitaxy，MOVPE)、磁溅射方式等。
综上所述，对于本申请实施例提供的半导体器件而言：
一方面，通过在硅衬底1表面设置纳米级尺寸的纳米凸起结构12，也即纳米凸起结构12的三维尺寸(即长、宽、高)均处于纳米级尺寸范围内，从而避免了对外延生长的氮化物膜层(如2、3)的厚度限制，采用纳米级厚度的氮化物膜层即可满足需求，进而提高了氮化物膜层的外延生长效率低，降低了半导体器件的成本。
另一方面，通过设置纳米凸起结构12具有不同倾斜角(也即晶面指数)的侧壁，即 纳米凸起结构12的侧壁角度多变，从而能够使得后续生长的氮化物膜层的位错弯曲，有助于氮化物膜层应力的释放，进而降低了外延层的位错密度，提升了外延层中氮化物晶体质量，抑制了外延层出现表面龟裂现象、晶圆翘曲、厚度不均等问题。
另外，对于本申请实施例提供的半导体器件中的硅衬底而言，在一些可能实现的方式中，基底11与纳米凸起结构12可以为一体结构，也即基底11与纳米凸起结构12(即硅衬底1)通过同一片硅晶圆制作加工得到，从而能够简化制作工艺，降低制作成本。当然，在一些可能实现的方式中，基底11与纳米凸起结构12也可以是连接的两部分组成，例如，硅衬底1可以通过两片层叠压合的晶圆进行制作加工得到；本申请以下实施例均是以基底11与纳米凸起结构12为一体结构为例进行示意说明的。
以下对设置在硅衬底1表面的纳米凸起结构12的设置形式进行说明。
对于上述纳米凸起结构12具有多种不同倾斜角的侧壁而言，本申请对纳米凸起结构12的侧壁形状、侧壁倾斜角(包括锐角、钝角、直角等)的大小等均不作限制，只要保证纳米凸起结构12通过多变的侧壁角度，使得后续外延生长的氮化物膜层中位错能够发生弯曲，提高氮化物膜层的质量即可。
例如，在一些可能实现的方式中，纳米凸起结构12是棱锥结构，该棱锥结构的侧壁倾斜角从下到上逐渐增加。
又例如，在一些可能实现的方式中，纳米凸起结构12是棱锥台结构，该棱锥台结构的侧壁倾斜角从下到上逐渐增加；或者，该棱锥台结构的侧壁，在中间区域具有较大的倾斜角，在两端区域具有较小的倾斜角。
再例如，在一些可能实现的方式中，纳米凸起结构12可以是近似圆形凸起结构，且该圆形凸起结构具有无规则分布的多种倾斜表面。
当然，考虑到纳米凸起结构12的实际制作，为了尽可能的简化工艺，降低成本，本申请中可以采用湿法刻蚀的方式来形成纳米凸起结构12；可以理解的是，湿法刻蚀是通过刻蚀液逐渐从表层向深层进行刻蚀，从而得到实际所需要的结构；因此，对于本申请而言，在采用湿法刻蚀形成纳米凸起结构12时，通过控制刻蚀条件，能够使得纳米凸起结构12在厚度方向上(即从上到下)呈现出多层不同倾斜角的侧壁外貌，当然，同层侧壁的倾斜角可以相同或者大致相同。
当然，上述具有多层不同侧壁倾斜角的纳米凸起结构12的制作，并不限制于采用湿法刻蚀，也可以采用其他的制作方法进行制作。
需要说明的是，对于上述纳米凸起结构12具有的多层不同倾斜角的侧壁而言，仅是针对纳米凸起结构12侧壁呈现出的外貌(或外轮廓)结构为叠层结构，并不必然意味着物理上的层间结构，本申请实施例均是以该纳米凸起结构12自身为单层的一体结构为例进行说明的。
本申请对上述叠层设置的纳米凸起结构12的侧壁层数均不作限制。
例如，在一些可能实现的方式中，该纳米凸起结构12可以具有两层不同倾斜角的侧壁。
又例如，在一些可能实现的方式中，该纳米凸起结构12也可以具有三层不同倾斜角的侧壁。
再例如，在一些可能实现的方式中，该纳米凸起结构12也可以具有四层不同倾斜角 的侧壁。
另外，上述叠层设置的纳米凸起结构12中位于不同层的椎体形状可以相同(例如，可以均为八棱锥)，也可以不同(例如，一个为八棱锥，另一个为四棱锥)；本申请对此均不作限制。
以下通过具体实施例对纳米凸起结构12的叠层设置方式进行说明。
纳米凸起结构12的叠层设置方式一：
在一些可能实现的方式中，参考图2和图3(图2中示出的纳米凸起结构12的扫描电镜图)所示，纳米凸起结构12可以包括纳米棱锥台a1以及位于纳米凸起结构a1顶部的纳米棱锥a2；该纳米凸起结构12通过纳米棱锥台a1的底部与基底11连接。
示意的，参考图3中(a)所示，纳米棱锥台a1可以为八棱锥台结构，纳米棱锥a2可以为四棱锥；其中，纳米棱锥台a1和纳米棱锥a2可以均具有四重对称特征。
在此基础上，如图2所示，在该纳米凸起结构12中，纳米棱锥a2的侧壁倾斜角β1大于纳米棱锥台a1的侧壁倾斜角β2；在此情况下，通过在纳米棱锥台a1的顶部设置具有较大倾斜角度的纳米棱锥a2，从而能够增大纳米凸起结构12的侧面积(可以提升30％以上)，从而进一步降低外延生长的氮化物膜层的位错密度，提升氮化物晶体质量。
示意的，在一些可能实现的方式中，上述纳米棱锥a2的侧壁倾斜角β1可以为60°～85°，纳米棱锥台a1的侧壁倾斜角β2可以为20°～50°。例如，在一些实施例中，纳米棱锥a2的侧壁倾斜角β1可以为60°、70°、80°、85°，纳米棱锥台a1的侧壁倾斜角β2可以为20°、30°、40°、50°。
纳米凸起结构12的叠层设置方式二：
在一些可能实现的方式中，参考图4所示，纳米凸起结构12可以包括：叠层设置的第一纳米棱锥台b1、第二纳米棱锥台b2、第三纳米棱锥台b3；该纳米凸起结构12通过第一纳米棱锥台b1的底部与基底11连接。其中，第二纳米棱锥台b2的侧壁倾斜角大于第一纳米棱锥台b2的侧壁倾斜角，第三纳米棱锥台b3为倒棱锥台结构；并且第三纳米棱锥台b3在基底上的投影位于第一纳米棱锥台b1在基底11上的投影内部(参考图4中(a))。
示意的，参考图4中(a)所示，第一纳米棱锥台b1、第二纳米棱锥台b2、第三纳米棱锥台b3可以为八棱锥台结构，且均具有四重对称特征。
在此情况下，该纳米凸起结构12的侧壁具有三种不同的倾斜角度(晶面指数)，从而能够进一步降低外延生长的氮化物膜层(2、3)的位错密度，提升氮化物晶体的质量。
需要说明的是，本申请中所涉及的棱锥台(如a1、b1、b2、b3)，也可以称为棱台、截棱锥(truncated pyramid)等。
另外，对于前述位于基底11表面分散设置的多个纳米凸起结构12而言，为了进一步的降低在硅衬底1表面外延生长的氮化物膜层(2、3)的位错密度，提升晶体质量，在一些可能实现的方式中，可以设置多个纳米凸起结构12呈阵列排布；当然，本申请对于多个纳米凸起结构12的具体阵列排布方式不做限制。
例如，在一些可能实现的方式中，如图5所示，基底11表面分散设置的多个纳米凸起结构12可以呈四方对称阵列排布；也即位于相邻两行的各纳米凸起结构12，沿列方向上对齐分布；示意的，位于同行相邻的两个纳米凸起结构12以及位于同列相邻的两个纳米凸起结构12之间的距离可以相同。
又例如，在一些可能实现的方式中，如图6所示，基底11表面分散设置的多个纳米凸起结构12可以呈六方对称阵列排布；也即位于相邻两行纳米凸起结构12中，其中，一行的各纳米凸起结构12与另一行中相邻两个纳米凸起结构12的中间位置相对，也就是说，相邻两行纳米凸起结构12错位分布。
另外，以下对通过在硅衬底1的表面分散排布的纳米凸起结构12，来提升后续外延生长的氮化物膜层的质量的理论依据和影响机制进行简单的说明的。
第一、硅衬底1表面分散排布的纳米凸起结构12能够诱导外延生长的氮化物内部拉、压应力分散呈阵列分布(如呈阵列分布)，应力相互中和并充分释放，进而抑制表面龟裂现象和严重的晶圆翘曲问题。
第二、硅衬底1表面分散排布的纳米凸起结构12地势起伏，能够诱导外延生长的氮化物的形核岛在合并过程中产生的表面张力方向交错、相互中和，张力充分释放，进而抑制表面龟裂现象产生。
第三、硅衬底1表面分散排布的纳米凸起结构12能够诱导外延生长的氮化物形核岛横向合并，位错弯曲，降低位错密度，进而提升晶体质量。
示意的，在一些可能实现的方式中，采用本申请一些实施例提供的纳米凸起结构12的硅衬底，能够使得后续外延生长的氮化物膜层的位错密度降低2～3个数量级，可以降低至10 7cm -2～10 8cm -2。
可以理解的是，通过纳米凸起结构12的设置，显著提升了硅衬底表面外延氮化物的晶体质量，从而解决了硅衬底1外延氮化物存在的表面龟裂、高位错密度、晶圆翘曲、厚度不均、半导体器件有源区掺杂不均等问题；进而有助于提升硅衬底的氮化物基半导体器件的性能，尤其是有助于制备高性能光电、功率、射频器件，能够提高光电器件内量子效率和寿命，可降低功率器件的漏电电流、增大击穿电压，进而提升器件的可靠性。
示意的，以GaN/AlN晶体器为例，通过设置纳米凸起结构12，有助于实现大尺寸(如现6～8寸)硅衬底1在有源区表面高质量、无裂纹、翘曲低的氮化物的MOVPE外延生长，从而提升GaN/AlN晶体器件的可靠性。
另外，本申请实施例还提供一种半导体器件的制作方法，如图7所示，该制作方法包括：
步骤01、参考图8中(a)所示，在硅片10的表面形成掩膜图案层20；其中，该掩膜图案层20中包括多个分散的掩膜图案21。
示意的，在一些可能实现的方式中，上述步骤01可以包括：先在硅片10的表面沉积厚度为10nm～300nm的二氧化硅薄膜(即SiO 2薄膜)；然后对SiO 2薄膜进行光刻，形成掩膜图案层20。该掩膜图案层20中包括阵列分布(如四方对称阵列分布)的多个圆柱形的SiO 2掩膜图案(21)；圆柱形的SiO 2掩膜图案(21)的直径可以为1μm～2μm，相邻两个圆柱形的SiO 2掩膜图案之间的距离可以在1μm～3μm。
也就是说，通过步骤01可以得到表面覆盖有多个掩膜图案21的硅片10。
步骤02、参考图8中(b)所示，采用四甲基氢氧化铵(tetramethylammonium hydroxide，TMAH)溶液，对形成有掩膜图案层20的硅片10表面进行刻蚀，以得到在对应掩膜图案21的位置形成有纳米凸起结构12的硅衬底1，并且该纳米凸起结构12具有多种不同倾斜角的侧壁。
示意的，在一些可能实现的方式中，上述步骤02可以包括：采用质量浓度为1％～20％的TMAH溶液，在温度40℃～100℃的条件下，对形成有掩膜图案21的硅片10表面进行2min～20min刻蚀，以得到在对应掩膜图案21的位置形成有纳米凸起结构12的硅衬底1。
示例的，上述步骤02的刻蚀条件中，TMAH溶液的浓度可以为1wt％、3wt％、5wt％、8wt％、15wt％、20wt％；刻蚀温度可以为40℃、50℃、60℃、80℃、100℃；刻蚀时间可以为2min、10min、15min、20min，从而在硅衬底1的表面形成三维尺寸(即长、宽、高方向上的尺寸)均处于200nm～800nm的范围内的纳米凸起结构12。
示意的，在一些可能实现的方式中，上述步骤02可以包括：将前述步骤01中形成的表面覆盖有多个掩膜图案21的硅片10放置在聚四氟乙烯花篮中，然后浸入1wt％～20wt％的TMAH的水溶液中，并调整温度至40℃～100℃，进行刻蚀2min～20min，得到表面形成有纳米凸起结构12的硅衬底1；并且该纳米凸起结构12的侧壁分为多层，每一层侧壁的倾斜角不同，当然位于同层侧壁的倾斜角可以相同或者大致相同。
此处可以理解的是的，通过控制步骤02中刻蚀条件不同，如TMAH溶液的浓度、刻蚀温度、刻蚀时间中至少一个条件不同，即可获得不同形状结构的纳米凸起结构12。例如，在一些可能实现的方式中，可以设定刻蚀时间设定为20min，从而形成图3中示出的顶部为纳米棱锥a2，下部为纳米棱锥台a1结构的纳米凸起结构12结构。在一些可能实现的方式中，可以设置刻蚀时间设定为10min，从而形成图4中示出的三叠层纳米棱锥台结构。
此处需要说明的是，根据形成的纳米凸起结构12结构的不同，可以对该半导体器件的制作方法进行适当的调整。
例如，对于通过步骤02形成图3中示出的顶部为纳米棱锥a2的纳米凸起结构12而言，步骤01中形成的掩膜图案21在形成纳米凸起结构12的过程中会自动脱落，从而也就无需单独设置去除掩膜图案21的工艺。
又例如，对于通过步骤02中形成如图4中示出的顶部为纳米棱锥台b3的纳米凸起结构12而言，步骤01中形成的掩膜图案21可能会保留在纳米凸起结构12的顶部。在此情况下，可以在步骤02之后，通过工艺去除位于纳米凸起结构12顶部的掩膜图案21。
示意的，在一些可能实现的方式中，上述去除位于纳米凸起结构12顶部的掩膜图案21的工艺可以包括：将保留有前述的掩膜图案21(如前述的圆柱形的SiO 2掩膜图案)的硅衬底1置于HF(氢氟酸)溶液中，通过HF溶液对掩膜图案21进行刻蚀(如刻蚀时间可以为0.5min～10min)，再用去离子水冲洗并用氮气吹干，从而得到表面仅保留纳米凸起结构12的硅衬底1。
步骤03、参考图8中(b)所示，采用氮化物在形成有纳米凸起结构12的硅衬底1表面，依次形成形核层2和外延层3。
示意的，在一些可能实现的方式中，上述步骤03可以包括：采用金属有机气相外延方法(MOVPE)或溅射方法在形成有纳米凸起结构12的硅衬底1表面，形成厚度为5nm～200nm的低温氮化物形核层2(如AlN薄膜层)；然后，采用金属有机气相外延方法(MOVPE)高温外延生长厚度为0.3μm～10μm的氮化物外延层3(如GaN薄膜层)；示意的，高温外延生长GaN晶体的相关生长参数可以是：衬底温度为1000～1140℃，三甲基镓流量：5～100sccm；NH 3气体流量为1000～8000sccm；载气为N 2/H 2/Ar。
综上所述，采用本申请实施例提供的半导体器件的制作方法，一方面，通过掩膜结合湿法刻蚀的方式形成纳米凸起结构，并该纳米凸起结构的侧壁具有多种不同的倾斜角，这样一来，避免了采用传统的干法刻蚀、纳米压印、电子束刻蚀(electron beam lithography，EBL)等昂贵的纳米制程工艺，也即工艺简单，价格低廉；同时形成的纳米凸起结构的侧壁角度多变，能够使得后续生长的氮化物膜层的位错弯曲，有助于氮化物膜层应力的释放，进而降低了外延层的位错密度，提升了外延层中氮化物晶体质量，抑制了外延层出现表面龟裂现象、晶圆翘曲、厚度不均等问题；另一方面，在纳米凸起结构的表面外延生长氮化物膜层(形核层和外延层)，通过纳米级厚度的氮化物膜层即可覆盖纳米凸起结构，无需外延生长微米级厚度氮化物膜层，进而提高了氮化物膜层的外延生长效率低，降低了半导体器件的成本。
当然，在步骤03之后，根据实际半导体器件的需要，对应制作其他的膜层结构即可；以GaN晶体管(即GaN HEMT)为例，在步骤03之后可以包括制作源漏层、栅极层、表面钝化层等膜层，具体可以参考相关技术进行制作即可，此处不再赘述。
另外，关于上述半导体器件的制作方法实施例中的其他相关内容，如纳米凸起结构的形状及侧壁倾斜角等，可以对应参考前述半导体器件实施例中对应的部分，此处不再赘述；关于前述半导体器件实施例中相关的结构，可以对应参考上述半导体器件的制作方法实施例对应制作方法，也可以结合相关技术进行适当的调整进行制作，本申请对此不做限制。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种半导体器件，其特征在于，包括：
    硅衬底；所述硅衬底包括基底以及位于所述基底表面分散设置的多个纳米凸起结构，所述纳米凸起结构的侧壁具有多种不同的倾斜角；
    形核层和外延层；所述形核层和所述外延层依次设置于所述硅衬底具有所述纳米凸起结构一侧的表面，且所述形核层和所述外延层中均包括氮化物材料。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述纳米凸起结构的侧壁分为多层，且每一层侧壁的倾斜角不同。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，
    所述基底与所述纳米凸起结构为一体结构。
  4. 根据权利要求1-3任一项所述的半导体器件，其特征在于，
    所述基底表面分散设置的多个纳米凸起结构呈阵列排布。
  5. 根据权利要求1-4任一项所述的半导体器件，其特征在于，
    所述纳米凸起结构包括纳米棱锥台以及位于所述纳米棱锥台顶部的纳米棱锥；所述纳米棱锥台与所述基底连接；
    所述纳米棱锥的侧壁倾斜角大于所述纳米棱锥台的侧壁倾斜角。
  6. 根据权利要求5所述的半导体器件，其特征在于，
    所述纳米棱锥的侧壁倾斜角为60°～85°。
  7. 根据权利要求1-4任一项所述的半导体器件，其特征在于，
    所述纳米凸起结构包括：叠层设置的第一纳米棱锥台、第二纳米棱锥台、第三纳米棱锥台；其中，所述第一纳米棱锥台与所述基底连接；
    所述第二纳米棱锥台的侧壁倾斜角大于所述第一纳米棱锥台的侧壁倾斜角，所述第三纳米棱锥台为倒棱锥台结构；
    所述第三纳米棱锥台在所述基底上的投影位于所述第一纳米棱锥台在所述基底上的投影内部。
  8. 根据权利要求1-7任一项所述的半导体器件，其特征在于，
    所述形核层采用AlN、GaN中的至少一种；
    所述外延层采用AlN、GaN、AlGaN中的至少一种。
  9. 一种半导体器件的制作方法，其特征在于，包括：
    在硅片的表面形成掩膜图案层；所述掩膜图案层中包括多个分散的掩膜图案；
    采用四甲基氢氧化铵溶液，对形成有所述掩膜图案层的硅片表面进行刻蚀，以得到在对应多个所述掩膜图案的位置分别形成有纳米凸起结构的硅衬底；其中，所述纳米凸起结构具有多种不同倾斜角的侧壁；
    采用氮化物在形成有所述纳米凸起结构的硅衬底表面依次形成形核层和外延层。
  10. 根据权利要求9所述的半导体器件的制作方法，其特征在于，
    所述采用四甲基氢氧化铵溶液，对形成有所述掩膜图案层的硅片表面进行刻蚀包括：
    采用质量浓度为1％～20％的四甲基氢氧化铵溶液，在温度40℃～100℃的条件下，对形成有所述掩膜图案的硅片表面进行2min～20min刻蚀。
  11. 根据权利要求9或10所述的半导体器件的制作方法，其特征在于，在所述采用氮化物在形成有所述纳米凸起结构的硅衬底表面依次形成形核层和外延层之前，所述制作方法还包括：
    去除位于所述纳米凸起结构顶部的掩膜图案。
  12. 一种终端设备，其特征在于，包括印刷线路板以及如权利要求1-8任一项所述的半导体器件；所述半导体器件与所述印刷线路板连接。
PCT/CN2021/071483 2021-01-13 2021-01-13 半导体器件及其制作方法、终端设备 WO2022151045A1 (zh)

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CN110797442A (zh) * 2018-08-02 2020-02-14 东莞市中图半导体科技有限公司 一种图形化衬底、led外延片及图形化衬底制备方法
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