WO2021215505A1 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- WO2021215505A1 WO2021215505A1 PCT/JP2021/016326 JP2021016326W WO2021215505A1 WO 2021215505 A1 WO2021215505 A1 WO 2021215505A1 JP 2021016326 W JP2021016326 W JP 2021016326W WO 2021215505 A1 WO2021215505 A1 WO 2021215505A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000002184 metal Substances 0.000 claims abstract description 65
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 38
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 abstract 4
- 230000000052 comparative effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.
- an insulating film is formed on the surface of the semiconductor layer having a trench, and a conductor is embedded in the trench.
- the insulating film on the surface of the semiconductor layer adjacent to the trench is removed by etching to expose the surface of the semiconductor layer, and a Schottky junction is formed on the surface of the semiconductor layer.
- a semiconductor device includes a semiconductor layer having a trench, an insulating film covering the inner surface of the trench, a conductor embedded in the trench covered with the insulating film, and the trench.
- the VDD layer forming a Schottky junction with the surface of the adjacent semiconductor layer and the end surface of the VDD layer located above the upper end surface of the insulating film covering the inner wall surface of the trench are continuous to the upper end surface of the insulating film.
- a metal layer for covering the metal layer is provided.
- the metal layer has a metal element of the same type as the metal element constituting the silicide layer.
- an insulating film is formed on the surface of a semiconductor layer having a trench, a conductor is embedded in the trench, and an insulating film on the surface of the semiconductor layer adjacent to the trench is formed.
- This is a method for manufacturing a semiconductor device in which a semiconductor layer is exposed by removing it by etching to form a Schottky junction in the semiconductor layer. Then, in the etching, the upper end surface of the insulating film covering the inner wall surface of the trench is lowered from the surface of the semiconductor layer.
- the metal layer In the formation of the Schottky junction, the metal layer is brought into contact with the surface of the semiconductor layer, and the metal layer is heat-treated to form a silicide layer by the reaction between the metal layer and the semiconductor layer.
- the interface of the semiconductor layer is the Schottky junction.
- a portion of the metal layer that covers at least the end surface of the silicide layer to the upper end surface of the insulating film is continuously left.
- the semiconductor device A1 of the embodiment of the present disclosure includes a semiconductor layer 11 having a trench 10, an insulating film 12, a conductor 13, a silicide layer 14, and a metal layer 15. , A top electrode 16 is provided.
- the insulating film 12 covers the inner surface 10a of the trench 10.
- the conductor 13 is embedded in the trench 10 covered with the insulating film 12.
- the silicide layer 14 forms a Schottky junction with the semiconductor layer surface 11a adjacent to the trench 10.
- the metal layer 15 continuously covers from the end surface 14a of the silicide layer 14 located above the upper end surface 12a of the insulating film 12 covering the inner wall surface 10a1 of the trench 10 to the upper end surface 12a of the insulating film 12.
- the conductor 13 for example, polysilicon may be applied.
- the semiconductor layer 11 are silicon
- the insulating film 12 is a silicon oxide film.
- the top electrode 16 for example, aluminum is applied.
- the silicide layer 14 is a silicide layer formed by the reaction between the semiconductor layer 11 and the metal layer 15.
- nickel silicide may be applied.
- the metal layer 15 covers the side surface 11b of the semiconductor layer 11 located above the upper end surface 12a of the insulating film 12. That is, the semiconductor layer surface 11a corresponding to the Schottky junction with the silicide layer 14 is located above the upper end surface 12a of the insulating film 12. Therefore, the side surface 11b of the semiconductor layer 11 continuous with the semiconductor layer surface 11a is located between the silicide layer 14 and the upper end surface 12a of the insulating film 12. If there is no metal layer 15, the side surface 11b of the semiconductor layer 11 comes into direct contact with the top electrode 16. Therefore, when a reverse voltage is applied, a current passing through the side surface 11b is generated, so that the leakage current becomes large.
- the side surface 11b of the semiconductor layer 11 is covered with the metal layer 15. Therefore, the side surface 11b of the semiconductor layer 11 does not come into direct contact with the top surface electrode 16.
- the metal layer 15 has a metal element of the same type as the metal element constituting the silicide layer 14 forming the Schottky junction.
- the metal layer 15 which is the same kind of metal as the Schottky joint constituent metal has a protective effect. That is, the side surface 11b is isolated from the top electrode 16 such as aluminum by the metal layer 15. As a result, it is possible to suppress the generation of a current passing through the side surface 11b when a reverse voltage is applied, and to suppress the leakage current to a low level.
- the upper surface electrode 16 is in contact with the upper surface of the VDD layer 14 via the opening of the metal layer 15. As a result, the VDD layer 14 forming the Schottky junction and the upper surface electrode 16 can be directly electrically connected.
- the insulating film 12 of the semiconductor layer surface 11a adjacent to the trench 10 is removed by etching to expose the surface 11c of the semiconductor layer 11 as shown in FIG.
- the insulating film 12 is overetched in order to sufficiently expose the semiconductor layer surface 11c.
- the upper end surface 12a of the insulating film 12 covering the inner wall surface 10a1 of the trench 10 is etched deeper. That is, the upper end surface 12a of the insulating film 12 covering the inner wall surface 10a1 of the trench 10 is lowered from the semiconductor layer surface 11c. As shown in FIG. 4, the upper end surface 12a is located below the semiconductor layer surface 11c.
- the insulating film on the semiconductor layer surface 11c is sufficiently removed.
- the upper and lower sides are in the direction in which the trench 10 is dug down from the surface of the semiconductor layer 11 is downward, and vice versa. It does not mean the vertical direction (gravity direction) during use.
- a metal layer 15 is formed on the semiconductor layer surface 11c, the upper end surface 12a of the insulating film 12, and the upper surface 13a of the conductor 13, and the metal layer 15 is brought into contact with the semiconductor layer surface 11c. Then, by heat-treating to form the silicide layer 14 by the reaction between the metal layer 15 and the semiconductor layer 11, as shown in FIG. 6, the interface between the silicide layer 14 and the semiconductor layer 11, that is, the semiconductor layer surface 11a is formed. Schottky joint is used.
- the portion of the metal layer 15 that covers the upper surface of the silicide layer 14 is removed to form an opening. After that, the upper surface electrode 16 in contact with the upper surface of the silicide layer 14 is formed through the opening.
- the metal layer 15 is also left on the upper surface 13a of the conductor 13, but this may be removed.
- FIG. 7 and 8 show a semiconductor device B1 of a comparative example.
- the semiconductor device B1 of the comparative example has no metal layer 15 as compared with the semiconductor device A1 of the present embodiment, and the upper surface electrode 16 is in contact with the silicide layer 14, the upper end surface 12a of the insulating film 12, and the upper surface 13a of the conductor 13. It differs only in that it does, and the others are common.
- Such a semiconductor device B1 can be manufactured by removing all of the metal layer 15 before the upper surface electrode forming step, as compared with the manufacturing method of the present embodiment.
- the semiconductor device A1 of the present embodiment and the semiconductor device B1 of the comparative example were simulated by designating common conditions, and the results were as shown in FIG. As shown in FIG. 9, the semiconductor device A1 of the present embodiment can suppress the reverse current to be lower than that of the semiconductor device B1 of the comparative example, and the reverse direction characteristics are improved. It was confirmed that the leakage current can be suppressed low by the protective effect of the metal layer 15 described above.
- the leakage current at the edge of the Schottky junction can be suppressed low when a reverse voltage is applied due to the protection effect of the metal layer 15. Further, the insulating film on the surface 11c of the semiconductor layer is sufficiently removed, and the device characteristics are good. According to the above-mentioned manufacturing method of the embodiment of the present disclosure, it is possible to manufacture a semiconductor device capable of suppressing a low leakage current when a reverse voltage is applied due to the protective effect of the metal layer 15. Further, in the manufactured semiconductor device, the insulating film on the semiconductor layer surface 11c is sufficiently removed, and the device characteristics are good.
- the metal layer 15 is opened on the VDD layer 14, and the VDD layer 14 and the upper surface electrode 16 are directly connected to each other.
- a structure may be implemented in which the silicide layer 14 and the upper surface electrode 16 are electrically connected via the metal layer 15. In that case, the step of opening the metal layer 15 is unnecessary.
- the side surface 11b of the semiconductor layer 11 is located between the silicide layer 14 and the upper end surface 12a of the insulating film 12.
- the peripheral portion (from the end surface 14a to the upper end surface 12a) of the Schottky junction is formed by the metal layer 15. Covering it has the effect of suppressing leakage current.
- the upper end surface 12a of the insulating film 12 may be at the same depth as or slightly above the semiconductor layer surface 11a, and the insulating film 12 may cover only the lower portion of the end surface 14a and not the upper portion.
- the present disclosure is not limited to the case where the side surface 11b of the semiconductor layer 11 is located between the silicide layer 14 and the upper end surface 12a of the insulating film 12.
- the side surface 11b of the semiconductor layer 11 is located between the silicide layer 14 and the upper end surface 12a of the insulating film 12.
- the effect of suppressing the leak current is remarkable according to the present invention.
- the ⁇ rice field In the above embodiment, the ⁇ rice field. However, it goes without saying that the same effect can be obtained even if the metal layer 15 is removed and then a metal layer made of the same kind of metal element is formed again to form the metal layer 15. However, according to the above embodiment, the number of steps is small, the production efficiency is good, and the metal layer for forming the silicide layer 14 is effectively used, so that the material is not wasted and it is economical.
- the present disclosure can be used for semiconductor devices and methods for manufacturing semiconductor devices.
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Abstract
Description
〔半導体装置〕
図1及び図2よって示すように本開示の一実施形態の半導体装置A1は、トレンチ10を有した半導体層11と、絶縁膜12と、導電体13と、シリサイド層14と、金属層15と、上面電極16とを備える。絶縁膜12は、トレンチ10の内面10aを覆う。導電体13は、絶縁膜12で覆われたトレンチ10内に埋設されている。シリサイド層14は、トレンチ10に隣接した半導体層表面11aとショットキー接合を形成する。金属層15は、トレンチ10の内壁面10a1を覆う絶縁膜12の上端面12aより上に位置するシリサイド層14の端面14aから当該絶縁膜12の上端面12aまでを連続して覆う。 導電体13としては、例えばポリシリコンを適用してもよい。半導体層11は、シリコン、絶縁膜12はシリコン酸化膜が例として挙げられる。上面電極16としては、例えばアルミニウムが適用される。
シリサイド層14は、半導体層11と金属層15との反応によるシリサイド層である。シリサイド層14としては、例えばニッケルシリサイドを適用してもよい。
仮に、金属層15が無い場合、半導体層11の側面11bが上面電極16に直接接触してしまう。そのため、逆電圧印加時に側面11bを通る電流が生じることで、リーク電流が大きくなる。
本実施形態の半導体装置A1によれば、金属層15により半導体層11の側面11bを覆っている。そのため、半導体層11の側面11bが上面電極16に直接接触してしまうことはない。金属層15は、ショットキー接合を形成するシリサイド層14を構成する金属元素と同種の金属元素を有している。このようなショットキー接合構成金属と同種金属である金属層15によりプロテクト効果がある。すなわち、アルミニウム等の上面電極16から側面11bを金属層15により隔絶する。これにより、逆電圧印加時に側面11bを通る電流の発生を抑えて、リーク電流を低く抑えることができる。
上記の半導体装置A1を得るための一例の製造方法につき説明する。
(絶縁膜形成、導電体埋設工程)
まず、図3に示すようにトレンチ10を有した半導体層11の表面に絶縁膜12を形成し、当該トレンチ10内に導電体13を埋め込む。導電体13の上面13aをトレンチ10内に収める。
次に、トレンチ10に隣接した半導体層表面11aの絶縁膜12をエッチングにより除去して図4に示すように半導体層11の表面11cを露出させる。このとき、半導体層表面11cを十分に露出させるために絶縁膜12がオーバーエッチされる。これにより、トレンチ10の内壁面10a1を覆う絶縁膜12の上端面12aがより深くエッチングされる。すなわち、トレンチ10の内壁面10a1を覆う絶縁膜12の上端面12aを、半導体層表面11cより下げる。図4に示すように半導体層表面11cより上端面12aが下に位置する。この場合、半導体層表面11c上の絶縁膜は十分に除去される。なお、本半導体装置及びその製造方法の説明においての上下は、半導体層11の表面からトレンチ10が掘り下がっている方向が下、その逆を上とするものであり、本半導体装置の製造時又は使用時の上下方向(重力方向)を言うものではない。
その後、図5に示すように半導体層表面11c、絶縁膜12の上端面12a及び導電体13の上面13a上に金属層15を形成し、半導体層表面11cに金属層15を接触させる。その上で、熱処理して図6に示すように金属層15と半導体層11との反応によるシリサイド層14を形成することで、シリサイド層14と半導体層11の界面、すなわち、半導体層表面11aをショットキー接合とする。
次に、金属層15を開口した後、上面電極16としてアルミニウム等をシリサイド層14及び金属層15の上に形成し図1、図2に示した構造の半導体装置A1を得る。その他必要な工程を実施して半導体装置A1を完成させる。
本工程において金属層15については、少なくともシリサイド層14の端面14aから絶縁膜12の上端面12aまでを覆う部分を連続して残す。すなわち、ショットキー接合の形成後、金属層15のシリサイド層14の端面14aから絶縁膜12の上端面12aまでを覆う部分(本実施形態では側面11bを覆う部分が含まれる)を連続して残しつつ、金属層15のシリサイド層14の上面を覆う部分を除去して開口部を形成する。その後、当該開口部を介してシリサイド層14の上面に接する上面電極16を形成する。
本実施形態では、導電体13の上面13a上についても金属層15を残すが、これを除去してもよい。
図7及び図8は、比較例の半導体装置B1を示す。比較例の半導体装置B1は、上記本実施形態の半導体装置A1に対して、金属層15が無く、上面電極16がシリサイド層14、絶縁膜12の上端面12a及び導電体13の上面13aに接触している点でのみ異なり、その他は共通である。このような半導体装置B1は、上記本実施形態の製造方法に対して、上面電極形成工程前に金属層15の全部を除去することで製造できる。
本実施形態の半導体装置A1及び比較例の半導体装置B1に関し、共通の条件を指定して逆方向の電圧‐電流特性をシミュレーションしたところ図9に示す通りとなった。
図9に示すように本実施形態の半導体装置A1は、比較例の半導体装置B1に対して逆方向電流を低く抑えることができ、逆方向特性が改善した。
上述した金属層15のプロテクト効果によりリーク電流を低く抑えることができると確認できた。
以上の本開示の実施形態の半導体装置によれば、金属層15のプロテクト効果により、逆電圧印加時にショットキー接合の縁部でのリーク電流を低く抑えることができる。
また、半導体層表面11c上の絶縁膜が十分に除去されており、デバイス特性が良好である。
以上の本開示の実施形態の製造方法によれば、金属層15のプロテクト効果により、逆電圧印加時のリーク電流を低く抑えることができる半導体装置を製造することができる。
また製造される半導体装置は、半導体層表面11c上の絶縁膜が十分に除去されており、デバイス特性が良好である。
上記実施形態にあっては、シリサイド層14上で金属層15を開口し、シリサイド層14と上面電極16とを直接接続した。しかし、シリサイド層14と上面電極16とが金属層15を介して電気的に接続する構造を実施してもよい。その場合、金属層15を開口する工程は不要である。
例えば、絶縁膜12の上端面12aが半導体層表面11aと同じ深さ位置、又はわずかに上であって、絶縁膜12が端面14aの下部のみしか覆わず、上部を覆わない場合がある。この場合にも、絶縁膜12によるショットキー接合の周縁部の被覆保護が不十分となりリーク電流が増大する要因となる。このような場合にも、ショットキー接合の周縁部(端面14aから上端面12aまで)を金属層15で覆うことで、リーク電流を抑える効果がある。
したがって、本開示は、半導体層11の側面11bがシリサイド層14と絶縁膜12の上端面12aとの間に位置する場合に限られない。但し、半導体層11の側面11bがシリサイド層14と絶縁膜12の上端面12aとの間に位置する場合には、本発明によりリーク電流を抑える効果が顕著である。
11 半導体層
11a 半導体層表面
12 絶縁膜
13 導電体
14 シリサイド層
15 金属層
16 上面電極
A1 半導体装置
Claims (6)
- トレンチを有した半導体層と、
前記トレンチの内面を覆う絶縁膜と、
前記絶縁膜で覆われた前記トレンチ内に埋設された導電体と、
前記トレンチに隣接した半導体層表面とショットキー接合を形成するシリサイド層と、
前記トレンチの内壁面を覆う前記絶縁膜の上端面より上に位置する前記シリサイド層の端面から当該絶縁膜の上端面までを連続して覆う金属層と、
を備え、
前記金属層は、前記シリサイド層を構成する金属元素と同種の金属元素を有する半導体装置。 - 前記シリサイド層は、前記半導体層と前記金属層との反応によるシリサイド層である請求項1に記載の半導体装置。
- 前記金属層は、前記絶縁膜の上端面より上に位置する前記半導体層の側面を覆う請求項1又は請求項2に記載の半導体装置。
- 前記金属層の開口部を介して前記シリサイド層の上面に接する上面電極を備える請求項1から請求項3のうちいずれか一に記載の半導体装置。
- トレンチを有した半導体層の表面に絶縁膜を形成し、当該トレンチ内に導電体を埋め込み、当該トレンチに隣接した半導体層表面の絶縁膜をエッチングにより除去して半導体層を露出させ、前記半導体層にショットキー接合を形成する半導体装置の製造方法であって、
前記エッチングにおいては、前記トレンチの内壁面を覆う絶縁膜の上端面を、前記半導体層表面より下げ、
前記ショットキー接合の形成においては、前記半導体層表面に金属層を接触させて形成し、熱処理して当該金属層と前記半導体層との反応によるシリサイド層を形成することで、当該シリサイド層と前記半導体層の界面を前記ショットキー接合とし、
前記ショットキー接合の形成後、前記金属層の少なくとも前記シリサイド層の端面から当該絶縁膜の上端面までを覆う部分を連続して残す半導体装置の製造方法。 - 前記ショットキー接合の形成後、前記金属層の前記シリサイド層の端面から当該絶縁膜の上端面までを覆う部分を連続して残しつつ、前記金属層の前記シリサイド層の上面を覆う部分を除去して開口部を形成し、
その後、前記開口部を介して前記シリサイド層の上面に接する上面電極を形成する請求項5に記載の半導体装置の製造方法。
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WO2012083230A2 (en) * | 2010-12-17 | 2012-06-21 | Diodes Zetex Semiconductors Limited | High efficiency rectifier |
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TW201442253A (zh) * | 2013-04-19 | 2014-11-01 | Economic Semiconductor Corp | 半導體裝置及其終端區結構 |
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JP2008034572A (ja) * | 2006-07-28 | 2008-02-14 | Matsushita Electric Ind Co Ltd | 半導体装置とその製造方法 |
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