WO2021213036A1 - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2021213036A1
WO2021213036A1 PCT/CN2021/079709 CN2021079709W WO2021213036A1 WO 2021213036 A1 WO2021213036 A1 WO 2021213036A1 CN 2021079709 W CN2021079709 W CN 2021079709W WO 2021213036 A1 WO2021213036 A1 WO 2021213036A1
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Prior art keywords
signal
area
display
circuit
signal line
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PCT/CN2021/079709
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English (en)
French (fr)
Inventor
孙泽鹏
张勇
秦相磊
王建
李彦辰
林坚
张丽敏
杨智超
唐亮珍
段智龙
安亚帅
乜玲芳
金红贵
田丽
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/764,448 priority Critical patent/US11927844B2/en
Publication of WO2021213036A1 publication Critical patent/WO2021213036A1/zh

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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • Liquid crystal display panels are widely used in the display field due to their many advantages such as energy saving, low radiation and high definition.
  • the array substrate in the liquid crystal display panel generally includes: a base substrate having a display area and a non-display area, a gate drive circuit located in the non-display area, and a gate drive circuit located in the non-display area and connected to the gate drive circuit.
  • Multiple signal lines are generally located in the packaging area for coating the frame sealant included in the non-display area, so the multiple signal lines are generally covered by the frame sealant.
  • the via holes used to electrically connect the multiple signal lines and the gate driving circuit will also be covered by the encapsulant.
  • the present disclosure provides a display substrate, a manufacturing method thereof, and a display device.
  • the technical solutions are as follows:
  • a display substrate is provided, and the display substrate includes:
  • a base substrate has a display area and a non-display area surrounding the display area, the non-display area includes a peripheral area and an encapsulation area sequentially arranged in a direction away from the display area, the package Encapsulating glue is coated in the area;
  • a gate drive circuit the gate drive circuit is located in the non-display area
  • a plurality of first signal lines, the plurality of first signal lines are located in the peripheral area, and the plurality of first signal lines are connected to the gate driving circuit;
  • a plurality of second signal lines, the plurality of second signal lines are located in the non-display area, and the plurality of second signal lines are connected to the gate driving circuit;
  • the first signal line and the second signal line are both used to provide signals for the gate drive circuit, and the frequency of the signal provided by the first signal line is lower than that provided by the second signal line. The frequency of the signal.
  • the first signal line includes: a DC power line for providing a DC power signal.
  • the first signal line includes: a start signal line for providing a start driving signal.
  • the second signal line includes: a clock signal line for providing a clock signal.
  • the gate driving circuit includes: an input sub-circuit, an output sub-circuit, a pull-down sub-circuit, and a reset sub-circuit;
  • the input sub-circuit is respectively connected to the input signal terminal, the first power line, and the pull-up node, and is configured to output to the pull-up node the input signal provided by the first power line in response to the input signal provided by the input signal terminal.
  • the first power signal ;
  • the output sub-circuit is respectively connected to the pull-up node, the clock signal line and the output terminal, and is configured to output the clock signal provided by the clock signal line to the output terminal in response to the potential of the pull-up node;
  • the pull-down sub-circuit is connected to the second power line, the third power line, the fourth power line, the pull-up node, and the output terminal, respectively, and the pull-down sub-circuit is configured to respond to the potential of the pull-up node ,
  • the second power signal provided by the second power line and the third power signal provided by the third power line respectively output the fourth power signal provided by the fourth power line to the pull-up node and the output terminal Power signal
  • the reset sub-circuit is connected to a reset signal terminal, a start signal line, a fifth power line, the fourth power line, and the pull-up node, respectively, and the reset sub-circuit is configured to provide in response to the reset signal terminal Reset signal for outputting the fifth power signal provided by the fifth power line to the pull-up node; The fourth power signal.
  • the first signal line includes: one of the first power line, the second power line, the third power line, the fourth power line, and the fifth power line Or more.
  • the display substrate further includes: a transistor device layer on the base substrate;
  • the transistor device layer is used to form a plurality of thin film transistors included in the gate driving circuit, and a via hole is provided in the transistor device layer, and the via hole is used to connect the gate layer in the transistor device layer And source and drain layer.
  • the display substrate includes: a plurality of the gate driving circuits cascaded sequentially;
  • the number of the via holes provided in the region where each gate drive circuit is located is smaller than the number of thin film transistors included in the gate drive circuit.
  • each of the gate drive circuits includes eleven thin film transistors; and each of the gate drive circuits is provided with ten vias in the region.
  • one via hole is located in the packaging area, and the remaining via holes are located in the peripheral area.
  • the plurality of second signal lines are located in the peripheral area.
  • the plurality of second signal lines are located in the packaging area.
  • a method for manufacturing a display substrate for manufacturing the display substrate as described in the above aspect, and the method includes:
  • a base substrate is provided, the base substrate has a display area and a non-display area surrounding the display area, the non-display area includes a peripheral area and an encapsulation area sequentially arranged in a direction away from the display area, the The packaging area is coated with packaging glue;
  • the first signal line and the second signal line are both used to provide signals for the gate drive circuit, and the frequency of the signal provided by the first signal line is lower than that provided by the second signal line. The frequency of the signal.
  • a display device comprising: a signal providing circuit, and the display substrate as described in the foregoing aspect;
  • the signal providing circuit is connected to a signal line included in the display substrate, and is used to provide a driving signal to the signal line.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by one or more embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of a gate driving circuit provided by one or more embodiments of the present disclosure
  • FIG. 3 is a schematic structural diagram of another gate driving circuit provided by one or more embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another display substrate provided by one or more embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a transistor device layer provided by one or more embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of yet another display substrate provided by one or more embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by one or more embodiments of the present disclosure.
  • FIG. 8 is a flowchart of a manufacturing method of a display substrate provided by one or more embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display device provided by one or more embodiments of the present disclosure.
  • product tests are generally performed on each component included in the display device under a specific temperature and humidity environment before the display device is shipped.
  • a product reliability test performed on the display substrate included in the display device in an 85% humidity environment at 85 degrees Celsius (°C) may also be referred to as 8585 reliability verification.
  • the display substrate is prone to cross-stripe defects due to via corrosion, which is generally manifested as a conductive film layer made of indium tin oxide (ITO) material, that is, the ITO conductive film layer is white.
  • via corrosion is generally caused by moisture ingress due to poor sealing.
  • the ITO conductive film layer when the ITO conductive film layer is connected to the cathode, if water vapor enters, the ITO conductive film layer is prone to electrochemical corrosion reaction to generate elemental indium (In), which is generally white. After being changed to In, the sheet resistance of the ITO conductive film layer will become larger, resulting in a larger resistance at the position where the via is used to bridge the signal line. If it is operated in a high temperature and high humidity environment for a long time, the heat at the via hole will become larger and larger, which will eventually cause the via hole to be corroded and burned. Moreover, the efficiency and degree of via corrosion are positively correlated with the absolute value of the cathode voltage. That is, if the absolute value of the cathode voltage is larger, the via hole corrosion is faster and more serious.
  • FIG. 1 is a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 1, the display substrate may include:
  • the base substrate 01 may have a display area A1 and a non-display area A2 surrounding the display area A1.
  • the display area A1 is provided with a plurality of pixels arranged in an array.
  • the non-display area A2 may include a peripheral area A21 and an encapsulation area A22 arranged in a direction away from the display area A1, and the encapsulation area A22 may be coated with an encapsulation glue (not shown in FIG. 1).
  • the gate driving circuit 02 may be located in the non-display area A2.
  • the gate driving circuit 02 can be used to provide gate driving signals for one or more rows of pixels in the display area A1.
  • the gate driving circuit 02 shown therein is partially located in the peripheral area A21 included in the non-display area A2, and partially located in the package area A22 included in the non-display area A2.
  • first signal lines 03 There are a plurality of first signal lines 03, the plurality of first signal lines 03 may be located in the peripheral area A21, and the plurality of first signal lines 03 may be connected to the gate driving circuit 02.
  • the plurality of second signal lines 04 may be located in the non-display area A2, and the plurality of second signal lines 04 may be connected to the gate driving circuit 02.
  • the plurality of second signal lines 04 shown therein are all located in the packaging area A22 included in the non-display area A2.
  • the first signal line 03 and the second signal line 04 can both be used to provide signals for the gate driving circuit 02, and the frequency of the signal provided by the first signal line 03 can be lower than that provided by the second signal line 04
  • the frequency of the signal may be a low-frequency signal line
  • the second signal line 04 may be a high-frequency signal line.
  • Low-frequency signal lines refer to signal lines with a low frequency range, slow signal changes and relatively smooth waveforms
  • high-frequency signal lines refer to signal lines with high frequency ranges, rapid signal changes, and waveforms that are prone to sudden changes.
  • the embodiment of the present disclosure arranges the low-frequency signal line in the non-encapsulating adhesive coating area to avoid the poor packaging of the encapsulating adhesive.
  • the embodiments of the present disclosure provide a display substrate, which includes a base substrate having a display area and a non-display area, a gate drive circuit, and a first signal line and a gate drive circuit connected to the gate drive circuit.
  • the non-display area includes an encapsulation area coated with an encapsulation glue and a peripheral area. Since the first signal line for providing a signal with a lower frequency is located in the peripheral area and not in the packaging area, the first signal line will not be covered by the packaging glue. As a result, it is possible to avoid the problem of water vapor entering the packaging area due to poor packaging, causing the vias to be corroded due to the influence of the low-frequency signal line.
  • the display substrate provided by the embodiments of the present disclosure has a higher yield and a better display effect.
  • the gate drive circuit 02 in order to drive the gate drive circuit 02 to work normally, the gate drive circuit 02 generally needs to be connected to a DC power line for providing a DC power signal, a clock signal line for providing a clock signal, and/or a clock signal line for providing a The start signal line of the start drive signal is connected.
  • the clock signal line belongs to the high-frequency signal line with respect to the DC power line and the start signal line, that is, the DC power line and the start signal line can be divided into low-frequency signal lines. Therefore, in the embodiment of the present disclosure, the first signal line 03 may include a DC power line and/or a start signal line.
  • the second signal line 04 may include: a clock signal line.
  • FIG. 2 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit 02 may include: an input sub-circuit 021, an output sub-circuit 022, a pull-down sub-circuit 023, and a reset sub-circuit 024.
  • the input sub-circuit 021 may be connected to the input signal terminal IN, the first power line VDS, and the pull-up node PU, respectively.
  • the input sub-circuit 021 can be used to pull up the node PU to output the first power signal provided by the first power line VDS in response to the input signal provided by the input signal terminal IN.
  • the first power signal may be a DC power signal, and the potential of the first power signal may be an effective potential.
  • the first power signal may be a non-DC power signal, and only when the potential of the input signal is an effective potential, the potential of the first power signal is an effective potential.
  • the input sub-circuit 021 may output the first power signal at the effective potential to the pull-up node PU when the potential of the input signal provided by the input signal terminal IN is the effective potential, so as to charge the pull-up node PU.
  • the output sub-circuit 022 can be connected to the pull-up node PU, the clock signal line CLK, and the output terminal OUT, respectively.
  • the output sub-circuit 022 can be used to output the clock signal provided by the clock signal line CLK to the output terminal OUT in response to the potential of the pull-up node PU.
  • the output sub-circuit 022 may output the clock signal provided by the clock signal line CLK to the output terminal when the potential of the pull-up node PU is an effective potential.
  • the pull-down sub-circuit 023 may be connected to the second power line GCH, the third power line GCL, the fourth power line VGL, the pull-up node PU, and the output terminal OUT, respectively.
  • the pull-down sub-circuit 023 can be used to pull up the node PU and the output terminal OUT in response to the potential of the pull-up node PU, the second power signal provided by the second power line GCH, and the third power signal provided by the third power line GCL, respectively
  • the fourth power signal provided by the fourth power line VGL is output.
  • the second power signal and the third power signal may both be DC power signals.
  • the second power signal and the third power signal may be non-direct current power signals, and when noise reduction is required for the pull-up node PU and the output terminal OUT, the potential remains at an effective potential.
  • the fourth power signal may be a DC power signal, and the potential of the fourth power signal may be an invalid potential.
  • the pull-down sub-circuit 023 may output the first pull-up node PU and the output terminal OUT at the invalid potential under the control of the second power signal or the third power signal.
  • Four power signals so as to achieve noise reduction on the pull-up node PU and the output terminal OUT.
  • the reset sub-circuit 024 can be connected to the reset signal terminal RST, the start signal line STV0, the fifth power line VSD, the fourth power line VGL, and the pull-up node PU, respectively.
  • the reset sub-circuit 024 can be used to pull up the node PU to output the fifth power signal provided by the fifth power line VSD in response to the reset signal provided by the reset signal terminal RST. And it can be used to output the fourth power signal from the pull-up node PU in response to the start driving signal provided by the start signal line STV0.
  • the fifth power signal may be a DC power signal, and the potential of the fifth power signal may be an invalid potential.
  • the fifth power signal may be a non-direct current power signal, and only when the potential of the reset signal is an effective potential, the potential of the fifth power signal is an effective potential.
  • the reset sub-circuit 024 may output the fourth power signal at an invalid potential to the pull-up node PU when the potential of the reset signal provided by the reset signal terminal RST is an effective potential, thereby achieving noise reduction on the pull-up node PU.
  • the reset sub-circuit 024 can output the fourth power signal at the inactive potential to the pull-up node PU when the potential of the start drive signal provided by the start signal line STV0 is at the effective potential, thereby realizing the lowering of the pull-up node PU. noise.
  • the actual signal line STV0 can provide a starting drive signal at a valid potential before the start of each frame scan to achieve a total reset of the pull-up node PU, which can also be improved to a certain extent. Defective horizontal stripes.
  • the gate driving circuit 02 may have an 11T1C structure, that is, the gate driving circuit 02 may include 11 thin film transistors and 1 capacitor.
  • the gate driving circuit 02 can also have other structures, such as 16T1C.
  • FIG. 3 shows a schematic structural diagram of a gate driving circuit.
  • the input sub-circuit 021 may include a first transistor M1.
  • the gate of the first transistor M1 can be connected to the input signal terminal IN, the first electrode can be connected to the first power line VDS, and the second electrode can be connected to the pull-up node PU.
  • the output sub-circuit 022 may include a second transistor M2 and a capacitor C1.
  • the gate of the second transistor M2 can be connected to the pull-up node PU
  • the first electrode can be connected to the clock signal line CLK
  • the second electrode can be connected to the output terminal OUT.
  • One end of the capacitor C1 can be connected to the pull-up node PU, and the other end can be connected to the output terminal OUT.
  • the pull-down sub-circuit 023 may include: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.
  • the gate and the first electrode of the third transistor M3 may both be connected to the second power line GCH, and the second electrode may be connected to the gate of the fourth transistor M4 and the second electrode of the fifth transistor M5.
  • the first pole of the fourth transistor M4 may be connected to the second power line GCH, and the second pole may be connected to the pull-down node PD.
  • the gate of the fifth transistor M5 and the gate of the sixth transistor M6 may both be connected to the pull-up node PU, and the first pole of the fifth transistor M5 and the first pole of the sixth transistor M6 may both be connected to the fourth power line VGL .
  • the second pole of the sixth transistor M6 may be connected to the pull-down node PD.
  • the gate of the seventh transistor M7 and the gate of the eighth transistor M8 may both be connected to the pull-down node PD, the first pole of the seventh transistor M7 and the first pole of the eighth transistor M8 may be connected to the fourth power line VGL,
  • the second pole of the seven transistor M7 may be connected to the pull-up node PU, and the second pole of the eighth transistor M8 may be connected to the output terminal OUT.
  • the gate of the ninth transistor M9 may be connected to the third power line GCL, the first pole may be connected to the fourth power line VGL, and the second pole may be connected to the output terminal OUT.
  • the reset sub-circuit 024 may include: a tenth transistor M10 and an eleventh transistor M11.
  • the gate of the tenth transistor M10 can be connected to the reset signal terminal RST
  • the first electrode can be connected to the fifth power line VSD
  • the second electrode can be connected to the pull-up node PU.
  • the gate of the eleventh transistor M11 may be connected to the start signal line STV0
  • the first pole may be connected to the fourth power line VGL
  • the second pole may be connected to the pull-up node PU.
  • the display substrate protected by the embodiments of the present disclosure may include a plurality of gate driving circuits 02 sequentially cascaded.
  • the output terminal OUT of each stage of shift register unit may be respectively connected to the input signal terminal IN of the previous stage of shift register unit and the reset signal terminal RST of the next stage of shift register unit.
  • the multiple gate drive circuits 02 in the cascade can use a 4-phase clock, that is, the multiple gate drive circuits 02 in the cascade can be divided into multiple groups, and each group can include four gate drive circuits 02.
  • the four gate driving circuits 02 can be connected to four clock signal lines respectively in sequence.
  • other clocks such as 6-phase clock or 8-phase clock can also be used.
  • three start signal lines can be used.
  • the multiple gate drive circuits 02 cascaded can be divided into multiple groups.
  • Each group may include three gate driving circuits 02, and the three gate driving circuits 02 may be connected to the three start signal lines respectively in sequence. Of course, more start signal lines can also be used.
  • the embodiments of the present disclosure do not limit this.
  • the first signal line 03 located in the peripheral area A21 may include: a first power line VDS, a second power line GCH, a third power line GCL, and a fourth power line VGL And one or more of the fifth power line VSD.
  • FIG. 4 shows a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the first signal line 03 located in the peripheral area A21 includes: a first power line VDS, a second power line GCH, a third power line GCL, and a fourth power line VGL , The fifth power line VSD and the start signal line STV0.
  • the second signal line 04 located in the packaging area A22 includes: a clock signal line CLK1, a clock signal line CLK2, a clock signal line CLK3, a clock signal line CLK4, and two other start signal lines STV1 and STV2.
  • the display substrate may further include: a transistor device layer on the base substrate 01.
  • the transistor device layer can be used to form a plurality of thin film transistors included in the gate driving circuit 02, for example, to form the 11 thin film transistors M1 shown in FIGS. 3 and 4.
  • FIG. 5 is a schematic diagram of a structure of a transistor device layer provided by an embodiment of the present disclosure.
  • the transistor device layer 05 may include: a gate layer 051, a gate insulation (GI) layer, which is located on one side of the base substrate 01 and sequentially stacked in a direction away from the base substrate 01. ) Layer 052, source drain (SD) layer 053, passivation (PVX) layer 054, and conductive film layer ITO 055. It should be noted that the transistor device layer may be referred to as a bottom gate structure.
  • GI gate insulation
  • VX passivation
  • the transistor device layer 05 may be provided with a via K, and the via K may be used to connect the gate layer 051 and the source-drain layer 053 in the transistor device layer 05, so that the gate layer 051 and the source-drain layer The signal between 053 is on. That is, each via hole K can be provided in the same layer as the gate layer 051 and the source and drain layer 053, and each via hole K needs to penetrate to the gate layer 051 so that the gate layer 051 is exposed for the conductive film layer When 055 is disposed in the via hole K, it can electrically connect the gate layer 051 and the source-drain layer 053.
  • the number of vias provided in the area where each gate drive circuit 02 is located may be smaller than the number of thin film transistors included in the gate drive circuit 02.
  • the number of M1 Since the number of via holes is reduced, it is also avoided that a larger number of via holes are corroded, which is more likely to cause horizontal stripes.
  • each gate driving circuit 02 includes a total of 11 thin film transistors M1.
  • a total of ten via holes K1 to K10 are provided in the area where each gate driving circuit 02 is located.
  • the structure of each via hole can refer to the structure of the via hole K shown in FIG. 5.
  • FIG. 6 shows a schematic diagram of a structure including only a base substrate 01 and via holes.
  • only one via hole K1 may be located in the package area A22, and the remaining via holes (for example, the via holes K2 to K10 shown in FIG. 4) may all be located in the peripheral area A21.
  • the via hole K1 located in the package area A22 may be a via hole for connecting the clock signal line CLK1 to the first pole of the thin film transistor M2, so that it can be used as a thin film transistor M2.
  • the clock signal line CLK1 can output a clock signal to the second pole of the thin film transistor M2.
  • the via K2 can be used to connect the fourth power line VGL to the first pole of the thin film transistor M9, so that when the thin film transistor M9 is turned on under the control of the gate potential, the fourth power line VGL can transmit the fourth power signal Output to the second pole of the thin film transistor M9.
  • the via K3 can be used to connect the second pole of the thin film transistor M2 and the second pole of the thin film transistor M9 to the output terminal OUT, so that the thin film transistor M2 outputs a clock signal to the output terminal OUT, or the thin film transistor M9 outputs a clock signal to the output terminal OUT.
  • the terminal OUT outputs the fourth power signal.
  • the via K4 can be used to connect the fifth power line VSD to the first pole of the thin film transistor M10, so that when the thin film transistor M10 is turned on under the control of the gate potential, the fifth power line VSD can transmit the fifth power signal Output to the second pole of the thin film transistor M10.
  • the via K5 can be used to connect the first power line VDS to the first pole of the thin film transistor M1, so that when the thin film transistor M1 is turned on under the control of the gate potential, the first power line VDS can transmit the first power signal Output to the second pole of the thin film transistor M1.
  • the via K6 can be used to connect the fourth power line VGL to the first pole of the thin film transistor M11, so that when the thin film transistor M11 is turned on under the control of the gate potential, the fourth power line VGL can transmit the fourth power signal Output to the second pole of the thin film transistor M11.
  • the via K7 can be used to connect the second power line GCH to the first pole of the thin film transistor M4, so that when the thin film transistor M4 is turned on under the control of the gate potential, the second power line GCH can connect the first power The signal is output to the second pole of the thin film transistor M4.
  • the via K8 can be used to electrically connect the second pole of the thin film transistor M3 to the gate of the thin film transistor M4, so that the potential of the second pole of the thin film transistor M3 can be output to the gate of the thin film transistor M4 to control the thin film transistor M4 On-off state.
  • the via K9 can be used to electrically connect the second pole of the thin film transistor M4 and the gate of the thin film transistor M8, so that the potential of the second pole of the thin film transistor M4 can be output to the gate of the thin film transistor M8 to control the thin film transistor M8. On-off state.
  • Via hole K10 can be used as a via hole connecting the pull-up node PU and each thin film transistor (such as M2, M6, M7, M11, M1, and M10) to realize the control of each thin film transistor, or to control each thin film transistor The on-off state.
  • each thin film transistor such as M2, M6, M7, M11, M1, and M10
  • the first electrode may be the source of the thin film transistor, and correspondingly, the second electrode may be the drain of the thin film transistor; or, the first electrode may be the drain of the thin film transistor, and correspondingly, the second electrode may be the drain of the thin film transistor.
  • the electrode may be the source of a thin film transistor.
  • a via hole K1 located in the packaging area A22 may be 450 micrometers ( ⁇ m) from the packaging area A22 close to the peripheral area A21.
  • the pattern filled in A22 shown in FIG. 6 may be an encapsulating glue.
  • L1 is the cutting line, that is, the position of L1 is the edge of the display substrate (panel).
  • the number of vias needs to be greater than the number of thin film transistors included in the gate drive circuit.
  • the number of vias is generally about 12.
  • a larger number of vias are generally located in the package area A22.
  • the number of vias included in the package area A22 is generally about five.
  • the via hole closest to the package area A22 close to the peripheral area A21 will also have a shorter distance from the package area A22 on the side close to the peripheral area A21, generally about 240 ⁇ m.
  • the width of the area occupied by the gate driving circuit 02 will also be relatively large, generally about 660 ⁇ m.
  • the arrangement of the embodiments of the present disclosure can also reduce the width of the area occupied by the gate driving circuit 02 from 660 ⁇ m in the related art to 640 ⁇ m.
  • the plurality of second signal lines 04 described in the embodiment of the present disclosure may all be located in the packaging area A22.
  • the plurality of second signal lines 04 may also be located in the peripheral area A21. That is, all the signal lines connected to the gate drive circuit 02 are not covered by the encapsulant.
  • FIG. 7 takes the non-display area A2 including twelve signal lines, and six signal lines are located in the peripheral area and six signal lines are located in the packaging area as an example, showing a schematic structural diagram of another display substrate.
  • the coating width of the packaging glue S1 in the packaging area may be 650 ⁇ m, and after coating, the packaging glue S1 overflows 100 ⁇ m to the left and right sides respectively.
  • the cutting line L1 is generally located at a position of the packaging glue S1 close to 100 ⁇ m in the peripheral area. That is, the distance between the cutting line L1 and the side of the packaging area close to the display area is 550 ⁇ m. In addition, the distance between the cutting line L1 and the side of the non-display area A2 close to the display area A1 may be 1000 ⁇ m.
  • FIG. 7 is only a schematic illustration, and the coating width of the encapsulant may be different based on display substrates of different areas.
  • the area of the non-display area A2 is generally much smaller than the area of the display area A1.
  • the ratio of the display area A1 and the non-display area A2 shown in the drawings of the embodiments of the present disclosure is only a schematic illustration.
  • the embodiments of the present disclosure provide a display substrate, which includes a base substrate having a display area and a non-display area, a gate drive circuit, and a first signal line and a gate drive circuit connected to the gate drive circuit.
  • the non-display area includes an encapsulation area coated with an encapsulation glue and a peripheral area. Since the first signal line for providing a signal with a lower frequency is located in the peripheral area and not in the packaging area, the first signal line will not be covered by the packaging glue. As a result, it is possible to avoid the problem of water vapor entering the packaging area due to poor packaging, causing the vias to be corroded due to the influence of the low-frequency signal line.
  • the display substrate provided by the embodiments of the present disclosure has a higher yield and a better display effect.
  • FIG. 8 is a manufacturing method of a display substrate provided by an embodiment of the present disclosure, which is used to manufacture the display substrate shown in FIG. 1 or FIG. 4. As shown in Figure 8, the method may include:
  • Step 801 Provide a base substrate.
  • the base substrate may have a display area A1 and a non-display area A2 surrounding the display area A1.
  • the non-display area A2 may include a peripheral area A21 and an encapsulation area A22 sequentially arranged in a direction away from the display area A1.
  • the packaging area A22 may be coated with packaging glue.
  • Step 802 forming a gate driving circuit in the non-display area.
  • the gate driving circuit 02 may be formed in a part of the peripheral area A21 and a part of the package area A22.
  • Step 803 forming a plurality of first signal lines connected to the gate driving circuit in the peripheral area.
  • a plurality of first signal lines 03 connected to the gate driving circuit 02 may be formed only in the peripheral area A21 that is not coated with the encapsulant.
  • Step 804 In the non-display area, a plurality of second signal lines connected to the gate driving circuit are formed.
  • multiple second signal lines 04 connected to the gate driving circuit 02 may be formed only in the packaging area A22 coated with the packaging glue.
  • a plurality of second signal lines 04 connected to the gate driving circuit 02 may be formed only in the peripheral area A21.
  • a plurality of second signal lines 04 connected to the gate driving circuit 02 may be formed in a part of the peripheral area A21 and a part of the package area A22.
  • the first signal line 03 and the second signal line 04 can both be used to provide signals for the gate driving circuit 02, and the frequency of the signal provided by the first signal line 03 can be lower than that provided by the second signal line 04 The frequency of the signal. That is, the first signal line 03 may be a low-frequency signal line, and the second signal line 04 may be a high-frequency signal line.
  • the embodiments of the present disclosure provide a method for manufacturing a display substrate.
  • the method includes: forming a base substrate having a display area and a non-display area, a gate drive circuit, and a first signal line and a second signal line connected to the gate drive circuit, and the non-display area includes an encapsulant coated Encapsulation area and surrounding area. Since the first signal line that provides a signal with a lower frequency is formed in the peripheral area instead of the packaging area, the first signal line can be prevented from being covered by the packaging glue. As a result, it is possible to avoid the problem of water vapor entering the packaging area due to poor packaging, causing the vias to be corroded due to the influence of the low-frequency signal line.
  • the display substrate manufactured by the manufacturing method of the display substrate provided by the embodiment of the present disclosure has a higher yield rate and a better display effect.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include: a signal providing circuit 10 and a display substrate 20 as shown in FIG. 1 or FIG. 4.
  • the signal providing circuit 10 may be connected to a signal line included in the display substrate 20, and the signal providing circuit 10 may be used to provide a driving signal to the signal line.
  • the signal providing circuit 10 may be a timing controller.
  • the display substrate 20 may include a plurality of first signal lines 03 and a plurality of second signal lines 04, and the signal supply circuit 10 may be connected to each first signal line 03 and each second signal line.
  • the signal line 04 is connected and used to provide a driving signal for each first signal line 03 and each second signal line 04.
  • the display device may be any product or component with a display function, such as a liquid crystal display, electronic paper, mobile phone, tablet computer, television, monitor, and notebook computer.
  • a display function such as a liquid crystal display, electronic paper, mobile phone, tablet computer, television, monitor, and notebook computer.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance.
  • plurality refers to two or more, unless specifically defined otherwise.
  • and/or is only an association relationship describing the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone. three conditions.

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Abstract

一种显示基板及其制造方法、显示装置。显示基板包括具有显示区（A1）和非显示区（A2）的衬底基板（01），栅极驱动电路（02），以及与栅极驱动电路（02）连接的第一信号线（03）和第二信号线（04），非显示区（A2）包括涂覆封装胶的封装区（A22）和周边区（A21）。由于用于提供较低频率的信号的第一信号线（03）位于周边区（A21）而不位于封装区（A22），因此第一信号线（03）不会被封装胶所覆盖。由此，可以避免因封装不良导致水汽进入封装区域，造成过孔受低频信号线影响而被腐蚀的问题，显示基板的良率较高，显示效果较好。

Description

显示基板及其制造方法、显示装置
本公开要求于2020年4月23日提交的申请号为202010327231.9、发明名称为“显示基板及其制造方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及其制造方法、显示装置。
背景技术
液晶显示面板因其节能、辐射低以及清晰度高等诸多优点被广泛应用于显示领域。
相关技术中，液晶显示面板中的阵列基板一般包括：具有显示区和非显示区的衬底基板，位于该非显示区的栅极驱动电路，以及位于非显示区且与栅极驱动电路连接的多条信号线。其中，该多条信号线一般均位于非显示区包括的用于涂覆封框胶的封装区域内，因此该多条信号线一般均被封框胶覆盖。相应的，用于使得多条信号线与栅极驱动电路能够电连接的过孔也会被封装胶覆盖。
但是，因封装胶封装不良，可能导致水汽等进入封装区域，进而可能导致过孔被腐蚀，液晶显示面板的良率较差。
发明内容
本公开提供了一种显示基板及其制造方法、显示装置，所述技术方案如下：
一些实施方式中，提供了一种显示基板，所述显示基板包括：
衬底基板，所述衬底基板具有显示区和围绕所述显示区的非显示区，所述非显示区包括沿远离所述显示区的方向依次排布的周边区和封装区，所述封装区内涂覆有封装胶；
栅极驱动电路，所述栅极驱动电路位于所述非显示区；
多条第一信号线，所述多条第一信号线位于所述周边区，且所述多条第一 信号线与所述栅极驱动电路连接；
多条第二信号线，所述多条第二信号线位于所述非显示区，且所述多条第二信号线与所述栅极驱动电路连接；
其中，所述第一信号线和所述第二信号线均用于为所述栅极驱动电路提供信号，且所述第一信号线提供的信号的频率，低于所述第二信号线提供的信号的频率。
一些实施方式中，所述第一信号线包括：用于提供直流电源信号的直流电源线。
一些实施方式中，所述第一信号线包括：用于提供起始驱动信号的起始信号线。
一些实施方式中，所述第二信号线包括：用于提供时钟信号的时钟信号线。
一些实施方式中，所述栅极驱动电路包括：输入子电路、输出子电路、下拉子电路和复位子电路；
所述输入子电路分别与输入信号端、第一电源线和上拉节点连接，用于响应于所述输入信号端提供的输入信号，向所述上拉节点输出所述第一电源线提供的第一电源信号；
所述输出子电路分别与所述上拉节点、时钟信号线和输出端连接，用于响应于所述上拉节点的电位，向所述输出端输出所述时钟信号线提供的时钟信号；
所述下拉子电路分别与第二电源线、第三电源线、第四电源线、所述上拉节点和所述输出端连接，所述下拉子电路用于响应于所述上拉节点的电位、所述第二电源线提供的第二电源信号和所述第三电源线提供的第三电源信号，向所述上拉节点和所述输出端分别输出所述第四电源线提供的第四电源信号；
所述复位子电路分别与复位信号端、起始信号线、第五电源线、所述第四电源线和所述上拉节点连接，所述复位子电路用于响应于所述复位信号端提供的复位信号，向所述上拉节点输出所述第五电源线提供的第五电源信号；以及用于响应于所述起始信号线提供的起始驱动信号，向所述上拉节点输出所述第四电源信号。
一些实施方式中，所述第一信号线包括：所述第一电源线、所述第二电源线、所述第三电源线、所述第四电源线和所述第五电源线中的一个或多个。
一些实施方式中，所述显示基板还包括：位于所述衬底基板上的晶体管器 件层；
所述晶体管器件层用于形成所述栅极驱动电路包括的多个薄膜晶体管，且所述晶体管器件层中设置有过孔，所述过孔用于连接所述晶体管器件层中的栅极层和源漏极层。
一些实施方式中，所述显示基板包括：依次级联的多个所述栅极驱动电路；
每个所述栅极驱动电路所在区域中设置的所述过孔的数量，小于所述栅极驱动电路包括的薄膜晶体管的数量。
一些实施方式中，每个所述栅极驱动电路包括十一个薄膜晶体管；每个所述栅极驱动电路所在区域中设置有十个过孔。
一些实施方式中，所述十个过孔中，一个所述过孔位于所述封装区，其余所述过孔均位于所述周边区。
一些实施方式中，所述多条第二信号线位于所述周边区。
一些实施方式中，所述多条第二信号线位于所述封装区。
一些实施方式中，提供了一种显示基板的制造方法，用于制造如上述方面所述的显示基板，所述方法包括：
提供衬底基板，所述衬底基板具有显示区和围绕所述显示区的非显示区，所述非显示区包括沿远离所述显示区的方向依次排布的周边区和封装区，所述封装区内涂覆有封装胶；
在所述非显示区，形成栅极驱动电路；
在所述周边区，形成与所述栅极驱动电路连接的多条第一信号线；
在所述非显示区，形成与所述栅极驱动电路连接的多条第二信号线；
其中，所述第一信号线和所述第二信号线均用于为所述栅极驱动电路提供信号，且所述第一信号线提供的信号的频率，低于所述第二信号线提供的信号的频率。
一些实施方式中，提供了一种显示装置，所述显示装置包括：信号提供电路，以及如上述方面所述的显示基板；
所述信号提供电路与所述显示基板包括的信号线连接，用于向所述信号线提供驱动信号。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开一个或多个实施例提供的显示基板的结构示意图；
图2是本公开一个或多个实施例提供的一种栅极驱动电路的结构示意图；
图3是本公开一个或多个实施例提供的另一种栅极驱动电路的结构示意图；
图4是本公开一个或多个实施例提供的另一种显示基板的结构示意图；
图5是本公开一个或多个实施例提供的一种晶体管器件层的结构示意图；
图6是本公开一个或多个实施例提供的又一种显示基板的结构示意图；
图7是本公开一个或多个实施例提供的再一种显示基板的结构示意图；
图8是本公开一个或多个实施例提供的一种显示基板的制造方法流程图；
图9是本公开一个或多个实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的发明构思的目的、技术方案和优点更加清楚，下面将结合附图和一些实施例对本公开实施例保护的发明构思做详细描述。
为了确保显示装置的合格率和良率，在显示装置出厂之间，一般均会在特定温度和特定湿度环境下对显示装置包括的各组成部分进行产品测试。例如，在85摄氏度(℃)百分之85％湿度环境下对显示装置包括的显示基板进行的产品信赖性测试，该测试也可以称为8585信赖性验证。
在8585信赖性验证时发现，显示基板容易因过孔腐蚀产生横纹不良，一般表现为由氧化铟锡(indium tin oxide，ITO)材料制成的导电膜层，即ITO导电膜层泛白。且，过孔腐蚀一般均是由于封装胶(seal)封装不良导致水汽进入所造成。下述对过孔腐蚀原理进行说明：其中，ITO导电膜层连接显示基板中的发光元件的阳极和阴极的不同化学反应如下：
阴极反应：In2O3+3H2O+6e→2In+6OH-
阳极反应：4OH-→O2+2H2O+4e
基于上述化学反应可知，当ITO导电膜层连接阴极时，若水汽进入，则ITO 导电膜层容易发生电化学腐蚀反应，生成单质铟(In)，该单质In一般呈现为白色。在变为In后，ITO导电膜层的方块电阻会变大，导致过孔用于搭接信号线的位置处阻值变大。若长期处于高温高湿环境下运行，则过孔处的热量会越来越大，最终导致过孔被腐蚀烧毁。且，过孔腐蚀的效率和程度与阴极电压的绝对值正相关。即若阴极电压的绝对值越大，过孔腐蚀的越快且越严重。
本公开实施例提供一种显示基板，可以解决过孔易被腐蚀的问题。图1是本公开实施例提供的一种显示基板。如图1所示，该显示基板可以包括：
衬底基板01，该衬底基板01可以具有显示区A1和围绕显示区A1的非显示区A2。其中，该显示区A1中设置有多个阵列排布的像素。该非显示区A2可以包括沿远离显示区A1的方向依次排布的周边区A21和封装区A22，该封装区A22内可以涂覆有封装胶(图1中未示出)。
栅极驱动电路02，该栅极驱动电路02可以位于非显示区A2。该栅极驱动电路02可以用于为该显示区A1中的一行或多行像素提供栅极驱动信号。
例如，参考图1，其示出的栅极驱动电路02，部分位于非显示区A2包括的周边区A21，部分位于非显示区A2包括的封装区A22。
多条第一信号线03，该多条第一信号线03可以位于周边区A21，且该多条第一信号线03可以与栅极驱动电路02连接。
多条第二信号线04，该多条第二信号线04可以位于非显示区A2，且该多条第二信号线04可以与栅极驱动电路02连接。
例如，参考图1，其示出的多条第二信号线04均位于非显示区A2包括的封装区A22。
其中，该第一信号线03和第二信号线04可以均用于为栅极驱动电路02提供信号，且该第一信号线03提供的信号的频率，可以低于第二信号线04提供的信号的频率。即，第一信号线03可以为低频信号线，第二信号线04可以为高频信号线。低频信号线是指频率范围较低、信号变化缓慢且波形较为平滑的信号线，高频信号线是指频率范围较高、信号变化快速且波形易突变的信号线。
基于上述过孔腐蚀原理分析，由于ITO导电膜层连接低频信号线时易与水汽发生反应，因此本公开实施例通过将低频信号线设置于非封装胶涂覆区域，以避免封装胶封装不良导致水汽进入时造成过孔腐蚀的现象。
综上所述，本公开实施例提供了一种显示基板，该显示基板包括具有显示区和非显示区的衬底基板，栅极驱动电路，以及与栅极驱动电路连接的第一信号线和第二信号线，该非显示区包括涂覆封装胶的封装区和周边区。由于用于提供较低频率的信号的第一信号线位于周边区而不位于封装区，因此第一信号线不会被封装胶所覆盖。由此，可以避免因封装不良导致水汽进入封装区域，造成过孔受低频信号线影响而被腐蚀的问题。本公开实施例提供的显示基板的良率较高，显示效果较好。
可选的，为了驱动栅极驱动电路02正常工作，栅极驱动电路02一般需要与用于提供直流电源信号的直流电源线，用于提供时钟信号的时钟信号线，和/或用于提供起始驱动信号的起始信号线连接。
而由于时钟信号线提供的时钟信号的波形变化较频繁，直流电源线不存在波形变化，起始信号线一般仅波形变化一次。因此可知，时钟信号线相对于直流电源线和起始信号线属于高频信号线，即，直流电源线和起始信号线可以划分为低频信号线。因此，在本公开实施例中，该第一信号线03可以包括直流电源线，和/或，起始信号线。该第二信号线04可以包括：时钟信号线。
可选的，图2是本公开实施例提供的一种栅极驱动电路的结构示意图。如图2所示，该栅极驱动电路02可以包括：输入子电路021、输出子电路022、下拉子电路023和复位子电路024。
其中，输入子电路021可以分别与输入信号端IN、第一电源线VDS和上拉节点PU连接。该输入子电路021可以用于响应于输入信号端IN提供的输入信号，向上拉节点PU输出第一电源线VDS提供的第一电源信号。
可选的，该第一电源信号可以为直流电源信号，且该第一电源信号的电位可以为有效电位。或者，该第一电源信号可以为非直流电源信号，且仅在输入信号的电位为有效电位时，该第一电源信号的电位为有效电位。
示例的，该输入子电路021可以在输入信号端IN提供的输入信号的电位为有效电位时，向上拉节点PU输出处于有效电位的第一电源信号，从而实现对上拉节点PU的充电。
该输出子电路022可以分别与上拉节点PU、时钟信号线CLK和输出端OUT连接。该输出子电路022可以用于响应于上拉节点PU的电位，向输出端OUT 输出时钟信号线CLK提供的时钟信号。
示例的，该输出子电路022可以在上拉节点PU的电位为有效电位时，向输出端输出时钟信号线CLK提供的时钟信号。
该下拉子电路023可以分别与第二电源线GCH、第三电源线GCL、第四电源线VGL、上拉节点PU和输出端OUT连接。该下拉子电路023可以用于响应于上拉节点PU的电位、第二电源线GCH提供的第二电源信号和第三电源线GCL提供的第三电源信号，向上拉节点PU和输出端OUT分别输出第四电源线VGL提供的第四电源信号。
可选的，该第二电源信号和第三电源信号可以均为直流电源信号。或者，该第二电源信号和第三电源信号可以为非直流电源信号，且在需要对上拉节点PU和输出端OUT降噪时，电位保持为有效电位。该第四电源信号可以为直流电源信号，且该第四电源信号的电位可以为无效电位。
示例的，该下拉子电路023可以在上拉节点PU的电位为无效电位时，在第二电源信号或第三电源信号的控制下，向上拉节点PU和输出端OUT分别输出处于无效电位的第四电源信号，从而实现对上拉节点PU和输出端OUT的降噪。
该复位子电路024可以分别与复位信号端RST、起始信号线STV0、第五电源线VSD、第四电源线VGL和上拉节点PU连接。该复位子电路024可以用于响应于复位信号端RST提供的复位信号，向上拉节点PU输出第五电源线VSD提供的第五电源信号。以及可以用于响应于起始信号线STV0提供的起始驱动信号，向上拉节点PU输出第四电源信号。
可选的，该第五电源信号可以为直流电源信号，且该第五电源信号的电位可以为无效电位。或者，该第五电源信号可以为非直流电源信号，且仅在复位信号的电位为有效电位时，该第五电源信号的电位为有效电位。
示例的，该复位子电路024可以在复位信号端RST提供的复位信号的电位为有效电位时，向上拉节点PU输出处于无效电位的第四电源信号，从而实现对上拉节点PU的降噪。以及，该复位子电路024可以在起始信号线STV0提供的起始驱动信号的电位为有效电位时，向上拉节点PU输出处于无效电位的第四电源信号，从而实现对上拉节点PU的降噪。
需要说明的是，该其实信号线STV0可以在每帧扫描开始之前，先提供处于有效电位的起始驱动信号，以实现对上拉节点PU的总复位(total reset)，也可 以一定程度上改善横纹不良现象。
可选的，对于图2所示的栅极驱动电路，该栅极驱动电路02可以为11T1C结构，即该栅极驱动电路02可以包括11个薄膜晶体管和1个电容器。当然，该栅极驱动电路02也可以为其他结构，如16T1C。以11T1C结构为例，图3示出了一种栅极驱动电路的结构示意图。
参考图3，输入子电路021可以包括第一晶体管M1。该第一晶体管M1的栅极可以与输入信号端IN连接，第一极可以与第一电源线VDS连接，第二极可以与上拉节点PU连接。
继续参考图3，输出子电路022可以包括第二晶体管M2和一个电容器C1。其中，该第二晶体管M2的栅极可以与上拉节点PU连接，第一极可以与时钟信号线CLK连接，第二极可以与输出端OUT连接。该电容器C1的一端可以与上拉节点PU连接，另一端可以与输出端OUT连接。
继续参考图3，下拉子电路023可以包括：第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8和第九晶体管M9。其中，第三晶体管M3的栅极和第一极可以均与第二电源线GCH连接，第二极可以与第四晶体管M4的栅极和第五晶体管M5的第二极连接。第四晶体管M4的第一极可以与第二电源线GCH连接，第二极可以与下拉节点PD连接。第五晶体管M5的栅极和第六晶体管M6的栅极可以均与上拉节点PU连接，第五晶体管M5的第一极和第六晶体管M6的第一极可以均与第四电源线VGL连接。第六晶体管M6的第二极可以与下拉节点PD连接。第七晶体管M7的栅极和第八晶体管M8的栅极可以均与下拉节点PD连接，第七晶体管M7的第一极和第八晶体管M8的第一极可以与第四电源线VGL连接，第七晶体管M7的第二极可以与上拉节点PU连接，第八晶体管M8的第二极可以与输出端OUT连接。第九晶体管M9的栅极可以与第三电源线GCL连接，第一极可以与第四电源线VGL连接，第二极可以与输出端OUT连接。
继续参考图3，复位子电路024可以包括：第十晶体管M10和第十一晶体管M11。其中，该第十晶体管M10的栅极可以与复位信号端RST连接，第一极可以与第五电源线VSD连接，第二极可以与上拉节点PU连接。该第十一晶体管M11的栅极可以与起始信号线STV0连接，第一极可以与第四电源线VGL连接，第二极可以与上拉节点PU连接。
还需要说明的是，本公开实施例保护的显示基板可以包括：依次级联的多个栅极驱动电路02。每一级移位寄存器单元的输出端OUT可以分别与上一级移位寄存器单元的输入信号端IN，以及下一级移位寄存器单元的复位信号端RST连接。且，该级联的多个栅极驱动电路02可以采用4相时钟，即可以将该级联的多个栅极驱动电路02划分为多组，每组可以包括四个栅极驱动电路02，且该四个栅极驱动电路02可以依次分别与4条时钟信号线连接。当然，也可以采用6相时钟或8相时钟等其他时钟数量另，可以采用三条起始信号线，与4相时钟同理，可以将级联的多个栅极驱动电路02划分为多组，每组可以包括三个栅极驱动电路02，且该三个栅极驱动电路02可以依次分别与该三条起始信号线连接。当然，也可以采用更多条起始信号线。本公开实施例对此均不作限定。
对于图2和图3所示的栅极驱动电路，位于周边区A21的第一信号线03可以包括：第一电源线VDS、第二电源线GCH、第三电源线GCL、第四电源线VGL和第五电源线VSD中的一个或多个。
示例的，以图3所示的栅极驱动电路，采用4相时钟，且包括3条起始信号线为例。图4示出了本公开实施例提供的另一种显示基板的结构示意图。参考图4可以看出，其示出的显示基板中，位于周边区A21的第一信号线03包括：第一电源线VDS、第二电源线GCH、第三电源线GCL、第四电源线VGL、第五电源线VSD和起始信号线STV0。位于封装区A22的第二信号线04包括：时钟信号线CLK1、时钟信号线CLK2、时钟信号线CLK3、时钟信号线CLK4和其他两条起始信号线STV1和STV2。
通过将较多条低频信号线均设置于周边区A21，可以使得较多过孔也相应的位于周边区A21，不被封装胶所覆盖，进一步避免了过孔被腐蚀的现象。
可选的，该显示基板还可以包括：位于衬底基板01上的晶体管器件层。该晶体管器件层可以用于形成栅极驱动电路02包括的多个薄膜晶体管，如用于形成图3和图4所示的11个薄膜晶体管M1。
图5是本公开实施例提供的一种晶体管器件层的结构示意图。如图5所示，该晶体管器件层05可以包括：位于衬底基板01的一侧，且沿远离衬底基板01的方向依次层叠的栅极(gate)层051、栅绝缘(gate insulation，GI)层052、源漏极(source drain，SD)层053、钝化(passivation，PVX)层054和导电膜层ITO 055。需要说明的是，该晶体管器件层可以称为底栅结构。
其中，该晶体管器件层05中可以设置有过孔K，该过孔K可以用于连接晶体管器件层05中的栅极层051和源漏极层053，使得栅极层051和源漏极层053之间的信号导通。即，每个过孔K均可以与栅极层051和源漏极层053同层设置，且每个过孔K需要贯穿至栅极层051，使得栅极层051暴露出来，以便导电膜层055设置于该过孔K内时，能够电连接栅极层051和源漏极层053。
可选的，在本公开实施例中，因第一信号线03的位置设置，可以使得每个栅极驱动电路02所在区域中设置的过孔的数量，小于栅极驱动电路02包括的薄膜晶体管M1的数量。由于降低了过孔的设置数量，因此还避免了因较多数量的过孔被腐蚀而更易造成横纹不良现象。
例如，参考图4，其示出的每个栅极驱动电路02共包括11个薄膜晶体管M1。每个栅极驱动电路02所在区域中共设置有十个过孔K1至K10。该十个过孔K1至K10中，每个过孔的结构均可以参考图5示出的过孔K的结构。
可选的，以图4所示的显示基板为例，图6示出了一种仅包括衬底基板01和过孔的结构示意图。如图6所示，该十个过孔中，仅一个过孔K1可以位于封装区A22，其余过孔(如，图4所示的过孔K2至K10)可以均位于周边区A21。
例如，结合图4示出的栅极驱动电路可知，该位于封装区A22的一个过孔K1可以为用于将时钟信号线CLK1接入薄膜晶体管M2的第一极的过孔，使得当薄膜晶体管M2在栅极电位的控制下导通时，时钟信号线CLK1可以将时钟信号输出至薄膜晶体管M2的第二极。位于周边区A21的其余过孔K2至K10中：
过孔K2，可以用于将第四电源线VGL接入薄膜晶体管M9的第一极，使得当薄膜晶体管M9在栅极电位的控制下导通时，第四电源线VGL可以将第四电源信号输出至薄膜晶体管M9的第二极。
过孔K3，可以用于将薄膜晶体管M2的第二极和薄膜晶体管M9的第二极接入输出端OUT，进而使得薄膜晶体管M2向输出端OUT输出时钟信号，或，使得薄膜晶体管M9向输出端OUT输出第四电源信号。
过孔K4，可以用于将第五电源线VSD接入薄膜晶体管M10的第一极，使得当薄膜晶体管M10在栅极电位的控制下导通时，第五电源线VSD可以将第五电源信号输出至薄膜晶体管M10的第二极。
过孔K5，可以用于将第一电源线VDS接入薄膜晶体管M1的第一极，使得当薄膜晶体管M1在栅极电位的控制下导通时，第一电源线VDS可以将第一电 源信号输出至薄膜晶体管M1的第二极。
过孔K6，可以用于将第四电源线VGL接入薄膜晶体管M11的第一极，使得当薄膜晶体管M11在栅极电位的控制下导通时，第四电源线VGL可以将第四电源信号输出至薄膜晶体管M11的第二极。
过孔K7，可以用于将第第二电源线GCH接入薄膜晶体管M4的第一极，使得当薄膜晶体管M4在栅极电位的控制下导通时，第二电源线GCH可以将第一电源信号输出至薄膜晶体管M4的第二极。
过孔K8，可以用于将薄膜晶体管M3的第二极与薄膜晶体管M4的栅极电连接，使得薄膜晶体管M3第二极的电位可以输出至薄膜晶体管M4的栅极，以控制薄膜晶体管M4的通断状态。
过孔K9，可以用于将薄膜晶体管M4的第二极和薄膜晶体管M8的栅极电连接，使得薄膜晶体管M4第二极的电位可以输出至薄膜晶体管M8的栅极，以控制薄膜晶体管M8的通断状态。
过孔K10，可以作为上拉节点PU与各薄膜晶体管(如，M2、M6、M7、M11、M1和M10)连通的一个过孔，以实现对各薄膜晶体管的控制，或，控制各薄膜晶体管的通断状态。
需要说明的是，上述第一极可以为薄膜晶体管的源极，相应的，第二极可以为薄膜晶体管的漏极；或者，上述第一极可以为薄膜晶体管的漏极，相应的，第二极可以为薄膜晶体管的源极。
另，结合图4和图6所示大小的显示基板，位于封装区A22的一个过孔K1，距封装区A22靠近周边区A21的距离可以为450微米(μm)。当然，对于不同面积的显示基板，该位于封装区A22的一个过孔K1，距封装区A22靠近周边区A21的距离可以不同。图6示出的A22中填充的图案可以为封装胶。L1为切割线，即，L1所在位置即为显示基板(panel)的边缘。通过在封装区设置数量较少的过孔，可以避免较多过孔被腐蚀而带来更为严重的横纹不良现象。
对于图3所示结构的栅极驱动电路，相关技术中，由于起始信号线STV0、第二电源线GCH和第四电源线VGL均设置于封装区A22，因此为了保证各薄膜晶体管与各信号线的可靠连接，过孔的数量需要大于栅极驱动电路包括的薄膜晶体管的数量。如，过孔的数量一般约为12个。且，较多数量的过孔一般会位于封装区A22。如，封装区A22包括的过孔数量一般约为5个。除此之外， 封装区A22内，距封装区A22靠近周边区A21最近的过孔，距封装区A22靠近周边区A21一侧的距离也会较短，一般大约为240μm。另，栅极驱动电路02所占区域宽度也会较大，一般约为660μm。
而本公开实施例通过将第一信号线03设置于栅极驱动电路02靠近显示区A1的一侧，即设置于栅极驱动电路02的内侧，不仅可以使得原来的过孔由12个减少至10个，且可以将封装区A22内的过孔数量由5个减少至1个，且可以使得位于封装区A22的1个过孔距封装区A22靠近周边区A21一侧的距离增加至450μm。除此之外，本公开实施例的设置方式还可以使得栅极驱动电路02所占区域宽度由相关技术中的660μm减少至640μm。通过该设置方式，在实现窄边框的前提下，有效可靠的避免了封装胶封装不良导致的过孔腐蚀现象。另，为进一步确保过孔不被腐蚀，还可以使用防水性能较好的封装胶进行封装。
可选的，结合上述图1和图4，本公开实施例记载的多条第二信号线04可以均位于封装区A22。当然，为进一步确保良率，该多条第二信号线04还可以位于周边区A21。即，所有与栅极驱动电路02连接的信号线均不被封装胶覆盖。
图7以非显示区A2包括十二条信号线，且其中六条信号线位于周边区，六条信号线位于封装区为例，示出了又一种显示基板的结构示意图。如图7可以看出，封装胶S1在封装区域的涂覆宽度可以为650μm，且涂覆后，封装胶S1分别向左右两侧溢出100μm。切割线L1一般位于封装胶S1靠近周边区100μm的位置处。即切割线L1距封装区靠近显示区一侧的距离为550μm。另，切割线L1距非显示区A2靠近显示区A1一侧的距离可以为1000μm。
需要说明的是，图7仅是一种示意性说明，基于不同面积的显示基板，封装胶的涂覆宽度可以不同。另，非显示区A2的面积一般远小于显示区A1的面积，本公开实施例附图示出的显示区A1和非显示区A2的比例仅是示意性说明，
综上所述，本公开实施例提供了一种显示基板，该显示基板包括具有显示区和非显示区的衬底基板，栅极驱动电路，以及与栅极驱动电路连接的第一信号线和第二信号线，该非显示区包括涂覆封装胶的封装区和周边区。由于用于提供较低频率的信号的第一信号线位于周边区而不位于封装区，因此第一信号线不会被封装胶所覆盖。由此，可以避免因封装不良导致水汽进入封装区域，造成过孔受低频信号线影响而被腐蚀的问题。本公开实施例提供的显示基板的良率较高，显示效果较好。
图8是本公开实施例提供的一种显示基板的制造方法，用于制造如图1或图4所示的显示基板。如图8所示，该方法可以包括：
步骤801、提供衬底基板。
可选的，参考图1，该衬底基板可以具有显示区A1和围绕显示区A1的非显示区A2。该非显示区A2可以包括沿远离显示区A1的方向依次排布的周边区A21和封装区A22。且，该封装区A22内可以涂覆有封装胶。
步骤802、在非显示区，形成栅极驱动电路。
可选的，参考图1和图4，可以在部分周边区A21和部分封装区A22形式栅极驱动电路02。
步骤803、在周边区，形成与栅极驱动电路连接的多条第一信号线。
可选的，参考图1，可以仅在未涂覆有封装胶的周边区A21形成与栅极驱动电路02连接的多条第一信号线03。
步骤804、在非显示区，形成与栅极驱动电路连接的多条第二信号线。
可选的，参考图1，可以仅在涂覆有封装胶的封装区A22形成与栅极驱动电路02连接的多条第二信号线04。或者，可以仅在周边区A21形成与栅极驱动电路02连接的多条第二信号线04。又或者，可以在部分周边区A21和部分封装区A22形成与栅极驱动电路02连接的多条第二信号线04。
其中，该第一信号线03和第二信号线04可以均用于为栅极驱动电路02提供信号，且该第一信号线03提供的信号的频率，可以低于第二信号线04提供的信号的频率。即，该第一信号线03可以为低频信号线，第二信号线04可以为高频信号线。
综上所述，本公开实施例提供了一种显示基板的制造方法。该方法包括：形成具有显示区和非显示区的衬底基板，栅极驱动电路，以及与栅极驱动电路连接的第一信号线和第二信号线，该非显示区包括涂覆封装胶的封装区和周边区。由于是在周边区而不是封装区形成提供较低频率的信号的第一信号线，因此可以使得第一信号线不会被封装胶所覆盖。由此，可以避免因封装不良导致水汽进入封装区域，造成过孔受低频信号线影响而被腐蚀的问题。本公开实施例提供的显示基板的制造方法制成的显示基板的良率较高，显示效果较好。
图9是本公开实施例提供的一种显示装置的结构示意图。如图9所示，该显示装置可以包括：信号提供电路10，以及如图1或图4所示的显示基板20。该信号提供电路10可以与显示基板20包括的信号线连接，该信号提供电路10可以用于向信号线提供驱动信号。如，该信号提供电路10可以为时序控制器。
例如，结合图1和图9，该显示基板20可以包括多条第一信号线03和多条第二信号线04，该信号提供电路10可以与每条第一信号线03和每条第二信号线04连接，并用于为该每条第一信号线03和每条第二信号线04提供驱动信号。
可选的，该显示装置可以为：液晶显示器、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。术语“和/或”，仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
以上所述仅为本公开的可选实施例，并不用以限制本公开实施例，凡在本公开实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开实施例的保护范围之内。

Claims (15)

  1. 一种显示基板，所述显示基板包括：
    衬底基板，所述衬底基板具有显示区和围绕所述显示区的非显示区，所述非显示区包括沿远离所述显示区的方向依次排布的周边区和封装区，所述封装区内涂覆有封装胶；
    栅极驱动电路，所述栅极驱动电路位于所述非显示区；
    多条第一信号线，所述多条第一信号线位于所述周边区，且所述多条第一信号线与所述栅极驱动电路连接；
    多条第二信号线，所述多条第二信号线位于所述非显示区，且所述多条第二信号线与所述栅极驱动电路连接；
    其中，所述第一信号线和所述第二信号线均用于为所述栅极驱动电路提供信号，且所述第一信号线提供的信号的频率，低于所述第二信号线提供的信号的频率。
  2. 根据权利要求1所述的显示基板，其中，所述第一信号线包括：用于提供直流电源信号的直流电源线。
  3. 根据权利要求1所述的显示基板，其中，所述第一信号线包括：用于提供起始驱动信号的起始信号线。
  4. 根据权利要求1至3任一所述的显示基板，其中，所述第二信号线包括：用于提供时钟信号的时钟信号线。
  5. 根据权利要求1至4任一所述的显示基板，其中，所述栅极驱动电路包括：输入子电路、输出子电路、下拉子电路和复位子电路；
    所述输入子电路分别与输入信号端、第一电源线和上拉节点连接，用于响应于所述输入信号端提供的输入信号，向所述上拉节点输出所述第一电源线提供的第一电源信号；
    所述输出子电路分别与所述上拉节点、时钟信号线和输出端连接，用于响 应于所述上拉节点的电位，向所述输出端输出所述时钟信号线提供的时钟信号；
    所述下拉子电路分别与第二电源线、第三电源线、第四电源线、所述上拉节点和所述输出端连接，所述下拉子电路用于响应于所述上拉节点的电位、所述第二电源线提供的第二电源信号和所述第三电源线提供的第三电源信号，向所述上拉节点和所述输出端分别输出所述第四电源线提供的第四电源信号；
    所述复位子电路分别与复位信号端、起始信号线、第五电源线、所述第四电源线和所述上拉节点连接，所述复位子电路用于响应于所述复位信号端提供的复位信号，向所述上拉节点输出所述第五电源线提供的第五电源信号；以及用于响应于所述起始信号线提供的起始驱动信号，向所述上拉节点输出所述第四电源信号。
  6. 根据权利要求5所述的显示基板，其中，所述第一信号线包括：所述第一电源线、所述第二电源线、所述第三电源线、所述第四电源线和所述第五电源线中的一个或多个。
  7. 根据权利要求1至6任一所述的显示基板，其中，所述显示基板还包括：位于所述衬底基板上的晶体管器件层；
    所述晶体管器件层用于形成所述栅极驱动电路包括的多个薄膜晶体管，且所述晶体管器件层中设置有过孔，所述过孔用于连接所述晶体管器件层中的栅极层和源漏极层。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板包括：依次级联的多个所述栅极驱动电路；
    每个所述栅极驱动电路所在区域中设置的所述过孔的数量，小于所述栅极驱动电路包括的薄膜晶体管的数量。
  9. 根据权利要求8所述的显示基板，其中，每个所述栅极驱动电路包括十一个薄膜晶体管；每个所述栅极驱动电路所在区域中设置有十个过孔。
  10. 根据权利要求9所述的显示基板，其中，所述十个过孔中，一个所述过 孔位于所述封装区，其余所述过孔均位于所述周边区。
  11. 根据权利要求1至10任一所述的显示基板，其中，所述多条第二信号线位于所述周边区。
  12. 根据权利要求1至11任一所述的显示基板，其中，所述多条第二信号线位于所述封装区。
  13. 根据权利要求6所述的显示基板，其中，
    所述第二信号线包括：用于提供时钟信号的时钟信号线；且所述多条第二信号线位于所述周边区，或，位于所述封装区；
    所述显示基板还包括：位于所述衬底基板上的晶体管器件层，所述晶体管器件层用于形成所述栅极驱动电路包括的多个薄膜晶体管，且所述晶体管器件层中设置有过孔，所述过孔用于连接所述晶体管器件层中的栅极层和源漏极层；
    所述显示基板包括：依次级联的多个所述栅极驱动电路；每个所述栅极驱动电路包括十一个薄膜晶体管；每个所述栅极驱动电路所在区域中设置有十个过孔；所述十个过孔中，一个所述过孔位于所述封装区，其余所述过孔均位于所述周边区。
  14. 一种显示基板的制造方法，其中，用于制造如权利要求1至13任一所述的显示基板，所述方法包括：
    提供衬底基板，所述衬底基板具有显示区和围绕所述显示区的非显示区，所述非显示区包括沿远离所述显示区的方向依次排布的周边区和封装区，所述封装区内涂覆有封装胶；
    在所述非显示区，形成栅极驱动电路；
    在所述周边区，形成与所述栅极驱动电路连接的多条第一信号线；
    在所述非显示区，形成与所述栅极驱动电路连接的多条第二信号线；
    其中，所述第一信号线和所述第二信号线均用于为所述栅极驱动电路提供信号，且所述第一信号线提供的信号的频率，低于所述第二信号线提供的信号的频率。
  15. 一种显示装置，其中，所述显示装置包括：信号提供电路，以及如权利要求1至13任一所述的显示基板；
    所述信号提供电路与所述显示基板包括的信号线连接，用于向所述信号线提供驱动信号。
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