WO2021212793A1 - 一种具有相同栅源掺杂的场效应晶体管、元胞结构及制备方法 - Google Patents

一种具有相同栅源掺杂的场效应晶体管、元胞结构及制备方法 Download PDF

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WO2021212793A1
WO2021212793A1 PCT/CN2020/124344 CN2020124344W WO2021212793A1 WO 2021212793 A1 WO2021212793 A1 WO 2021212793A1 CN 2020124344 W CN2020124344 W CN 2020124344W WO 2021212793 A1 WO2021212793 A1 WO 2021212793A1
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conductivity type
gate
source
region
field
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PCT/CN2020/124344
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English (en)
French (fr)
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黄兴
陈欣璐
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派恩杰半导体（杭州）有限公司
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Priority claimed from CN202010313779.8A external-priority patent/CN111509034A/zh
Priority claimed from CN202010725690.2A external-priority patent/CN111933698A/zh
Application filed by 派恩杰半导体（杭州）有限公司 filed Critical 派恩杰半导体（杭州）有限公司
Priority to EP20931964.9A priority Critical patent/EP4141960A4/en
Priority to JP2022564223A priority patent/JP2023522273A/ja
Priority to US17/920,301 priority patent/US20230178636A1/en
Publication of WO2021212793A1 publication Critical patent/WO2021212793A1/zh

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Definitions

  • the invention belongs to the field of semiconductor technology, and specifically relates to a field effect transistor with the same gate-source doping, a cell structure and a preparation method.
  • SiC junction field effect transistor (JFET) device has received extensive attention.
  • SiC JFETs are easier to reduce the cell size and bring lower on-resistance. Because SiO 2 will excite more interface states at high temperatures, SiC JFET devices can maximize the high temperature and high pressure characteristics of SiC materials.
  • the traditional SiC JFET is controlled by a PN junction. After the carriers flow out from the source of the device, they pass through a long and narrow channel region, flow into the drift region of the device, and are finally collected by the drain of the device.
  • the device channel is controlled by two PN junctions located between the gate and the source to control the turn-off and turn-on of the device.
  • the built-in potential (hereinafter referred to as "the built-in potential of the gate”) causes the channel to be depleted to a certain extent, resulting in higher channel resistance; when the device is working at high current (near the saturation region), the built-in potential of the gate Causes the channel to enter the pinch-off state prematurely, causes the current to saturate prematurely, and causes the conduction loss during this operation to be too high.
  • the present invention is used to provide a field-effect transistor with the same gate-source doping, a cell structure, and a manufacturing method.
  • the present invention adopts the following technical solutions:
  • the first aspect of the present invention provides a field effect transistor cell structure with the same gate-source doping, including:
  • a silicon carbide substrate, the doping type of the silicon carbide substrate material is the first conductivity type
  • a first conductive type semiconductor epitaxial layer and a first electrode are respectively provided on the front and back sides of the silicon carbide substrate;
  • a second conductivity type suspension area, a first conductivity type gate injection area, and a first conductivity type source injection area are sequentially arranged on the first conductivity type semiconductor epitaxial layer.
  • the gate injection area is provided with a gate, and the source injection A source electrode is arranged on the region, and an inter-electrode medium is arranged between the gate injection region and the source injection region, and the inter-electrode medium is used to isolate the gate and the source.
  • the contact portion of the second conductivity type suspension region (005) and the first conductivity type source injection region (007) has the same structure as the first conductivity type source injection region (007), and both are set to have terminals Sharp corners.
  • the terminal sharp angle is 0-180 degrees.
  • the thickness of the first conductive type semiconductor epitaxial layer 002 is 5 to 250 um, and the doping concentration is 1 ⁇ 10 14 cm -3 -5 ⁇ 10 18 cm -3 .
  • the gate injection area on one side of the cell is connected to the gate, and the gate injection area and the source injection area on the other side of the cell are both connected to the source.
  • the doping of the first conductivity type and the second conductivity type is 1 ⁇ 10 14 cm ⁇ 3 -2 ⁇ 10 21 cm ⁇ 3 uniform or non-uniform doping.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the second aspect of the present invention provides a field-effect transistor with the same gate-source doping, including a plurality of cell structures and field limiting ring terminal junctions as described above, and when the junction terminal is fabricated, the injection junction terminal and the cell are etched The second conductivity type suspension area of the structure is simultaneously etched and implanted using the same photolithography mask.
  • the third aspect of the present invention provides a field-effect transistor with the same gate-source doping, including a number of cell structures as described above, junction terminal extensions and field-limited loop junction terminals, and when the junction terminal is fabricated, etching and implanting The junction terminal and the second conductivity type suspended region of the cell structure are simultaneously etched and implanted using the same photolithography mask.
  • the fourth aspect of the present invention provides a method for preparing a cell structure of field effect transistors with the same gate-source doping, including the following steps:
  • a silicon carbide substrate is used.
  • the doping type of the substrate material is the first conductivity type.
  • a semiconductor epitaxial layer of the first conductivity type is provided on the front surface of the silicon carbide substrate.
  • the silicon carbide mesa is formed by an etching process, and the etching depth is 0.5 to 5um;
  • the specific process includes: adopting at least one oblique implantation and vertical implantation of Al ions to form the second conductivity type suspension area, so that the bottom and sidewalls of the trench are uniformly implanted;
  • the alloy contains at least one of silicide or carbide
  • the step further includes: adding at least one inclined implantation to form a channel implantation region.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the fifth aspect of the present invention provides a method for manufacturing a field-effect transistor with the same gate-source doping.
  • the field-effect transistor includes a plurality of cell structures and field limiting loop terminal junctions, wherein the cell structure adopts any one of the above-mentioned cell structures.
  • the sixth aspect of the present invention provides a method for preparing a field-effect transistor with the same gate-source doping.
  • the field-effect transistor includes a plurality of cell structures and junction terminal extensions and field-limited loop junction terminals, wherein the cell structure adopts such as In any of the above-mentioned preparation methods, and when the junction terminal is fabricated, the etching and implantation of the junction terminal and the second conductivity type suspension region of the cell structure are simultaneously etched and implanted using the same photolithography mask.
  • a gate with a first conductivity type and a second conductivity type floating area surrounding the gate are introduced to control the device channel, which can increase the forward bias of the device gate so that Vgs can be The bias is greater than the forward turn-on voltage of the pn junction.
  • the device can conduct a larger current when it enters a saturated state.
  • a gate is connected to the source, so that the structure can reduce Cgd, thereby reducing switching loss.
  • FIG. 1 is a schematic structural diagram of a first conductive type semiconductor epitaxial layer provided on the front surface of a silicon carbide substrate in method embodiment 1;
  • FIG. 2 is a schematic diagram of the structure of the silicon carbide mesa produced by an etching process in the first method embodiment
  • FIG. 3 is a schematic diagram of a structure of forming a second conductivity type suspension region in the first method embodiment
  • FIG. 4 is a schematic diagram of the structure of forming the gate implantation region and the source implantation region in the first method embodiment
  • FIG. 5 is a schematic diagram of the structure of forming an electrode isolation medium in the first method embodiment
  • FIG. 6 is a schematic diagram of the structure of forming the gate electrode and the source electrode in the first method embodiment
  • FIG. 7 is a schematic diagram of the structure of forming a channel implantation region in the second method embodiment
  • FIG. 8 is a schematic diagram of a structure in which a gate is connected to a source in the third method embodiment
  • FIG. 9 is a schematic diagram of the etching and implantation of the junction terminal and the active region of the cell structure at the same time in the fourth method embodiment
  • FIG. 10 is a schematic diagram of the structure of etching and implanting the junction terminal and the active region of the cell structure at the same time in the fifth method embodiment.
  • 11 is a schematic structural diagram of the space charge region between the channel injection region and the second conductivity type suspension region being closed when the device is turned off;
  • FIG. 12 is a schematic diagram of the structure of the space charge division when the device is turned on
  • FIG. 13 is a comparative schematic diagram of increasing the voltage that can be applied to the gate compared with a conventional JFET device
  • Figure 14 is a schematic diagram showing the increase and saturation current compared with the traditional JFET device
  • FIG. 15 is a schematic cross-sectional structure diagram of a field effect transistor cell structure with the same gate-source doping according to another embodiment of the present invention.
  • 16 is a three-dimensional structure diagram of a second conductivity type semiconductor suspension region with sharp terminal corners in a field-effect transistor cell structure with the same gate-source doping according to another embodiment of the present invention
  • 17 is a schematic diagram of a cross-sectional structure of a second conductivity type semiconductor suspension region with sharp terminal corners in a field-effect transistor cell structure with the same gate-source doping according to another embodiment of the present invention.
  • FIG. 19 is a schematic diagram of a three-dimensional structure with a rectangular second conductivity type semiconductor suspended region in a field-effect transistor cell structure with the same gate-source doping according to another embodiment of the present invention.
  • 20 is a schematic cross-sectional structure diagram of a rectangular second conductivity type semiconductor suspended region in a field-effect transistor cell structure with the same gate-source doping according to another embodiment of the present invention
  • FIG. 21 is a top view of the layout of the active area of the device with rectangular cells.
  • the embodiment of the invention discloses a preparation method of a field effect transistor cell structure with the same gate-source doping, which comprises the following steps:
  • a silicon carbide substrate 001 is used, the doping type of the substrate material is the first conductivity type, and the first conductivity type semiconductor epitaxial layer 002 is provided on the front surface of the silicon carbide substrate 001,
  • the mask material is lithographically etched with a photoresist to cover part of the surface, and the silicon carbide mesa is etched by ICP (Inductively Coupled Plasma), with an etching depth of 0.5 to 5um, and other etching processes can also be used.
  • ICP Inductively Coupled Plasma
  • the same photolithography mask material is used for ion implantation of the suspension region.
  • the specific process includes: adopting at least one oblique implantation and vertical implantation of Al ions to form the second conductivity type suspension region 005, so that the bottom and sides of the trench The wall is injected uniformly.
  • the masking layer is peeled off, and vertical N implantation is performed to form the gate implantation region 006 and the source implantation region 007 of the first conductivity type, and then form a good ohmic contact with the metal;
  • a dielectric layer is grown on the sidewall of the trench as the electrode isolation dielectric 010 to isolate the gate implantation region 006 and the source implantation region 007;
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the doping of the first conductivity type and the second conductivity type is uniform or non-uniform doping of 1 ⁇ 10 14 cm -3 -2 ⁇ 10 21 cm -3.
  • the thickness of the first conductivity type semiconductor epitaxial layer 002 is 5 to 250 um, and the doping concentration is 1 ⁇ 10 14 cm -3 -5 ⁇ 10 18 cm -3 .
  • a channel implantation region 004 formed by at least one oblique implantation is added.
  • the implantation energy in the ion implantation of the suspension region is large and the implantation depth is deep, which will change the doping concentration of the epitaxial layer.
  • the implantation energy does not stay on the surface of the trench, but reaches the channel.
  • the implantation concentration of the channel can be increased to further reduce Small on-resistance Rdson.
  • the gate implantation region 006 on one side of the cell is connected to the gate 008, and the gate implantation on the other side of the cell is
  • the region 006 and the source injection region 007 are commonly connected to the source 009, so that the structure can reduce the Cgd, thereby reducing the switching loss.
  • an embodiment of the present invention also provides a method for preparing a field effect transistor with the same gate-source doping.
  • the field effect transistor includes a plurality of cell structures and field limiting ring terminal junctions, wherein method embodiment 1 is adopted.
  • One of to 3 is prepared, and when the junction terminal is fabricated, the junction terminal is etched and implanted and the second conductivity type suspension region of the cell structure is simultaneously etched and implanted using the same photolithography mask.
  • an embodiment of the present invention also provides a method for preparing a field-effect transistor with the same gate-source doping.
  • the field-effect transistor includes a number of cell structures and junction terminal extensions and field-limited loop junction terminals, wherein the cell The structure is prepared by one of the method embodiments 1 to 3, and when the junction terminal is fabricated, the junction terminal and the second conductivity type suspension area of the cell structure are simultaneously etched and implanted using the same photolithography mask. .
  • the cell structure of field effect transistors with the same gate-source doping and field-effect transistors with the same gate-source doping can be prepared, which will be specifically described in the following structural examples.
  • a field-effect transistor cell structure with the same gate-source doping prepared by method embodiment 1, as shown in Fig. 6, includes:
  • the silicon carbide substrate 001, the doping type of the silicon carbide substrate material is the first conductivity type
  • a first conductivity type semiconductor epitaxial layer 002 and a first electrode 003 are respectively provided on the front and back of the silicon carbide substrate 001;
  • a second conductivity type suspension region 005, a first conductivity type gate injection region 006, and a first conductivity type source injection region 007 are sequentially arranged on the first conductivity type semiconductor epitaxial layer 002, and the gate injection region 006 is provided with a gate.
  • the thickness of the first conductivity type semiconductor epitaxial layer 002 is 5 to 250 um, and the doping concentration is 1 ⁇ 10 14 cm -3 -5 ⁇ 10 18 cm -3 .
  • the embodiment of the present invention introduces a gate having a first conductivity type and a suspension region of a second conductivity type surrounding the gate on the basis of a traditional JFET to control the channel of the device.
  • the present invention increases the voltage and saturation current that can be applied to the gate, as shown in FIG. 13 and FIG. 14.
  • the doping of the first conductivity type and the second conductivity type is uniform or non-uniform doping of 1 ⁇ 10 14 cm -3 -2 ⁇ 10 21 cm -3.
  • channel implantation is formed by adding at least one inclined implantation on the epitaxial layer District 004.
  • the threshold voltage of the JFET device can be adjusted. Referring to Figure 11, when the device is turned off, the space charge region between the channel injection region 004 and the second conductivity type suspension region 005 is closed; refer to Figure 12, when the device is turned on, the space charge region is separated.
  • one of the gates is connected to the source, so that the structure can reduce Cgd, thereby reducing switching loss.
  • the gate injection region 006 on one side of the cell is connected to the gate 008, and the gate injection region 006 and the source injection region on the other side of the cell 007 is connected to the source 009 together, so that the structure can reduce the Cgd, thereby reducing the switching loss.
  • an embodiment of the present invention provides a field-effect transistor with the same gate-source doping, including a number of cell structures and field limiting ring terminal junctions as in any one of structural embodiments 1 to 4, and the junction terminal is fabricated At the same time, the same photolithography mask is used to etch and implant the junction terminal and the second conductivity type floating region of the cell structure at the same time.
  • a field effect transistor with the same gate-source doping is characterized in that it includes a number of cell structures as in any one of structural embodiments 1 to 4, as well as junction terminal extensions and field-limited loop junction terminals.
  • the junction terminal is fabricated, the junction terminal is etched and implanted and the second conductivity type floating region of the cell structure is simultaneously etched and implanted using the same photolithography mask.
  • the embodiment of the present invention discloses a cell structure of field effect transistors with the same gate-source doping.
  • the view shows a cross-sectional view of the XY plane in a spatial rectangular coordinate system, including:
  • the silicon carbide substrate 001, the doping type of the silicon carbide substrate material is the first conductivity type
  • a first conductivity type semiconductor epitaxial layer 002 and a first electrode 003 are respectively provided on the front and back of the silicon carbide substrate 001;
  • a second conductivity type suspension region 005, a first conductivity type gate injection region 006, and a first conductivity type source injection region 007 are sequentially arranged.
  • a gate 008 is provided on the region 006, a source 009 is provided on the first conductivity type source injection region 007, and the first conductivity type gate injection region 006 and the first conductivity type source injection region 007 are provided between
  • the inter-electrode dielectric 010 is used to isolate the gate 008 and the source 009, wherein the contact part of the second conductivity type floating region 005 and the first conductivity type source injection region 007 is connected to the first conductivity type source
  • the injection regions 007 have the same structure, and they are all set to have terminal sharp corners.
  • Figure 19 is a three-dimensional view of the smallest half-cell structure
  • Figure 20 is the YZ plane
  • Fig. 21 is a top view of the layout of the active area of the device with rectangular cells.
  • This trench device controls the channel of the device due to the introduction of a gate with a first conductivity type and a second conductivity type floating area surrounding the gate.
  • the rear, left, and right injections in four different directions can avoid gate-source short circuit. As shown in Figure 21, each injection can only be injected into one surface of the cell.
  • the first conductivity type of the device will be penetrated at the edge of the device cell, which will short-circuit the gate source (see FIG. 20).
  • the actual implementation process will need to minimize the number of injections.
  • the embodiment of the present invention avoids this problem by introducing the cell layout structure with the terminal sharp corners into the second conductivity type suspension area 005.
  • Figure 16 is a three-dimensional view of the smallest half-cell structure
  • Figure 17 is a cross-sectional view of the YZ plane
  • Figure 18 is a terminal with a terminal
  • the sharp angle of the terminal is 0 to 180 degrees.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the doping of the first conductivity type and the second conductivity type is uniform or non-uniform doping of 1 ⁇ 10 14 cm -3 -2 ⁇ 10 21 cm -3.
  • the thickness of the first conductivity type semiconductor epitaxial layer 002 is 5 to 250 um, and the doping concentration is 1 ⁇ 10 14 cm -3 -5 ⁇ 10 18 cm -3 .

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Abstract

本发明公开了一种具有相同栅源掺杂的场效应晶体管、元胞结构及制备方法。其中具有相同栅源掺杂的场效应晶体管元胞结构，包括：碳化硅衬底，该碳化硅衬底材料的掺杂类型为第一导电类型；在碳化硅衬底的正面和背面分别设有第一导电类型半导体外延层和第一电极；在第一导电类型半导体外延层上依次设置有第二导电类型悬浮区、第一导电类型栅极注入区、第一导电类型源极注入区，栅极注入区上设置有栅极，源极注入区上设置有源极，栅极注入区和源极注入区之间设置有极间介质，所述极间介质用于对栅极和源极进行隔离。

Description

一种具有相同栅源掺杂的场效应晶体管、元胞结构及制备方法 技术领域
本发明属于半导体技术领域，具体涉及一种具有相同栅源掺杂的场效应晶体管、元胞结构及制备方法。
背景技术
随着材料技术的发展与成熟，SiC材料的宽禁带特性使其具有更高的温度特性和耐压特性，可以突破Si基器件的限制。由于SiC/SiO 2界面的性能和可靠性仍需要进一步的提高，SiC结型场效应晶体管(Junction Field Effect Transistor，JFET)器件结构受到了广泛的关注。SiC JFET除了避免SiC/SiO 2界面缺陷带来的问题，更容易减小元胞尺寸带来更低的导通电阻。由于SiO 2在高温下会激发更多的界面态，因此SiC JFET器件可以最大限度的发掘SiC材料在高温高压特性。
传统的SiC JFET通过PN结控制，载流子从器件的源极流出后，经过一个狭长的沟道区域，流入器件漂移区，并最终被器件漏极收集。器件沟道由位于栅极和源极间的两个PN结控制，从而控制器件的关断和开启。但传统JFET的P型栅极在器件应用层面带来了很多不利影响：首先，在器件导通时，为了避免PN结开通，器件栅极偏压Vgs不能超过PN结正向开启电压V F0(以碳化硅为例，V F0＝2.6V，即Vgs<V F0)；同时，若器件为常开型，在栅级零偏压导通时，P型栅极与N型沟道之间形成的内建电势(下称“栅极内建电势”)使沟道有一定程度的耗尽，导致沟道电阻较高；在器件处于大电流(临近饱和区)工作时，栅极内建电势导致沟道过早进入夹断状态，导致电流过早饱和，并使得该工作时的导通损耗过高。
发明内容
鉴于以上存在的技术问题，本发明用于提供一种具有相同栅源掺杂的场效应晶体管、元胞结构及制备方法。
为解决上述技术问题，本发明采用如下的技术方案：
本发明第一方面提供一种具有相同栅源掺杂的场效应晶体管元胞结构，包括：
碳化硅衬底，该碳化硅衬底材料的掺杂类型为第一导电类型，
在碳化硅衬底的正面和背面分别设有第一导电类型半导体外延层和第一电极；
在第一导电类型半导体外延层上依次设置有第二导电类型悬浮区、第一导电类型栅极注入区、第一导电类型源极注入区，栅极注入区上设置有栅极，源极注入区上设置有源极，栅极注入区和源极注入区之间设置有极间介质，所述极间介质用于对栅极和源极进行隔离。
优选地，所述第二导电类型悬浮区(005)与第一导电类型源极注入区(007)的接触部与第一导电类型源极注入区(007)结构相同，且都设置为具有终端尖角。
优选地，所述终端尖角为0～180度。
优选地，所述第一导电类型半导体外延层002厚度为5～250um，掺杂浓度为1×10 14cm -3-5×10 18cm -3。
优选地，元胞一侧的栅极注入区与栅极连接，元胞另一侧的栅极注入区和源极注入区共同连到源极。
优选地，第一导电类型和第二导电类型的掺杂为1×10 14cm -3-2×10 21cm -3的均匀或非均匀掺杂。
优选地，所述第一导电类型为N型，所述第二导电类型为P型。
优选地，所述第一导电类型为P型，所述第二导电类型为N型。
本发明第二方面提供一种具有相同栅源掺杂的场效应晶体管，包括若干如上所述的元胞结构以及场限环终端结，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
本发明第三方面提供一种具有相同栅源掺杂的场效应晶体管，包括若干如上所述的元胞结构以及结终端扩展和加场限环结终端，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
本发明第四方面提供一种具有相同栅源掺杂的场效应晶体管元胞结构的制备方法，包括以下步骤：
(a)采用碳化硅衬底，该衬底材料的掺杂类型为第一导电类型，在碳化硅衬底的正面设有第一导电类型半导体外延层，用光刻板光刻掩膜材料，遮蔽部分表面，用刻蚀工艺出碳化硅台面，刻蚀深度在0.5到5um；
(b)使用同一光刻掩膜材料进行悬浮区的离子注入，具体工艺包括：采用至少一次倾斜注入和垂直注入Al离子形成第二导电类型悬浮区，使得沟槽底部和侧壁均匀注入；
(c)剥离掩蔽层，进行垂直N注入，形成第一导电类型的栅极注入区和源极注入区；
(d)在槽的侧壁生长介质层作为电极隔离介质，对栅极和源极进行隔离；
(e)沉积金属并通过退火分别在第一导电类型的栅极注入区、源极注入区和衬底表面作为欧姆接触，合金包含硅化物或者碳化物中的至少一种
优选地，步骤进一步包括：增加至少一次倾斜注入，形成沟道注入区。
优选地，所述第一导电类型为N型，所述第二导电类型为P型。
优选地，所述第一导电类型为P型，所述第二导电类型为N型。
本发明第五方面提供一种具有相同栅源掺杂的场效应晶体管的制备方法，所述场效应晶体管包括若干元胞结构以及场限环终端结，其中元胞结构采用如上任一所述的制备方法，且在制作结终端时，刻蚀注入结终端与元胞结构的第 二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
本发明第六方面提供一种具有相同栅源掺杂的场效应晶体管的制备方法，所述场效应晶体管包括若干元胞结构以及结终端扩展和加场限环结终端，其中元胞结构采用如上任一所述的制备方法，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
采用本发明具有如下的有益效果：
(1)在传统JFET的基础上引入具有第一导电类型的栅极和包围该栅极的第二导电类型悬浮区来控制器件沟道，可以增加器件栅极的正向偏压，使得Vgs可以偏置在大于pn结正向开启电压的位置。
(2)当Vgs＝0V时，由于沟道处的PN结不存在内建电势引入的反偏，器件导通电阻更低。
(3)在大电流导通情况下，器件进入饱和状态可以导通更大的电流。
(4)一个栅极连到源极，使得结构可以减小Cgd，从而减小开关损耗。
(5)通过具有终端尖角的第二导电类型悬浮区的引入，使得两个方向注入即可完成第二导电类型悬浮区的注入，解决采用两个方向注入时栅源短路的问题。
附图说明
图1为方法实施例一中碳化硅衬底的正面设有第一导电类型半导体外延层的结构示意图；
图2为方法实施例一中用刻蚀工艺出碳化硅台面的结构示意图；
图3为方法实施例一中形成第二导电类型悬浮区的结构示意图；
图4为方法实施例一中形成栅极注入区和源极注入区的结构示意图；
图5为方法实施例一中形成电极隔离介质的结构示意图；
图6为方法实施例一中形成栅极和源极的结构示意图；
图7为方法实施例二中形成沟道注入区的结构示意图；
图8为方法实施例三中一个栅极连到源极的结构示意图；
图9为方法实施例四中刻蚀注入结终端与元胞结构的有源区同时刻蚀注入的结构示意图；
图10为方法实施例五中刻蚀注入结终端与元胞结构的有源区同时刻蚀注入的结构示意图。
图11为当器件关断时沟道注入区和第二导电类型悬浮区之间的空间电荷区闭合的结构示意图；
图12为当器件导通时空间电荷区分开的结构示意图；
图13为与传统的JFET器件相比提高了栅极可加的电压的对比示意图；
图14为与传统的JFET器件相比提高了和饱和电流的对比示意图；
图15为本发明又一实施例的具有相同栅源掺杂的场效应晶体管元胞结构的剖面结构示意图；
图16为本发明又一实施例的具有相同栅源掺杂的场效应晶体管元胞结构中具有终端尖角的第二导电类型半导体悬浮区的立体结构示意图；
图17为本发明又一实施例的具有相同栅源掺杂的场效应晶体管元胞结构中具有终端尖角的第二导电类型半导体悬浮区的剖面结构示意图；
图18为具有终端尖角元胞版图元胞的器件有源区版图的布局俯视图；
图19为本发明又一实施例具有相同栅源掺杂的场效应晶体管元胞结构中具有矩形第二导电类型半导体悬浮区的立体结构示意图；
图20为本发明又一实施例的具有相同栅源掺杂的场效应晶体管元胞结构中具有矩形第二导电类型半导体悬浮区的剖面结构示意图；
图21为具有矩形元胞的器件有源区版图的布局俯视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部 的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
方法实施例1
本发明实施例公开了一种具有相同栅源掺杂的场效应晶体管元胞结构的制备方法，包括以下步骤：
(a)参见图1与图2，采用碳化硅衬底001，该衬底材料的掺杂类型为第一导电类型，在碳化硅衬底001的正面设有第一导电类型半导体外延层002，用光刻板光刻掩膜材料，遮蔽部分表面，用ICP(Inductively Coupled Plasma，感应耦合等离子体)刻蚀出碳化硅台面，刻蚀深度在0.5到5um，也可以采用其他刻蚀工艺。
(b)参见图3，使用同一光刻掩膜材料进行悬浮区的离子注入，具体工艺包括：采用至少一次倾斜注入和垂直注入Al离子形成第二导电类型悬浮区005，使得沟槽底部和侧壁均匀注入。
(c)参见图4，剥离掩蔽层，进行垂直N注入，形成第一导电类型的栅极注入区006和源极注入区007之后与金属形成良好的欧姆接触；
(d)参见图5，在槽的侧壁生长介质层作为电极隔离介质010，对栅极注入区006和源极注入区007进行隔离；
(e)参见图6，沉积金属并通过退火分别在栅极、源极和漏极的第一导电类型表面形成硅化物作为欧姆接触，即形成栅极、源极和漏极。
本领域技术人员可以理解的是，在一些具体应用实例中，第一导电类型为N型，第二导电类型为P型。在其他一些应用实例中，第一导电类型为P型，第二导电类型为N型。
在优选的应用实例中，第一导电类型和第二导电类型的掺杂为1×10 14cm -3-2×10 21cm -3的均匀或非均匀掺杂。
其中，优选的应用实例中，第一导电类型半导体外延层002厚度为5～250um，掺杂浓度为1×10 14cm -3-5×10 18cm -3。
方法实施例2
在方法实施例1的基础上，进一步参见图7，在步骤(b)的基础上，增加了至少一次倾斜注入形成的沟道注入区004，此次注入能量会比使用同一光刻掩膜材料进行悬浮区的离子注入中的注入能量大注入深度深，从而会改变外延层的掺杂浓度，注入能量不是停留在沟槽表面，而是达到沟道，可以增加沟道的注入浓度从而进一步减小导通电阻Rdson。
方法实施例3
在方法实施例1和方法实施例2的基础上，参见图8，进一步包括步骤(f)，元胞一侧的栅极注入区006与栅极008连接，元胞另一侧的栅极注入区006和源极注入区007共同连到源极009，使得结构可以减小Cgd，从而减小开关损耗。
方法实施例4
参见图9，本发明实施例还提供了一种具有相同栅源掺杂的场效应晶体管的制备方法，所述场效应晶体管包括若干元胞结构以及场限环终端结，其中采用方法实施例1至3中的一种进行制备，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
方法实施例5
参见图10，本发明实施例还提供了一种具有相同栅源掺杂的场效应晶体管的制备方法，场效应晶体管包括若干元胞结构以及结终端扩展和加场限环结终端，其中元胞结构采用方法实施例1至3中的一种进行制备，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
通过以上方法，可制备出具有相同栅源掺杂的场效应晶体管的元胞结构以及具有相同栅源掺杂的场效应晶体管，以下通过结构实施例进行具体的描述。
结构实施例1
通过方法实施例1制备的一种具有相同栅源掺杂的场效应晶体管元胞结 构，参见图6，包括：
碳化硅衬底001，该碳化硅衬底材料的掺杂类型为第一导电类型，
在碳化硅衬底001的正面和背面分别设有第一导电类型半导体外延层002和第一电极003(即图示中的漏极)；
在第一导电类型半导体外延层002上依次设置有第二导电类型悬浮区005、第一导电类型栅极注入区006、第一导电类型源极注入区007，栅极注入区006上设置有栅极008，源极注入区上设置有源极009，栅极注入区006和源极注入区007之间设置有极间介质010，极间介质010用于对栅极008和源极009进行隔离。
其中，优选的应用实例中，第一导电类型半导体外延层002厚度为5～250um，掺杂浓度为1×10 14cm -3-5×10 18cm -3。
本发明实施例在传统JFET的基础上引入具有第一导电类型的栅极和包围该栅极的第二导电类型悬浮区来控制器件沟道。可以增加器件栅极的正向偏压，使得Vgs可以偏置在大于pn结正向开启电压的位置(以碳化硅为例，可以V GS＝20V)。同时，当Vgs＝0V时，由于沟道处的PN结不存在内建电势引入的反偏，器件导通电阻更低。在大电流导通情况下，器件进入饱和状态可以导通更大的电流。即相较于传统的JFET器件，本发明提高了栅极可加的电压和饱和电流，如图13和图14所示。
在优选的应用实例中，第一导电类型和第二导电类型的掺杂为1×10 14cm -3-2×10 21cm -3的均匀或非均匀掺杂。
结构实施例2
通过方法实施例2制备的一种具有相同栅源掺杂的场效应晶体管元胞结构，参见图7，在结构实施例1的基础上，通过在外延层上增加至少一次倾斜注入形成沟道注入区004。
通过调节沟道注入区004和第二导电类型悬浮区005的掺杂浓度，可以调节该JFET器件的阈值电压。参见图11，当器件关断时，沟道注入区004和第 二导电类型悬浮区005之间的空间电荷区闭合；参见图12，当器件导通时，空间电荷区分开。
结构实施例3
参见图8，在实施例1和实施例2的基础上，其中一个栅极连到源极，使得结构可以减小Cgd，从而减小开关损耗。
结构实施例4
在结构实施例1和结构实施例2的基础上，参见图8，元胞一侧的栅极注入区006与栅极008连接，元胞另一侧的栅极注入区006和源极注入区007共同连到源极009，使得结构可以减小Cgd，从而减小开关损耗。
结构实施例5
参见图9，本发明实施例提供的一种具有相同栅源掺杂的场效应晶体管，包括若干如结构实施例1至4任一的元胞结构以及场限环终端结，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
结构实施例6
参见图10，一种具有相同栅源掺杂的场效应晶体管，其特征在于，包括若干如结构实施例1至4任一的元胞结构以及结终端扩展和加场限环结终端，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
结构实施例7
参见图15，本发明实施例公开了一种具有相同栅源掺杂的场效应晶体管元胞结构，视图所示为空间直角坐标系中XY平面的剖视图，包括：
碳化硅衬底001，该碳化硅衬底材料的掺杂类型为第一导电类型，
在碳化硅衬底001的正面和背面分别设有第一导电类型半导体外延层002和第一电极003；
在第一导电类型半导体外延层002上依次设置有第二导电类型悬浮区005、 第一导电类型栅极注入区006、第一导电类型源极注入区007，第一导电类型栅极栅极注入区006上设置有栅极008，第一导电类型源极注入区007上设置有源极009，第一导电类型栅极栅极注入区006和第一导电类型源极注入区007之间设置有极间介质010，极间介质010用于对栅极008和源极009进行隔离，其中第二导电类型悬浮区005与第一导电类型源极注入区007的接触部与第一导电类型源极注入区007结构相同，且都设置为具有终端尖角。
对于具有以上剖面结构的器件的制作，经常会采用方形和长方形的版图布局进行刻蚀和注入，参见图19至图21，图19为最小的半个元胞结构的立体图，图20为YZ平面的剖视图，图21为具有矩形元胞的器件有源区版图的布局俯视图。以上结构的JFET器件的元胞结构，这种沟槽器件由于引入的具有第一导电类型的栅极和包围该栅极的第二导电类型悬浮区来控制器件的沟道，需要进行包括前、后、左、右四个不同方向的注入才能避免栅源短路，参见图21所示，每次注入都只能注入到元胞的一个面。如果采用两个方向(只包含前、后)的注入，会使得在器件元胞的边缘部分造成器件第一导电类型的通穿，从而使得栅源短路(见图20)。而为了减少制作周期和成本考虑，实际实施过程中会需要尽量减少注入的次数。本发明实施例通过第二导电类型悬浮区005引入终端尖角的元胞版图结构规避这一问题，在进行前向注入时，可以同时注入到元胞结构的前向三个面，后向注入时，也能同时注入到元胞结构的后向三个面，参见图18所示，从而使得可以从四个方向的注入减少到两个方向的注入，可以缩短一半的注入制作周期，例如，采用图19至图21的结构需要使用四个方向进行注入，每个方向注入需要2个小时，总共需要8小时，而采用图16至图18的结构进行注入，只需进行前后两个方向的注入，每个方向注入需要2个小时，总共只需要4小时，参见图16至图18，图16为最小的半个元胞结构的立体图，图17为YZ平面的剖视图，图18为具有终端尖角元胞的器件有源区版图的布局俯视图。
进一步的，具体应用实例中，终端尖角为0～180度。
本领域技术人员可以理解的是，在一些具体应用实例中，第一导电类型为N型，第二导电类型为P型。在其他一些应用实例中，第一导电类型为P型，第二导电类型为N型。
在优选的应用实例中，第一导电类型和第二导电类型的掺杂为1×10 14cm -3-2×10 21cm -3的均匀或非均匀掺杂。
其中，优选的应用实例中，第一导电类型半导体外延层002厚度为5～250um，掺杂浓度为1×10 14cm -3-5×10 18cm -3。
应当理解，本文所述的示例性实施例是说明性的而非限制性的。尽管结合附图描述了本发明的一个或多个实施例，本领域普通技术人员应当理解，在不脱离通过所附权利要求所限定的本发明的精神和范围的情况下，可以做出各种形式和细节的改变。

Claims (16)

  1. 一种具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，包括：
    碳化硅衬底(001)，该碳化硅衬底材料的掺杂类型为第一导电类型，
    在碳化硅衬底(001)的正面和背面分别设有第一导电类型半导体外延层(002)和第一电极(003)；
    在第一导电类型半导体外延层(002)上依次设置有第二导电类型悬浮区(005)、第一导电类型栅极注入区(006)、第一导电类型源极注入区(007)，栅极注入区(006)上设置有栅极(008)，源极注入区上设置有源极(009)，第一导电类型栅极注入区(006)和第一导电类型源极注入区(007)之间设置有极间介质(010)，所述极间介质(010)用于对栅极(008)和源极(009)进行隔离。
  2. 如权利要求1所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，所述第二导电类型悬浮区(005)与第一导电类型源极注入区(007)的接触部与第一导电类型源极注入区(007)结构相同，且都设置为具有终端尖角。
  3. 如权利要求2所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，所述终端尖角为0～180度。
  4. 如权利要求1至3任一所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，所述第一导电类型半导体外延层(002)厚度为5～250um，掺杂浓度为1×10 14cm -3-5×10 18cm -3。
  5. 如权利要求1至3任一所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，元胞一侧的栅极注入区(006)与栅极(008)连接，元胞另一侧的栅极注入区(006)和源极注入区(007)共同连到源极(009)。
  6. 如权利要求1至3任一所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，第一导电类型和第二导电类型的掺杂为1×10 14cm -3-2× 10 21cm -3的均匀或非均匀掺杂。
  7. 如权利要求1至3任一所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型。
  8. 如权利要求1至3任一所述的具有相同栅源掺杂的场效应晶体管元胞结构，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型。
  9. 一种具有相同栅源掺杂的场效应晶体管，其特征在于，包括若干如权利要求1至8任一所述的元胞结构以及场限环结终端，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
  10. 一种具有相同栅源掺杂的场效应晶体管，其特征在于，包括若干如权利要求1至8任一所述的元胞结构以及结终端扩展和加场限环结终端，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
  11. 一种具有相同栅源掺杂的场效应晶体管元胞结构的制备方法，其特征在于，包括以下步骤：
    (a)采用碳化硅衬底(001)，该衬底材料的掺杂类型为第一导电类型，在碳化硅衬底(001)的正面设有第一导电类型半导体外延层(002)，用光刻板光刻掩膜材料，遮蔽部分表面，用刻蚀工艺出碳化硅台面，刻蚀深度在0.5到5um；
    (b)使用同一光刻掩膜材料进行悬浮区的离子注入，具体工艺包括：采用至少一次倾斜注入和垂直注入Al离子形成第二导电类型悬浮区(005)，使得沟槽底部和侧壁均匀注入；
    (c)剥离掩蔽层，进行垂直N注入，形成第一导电类型的栅极注入区(006)和源极注入区(007)；
    (d)在槽的侧壁生长介质层作为电极隔离介质(010)，对栅极和源极进行隔离；
    (e)沉积金属并通过退火分别在第一导电类型的栅极注入区(006)、源极 注入区(007)和衬底(001)表面形成合金作为欧姆接触，合金包含硅化物或者碳化物中的至少一种。
  12. 如权利要求11所述的具有相同栅源掺杂的场效应晶体管元胞结构的制备方法，其特征在于，步骤(b)进一步包括：增加至少一次倾斜注入，形成具有第一导电类型的沟道注入区(004)。
  13. 如权利要求11或12所述的具有相同栅源掺杂的场效应晶体管元胞结构的制备方法，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型。
  14. 如权利要求11或12所述的具有相同栅源掺杂的场效应晶体管元胞结构的制备方法，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型。
  15. 一种具有相同栅源掺杂的场效应晶体管的制备方法，其特征在于，所述场效应晶体管包括若干元胞结构以及场限环终端结，其中元胞结构采用权利要求11至14任一所述的制备方法，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
  16. 一种具有相同栅源掺杂的场效应晶体管的制备方法，其特征在于，所述场效应晶体管包括若干元胞结构以及结终端扩展和加场限环结终端，其中元胞结构采用权利要求11至14任一所述的制备方法，且在制作结终端时，刻蚀注入结终端与元胞结构的第二导电类型悬浮区同时使用同一块光刻掩膜版刻蚀注入。
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