WO2021203415A1 - 驱动基板及其制作方法、显示装置 - Google Patents

驱动基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021203415A1
WO2021203415A1 PCT/CN2020/084206 CN2020084206W WO2021203415A1 WO 2021203415 A1 WO2021203415 A1 WO 2021203415A1 CN 2020084206 W CN2020084206 W CN 2020084206W WO 2021203415 A1 WO2021203415 A1 WO 2021203415A1
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Prior art keywords
layer
insulating layer
wiring
base substrate
thickness
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PCT/CN2020/084206
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English (en)
French (fr)
Inventor
曹占锋
王珂
汪建国
张国才
袁广才
董学
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2021572429A priority Critical patent/JP7485467B2/ja
Priority to KR1020227013891A priority patent/KR20220165719A/ko
Priority to CN202080000512.1A priority patent/CN113875011A/zh
Priority to US17/260,778 priority patent/US20210359182A1/en
Priority to PCT/CN2020/084206 priority patent/WO2021203415A1/zh
Priority to EP20897613.4A priority patent/EP4135039A4/en
Publication of WO2021203415A1 publication Critical patent/WO2021203415A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, in particular to a drive substrate, a manufacturing method thereof, and a display device.
  • HDR High-Dynamic Range
  • the embodiments of the present disclosure provide a drive substrate, a manufacturing method thereof, and a display device, which can reduce the number of patterning processes for manufacturing the drive substrate.
  • a drive substrate including:
  • a plurality of first traces located on a side of the stress buffer layer away from the base substrate, the first traces having a first thickness
  • a first insulating layer located on a side of the first wiring away from the base substrate
  • a plurality of second wiring structures located on the side of the first insulating layer away from the base substrate, each of the first wiring passes through a first via hole penetrating the first insulating layer and at least one of the The second wiring structure is connected, the second wiring structure has a second thickness, and the second thickness is smaller than the first thickness;
  • a second insulating layer located on a side of the second wiring structure away from the base substrate;
  • the electronic component located on the side of the second insulating layer away from the base substrate is connected to the second wiring structure through a second via hole penetrating the second insulating layer.
  • the first trace includes a stacked copper layer and a first metal layer, the first metal layer is located on a side of the copper layer close to the base substrate, and the first metal layer
  • the adhesion force with the stress buffer layer is greater than the adhesion force between the copper layer and the stress buffer layer.
  • the thickness of the copper layer is 1-30um.
  • the first trace further includes a first conductive protection layer on a side of the copper layer close to the base substrate.
  • the second wiring structure includes at least one second wiring layer, and each second wiring layer includes a plurality of second wirings.
  • An insulating layer is spaced between two adjacent second wiring layers. From close to the base substrate to a direction away from the base substrate, each second wiring of the previous layer is at least One second trace is connected, and each second trace of the last layer is connected to at least one of the electronic components.
  • the second wiring includes a stacked copper layer and a second metal layer, the second metal layer is located on a side of the copper layer close to the base substrate, and the second metal layer is connected to the first metal layer.
  • the adhesion of the insulating layer is greater than the adhesion of the copper layer and the first insulating layer.
  • the drive substrate includes a display area and a fan-out area located at the periphery of the display area, and the drive substrate further includes:
  • the first insulating layer includes:
  • a first inorganic insulating layer and a first organic insulating layer are stacked, and the first organic insulating layer is located on a side of the first inorganic insulating layer away from the base substrate.
  • the driving substrate further includes:
  • the fourth inorganic insulating layer is located on the side of the first organic insulating layer away from the base substrate, and the second wiring structure is located on the side of the fourth inorganic insulating layer away from the base substrate.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned driving substrate.
  • the embodiment of the present disclosure also provides a manufacturing method of a driving substrate, including:
  • first insulating layer covering the first wiring, the first insulating layer including a first via hole exposing a part of the surface of the first wiring;
  • a plurality of second wiring structures are formed on the first insulating layer, and each of the first wirings is connected to at least one of the second wiring structures through a first via hole penetrating the first insulating layer,
  • the second wiring structure has a second thickness, and the second thickness is smaller than the first thickness
  • An electronic element is disposed on the second insulating layer, and the electronic element is connected to the second wiring structure through a second via hole penetrating the second insulating layer.
  • forming the first trace includes:
  • a first conductive layer with a first thickness is deposited on the stress buffer layer, and the first conductive layer is patterned to form the first wiring.
  • forming the first trace includes:
  • a seed layer with a thickness less than the first thickness is deposited on the stress buffer layer, a negative photoresist is formed on the seed layer, and the photoresist is exposed and developed to form a photoresist removal area and photolithography A resist retention area, where the photoresist removal area corresponds to the first trace to be formed;
  • the seed layer retained and removed by the photoresist is etched, and the third conductive layer and the seed layer located in the photoresist removal area constitute the first wiring.
  • forming the first trace includes:
  • a seed layer with a thickness less than the first thickness is deposited on the stress buffer layer, a photoresist is formed on the seed layer, and the photoresist is exposed and developed to form a photoresist removal area and a photoresist retention area ,
  • the photoresist reserved area corresponds to the first trace to be formed, and the seed layer in the photoresist removal area is etched to form a pattern of the seed layer;
  • a third conductive pattern is grown on the pattern of the seed layer by an electroplating method, and the third conductive pattern and the pattern of the seed layer form the first wiring.
  • the method before the third conductive pattern is grown on the pattern of the seed layer by an electroplating method, the method further includes:
  • the pattern of the third organic insulating layer includes a third organic insulating layer reserved area and a third organic insulating layer removed area, the first 3.
  • the organic insulating layer removal area coincides with the area where the pattern of the seed layer is located;
  • the third inorganic insulating layer is etched to form the pattern of the third inorganic insulating layer.
  • the first insulating layer includes a first inorganic insulating layer and a first organic insulating layer that are stacked, and forming the first insulating layer includes:
  • the first inorganic insulating layer Etching is performed to form a pattern of the first inorganic insulating layer including a fourth via hole, and the third via hole communicates with the fourth via hole to form the first via hole.
  • the second wiring structure includes at least one second wiring layer, and each of the second wiring layers includes a plurality of second wirings, forming all the second wiring layers on the first insulating layer.
  • the second trace includes:
  • a second conductive layer is formed on the first insulating layer by low-temperature deposition, and the second conductive layer is patterned to form the second wiring.
  • the temperature of the low-temperature deposition is not more than 50 degrees Celsius.
  • FIG. 1 is a schematic plan view of a display area of a driving substrate according to an embodiment of the disclosure
  • Figure 2 is an equivalent circuit diagram of part C in Figure 1;
  • 3-22 are schematic diagrams of the manufacturing process of the drive substrate according to the embodiments of the disclosure.
  • HDR High-Dynamic Range, high dynamic range image
  • Perfect HDR requires high contrast and excellent color expression.
  • the area light source controlled by zone can realize HDR technology, which greatly improves the display effect.
  • the surface light source is composed of LED chips arranged in an array, because the LED needs to be driven by a large current, in order to minimize the loss of electrical signals in the signal line, a thick copper process (copper with a thickness of 1-20 ⁇ m) is required to manufacture The wiring of the LED substrate.
  • LEDs are bound on printed circuit boards, and printed circuit boards are usually of small size due to cost constraints.
  • the signal circuit for driving the LED can be fabricated on a large-size glass substrate to form a non-spliced large-size surface light source to reduce production costs.
  • the texture of the glass substrate is relatively brittle, and the stress generated when a thick copper layer is formed on the glass substrate will cause the glass substrate to break.
  • multiple patterning processes can be used to form multiple thinner copper layers, and multiple thinner copper layers can form a thicker copper layer.
  • this will result in a large number of patterning processes for manufacturing the drive substrate, which affects the production cycle of the drive substrate, and causes the production cost of the drive substrate to be relatively high.
  • the embodiments of the present disclosure provide a drive substrate, a manufacturing method thereof, and a display device, which can reduce the number of patterning processes for manufacturing the drive substrate.
  • An embodiment of the present disclosure provides a driving substrate, including:
  • the first wiring is far away from the first insulating layer on the side of the base substrate; a plurality of second wiring structures located on the side of the first insulating layer far from the base substrate, each of the first The wiring is connected to at least one of the second wiring structure through a first via hole penetrating the first insulating layer, the second wiring structure has a second thickness, and the second thickness is smaller than the first thickness;
  • the second wiring structure is away from the second insulating layer on the side of the base substrate; the electronic components located on the side of the second insulating layer away from the base substrate pass through the second insulating layer
  • the second via hole is connected to the second wiring structure.
  • the stress generated when the conductive layer is formed on the base substrate can be relieved, so that the base substrate will not be fragmented, so that a conductive layer with a larger thickness can be formed on the base substrate, and the larger thickness can be used.
  • the large conductive layer is used to make the first trace of the first thickness through a patterning process.
  • the thickness of the first trace is relatively large, which can meet the resistivity requirements of the driving substrate for the trace, and can drive the electrons arranged on the base substrate. Components to realize a large-size drive substrate. In this way, there is no need to form the first wiring with the first thickness through multiple patterning processes, and the number of patterning processes for manufacturing the driving substrate can be reduced.
  • the first thickness may be greater than 1 ⁇ m.
  • the thickness of the stress buffer layer may be 1500 angstroms; when the first thickness is 5um, the thickness of the stress buffer layer may be 3000 angstroms.
  • the orthographic projection of the first via on the base substrate does not exceed the orthographic projection of the first trace on the base substrate, that is, the aperture of the orthographic projection of the first via on the base substrate is not greater than that of the first via.
  • the base substrate may be a glass substrate or a quartz substrate.
  • the size of the base substrate can reach 3m*3m or more, so that the technical solution of the present disclosure can achieve mass production of large-sized drive substrates.
  • the electronic component may be an LED with a size in the micrometer level, that is, the technical solution of the present disclosure can realize a large-sized LED substrate.
  • the second wiring structure may include at least one second wiring layer, and each second wiring layer includes a plurality of second wirings, and two adjacent second wiring layers An insulating layer is spaced between the wire layers, and each second wire of the previous layer is connected to at least one second wire of the next layer in the direction from close to the base substrate to away from the base substrate, Each second trace on the last layer is connected to at least one electronic component.
  • the orthographic projection of the second via on the base substrate does not exceed the orthographic projection of the second trace on the base substrate, that is, the aperture of the orthographic projection of the second via on the base substrate is not larger than the first 2.
  • the line width of the orthographic projection of the trace on the base substrate is not larger than the first 2.
  • the wiring structure may include a first wiring layer and a second wiring layer, the first wiring layer includes a plurality of mutually insulated first wirings, and the second wiring layer
  • the wire layer includes a plurality of second wires insulated from each other, each of the first wires is connected to at least one of the second wires through a via hole penetrating the first insulating layer, and each of the second wires is The wire is connected to at least one electronic component through a via hole penetrating the second insulating layer.
  • the first trace can be connected to multiple second traces.
  • the first trace transmits a large current, so the thickness of the first trace is relatively large; the second trace is mainly used to connect electronic components, and the second trace is mainly used to connect electronic components.
  • the current on the trace is relatively small compared to the current transmitted by the first trace, and the thickness may also be small.
  • the second thickness may be 0.6-0.9um.
  • FIG. 1 is a schematic plan view of a display area of a driving substrate according to an embodiment of the disclosure.
  • the driving substrate includes a display area as shown in FIG. 1 and a fan-out area located at the periphery of the display area.
  • the right half of FIG. 7 is a schematic cross-sectional view of the fan-out area of the drive substrate.
  • the display area is provided with electronic components for emitting light; the fan-out area is used for Flexible circuit board or printed circuit board for bonding. As shown in FIG.
  • the driving substrate includes: a base substrate 1; a stress buffer layer 2 located on the base substrate 1; Wiring 3, the first wiring 3 is composed of a first metal layer 31 and a copper layer 32; the first insulating layer 6 covering the first wiring 3, the first insulating layer 6 includes a first inorganic insulating layer 61 and a first organic insulating layer 61 Insulating layer 62; the second wiring 4 located on the first insulating layer 6, the second wiring 4 is composed of a second metal layer 41 and a copper layer 42; the second insulating layer 12 covering the second wiring 4;
  • the LEDs 7 on the second insulating layer 12 are connected to the second wiring 4 through a via hole penetrating the second insulating layer 12, and the second wiring 4 can be connected to a plurality of LEDs 7 to connect adjacent LEDs 7.
  • each LED 7 includes an epitaxial layer 73 and N pad 71 and P pad 72.
  • N pad 71 and P pad 72 of LED 7 respectively pass through the via hole penetrating the second insulating layer 12 and the second at different positions. Route 4 connection.
  • each group of second traces 4 is connected to four LEDs 7, and each group of second traces 4 can be distributed approximately in a square ring shape.
  • each group of second traces 4 is not limited to forming a ring shape. Other shapes are also possible.
  • Fig. 2 is an equivalent circuit diagram of part C in Fig. 1.
  • each group of second wiring 4 includes an anode wiring 51, a connecting wire 53 and a cathode wiring 52, and each group of second wiring 4 is connected to four Two LEDs, four LEDs are connected in two strings and two in parallel, wherein the anode trace 51 is connected to the anodes of the two LEDs, the cathode trace 52 is connected to the cathodes of the two LEDs, and the connecting line 53 is connected to the anode of one LED and with it. The cathode of the adjacent LED.
  • the first wiring 3 is not limited to using copper, and other metals, such as silver, aluminum, etc., can also be used.
  • the first trace 3 includes a copper layer 32, and the thickness of the copper layer 32 can be adjusted according to the size of the current load. The greater the current load, the greater the thickness of the copper layer 32.
  • the thickness of the copper layer 32 may be 1-30 ⁇ m, and in some embodiments, it may be 2 ⁇ m.
  • the copper layer 32 can be completed by sputtering, electroplating, electroless plating, etc.
  • the stress buffer layer 2 can be made of one or more insulating materials among silicon nitride, silicon oxide and silicon oxynitride, and the stress of the formed copper layer 32 The direction is opposite, which can offset the stress generated when the copper layer 32 is formed, and avoid the fragmentation of the base substrate 1.
  • the thickness of the stress buffer layer 2 may be 500-3000 angstroms.
  • Compressive stress refers to the stress that resists the compressive tendency of the object.
  • Tensile stress is the reaction force of the object to the external force that makes the object tensile.
  • the direction of the compressive stress and tensile stress are opposite, and as the thickness of the film increases, the stress becomes larger. .
  • the copper layer 32 exhibits tensile stress, and the stress buffer layer 2 exhibits compressive stress.
  • a layer of silicon nitride showing compressive stress is first deposited on the base substrate, and then a layer of copper layer showing tensile stress is deposited, due to the stress buffer layer and the copper layer The direction of the stress is opposite, and the stress is offset, so the warpage of the base substrate can be greatly reduced.
  • a stress buffer layer a copper layer with a thickness of 3 ⁇ m can be formed on the base substrate. At this time, the warpage of the base substrate is only equivalent to that of the stress-free buffer layer.
  • the copper layer with a thickness of 3 ⁇ m can be used to prepare the first trace 3 with a resistance performance that meets the requirements. Therefore, the copper layer with a thickness of 3 ⁇ m can be used to prepare the first trace through a patterning process.
  • the wiring 3 does not require multiple patterning processes to respectively form multiple thinner copper layers to form the first wiring 3 with a thicker thickness.
  • the first trace 3 further includes a first metal layer 31 located on the side of the copper layer 32 close to the base substrate 1.
  • the adhesion between the first metal layer 31 and the stress buffer layer 2 Greater than the adhesion between the copper layer 32 and the stress buffer layer 2, so that the adhesion between the first trace 3 and the stress buffer layer 2 can be increased through the first metal layer 31, and prevent the first trace 3 from being removed from the base substrate 1.
  • the first metal layer 31 may use at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and may also use metal oxides such as IGZO, IZO, GZO, and ITO.
  • the thickness of the first metal layer 31 does not need to be set to be large, and may be 200-500 angstroms.
  • the first trace 3 may also include a first conductive protection layer located on the side of the copper layer 32 away from the base substrate 1.
  • the conductive protective layer may be a metal or a transparent conductive material that is not easily oxidized.
  • the first conductive protective layer may be at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi.
  • the first conductive protection layer can prevent oxidation of the surface of the copper layer 32, and the thickness of the first conductive protection layer may be 50-500 angstroms.
  • the first wiring 3 is covered with a first insulating layer 6.
  • the first insulating layer 6 includes a first inorganic insulating layer 61.
  • the first inorganic insulating layer 61 can be made of silicon nitride, silicon oxide, or nitrogen. Inorganic insulating materials such as silicon oxide protect the first trace 3 from being oxidized in the subsequent high-temperature process.
  • the thickness of the first inorganic insulating layer 61 can be 500-3000 angstroms; due to the limitation of the process, the thickness of the first inorganic insulating layer 61 The thickness is small, smaller than the thickness of the first trace 3, and cannot meet the requirements of planarization.
  • the first insulating layer 6 also includes a first organic insulating layer 62.
  • the first organic insulating layer 62 can be made of organic insulating materials with a larger thickness.
  • organic resin fills the recesses existing between the patterns of the first trace 3 to provide a flat surface for the subsequent process and avoid large step differences in the subsequent process, so that the LED displacement problem will not occur during LED bonding.
  • the total thickness of the first insulating layer 6 should be greater than or equal to the thickness of the first wiring 3, and may be 1-30 ⁇ m.
  • a second wiring 4 is provided on the first insulating layer 6. Since the second wiring 4 functions to connect the anode and/or cathode pins of each LED, the thickness of the second wiring 4 does not need to be too large. It can be 3000-9000 angstroms, specifically 6000 angstroms. Due to the superior electrical conductivity of copper, copper can be used to make the second trace 4. As shown in FIG. 7, the second wiring 4 includes a copper layer 42, and the copper layer 42 can be completed by low-temperature deposition, sputtering, electroplating, electroless plating, or the like. In some embodiments, as shown in FIG. 7, the second trace 4 further includes a second metal layer 41 located on the side of the copper layer 42 close to the base substrate 1.
  • the adhesion between the second metal layer 41 and the first insulating layer 6 The adhesion force is greater than the adhesion force between the copper layer 42 and the first insulating layer 6, so that the second metal layer 41 can increase the adhesion force between the second wiring 4 and the first insulating layer 6, and prevent the second wiring 4 from escaping from the lining.
  • the base substrate 1 falls off.
  • the second metal layer 41 can be at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and metal oxides such as IGZO, IZO, GZO, and ITO can also be used.
  • the thickness of the second metal layer 41 does not need to be set to be large, and may be 200-500 angstroms.
  • the driving substrate further includes a fourth inorganic insulating layer 8 on the first insulating layer 6.
  • the fourth inorganic insulating layer 8 can The first organic insulating layer 62 is protected.
  • the fourth inorganic insulating layer 8 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the fourth inorganic insulating layer 8 can be 500-3000 angstroms.
  • the second wiring 4 is formed by a low-temperature deposition method, since the low-temperature deposition method will not cause damage to the first organic insulating layer 62, for example, the process of forming the fourth inorganic insulating layer 8 can be omitted.
  • the exposed surface of the second trace 4 in the display area will be covered with solder paste.
  • the LED to be bound can be soldered on the substrate by a reflow soldering process later, and the first part of the fan-out area B
  • the exposed surface of the second trace 4 is not covered by solder paste, and oxidation will occur during reflow soldering, which will affect the conductivity of the second trace 4.
  • a second conductive protective layer 13 is provided on the side away from the base substrate 1.
  • the second conductive protective layer 13 can be made of a metal or alloy that is not easily oxidized, or a transparent conductive material such as ITO.
  • the second conductive protective layer 13 can be used for The second trace 4 in the fan-out area is protected.
  • the light-emitting side of the drive substrate is the side of the LED7 away from the base substrate 1.
  • the reflective pattern 14 reflects the light emitted by the LED 7 irradiated on the reflective pattern 14 to the light emitting side, thereby improving the light utilization rate of the driving substrate. In some embodiments, as shown in FIGS.
  • the driving substrate further includes: a reflective pattern 14 on the side of the second insulating layer 12 away from the base substrate 1, and the reflective pattern 14
  • the orthographic projection on the base substrate 1 and the orthographic projection of the LED 7 on the base substrate 1 do not overlap, and the minimum horizontal distance between the orthographic projection of the reflective pattern 14 and the edge of the orthographic projection of the LED 7 can be 100um about.
  • the material of the reflective pattern 14 can be white ink, which is formed by screen printing, inkjet printing, etc.; the material of the reflective pattern 14 can also be metal, which is formed by a patterning process. It can be understood that the reflective pattern 14 may also include a portion disposed on the side of the LED 7 facing the base substrate 1 to further increase the reflectivity of light.
  • the second insulating layer 12 may only include an inorganic insulating layer for protecting the second wiring 4, but the thickness of the inorganic insulating layer is generally less than 6000 angstroms.
  • the protection effect of 4 is limited; in addition, before transferring the LED, it is necessary to form a solder paste on the exposed surface of the second trace 4 by means of stencil printing. If the protection effect is insufficient, the second trace 4 is likely to be damaged, so
  • the second insulating layer 12 may also include an organic insulating layer.
  • the organic insulating layer is located on the side of the inorganic insulating layer away from the base substrate 1.
  • the thickness of the organic insulating layer is generally about 1 to 3um, and specifically can be 2um.
  • the thickness of the insulating layer may be about 1000 angstroms. Since the thickness of the organic insulating layer is relatively large, the second wiring 4 can be better protected.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned driving substrate.
  • the display device may be any product or component with a display function, such as an LCD TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.
  • the above-mentioned driving substrate can be used as a surface light source of a display device.
  • the embodiment of the present disclosure also provides a method for manufacturing a drive substrate, including: providing a base substrate; forming a stress buffer layer on the base substrate; forming a first step on the stress buffer layer through a patterning process.
  • the first trace has a first thickness
  • a first insulation layer covering the first trace is formed, and the first insulation layer includes a first via that exposes the first trace
  • a second wiring structure is formed on the first insulating layer, each of the first wiring is connected to at least one of the second wiring structure through a first via hole penetrating the first insulating layer, and the second wiring structure
  • the wiring structure has a second thickness, and the second thickness is smaller than the first thickness; a second insulating layer covering the second wiring structure is formed, and the second insulating layer includes a second insulating layer exposing the second wiring structure.
  • Via; an electronic component is provided on the second insulating layer, and the electronic component is connected to the second wiring structure through a second via that penetrates the second insulating layer.
  • a stress buffer layer is provided on the base substrate, and the stress buffer layer can relieve the stress generated when the conductive layer is formed on the base substrate, so that the base substrate will not be broken, so that it can be on the base substrate.
  • a conductive layer with a larger thickness is formed, and the first trace with the first thickness is made through a patterning process using the conductive layer with a larger thickness.
  • the thickness of the first trace is relatively large, which can meet the resistivity of the drive substrate to the trace. It is required that the electronic components arranged on the base substrate can be driven to realize a large-sized drive substrate. In this way, there is no need to form the first wiring with the first thickness through multiple patterning processes, and the number of patterning processes for manufacturing the driving substrate can be reduced.
  • the manufacturing method of the drive substrate of this embodiment is used to manufacture the drive substrate in the above-mentioned embodiment.
  • forming the stress buffer layer includes:
  • At least one of the following materials is deposited on the base substrate to form the stress buffer layer: silicon nitride, silicon oxide, and silicon oxynitride.
  • a first conductive layer with a first thickness may be deposited on the stress buffer layer, and the first conductive layer may be patterned to form the first trace.
  • a first conductive layer with a first thickness may be formed on the stress buffer layer by electroplating, and the first conductive layer may be patterned to form the first trace.
  • the manufacturing method of the driving substrate specifically includes the following steps:
  • Step 1 As shown in FIG. 3, a base substrate 1 is provided, a stress buffer layer 2 is formed on the base substrate 1, and a first trace 3 is formed on the stress buffer layer 2;
  • the base substrate 1 may be a glass substrate, a quartz substrate or a flexible substrate.
  • the stress buffer layer 2 can be made of one or more insulating materials among silicon nitride, silicon oxide and silicon oxynitride, and the stress direction of the stress buffer layer 2 and the copper layer 32 to be formed are opposite, so that the stress buffer layer 2 can offset
  • the stress generated during the formation of the copper layer 32 avoids the fragmentation of the base substrate 1.
  • the thickness of the stress buffer layer 2 may be 500-3000 angstroms.
  • the first metal layer 31 can be formed on the stress buffer layer 2 first, and the adhesion between the first metal layer 31 and the stress buffer layer 2 is greater than that of the copper layer 32 and the stress buffer layer 2, so that the first metal layer 31 can increase the adhesion between the first trace 3 and the stress buffer layer 2, and prevent the first trace 3 from falling off the base substrate 1, specifically
  • the first metal layer 31 can be made of at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, and metal oxides such as IGZO, IZO, GZO, and ITO can also be used.
  • the thickness of the first metal layer 31 does not need to be set to be large, and may be 200 to 500 angstroms.
  • a copper layer 32 is formed on the first metal layer 31.
  • the copper layer 32 may be formed by sputtering, and the thickness of the copper layer 32 may be 1.0-2 ⁇ m.
  • the driving substrate includes a display area A and a fan-out area B, and both are formed in the display area A and the fan-out area B There is the first trace 3.
  • a first conductive protective layer can also be formed on the side of the copper layer 32 away from the base substrate 1.
  • the first conductive protective layer can be made of a metal or The transparent conductive material, specifically, the first conductive protection layer may use at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi.
  • the first conductive protection layer can protect the copper layer 32 and avoid oxidation of the surface of the copper layer 32.
  • the thickness of the first conductive protection layer does not need to be set to be large, and may be 50-500 angstroms.
  • Step 2 As shown in FIG. 4, a first insulating layer 6 covering the first wiring 3 is formed;
  • the first insulating layer 6 may include a first inorganic insulating layer 61 and a first organic insulating layer 62.
  • the first inorganic insulating layer 61 may be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., to protect the first wiring 3 It will not be oxidized in the subsequent high temperature process, and the thickness of the first inorganic insulating layer 61 can be 500-3000 angstroms; since the thickness of the first inorganic insulating layer 61 is small and smaller than the thickness of the first wiring 3, it cannot satisfy the requirements for planarization. According to the requirements, the first insulating layer 6 also includes a first organic insulating layer 62.
  • the first organic insulating layer 62 can be made of a relatively thick organic insulating material, such as organic resin, to fill the gaps between the first traces 3.
  • the subsequent process provides a flat surface to avoid large step differences in the subsequent process, so that no LED displacement problem occurs during LED bonding.
  • the total thickness of the first insulating layer 6 should be greater than or equal to the thickness of the first trace 3.
  • Step 3 As shown in FIG. 5, the first insulating layer 6 is patterned to form a via hole exposing the first wiring 3, and a second wiring 4 is formed on the first insulating layer 6;
  • the first organic insulating layer 62 can be exposed and developed to form a pattern of the first organic insulating layer 62 including the third via hole.
  • the first inorganic insulating layer The layer 61 is etched, such as dry etching, to form a pattern of the first inorganic insulating layer 61 including a fourth via hole.
  • the third via hole communicates with the fourth via hole to form a penetrating through the first insulating layer.
  • the first via hole 6 and the second trace 4 formed subsequently are connected to the first trace 3 through the first via hole.
  • Using the pattern of the first organic insulating layer 62 as a mask to etch the first inorganic insulating layer 61 can save the number of patterning processes.
  • the thickness of the second trace 4 does not need to be too large, and can be 3000-9000 angstroms. Due to the superior electrical conductivity of copper, copper can be used to make the second trace 4. Of course, other conductive materials can also be used to make the second trace 4.
  • the second trace 4 includes a second metal layer 41 and a copper layer 42.
  • the second metal layer 41 and the copper layer 42 can be formed by low-temperature deposition.
  • the low-temperature deposition method will not affect the first organic insulating layer. 62 caused damage.
  • the adhesion between the second metal layer 41 and the first insulating layer 6 is greater than the adhesion between the copper layer 42 and the first insulating layer 6, so that the second metal layer 41 can increase the insulation between the second wiring 4 and the first insulating layer.
  • the adhesion of the layer 6 prevents the second trace 4 from falling off the base substrate 1.
  • the second metal layer 41 may be at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi.
  • the thickness of the second metal layer 41 does not need to be set to be large, and can be 50-500 angstroms, and the thickness of the copper layer 42 can be about 6000 angstroms.
  • the second metal layer 41 and the copper layer 42 are patterned together to form the second wiring 4.
  • Step 4 As shown in FIG. 6, a second insulating layer 12 is formed;
  • the second insulating layer 12 may only include an inorganic insulating layer to protect the second wiring 4, but the thickness of the inorganic insulating layer is generally below 6000 angstroms, which does not protect the second wiring 4 very well;
  • a solder paste needs to be formed by stencil printing.
  • the second insulating layer 12 can also include an inorganic insulating layer with a thickness of about 6000 angstroms, or it can include an inorganic insulating layer and an organic insulating layer; the organic insulating layer is located on the side of the inorganic insulating layer away from the base substrate 1, and the thickness of the organic insulating layer is generally At this time, the thickness of the inorganic insulating layer may be about 1000 angstroms. Since the thickness of the organic insulating layer is relatively large, the second wiring 4 can be better protected.
  • the second insulating layer 12 includes an inorganic insulating layer and an organic insulating layer
  • the organic insulating layer can be exposed and developed first to form the pattern of the organic insulating layer, and then the organic insulating layer
  • the pattern of the insulating layer is a mask, and the inorganic insulating layer is etched, such as dry etching, to form the pattern of the inorganic insulating layer.
  • the pattern of the second insulating layer 12 is composed of the pattern of the inorganic insulating layer and the pattern of the organic insulating layer.
  • the pattern of the second insulating layer 12 exposes the second wiring 4.
  • Step 5 As shown in FIG. 7, a reflective pattern 14 is formed on the second insulating layer, and the LED 7 is fixed on the substrate;
  • the light emitted by the LED7 is directed in all directions.
  • the light emitted by the LED7 irradiated on the reflective pattern 14 can be reflected to the side away from the base substrate 1 through the reflective pattern 14, so as to improve the light utilization of the drive substrate.
  • the reflective pattern 14 can be made by screen printing and coating white ink, so there is no need to make the reflective pattern through a patterning process, which can save the number of patterning processes.
  • the reflective pattern 14 can also be formed by inkjet printing.
  • LED7 can be formed on the drive substrate through processes such as solder printing, die bonding, reflow soldering, and packaging.
  • LED 7 includes N pad 71 and P pad 72.
  • N pad 71 and P pad 72 of LED 7 respectively pass through the second insulating layer 12.
  • the vias are connected to the second trace 4 located at a different position.
  • the drive substrate of the embodiment shown in FIG. 7 can be obtained.
  • the drive substrate can be formed by four patterning processes, which can reduce the number of patterning processes for manufacturing the drive substrate and reduce the production cost of the drive substrate. .
  • the difference from the embodiment shown in FIG. 7 is that the first insulating layer 6 not only includes the first inorganic insulating layer 61 and the first organic insulating layer 62, but also It includes a fourth inorganic insulating layer 8 on the side of the first organic insulating layer 62 away from the base substrate 1.
  • a base substrate 1 is provided, the stress buffer layer 2 is formed, the first wiring 3 is formed, and the formation includes a first inorganic insulating layer 61 and a first organic insulating layer 62.
  • the first insulating layer 6 is patterned (as shown in Figure 8) to form a second trace 4 (as shown in Figure 9), a second insulating layer 12 is formed (as shown in Figure 10), the reflective pattern 14 and the transfer
  • the steps of binding the LED7 refer to the steps of the foregoing embodiment, and refer to the foregoing preparation method, which will not be repeated here.
  • the method further includes the following steps:
  • a fourth inorganic insulating layer 8 is formed, and the fourth inorganic insulating layer 8 is patterned to form a via hole exposing the first wiring 3;
  • a fourth inorganic insulating layer 8 is formed on the first insulating layer 6.
  • the fourth inorganic insulating layer 8 can protect the first organic insulating layer 62.
  • the fourth inorganic insulating layer 8 can be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the thickness of the fourth inorganic insulating layer 8 can be 500-3000 angstroms.
  • the fourth inorganic insulating layer 8 is patterned to form a pattern of the fourth inorganic insulating layer 8 including a fifth via.
  • the drive substrate of the embodiment shown in FIG. 11 can be obtained through five patterning processes, which reduces the number of patterning processes for manufacturing the drive substrate and reduces the production cost of the drive substrate.
  • the manufacturing method of the drive substrate also includes :
  • a second conductive protection layer 13 covering the second wiring 4 of the fan-out area is formed.
  • the second conductive protective layer 13 can be made of a metal or alloy that is not easily oxidized, and can also be made of a transparent conductive material such as ITO. If the second conductive protection layer 13 is formed on the side of the second trace 4 in the fan-out area away from the base substrate 1, a patterning process needs to be added.
  • the second insulating layer 12 can be formed, and the reflective pattern 14 and the LED 7 can be formed on the second insulating layer 12.
  • the steps of forming the second insulating layer 12, the light-reflecting pattern 14 and the LED 7 refer to the above-mentioned embodiment, and will not be repeated here.
  • the copper layer constituting the first wiring may be formed by electroplating, and the manufacturing method of the driving substrate specifically includes the following steps:
  • a base substrate 1 is provided, a stress buffer layer 2 is formed on the base substrate 1, a seed layer is formed on the stress buffer layer 2, and a negative photoresist is formed on the seed layer.
  • a photoresist removal area and a photoresist retention area are formed, and a photoresist pattern 17 is obtained.
  • the photoresist removal area corresponds to the first trace to be formed, that is, the first trace will be formed in Photoresist removal area.
  • the base substrate 1 may be a glass substrate, a quartz substrate or a flexible substrate.
  • the stress buffer layer 2 can be made of one or more insulating materials among silicon nitride, silicon oxide and silicon oxynitride.
  • the stress buffer layer 2 is opposite to the stress direction of the seed layer to be formed, so that the stress buffer layer 2 can offset the formation
  • the stress generated during the seed layer avoids the fragmentation of the base substrate 1.
  • the thickness of the stress buffer layer 2 may be 500-3000 angstroms.
  • the seed layer can be formed by sputtering.
  • the thickness of the seed layer is much smaller than the first thickness of the first trace to be formed.
  • the thickness of the seed layer can be 3000-6000 angstroms, so that the seed layer will not produce too much Stress.
  • the seed layer may include a first metal layer 15 and a copper layer 16. Since the adhesion between the copper layer 16 and the stress buffer layer 2 is not too strong, the first metal layer can be formed on the stress buffer layer 2 first. Layer 15, the adhesion between the first metal layer 15 and the stress buffer layer 2 is greater than the adhesion between the copper layer 16 and the stress buffer layer 2, so that the first trace 3 and the stress buffer layer 2 can be increased through the first metal layer 15 To prevent the first trace 3 from falling off the base substrate 1.
  • the first metal layer 15 can be made of at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, or IGZO , IZO, GZO, ITO and other metal oxides.
  • the thickness of the first metal layer 15 does not need to be set to be large, and may be 200 to 500 angstroms.
  • a negative photoresist can be used to form the photoresist pattern 17, and the photoresist pattern 17 with an inverted trapezoidal structure can be formed, which is beneficial to the subsequent formation of a copper layer with a positive trapezoidal structure, which in turn is beneficial to the subsequent insulating layer.
  • Deposition In order to facilitate subsequent removal of the photoresist, the thickness of the photoresist pattern 17 is not less than the thickness of the third conductive layer 18, preferably slightly larger than the thickness of the third conductive layer 18.
  • the technical solution of the present disclosure is not limited to the use of negative photoresist, and positive photoresist can also be used to form the photoresist pattern 17. If positive photoresist is used to form the photoresist pattern 17, the pattern 17 is formed
  • the slope angle of the pattern 17 of the photoresist is preferably greater than 80°.
  • Step 2 As shown in FIG. 15, a third conductive layer 18 is grown by an electroplating method on the seed layer where the photoresist pattern 17 is formed;
  • the third conductive layer 18 is formed.
  • the material of the third conductive layer 18 is copper, the stress generated by the copper layer formed by electroplating is small, and the copper layer formation speed is fast, and the third conductive layer 18 with a thickness of 1.0-20 um can be formed. As shown in FIG. 15, the third conductive layer 18 will not be formed in the region where the photoresist remains.
  • Step 3 Remove the photoresist in the photoresist reserved area, and etch the seed layer retained and removed by the photoresist, and the third conductive layer and the seed layer in the photoresist removal area are composed of
  • the first wiring 3 is as shown in FIG. 3.
  • the second wiring 4 is formed (as shown in FIG. 9), and the second insulating layer 12 is formed (as shown in FIG. 10). No longer.
  • the formed seed layer is patterned, and then the third conductive pattern 20 is grown on the pattern of the seed layer by electroplating.
  • the manufacturing method of the driving substrate specifically includes the following steps:
  • Step 1 As shown in Figure 16, a base substrate 1 is provided, a stress buffer layer 2 is formed on the base substrate 1, and a seed layer is formed on the stress buffer layer 2.
  • the thickness of the seed layer is much smaller than the first thickness.
  • a photoresist is formed on the seed layer, and the photoresist is exposed and developed to form a photoresist removal area and a photoresist retention area to obtain a photoresist pattern 19, the photoresist
  • the figure 19 defines the area of the first trace to be formed later.
  • Step 2 As shown in FIG. 17, the seed layer in the photoresist removal area is etched to remove the remaining photoresist to form a pattern of the seed layer;
  • Step 3 As shown in FIG. 18, a third conductive pattern 20 is grown on the pattern of the seed layer by an electroplating method.
  • the first insulating layer 6 including the first inorganic insulating layer 61 and the first organic insulating layer 62 as shown in FIG. 8
  • the fourth inorganic insulating layer 8 as shown in FIG. 8
  • the second wiring 4 as shown in FIG. 9
  • the second insulating layer 12 as shown in FIG. 10
  • the reflective pattern 14 for the above steps, please refer to the aforementioned preparation The method will not be repeated here.
  • the drive substrate of the embodiment shown in FIG. 11 can be obtained through five patterning processes, which reduces the number of patterning processes for manufacturing the drive substrate and reduces the production cost of the drive substrate.
  • a partial planarization layer may be formed first, and the manufacturing method of the driving substrate specifically includes the following steps:
  • Step 1 As shown in Figure 16, a base substrate 1 is provided, a stress buffer layer 2 is formed on the base substrate 1, a seed layer is formed on the stress buffer layer 2, and a photoresist is formed on the seed layer. After the photoresist is exposed and developed, a photoresist removal area and a photoresist retention area are formed, and a photoresist pattern 19 is obtained.
  • the photoresist pattern 19 corresponds to the first trace to be formed, that is, the first trace is formed. After the wiring, the orthographic projection of the first trace on the base substrate 1 coincides with the orthographic projection of the photoresist pattern 19 on the base substrate 1;
  • the base substrate 1 may be a glass substrate, a quartz substrate or a flexible substrate.
  • the stress buffer layer 2 can be made of one or more insulating materials among silicon nitride, silicon oxide and silicon oxynitride.
  • the stress buffer layer 2 is opposite to the stress direction of the seed layer to be formed, so that the stress buffer layer 2 can offset the formation
  • the stress generated during the seed layer avoids the fragmentation of the base substrate 1.
  • the thickness of the stress buffer layer 2 may be 500-3000 angstroms.
  • the seed layer can be formed by sputtering, the thickness of the seed layer is much smaller than the thickness of the first trace to be formed, the thickness of the seed layer can be 3000-6000 angstroms, so that too much stress will not be generated when the seed layer is formed .
  • the seed layer may include a first metal layer 15 and a copper layer 16. Since the adhesion between the copper layer 16 and the stress buffer layer 2 is not too strong, the first metal layer can be formed on the stress buffer layer 2 first. Layer 15, the adhesion between the first metal layer 15 and the stress buffer layer 2 is greater than the adhesion between the copper layer 16 and the stress buffer layer 2, so that the first trace 3 and the stress buffer layer 2 can be increased through the first metal layer 15 To prevent the first trace 3 from falling off the base substrate 1.
  • the first metal layer 15 can be made of at least one of the following: Mo, MoNb, MoTi, MoWu, MoNi, MoNiTi, or IGZO , IZO, GZO, ITO and other metal oxides.
  • the thickness of the first metal layer 15 does not need to be set to be large, and may be 200 to 500 angstroms.
  • a positive photoresist can be used to form the photoresist pattern 19.
  • the thickness of the pattern 19 of the photoresist does not need to be too large, and is generally 1 to 3 um, and may be 1.5 um.
  • Step 2 As shown in FIG. 17, the seed layer in the photoresist removal area is etched to remove the remaining photoresist to form a pattern of the seed layer;
  • Step 3 As shown in FIG. 19, a third inorganic insulating layer 21 and a third organic insulating layer 22 are formed;
  • Step 4 As shown in FIG. 20, the patterns of the third inorganic insulating layer 21 and the third organic insulating layer 22 are formed by one patterning process;
  • the third organic insulating layer 22 is exposed and developed first to form a pattern of the third organic insulating layer 22.
  • the pattern of the third organic insulating layer 22 includes a third organic insulating layer reserved area and a third organic insulating layer removed area , The removal area of the third organic insulating layer overlaps with the area where the pattern of the seed layer is located; using the pattern of the third organic insulating layer 22 as a mask, the third inorganic insulating layer 21 is etched to form The pattern of the third inorganic insulating layer 21.
  • the pattern of the third inorganic insulating layer 21 and the third organic insulating layer 22 is to provide a flat surface for the subsequent formation of the second trace 4.
  • a partial planarization layer is formed before the first trace 3 is formed. , So that subsequent flattening is easier.
  • Step 5 As shown in FIG. 21, a third conductive pattern 20 is grown on the pattern of the seed layer by an electroplating method
  • the third conductive pattern 20 that is grown is also a copper layer.
  • the copper layer formed by electroplating has low stress, and the copper layer is formed at a high speed, and a thicker copper layer can be formed.
  • a third conductive pattern 20 with a thickness of 1.5-20um is formed. As shown in FIG. 20, the third conductive pattern 20 is not formed in the area where the pattern of the seed layer is not provided.
  • the pattern of the seed layer and the third conductive pattern 20 form the first wiring 3.
  • Step 6 As shown in FIG. 22, a first insulating layer 6 covering the first wiring 3 is formed;
  • the first insulating layer 6 may include a first inorganic insulating layer 61 and a first organic insulating layer 62.
  • the first inorganic insulating layer 61 may be made of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., to protect the first wiring 3 It will not be oxidized in the subsequent high temperature process, and the thickness of the first inorganic insulating layer 61 can be 500-3000 angstroms; since the thickness of the first inorganic insulating layer 61 is small and smaller than the thickness of the first wiring 3, it cannot meet the requirements for planarization.
  • the first insulating layer 6 also includes a first organic insulating layer 62.
  • the first organic insulating layer 62 can be made of a relatively thick organic insulating material, such as organic resin, to fill the gaps between the first traces 3, which is
  • the subsequent process provides a flat surface to avoid a large step difference in the subsequent process, so that the LED displacement problem will not occur when the LED is bound.
  • the thickness of the first insulating layer 6 does not need to be too large, it can be about 1.5um, as long as the third inorganic insulating layer 21 and the third organic insulating layer
  • the total thickness of the layer 22 and the first insulating layer 6 may be greater than the thickness of the first wiring 3.
  • the first inorganic insulating layer 61 can also be omitted, and only the first organic insulating layer 62 can be retained.
  • the first insulating layer 6 is patterned to form the second wiring 4, and then the pattern of the second insulating layer 12 is formed, and the reflective pattern 14 and the LED 7 are formed on the second insulating layer 12.
  • the drive substrate of this embodiment can be obtained.
  • the drive substrate can be formed by six patterning processes, and the drive substrate can be manufactured with fewer patterning processes, and the production cost of the drive substrate can be reduced.
  • the second trace 4 in order to avoid contamination of the metal deposition equipment in the process of directly depositing metal on the organic insulating layer to form the second trace, the second trace 4 can be formed by a low-temperature deposition process, and the fourth inorganic trace can be omitted.
  • the insulating layer 8 can reduce one patterning process.
  • the first wiring 3 when the first wiring 3 is formed by electroplating, in order to avoid affecting the electroplating, the first wiring 3 may only include the first metal layer and the copper layer, and does not need to include the first conductive protection layer.
  • sequence number of each step cannot be used to limit the sequence of each step.
  • sequence of each step is changed without creative work. It is also within the protection scope of the present disclosure.

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Abstract

一种驱动基板及其制作方法、显示装置，属于显示技术领域。驱动基板包括：衬底基板（1）；位于衬底基板（1）上的应力缓冲层（2）；位于应力缓冲层（2）远离衬底基板（1）一侧的多个第一走线（3）；位于第一走线（3）远离衬底基板（1）一侧的第一绝缘层（6）；位于第一绝缘层（6）远离衬底基板（1）一侧的多个第二走线结构（4），每一第一走线（3）通过贯穿第二绝缘层（12）的第一过孔与至少一个第二走线结构（4）连接；位于第二走线结构（4）远离衬底基板（1）一侧的第二绝缘层（12）；位于第二绝缘层（12）远离衬底基板（1）一侧的电子元件（7），电子元件（7）通过贯穿第二绝缘层（12）的第二过孔与第二走线结构（4）连接。能够减少制作驱动基板的构图工艺的次数。

Description

驱动基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别是指一种驱动基板及其制作方法、显示装置。
背景技术
HDR(High-Dynamic Range)技术实现高对比度，高色域的显示效果，而具有HDR技术的显示装置中，需要大量的信号走线来传输电信号。因此，如何制作出能够承载大负载的信号走线，以减小线阻损耗，是半导体领域需要考虑的技术问题之一。
发明内容
本公开实施例提供一种驱动基板及其制作方法、显示装置，能够减少制作驱动基板的构图工艺的次数。
本公开的实施例提供技术方案如下：
一方面，提供一种驱动基板，包括：
衬底基板；
位于所述衬底基板上的应力缓冲层；
位于所述应力缓冲层远离所述衬底基板一侧的多个第一走线，所述第一走线具有第一厚度；
位于所述第一走线远离所述衬底基板一侧的第一绝缘层；
位于所述第一绝缘层远离所述衬底基板一侧的多个第二走线结构，每一所述第一走线通过贯穿所述第一绝缘层的第一过孔与至少一个所述第二走线结构连接，所述第二走线结构具有第二厚度，第二厚度小于第一厚度；
位于所述第二走线结构远离所述衬底基板一侧的第二绝缘层；
位于所述第二绝缘层远离所述衬底基板一侧的电子元件，所述电子元件通过贯穿所述第二绝缘层的第二过孔与所述第二走线结构连接。
一些实施例中，所述第一走线包括层叠设置的铜层和第一金属层，所述第一金属层位于所述铜层靠近所述衬底基板的一侧，所述第一金属层与所述应力缓冲层的粘附力大于所述铜层与所述应力缓冲层的粘附力。
一些实施例中，所述铜层的厚度为1-30um。
一些实施例中，所述第一走线还包括位于所述铜层靠近所述衬底基板一侧的第一导电保护层。
一些实施例中，所述第二走线结构包括至少一层第二走线层，每一所述第二走线层包括多条第二走线，在第二走线层为多层时，相邻两层第二走线层之间间隔有绝缘层，从靠近所述衬底基板到远离所述衬底基板的方向上，前一层的每一第二走线与后一层的至少一个第二走线连接，最后一层的每一第二走线与至少一个所述电子元件连接。
一些实施例中，
所述第二走线包括层叠设置的铜层和第二金属层，所述第二金属层位于所述铜层靠近所述衬底基板的一侧，所述第二金属层与所述第一绝缘层的粘附力大于所述铜层与所述第一绝缘层的粘附力。
一些实施例中，所述驱动基板包括显示区域和位于所述显示区域周边的扇出区域，所述驱动基板还包括：
覆盖所述扇出区域的所述第二走线的第二导电保护层。
一些实施例中，所述第一绝缘层包括：
层叠设置的第一无机绝缘层和第一有机绝缘层，所述第一有机绝缘层位于所述第一无机绝缘层远离所述衬底基板的一侧。
一些实施例中，所述驱动基板还包括：
位于所述第一有机绝缘层远离所述衬底基板一侧的第四无机绝缘层，所述第二走线结构位于所述第四无机绝缘层远离所述衬底基板的一侧。
本公开实施例还提供了一种显示装置，包括如上所述的驱动基板。
本公开实施例还提供了一种驱动基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上形成应力缓冲层；
在所述应力缓冲层上通过一次构图工艺形成多个第一走线，所述第一走线具有第一厚度；
形成覆盖所述第一走线的第一绝缘层，所述第一绝缘层包括暴露出所述第一走线部分表面的第一过孔；
在所述第一绝缘层上形成多个第二走线结构，每一所述第一走线通过贯穿所述第一绝缘层的第一过孔与至少一个所述第二走线结构连接，所述第二走线结构具有第二厚度，第二厚度小于第一厚度；
形成覆盖所述第二走线结构的第二绝缘层，所述第二绝缘层包括暴露出所述第二走线结构部分表面的第二过孔；
在所述第二绝缘层上设置电子元件，所述电子元件通过贯穿所述第二绝缘层的第二过孔与所述第二走线结构连接。
一些实施例中，形成所述第一走线包括：
在所述应力缓冲层上沉积第一厚度的第一导电层，对所述第一导电层进行构图，形成所述第一走线。
一些实施例中，形成所述第一走线包括：
在所述应力缓冲层上沉积厚度小于第一厚度的种子层，在所述种子层上形成负性的光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，所述光刻胶去除区域对应待形成的第一走线；
在形成有所述光刻胶的图形的所述种子层上以电镀方法生长出第三导电层；
去除所述光刻胶保留区域的光刻胶；
对所述光刻胶保留去除的种子层进行刻蚀，位于所述光刻胶去除区域的所述第三导电层和所述种子层组成所述第一走线。
一些实施例中，形成所述第一走线包括：
在所述应力缓冲层上沉积厚度小于第一厚度的种子层，在所述种子层上形成光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，所述光刻胶保留区域对应待形成的第一走线，对光刻胶去除区域的所述种子层进行刻蚀，形成种子层的图形；
在所述种子层的图形上以电镀方法生长出第三导电图形，所述第三导电图形和所述种子层的图形组成所述第一走线。
一些实施例中，在所述种子层的图形上以电镀方法生长出第三导电图形之前，所述方法还包括：
形成第三无机绝缘层；
在所述第三无机绝缘层上形成第三有机绝缘层；
对所述第三有机绝缘层进行曝光显影，形成第三有机绝缘层的图形，所述第三有机绝缘层的图形包括第三有机绝缘层保留区域和第三有机绝缘层去除区域，所述第三有机绝缘层去除区域与所述种子层的图形所在区域重合；
以所述第三有机绝缘层的图形为掩膜，对所述第三无机绝缘层进行刻蚀，形成所述第三无机绝缘层的图形。
一些实施例中，所述第一绝缘层包括层叠设置的第一无机绝缘层和第一有机绝缘层，形成所述第一绝缘层包括：
形成第一无机绝缘层；
形成第一有机绝缘层；
对所述第一有机绝缘层进行曝光显影，形成包括第三过孔的第一有机绝缘层的图形，以所述第一有机绝缘层的图形为掩膜，对所述第一无机绝缘层进行刻蚀，形成包括第四过孔的所述第一无机绝缘层的图形，所述第三过孔与所述第四过孔连通组成所述第一过孔。
一些实施例中，所述第二走线结构包括至少一层第二走线层，每一所述第二走线层包括多条第二走线，形成位于所述第一绝缘层上的所述第二走线包括：
在所述第一绝缘层上溅射形成第二导电层，对所述第二导电层进行构图，形成所述第二走线；或
在所述第一绝缘层上通过低温沉积方式形成第二导电层，对所述第二导电层进行构图，形成所述第二走线，低温沉积的温度不大于50摄氏度。
附图说明
图1为本公开实施例驱动基板的显示区域的平面示意图；
图2为图1中C部分的等效电路图；
图3-图22为本公开实施例驱动基板的制作流程示意图。
附图标记
1衬底基板；2应力缓冲层；3第一走线；31第一金属层；32铜层；4第二走线；41第二金属层；42铜层；6第一绝缘层；61第一无机绝缘层；62第一有机绝缘层；8第四无机绝缘层；12第二绝缘层；13第二导电保护层；14反光图形；15第一金属层；16铜层；17、19光刻胶的图形；18第三导电层；20第三导电图形；21第三无机绝缘层；22第三有机绝缘层；51阳极走线；52阴极走线；53连接线；7 LED；71 N pad；72 P pad；73外延层
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
HDR(High-Dynamic Range，高动态范围图像)技术可显著增强液晶显示器的对比度及观看体验，呈现完美的HDR需要高对比度、卓越的色彩表现力。分区控制的面光源可实现HDR技术，极大提升显示效果。当面光源由阵列排布的LED芯片构成时，由于LED发光所需要大电流驱动，为了尽量减小电信号在信号线中的损耗，需要采用厚铜工艺(厚度为1～20μm的铜)来制作LED基板的走线。相关技术中，将LED绑定在印刷电路板上，而印刷电路板由于成本的限制通常均为小尺寸规格，因此如果需要大尺寸的LED面光源，则需要由小尺寸的印刷电路板拼接而成，但相邻印刷电路板的拼接处需要留出FPC(柔性电路板)绑定位置，会导致LED面光源的边框很宽(通常为厘米级别)，影响了显示产品的分辨率和显示效果。
发明人发现，可以将驱动LED的信号线路制作在大尺寸的玻璃基板上,从而形成非拼接的大尺寸面光源以降低生产成本。然而玻璃基板的质地较脆，在玻璃基板上形成厚度较大的铜层时产生的应力会导致玻璃基板碎片。
为了降低形成厚度较大的铜层时产生的应力，可以通过多次构图工艺分别形成多个较薄的铜层，由多个较薄的铜层组成厚度较大的铜层。但这样会导致制作驱动基板的构图工艺的次数较多，影响了驱动基板的生产节拍，导致驱动基板的生产成本较大。
本公开实施例提供一种驱动基板及其制作方法、显示装置，能够减少制作驱动基板的构图工艺的次数。
本公开的实施例提供一种驱动基板，包括：
衬底基板；位于所述衬底基板上的应力缓冲层；位于所述应力缓冲层远离所述衬底基板一侧的多个第一走线，所述第一走线具有第一厚度；位于所述第一走线远离所述衬底基板一侧的第一绝缘层；位于所述第一绝缘层远离所述衬底基板一侧的多个第二走线结构，每一所述第一走线通过贯穿所述第一绝缘层的第一过孔与至少一个所述第二走线结构连接，所述第二走线结构具有第二厚度，第二厚度小于第一厚度；位于所述第二走线结构远离所述衬底基板一侧的第二绝缘层；位于所述第二绝缘层远离所述衬底基板一侧的电子元件，所述电子元件通过贯穿所述第二绝缘层的第二过孔与所述第二走线结构连接。
通过设置应力缓冲层，可以缓解在衬底基板上形成导电层时所产生的应力，使得衬底基板不会发生碎片，这样可以在衬底基板上形成厚度较大的导电层，并利用厚度较大的导电层通过一次构图工艺来制作第一厚度的第一走线，第一走线的厚度比较大，能够满足驱动基板对走线的电阻率要求，可以驱动设置在衬底基板上的电子元件，实现大尺寸的驱动基板。这样无需通过多次构图工艺来形成第一厚度的第一走线，可以减少制作驱动基板的构图工艺的次数。
具体地，第一厚度可以大于1μm。
其中，导电层的厚度越大，形成导电层时所产生的应力越大，应力缓冲层的厚度越大，即应力缓冲层的厚度与第一走线的厚度正相关。例如，在第一厚度为2um时，应力缓冲层的厚度可为1500埃；在第一厚度为5um时，应力缓冲层的厚度可为3000埃。
为了避免发生短路，第一过孔在衬底基板上的正投影不超出第一走线在衬底基板上的正投影，即第一过孔在衬底基板上的正投影的孔径不大于第一走线在衬底基板上的正投影的线宽。其中，衬底基板可以为玻璃基板或石英基板。衬底基板的尺寸可以达到3m*3m以上，从而利用本公开的技术方案能够实现大尺寸的驱动基板的量产。其中，电子元件可以为尺寸在微米级别的LED，即本公开的技术方案能够实现大尺寸的LED基板。
为了提高驱动基板上电子元件的密度，所述第二走线结构可以包括至少一层第二走线层，每层第二走线层包括多条第二走线，相邻两层第二走线层之间间隔有绝缘层，从靠近所述衬底基板到远离所述衬底基板的方向上，前一层的每一第二走线与后一层的至少一个第二走线连接，最后一层的每一第二走线与至少一个电子元件连接。
为了避免发生短路，第二过孔在衬底基板上的正投影不超出第二走线在衬底基板上的正投影，即第二过孔在衬底基板上的正投影的孔径不大于第二走线在衬底基板上的正投影的线宽。一具体实施例中，所述走线结构可以包括第一走线层和一第二走线层,，所述第一走线层包括多个相互绝缘的第一走线，所述第二走线层包括多个相互绝缘的第二走线，每一所述第一走线通过贯穿所述第一绝缘层的过孔与至少一个所述第二走线连接，每一所述第二走线通过贯穿所述第二绝缘层的过孔与至少一个电子元件连接。
本实施例中，第一走线可以与多个第二走线连接，第一走线传输大电流，故第一走线的厚度较大；第二走线主要用于连接电子元件，第二走线上的电流相对于第一走线传输的电流比较小，厚度也可以较小，具体地，第二厚度可以为0.6-0.9um。
图1为本公开实施例驱动基板的显示区域的平面示意图，驱动基板包括如图1所示的显示区域和位于显示区域周边的扇出区域，图7中左半部分为图1所示的驱动基板的显示区域在DD’方向上的截面示意图，图7中右半部分为驱动基板的扇出区域的截面示意图，其中，显示区域设置有电子元件，用于进行发光；扇出区域用于与柔性电路板或印刷电路板进行绑定。如图7所示，一具体实施例中，以电子元件为LED为例，驱动基板包括：衬底基板 1；位于衬底基板1上的应力缓冲层2；位于应力缓冲层2上的第一走线3，第一走线3由第一金属层31和铜层32组成；覆盖第一走线3的第一绝缘层6，第一绝缘层6包括第一无机绝缘层61和第一有机绝缘层62；位于第一绝缘层6上的第二走线4，第二走线4由第二金属层41和铜层42组成；覆盖第二走线4的第二绝缘层12；位于第二绝缘层12上的LED7，LED7通过贯穿第二绝缘层12的过孔与第二走线4连接，第二走线4可以与多个LED7连接，起到连接相邻LED7的作用。如图7所示，每个LED 7包括外延层73以及N pad 71和P pad 72，LED7的N pad 71和P pad 72分别通过贯穿第二绝缘层12的过孔与位于不同位置的第二走线4连接。
具体地，如图1所示，第二走线4划分为阵列排布的多组。在一些实施例中，每组第二走线4连接四个LED7，每组第二走线4可以大致沿方形环状分布，当然，每组第二走线4并不局限为构成环状，还可以为其他形状。
图2为图1中C部分的等效电路图，如图2所示，每组第二走线4包括阳极走线51、连接线53和阴极走线52，每组第二走线4连接四个LED，四个LED以两串两并的方式连接，其中，阳极走线51连接两个LED的阳极，阴极走线52连接两个LED的阴极，连接线53连接一个LED的阳极和与之相邻LED的阴极。
由于驱动基板的电流负载大，可以达到几十毫安，对走线的电阻性能要求高，需要采用电阻较小的金属，否则走线发热量大会导致温度过高；而铜的导电性能优越，因此，采用铜来作为第一走线3的主体。当然，第一走线3并不局限于采用铜，还可以采用其他金属，比如银、铝等。如图7所示，第一走线3包括铜层32，根据电流负载的大小可以调节铜层32的厚度，电流负载越大，则铜层32的厚度越大。铜层32的厚度可以为1～30μm，在一些实施例中，具体可以为2um。铜层32可以通过溅射、电镀、化学镀等方式完成，应力缓冲层2可以采用氮化硅、氧化硅和氮氧化硅中的一种或多种绝缘材料，与形成的铜层32的应力方向相反，这样可以抵消形成铜层32时所产生的应力，避免衬底基板1碎片。应力缓冲层2的厚度可以为500～3000埃。
压应力指抵抗物体有压缩趋势的应力，拉应力是物体对使物体有拉伸趋 势的外力的反作用力，压应力和拉应力的应力方向相反，且随着膜层厚度的增加，应力变大。铜层32表现出拉应力，而应力缓冲层2表现出压应力。以应力缓冲层2采用氮化硅为例，先在衬底基板上沉积一层表现为压应力的氮化硅，之后再沉积一层表现为拉应力的铜层，由于应力缓冲层与铜层的应力方向相反，出现应力抵消，因此可以大幅度降低衬底基板的翘曲度。经过实验验证，通过增加应力缓冲层可以在衬底基板上形成厚度为3μm的铜层，此时衬底基板的翘曲度仅相当于无应力缓冲层的情况下在衬底基板上形成厚度为1μm的铜层时衬底基板的翘曲度，利用厚度为3μm的铜层可以制备电阻性能满足要求的第一走线3，因此，可利用厚度为3μm的铜层通过一次构图工艺制备第一走线3，无需通过多次构图工艺分别形成多个较薄的铜层以构成厚度较厚的第一走线3。
在一些实施例中，如7所示，第一走线3还包括位于铜层32靠近衬底基板1一侧的第一金属层31，第一金属层31与应力缓冲层2的粘附力大于铜层32与应力缓冲层2的粘附力，这样通过第一金属层31可以增加第一走线3与应力缓冲层2的粘附力，防止第一走线3从衬底基板1上脱落，具体地，第一金属层31可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi，还可以采用IGZO、IZO、GZO、ITO等金属氧化物。第一金属层31的厚度无需设置的较大，可以为200-500埃。
由于铜层32在接触到空气后表面容易氧化，影响导电性能，一些实施例中，第一走线3还可以包括位于铜层32远离衬底基板1一侧的第一导电保护层，第一导电保护层可以选用不易氧化的金属或透明导电材料，具体地，第一导电保护层可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi。第一导电保护层可以避免铜层32的表面氧化，第一导电保护层的厚度可以为50-500埃。
在第一走线3上覆盖有第一绝缘层6，如图7所示，第一绝缘层6包括第一无机绝缘层61，第一无机绝缘层61可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，保护第一走线3在后续的高温工艺中不被氧化，第一无机绝缘层61的厚度可以为500-3000埃；由于工艺的限制，第一无机绝缘层 61的厚度较小，小于第一走线3的厚度，不能满足平坦化的要求，第一绝缘层6还包括第一有机绝缘层62，第一有机绝缘层62可以采用厚度较大的有机绝缘材料，比如有机树脂等，填充第一走线3图案之间存在的凹部，为后续工艺提供平整的表面，避免后续工艺出现大的段差，这样在进行LED绑定时不会发生LED位移问题。第一绝缘层6总的厚度应大于等于第一走线3的厚度，可以为1-30μm。
在第一绝缘层6上设置有第二走线4，由于第二走线4起到连接各个LED的阳极和/或阴极引脚的功能，故第二走线4的厚度不需要太大，可以为3000-9000埃，具体可以为6000埃。由于铜的导电性能优越，因此，可以采用铜来制作第二走线4。如图7所示，第二走线4包括铜层42，铜层42可以通过低温沉积、溅射、电镀、化学镀等方式完成。在一些实施例中，如图7所示，第二走线4还包括位于铜层42靠近衬底基板1一侧的第二金属层41，第二金属层41与第一绝缘层6的粘附力大于铜层42与第一绝缘层6的粘附力，这样通过第二金属层41可以增加第二走线4与第一绝缘层6的粘附力，防止第二走线4从衬底基板1上脱落，具体地，第二金属层41可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi，还可以采用IGZO、IZO、GZO、ITO等金属氧化物。第二金属层41的厚度无需设置的较大，可以为200-500埃。
若通过溅射方式在第一绝缘层6上形成第二走线4，溅射时的等离子体可能会对第一有机绝缘层62造成损伤，使得第一有机绝缘层62出现碎屑脱落的现象，脱落的碎屑会污染溅射腔室，为了避免这一情况，如图11所示，驱动基板还包括位于第一绝缘层6上的第四无机绝缘层8，第四无机绝缘层8可以对第一有机绝缘层62进行保护。第四无机绝缘层8可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第四无机绝缘层8的厚度可以为500-3000埃。
若通过低温沉积的方式形成第二走线4，由于低温沉积方式不会对第一有机绝缘层62造成损伤，因此如可以省去形成第四无机绝缘层8的工艺。
在将LED转移到基板之前，显示区域的第二走线4中裸露的表面会被锡 膏覆盖，后续可以通过回流焊工艺将待绑定的LED焊接在基板上，而扇出区域B的第二走线4裸露的表面没有锡膏覆盖，在回流焊中会发生氧化，影响第二走线4的导电性能，为了避免这个问题，如图13所示，在扇出区域的第二走线4远离衬底基板1的一侧设置有第二导电保护层13，第二导电保护层13可以采用不易氧化的金属或合金，还可以采用透明导电材料比如ITO，第二导电保护层13可以对扇出区域的第二走线4进行保护。
由于LED7发出的光线是朝向各个方向的，仅有一部分是朝驱动基板的出光侧出射，其中，驱动基板的出光侧是LED7远离衬底基板1的一侧，为了提高光线的利用率，可以通过反光图形14将LED7发出的照射到反光图形14上的光线反射至出光侧，提高驱动基板的光线利用率。在一些实施例中，如图7、图11和图13所示，所述驱动基板还包括：位于第二绝缘层12远离所述衬底基板1一侧的反光图形14，所述反光图形14在所述衬底基板1上的正投影与所述LED7在所述衬底基板1上的正投影不交叠，反光图形14的正投影与LED7的正投影的边缘的最小水平距离可以为100um左右。反光图形14的材料可以为白色油墨，通过丝网印刷、喷墨打印等方式形成；反光图形14的材料也可以为金属，通过构图工艺形成。可以理解的是，反光图形14也可以包括设置在所述LED7朝向衬底基板1一侧的部分，以进一步增加光线的反射率。
本公开的一些实施例中，第二绝缘层12可以仅包括一层无机绝缘层，用于对第二走线4进行保护，但是无机绝缘层的厚度一般在6000埃以下，对第二走线4的保护效果有限；此外，在转移LED之前，需要通过钢网印刷的方式在第二走线4裸露的表面形成锡膏，如在保护效果不足时容易对第二走线4造成损伤，故第二绝缘层12还可以包括一层有机绝缘层，有机绝缘层位于无机绝缘层远离衬底基板1的一侧，有机绝缘层的厚度一般为1～3um左右，具体可以为2um，这时无机绝缘层的厚度可以为1000埃左右，由于有机绝缘层的厚度比较大，因此可以对第二走线4进行较好的保护。
本公开实施例还提供了一种显示装置，包括如上所述的驱动基板。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任 何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
其中，电子元件为LED时，上述驱动基板可以作为显示装置的面光源。
本公开实施例还提供了一种驱动基板的制作方法，包括：提供一衬底基板；在所述衬底基板上形成应力缓冲层；在所述应力缓冲层上通过一次构图工艺形成第一走线，所述第一走线具有第一厚度；形成覆盖所述第一走线的第一绝缘层，所述第一绝缘层包括暴露出所述第一走线的第一过孔；在所述第一绝缘层上形成第二走线结构，每一所述第一走线通过贯穿所述第一绝缘层的第一过孔与至少一个所述第二走线结构连接，所述第二走线结构具有第二厚度，第二厚度小于第一厚度；形成覆盖所述第二走线结构的第二绝缘层，所述第二绝缘层包括暴露出所述第二走线结构的第二过孔；在所述第二绝缘层上设置电子元件，所述电子元件通过贯穿所述第二绝缘层的第二过孔与所述第二走线结构连接。
本实施例中，在衬底基板上设置应力缓冲层，应力缓冲层可以缓解在衬底基板上形成导电层时所产生的应力，使得衬底基板不会发生碎片，这样可以在衬底基板上形成厚度较大的导电层，并利用厚度较大的导电层通过一次构图工艺来制作第一厚度的第一走线，第一走线的厚度比较大，能够满足驱动基板对走线的电阻率要求，可以驱动设置在衬底基板上的电子元件，实现大尺寸的驱动基板。这样无需通过多次构图工艺来形成第一厚度的第一走线，可以减少制作驱动基板的构图工艺的次数。
本实施例的驱动基板的制作方法用于制作上述实施例中的驱动基板。
在一些实施例中，形成所述应力缓冲层包括：
在所述衬底基板上沉积以下至少一种材料形成所述应力缓冲层：氮化硅、氧化硅、氮氧化硅。
在一些实施例中，可以在所述应力缓冲层上沉积第一厚度的第一导电层，对所述第一导电层进行构图，形成所述第一走线。另外一些实施例中，还可以通过电镀方式在所述应力缓冲层上形成第一厚度的第一导电层，对所述第一导电层进行构图，形成所述第一走线。
由于铜具有良好的导电性能，能够满足驱动基板对走线的要求，因此，可以采用采用铜来制作驱动基板的走线。以采用铜制作走线，电子元件为LED为例，一实施例中，驱动基板的制作方法具体包括以下步骤：
步骤1、如图3所示，提供一衬底基板1，在衬底基板1上形成应力缓冲层2，在应力缓冲层2上形成第一走线3；
其中，衬底基板1可为玻璃基板、石英基板或柔性基板。
应力缓冲层2可以采用氮化硅、氧化硅和氮氧化硅中的一种或多种绝缘材料，应力缓冲层2与待形成的铜层32的应力方向相反，这样通过应力缓冲层2可以抵消形成铜层32时所产生的应力，避免衬底基板1碎片。应力缓冲层2的厚度可以为500～3000埃。
由于铜层32与应力缓冲层2的粘附力不是太强，因此可以先在应力缓冲层2上形成第一金属层31，第一金属层31与应力缓冲层2的粘附力大于铜层32与应力缓冲层2的粘附力，这样通过第一金属层31可以增加第一走线3与应力缓冲层2的粘附力，防止第一走线3从衬底基板1上脱落，具体地，第一金属层31可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi，还可以采用IGZO、IZO、GZO、ITO等金属氧化物。第一金属层31的厚度无需设置的较大，可以为200～500埃。
在第一金属层31上形成铜层32，铜层32可以通过溅射的方式形成，铜层32的厚度可以为1.0～2μm。
对第一金属层31和铜层32一起进行构图，形成第一走线3，如图3所示，驱动基板包括显示区域A和扇出区域B，在显示区域A和扇出区域B均形成有第一走线3。
由于铜层32在接触到空气后表面容易氧化，影响导电性能，因此在铜层32远离衬底基板1一侧还可以形成第一导电保护层，第一导电保护层可以选用不易氧化的金属或透明导电材料，具体地，第一导电保护层可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi。第一导电保护层可以保护铜层32，避免铜层32的表面氧化，第一导电保护层的厚度无需设置的较大，可以为50-500埃。
步骤2、如图4所示，形成覆盖第一走线3的第一绝缘层6；
第一绝缘层6可以包括第一无机绝缘层61和第一有机绝缘层62，第一无机绝缘层61可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，保护第一走线3在后续的高温工艺中不被氧化，第一无机绝缘层61的厚度可以为500-3000埃；由于第一无机绝缘层61的厚度较小，小于第一走线3的厚度，不能满足平坦化的要求，第一绝缘层6还包括第一有机绝缘层62，第一有机绝缘层62可以采用厚度较大的有机绝缘材料，比如有机树脂等，填充第一走线3之间的缝隙，为后续工艺提供平整的表面，避免后续工艺出现大的段差，这样在进行LED绑定时不会发生LED位移问题，第一绝缘层6总的厚度应大于等于第一走线3的厚度。
步骤3、如图5所示，对第一绝缘层6进行构图，形成暴露出第一走线3的过孔，在第一绝缘层6上形成第二走线4；
可以对第一有机绝缘层62进行曝光显影，形成包括第三过孔的第一有机绝缘层62的图形，以所述第一有机绝缘层62的图形为掩膜，对所述第一无机绝缘层61进行刻蚀，比如干法刻蚀，形成包括第四过孔的所述第一无机绝缘层61的图形，所述第三过孔与所述第四过孔连通组成贯穿第一绝缘层6的第一过孔，后续形成的第二走线4通过第一过孔与第一走线3连接。以第一有机绝缘层62的图形为掩膜对第一无机绝缘层61进行刻蚀，可以节省构图工艺的次数。
第二走线4的厚度不需要太大，可以为3000-9000埃。由于铜的导电性能优越，因此，可以采用铜来制作第二走线4。当然，也可以采用其他导电材料来制作第二走线4。
如图5所示，第二走线4包括第二金属层41和铜层42，可以通过低温沉积的方式形成第二金属层41和铜层42，低温沉积方式不会对第一有机绝缘层62造成损伤。其中，第二金属层41与第一绝缘层6的粘附力大于铜层42与第一绝缘层6的粘附力，这样通过第二金属层41可以增加第二走线4与第一绝缘层6的粘附力，防止第二走线4从衬底基板1上脱落，具体地，第二金属层41可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、 MoNiTi。第二金属层41的厚度无需设置的较大，可以为50-500埃，铜层42的厚度可以为6000埃左右。
对第二金属层41和铜层42一起进行构图，形成第二走线4。
步骤4、如图6所示，形成第二绝缘层12；
第二绝缘层12可以仅包括一层无机绝缘层，用于对第二走线4进行保护，但是无机绝缘层的厚度一般在6000埃以下，对第二走线4的保护不是很好；由于在将LED通过转移绑定的方式固定在驱动基板上时，需要通过钢网印刷的方式形成锡膏，在保护效果不好时容易对第二走线4造成损伤，因此，第二绝缘层12还可以包括厚度在6000埃左右的无机绝缘层，或者可以包括一层无机绝缘层和一层有机绝缘层；有机绝缘层位于无机绝缘层远离衬底基板1的一侧，有机绝缘层的厚度一般为2um左右，这时无机绝缘层的厚度可以为1000埃左右，由于有机绝缘层的厚度比较大，因此可以对第二走线4进行较好的保护。
在第二绝缘层12包括一层无机绝缘层和一层有机绝缘层时，在对第二绝缘层进行构图时，可以对有机绝缘层先进行曝光显影，形成有机绝缘层的图形，之后以有机绝缘层的图形为掩膜，对无机绝缘层进行刻蚀，比如干法刻蚀，形成无机绝缘层的图形，由无机绝缘层的图形和有机绝缘层的图形组成第二绝缘层12的图形，第二绝缘层12的图形暴露出第二走线4。
步骤5、如图7所示，在第二绝缘层上形成反光图形14，并将LED7固定在基板上；
LED7发出的光线是朝向各个方向的，为了提高光线的利用率，可以通过反光图形14将LED7发出的照射到反光图形14上的光线反射至远离衬底基板1一侧，提高驱动基板的光线利用率，所述反光图形14可以通过丝网印刷涂覆白色油墨制成，这样无需通过构图工艺制作反光图形，能够节省构图工艺的次数。反光图形14还可以通过喷墨打印的方式形成。
之后可以通过印刷焊锡、固晶、回流焊、封装等工序在驱动基板上形成LED7，LED 7包括N pad 71和P pad 72，LED7的N pad 71和P pad 72分别通过贯穿第二绝缘层12的过孔与位于不同位置的第二走线4连接。
经过上述步骤即可得到如图7所示的实施例的驱动基板，通过本实施例，可以通过四次构图工艺形成驱动基板，能够减少制作驱动基板的构图工艺的次数，降低驱动基板的生产成本。
另一实施例中，例如图11所示的实施例中，与图7所示的实施例的区别在于，第一绝缘层6不仅包括第一无机绝缘层61和第一有机绝缘层62，还包括位于第一有机绝缘层62远离衬底基板1一侧的第四无机绝缘层8。
形成例如图11所示的驱动基板的制作方法中，提供衬底基板1，形成所述应力缓冲层2，形成第一走线3，形成包括第一无机绝缘层61和第一有机绝缘层62的第一绝缘层6并图案化(如图8所示)，形成第二走线4(如图9所示)，形成第二绝缘层12(如图10所示)，反光图形14和转移绑定LED7的步骤参考上述实施例的步骤可参考前述制备方法，在此不再赘述。而在形成包括第一无机绝缘层61和第一有机绝缘层62的第一绝缘层6和形成第二走线4的步骤之间，还包括步骤：
如图8所示，形成第四无机绝缘层8，对第四无机绝缘层8进行构图，形成暴露出第一走线3的过孔；
在通过溅射方式在第一绝缘层6上形成第二走线4时，溅射时的等离子体可能会对第一有机绝缘层62造成损伤，使得第一有机绝缘层62出现碎屑脱落的现象，脱落的碎屑会污染溅射腔室，为了避免这一情况，在第一绝缘层6上形成第四无机绝缘层8，第四无机绝缘层8可以对第一有机绝缘层62进行保护。第四无机绝缘层8可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，第四无机绝缘层8的厚度可以为500-3000埃。对第四无机绝缘层8进行构图，形成包括第五过孔的所述第四无机绝缘层8的图形，所述第五过孔在所述衬底基板1上的正投影与所述第一过孔在所述衬底基板1上的正投影重合。
经过上述步骤通过五次构图工艺即可得到如图11所示的实施例的驱动基板，减少了制作驱动基板的构图工艺的次数，降低了驱动基板的生产成本。
在将LED转移到基板之前，显示区域的第二走线4中裸露的表面会被锡膏覆盖，后续可以通过回流焊工艺将待绑定的LED焊接在基板上，而扇出区 域B的第二走线4裸露的表面没有锡膏覆盖，在回流焊中会发生氧化，影响第二走线4的导电性能，为了避免这个问题，形成第二走线4后，驱动基板的制作方法还包括：
如图12所示，形成覆盖所述扇出区域的所述第二走线4的第二导电保护层13。第二导电保护层13可以采用不易氧化的金属或合金，还可以采用透明导电材料比如ITO。如果在扇出区域的所述第二走线4远离衬底基板1的一侧形成第二导电保护层13，需要增加一次构图工艺。
之后如图13所示，可以形成第二绝缘层12，并在第二绝缘层12上形成反光图形14和LED7。形成第二绝缘层12、反光图形14和LED7的步骤参考上述实施例，在此不再赘述。
另一实施例中，可以采用电镀的方式形成组成第一走线的铜层，驱动基板的制作方法具体包括以下步骤：
如图14所示，提供一衬底基板1，在衬底基板1上形成应力缓冲层2，在应力缓冲层2上形成种子层，在种子层上形成负性光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，得到光刻胶的图形17，光刻胶去除区域对应待形成的第一走线，即第一走线将会形成在光刻胶去除区域。其中，衬底基板1可为玻璃基板、石英基板或柔性基板。
应力缓冲层2可以采用氮化硅、氧化硅和氮氧化硅中的一种或多种绝缘材料，应力缓冲层2与待形成的种子层的应力方向相反，这样通过应力缓冲层2可以抵消形成种子层时所产生的应力，避免衬底基板1碎片。应力缓冲层2的厚度可以为500～3000埃。
其中，种子层可以采用溅射方式形成，种子层的厚度远小于待形成的第一走线的第一厚度，种子层的厚度可以为3000-6000埃，这样形成种子层时不会产生太大的应力。
如图14所示，种子层可以包括第一金属层15和铜层16，由于铜层16与应力缓冲层2的粘附力不是太强，因此可以先在应力缓冲层2上形成第一金属层15，第一金属层15与应力缓冲层2的粘附力大于铜层16与应力缓冲层2的粘附力，这样通过第一金属层15可以增加第一走线3与应力缓冲层2 的粘附力，防止第一走线3从衬底基板1上脱落，具体地，第一金属层15可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi，还可以采用IGZO、IZO、GZO、ITO等金属氧化物。第一金属层15的厚度无需设置的较大，可以为200～500埃。
本实施例可以采用负性光刻胶形成光刻胶的图形17，能够形成具有倒梯形结构的光刻胶的图形17，有利于后续形成正梯形结构的铜层，进而有利于后续绝缘层的沉积。为了方便后续光刻胶的去除，光刻胶的图形17的厚度不小于第三导电层18的厚度，最好稍大于第三导电层18的厚度。
当然，本公开的技术方案并不局限于采用负性光刻胶，也可以采用正性光刻胶形成光刻胶的图形17，如果采用正性光刻胶形成光刻胶的图形17，形成光刻胶的图形17的坡度角优选大于80°。
步骤2、如图15所示，在形成有光刻胶的图形17的种子层上以电镀方法生长出第三导电层18；
通过电镀方式，形成第三导电层18。第三导电层18的材料为铜时，采用电镀方式形成铜层产生的应力小，并且形成铜层的速度快，可以形成厚度为1.0～20um的第三导电层18。如图15所示，在保留有光刻胶的区域不会形成第三导电层18。
步骤3、去除光刻胶保留区域的光刻胶，对所述光刻胶保留去除的种子层进行刻蚀，位于所述光刻胶去除区域的所述第三导电层和所述种子层组成所述第一走线3，如图3所示。
之后，还包括形成包括第一无机绝缘层61和第一有机绝缘层62的第一绝缘层6并图案化(如图8所示)，形成第四无机绝缘层8并图案化(如图8所示)，形成第二走线4(如图9所示)，形成第二绝缘层12(如图10所示)，反光图形14和转移绑定LED7的步骤可参考前述制备方法，在此不再赘述。
再一实施例中，对形成的种子层进行图案化，再在种子层的图形上以电镀方法生长出第三导电图形20。驱动基板的制作方法具体包括以下步骤：
步骤1、如图16所示，提供一衬底基板1，在衬底基板1上形成应力缓冲层2，在应力缓冲层2上形成种子层，种子层的厚度远小于第一厚度，一 般在几千埃，在种子层上形成光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，得到光刻胶的图形19，所述光刻胶的图形19定义后续待形成的第一走线的区域。
步骤2、如图17所示，对光刻胶去除区域的种子层进行刻蚀，去除剩余的光刻胶，形成种子层的图形；
步骤3、如图18所示，在种子层的图形上以电镀方法生长出第三导电图形20。
之后，还包括，形成包括第一无机绝缘层61和第一有机绝缘层62的第一绝缘层6并图案化(如图8所示)，形成第四无机绝缘层8并图案化(如图8所示)，形成第二走线4(如图9所示)，形成第二绝缘层12(如图10所示)，反光图形14和转移绑定LED7的步骤，上述步骤可参考前述制备方法，在此不再赘述。
经过上述步骤通过五次构图工艺即可得到如图11所示的实施例的驱动基板，减少了制作驱动基板的构图工艺的次数，降低了驱动基板的生产成本。
又一实施例中，在形成第一走线3之前，可以先形成部分平坦化层，驱动基板的制作方法具体包括以下步骤：
步骤1、如图16所示，提供一衬底基板1，在衬底基板1上形成应力缓冲层2，在应力缓冲层2上形成种子层，在种子层上形成光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，得到光刻胶的图形19，所述光刻胶的图形19对应待形成的第一走线，即形成第一走线后，第一走线在衬底基板1上的正投影与光刻胶的图形19在衬底基板1上的正投影重合；
其中，衬底基板1可为玻璃基板、石英基板或柔性基板。
应力缓冲层2可以采用氮化硅、氧化硅和氮氧化硅中的一种或多种绝缘材料，应力缓冲层2与待形成的种子层的应力方向相反，这样通过应力缓冲层2可以抵消形成种子层时所产生的应力，避免衬底基板1碎片。应力缓冲层2的厚度可以为500～3000埃。
其中，种子层可以采用溅射方式形成，种子层的厚度远小于待形成的第 一走线的厚度，种子层的厚度可以为3000-6000埃，这样形成种子层时不会产生太大的应力。
如图16所示，种子层可以包括第一金属层15和铜层16，由于铜层16与应力缓冲层2的粘附力不是太强，因此可以先在应力缓冲层2上形成第一金属层15，第一金属层15与应力缓冲层2的粘附力大于铜层16与应力缓冲层2的粘附力，这样通过第一金属层15可以增加第一走线3与应力缓冲层2的粘附力，防止第一走线3从衬底基板1上脱落，具体地，第一金属层15可以采用以下至少一种：Mo、MoNb、MoTi、MoWu、MoNi、MoNiTi，还可以采用IGZO、IZO、GZO、ITO等金属氧化物。第一金属层15的厚度无需设置的较大，可以为200～500埃。
本实施例可以采用正性光刻胶形成光刻胶的图形19。光刻胶的图形19的厚度不需要太大，一般为1～3um，可以为1.5um。
步骤2、如图17所示，对光刻胶去除区域的种子层进行刻蚀，去除剩余的光刻胶，形成种子层的图形；
步骤3、如图19所示，形成第三无机绝缘层21和第三有机绝缘层22；
步骤4、如图20所示，通过一次构图工艺形成第三无机绝缘层21和第三有机绝缘层22的图形；
先对所述第三有机绝缘层22进行曝光显影，形成第三有机绝缘层22的图形，所述第三有机绝缘层22的图形包括第三有机绝缘层保留区域和第三有机绝缘层去除区域，所述第三有机绝缘层去除区域与所述种子层的图形所在区域重合；以所述第三有机绝缘层22的图形为掩膜，对所述第三无机绝缘层21进行刻蚀，形成所述第三无机绝缘层21的图形。
第三无机绝缘层21和第三有机绝缘层22的图形是为了给后续形成第二走线4提供平坦的表面，本实施例中，在形成第一走线3之前，先形成部分平坦化层，这样后续进行平坦化比较容易。
步骤5、如图21所示，在种子层的图形上以电镀方法生长出第三导电图形20；
由于种子层采用铜层，因此生长出的第三导电图形20也是铜层，采用电 镀方式形成铜层产生的应力小，并且形成铜层的速度快，可以形成厚度较大的铜层，具体可以形成厚度为1.5～20um的第三导电图形20。如图20所示，在未设置种子层的图形的区域不会形成第三导电图形20。种子层的图形和第三导电图形20组成了第一走线3。
步骤6、如图22所示，形成覆盖第一走线3的第一绝缘层6；
第一绝缘层6可以包括第一无机绝缘层61和第一有机绝缘层62，第一无机绝缘层61可以采用氮化硅、氧化硅、氮氧化硅等无机绝缘材料，保护第一走线3在后续的高温工艺中不被氧化，第一无机绝缘层61的厚度可以为500-3000埃；由于第一无机绝缘层61的厚度较小，小于第一走线3的厚度，不能满足平坦化的要求，第一绝缘层6还包括第一有机绝缘层62，第一有机绝缘层62可以采用厚度较大的有机绝缘材料，比如有机树脂等，填充第一走线3之间的缝隙，为后续工艺提供平整的表面，避免后续工艺出现大的段差，这样在进行LED绑定时不会发生LED位移问题。
由于事先已经形成了第三无机绝缘层21和第三有机绝缘层22，因此，第一绝缘层6的厚度不用太大，可以在1.5um左右，只要第三无机绝缘层21、第三有机绝缘层22和第一绝缘层6总的厚度大于第一走线3的厚度即可。
进一步，本步骤中，还可以省去第一无机绝缘层61，仅保留第一有机绝缘层62即可。
之后可以参考上述实施例的步骤，对第一绝缘层6进行构图，形成第二走线4，再形成第二绝缘层12的图形，并在第二绝缘层12上形成反光图形14和LED7，即可得到本实施例的驱动基板，通过本实施例，可以通过六次构图工艺形成驱动基板，能够以较少的构图工艺的次数制作驱动基板，能够降低驱动基板的生产成本。
上述实施例中，为了避免在有机绝缘层上直接沉积金属形成第二走线的过程中，对金属沉积设备的污染，可以采用低温沉积工艺形成第二走线4，则可以省去第四无机绝缘层8，能够减少一次构图工艺。上述实施例中，在采用电镀方式形成第一走线3时，为了避免影响电镀，第一走线3可以仅包括第一金属层和铜层，无需包括第一导电保护层。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种驱动基板，其特征在于，包括：
    衬底基板；
    位于所述衬底基板上的应力缓冲层；
    位于所述应力缓冲层远离所述衬底基板一侧的多个第一走线，所述第一走线具有第一厚度；
    位于所述第一走线远离所述衬底基板一侧的第一绝缘层；
    位于所述第一绝缘层远离所述衬底基板一侧的多个第二走线结构，每一所述第一走线通过贯穿所述第一绝缘层的第一过孔与至少一个所述第二走线结构连接，所述第二走线结构具有第二厚度，第二厚度小于第一厚度；
    位于所述第二走线结构远离所述衬底基板一侧的第二绝缘层；
    位于所述第二绝缘层远离所述衬底基板一侧的电子元件，所述电子元件通过贯穿所述第二绝缘层的第二过孔与所述第二走线结构连接。
  2. 根据权利要求1所述的驱动基板，其特征在于，
    所述第一走线包括层叠设置的铜层和第一金属层，所述第一金属层位于所述铜层靠近所述衬底基板的一侧，所述第一金属层与所述应力缓冲层的粘附力大于所述铜层与所述应力缓冲层的粘附力。
  3. 根据权利要求2所述的驱动基板的制作方法，其特征在于，所述铜层的厚度为1-30um。
  4. 根据权利要求2所述的驱动基板的制作方法，其特征在于，所述第一走线还包括位于所述铜层靠近所述衬底基板一侧的第一导电保护层。
  5. 根据权利要求1所述的驱动基板，其特征在于，所述第二走线结构包括至少一层第二走线层，每一所述第二走线层包括多条第二走线，在第二走线层为多层时，相邻两层第二走线层之间间隔有绝缘层，从靠近所述衬底基板到远离所述衬底基板的方向上，前一层的每一第二走线与后一层的至少一个第二走线连接，最后一层的每一第二走线与至少一个所述电子元件连接。
  6. 根据权利要求5所述的驱动基板，其特征在于，
    所述第二走线包括层叠设置的铜层和第二金属层，所述第二金属层位于所述铜层靠近所述衬底基板的一侧，所述第二金属层与所述第一绝缘层的粘附力大于所述铜层与所述第一绝缘层的粘附力。
  7. 根据权利要求5所述的驱动基板，其特征在于，所述驱动基板包括显示区域和位于所述显示区域周边的扇出区域，所述驱动基板还包括：
    覆盖所述扇出区域的所述第二走线的第二导电保护层。
  8. 根据权利要求1-7中任一项所述的驱动基板，其特征在于，所述第一绝缘层包括：
    层叠设置的第一无机绝缘层和第一有机绝缘层，所述第一有机绝缘层位于所述第一无机绝缘层远离所述衬底基板的一侧。
  9. 根据权利要求8所述的驱动基板，其特征在于，所述驱动基板还包括：
    位于所述第一有机绝缘层远离所述衬底基板一侧的第四无机绝缘层，所述第二走线结构位于所述第四无机绝缘层远离所述衬底基板的一侧。
  10. 一种显示装置，其特征在于，包括如权利要求1-9中任一项所述的驱动基板。
  11. 一种驱动基板的制作方法，其特征在于，包括：
    提供一衬底基板；
    在所述衬底基板上形成应力缓冲层；
    在所述应力缓冲层上通过一次构图工艺形成多个第一走线，所述第一走线具有第一厚度；
    形成覆盖所述第一走线的第一绝缘层，所述第一绝缘层包括暴露出所述第一走线部分表面的第一过孔；
    在所述第一绝缘层上形成多个第二走线结构，每一所述第一走线通过贯穿所述第一绝缘层的第一过孔与至少一个所述第二走线结构连接，所述第二走线结构具有第二厚度，第二厚度小于第一厚度；
    形成覆盖所述第二走线结构的第二绝缘层，所述第二绝缘层包括暴露出所述第二走线结构部分表面的第二过孔；
    在所述第二绝缘层上设置电子元件，所述电子元件通过贯穿所述第二绝 缘层的第二过孔与所述第二走线结构连接。
  12. 根据权利要求11所述的驱动基板的制作方法，其特征在于，形成所述第一走线包括：
    在所述应力缓冲层上沉积第一厚度的第一导电层，对所述第一导电层进行构图，形成所述第一走线。
  13. 根据权利要求11所述的驱动基板的制作方法，其特征在于，形成所述第一走线包括：
    在所述应力缓冲层上沉积厚度小于第一厚度的种子层，在所述种子层上形成负性的光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，所述光刻胶去除区域对应待形成的第一走线；
    在形成有所述光刻胶的图形的所述种子层上以电镀方法生长出第三导电层；
    去除所述光刻胶保留区域的光刻胶；
    对所述光刻胶保留去除的种子层进行刻蚀，位于所述光刻胶去除区域的所述第三导电层和所述种子层组成所述第一走线。
  14. 根据权利要求11所述的驱动基板的制作方法，其特征在于，形成所述第一走线包括：
    在所述应力缓冲层上沉积厚度小于第一厚度的种子层，在所述种子层上形成光刻胶，对所述光刻胶进行曝光显影后形成光刻胶去除区域和光刻胶保留区域，所述光刻胶保留区域对应待形成的第一走线，对光刻胶去除区域的所述种子层进行刻蚀，形成种子层的图形；
    在所述种子层的图形上以电镀方法生长出第三导电图形，所述第三导电图形和所述种子层的图形组成所述第一走线。
  15. 根据权利要求14所述的驱动基板的制作方法，其特征在于，在所述种子层的图形上以电镀方法生长出第三导电图形之前，所述方法还包括：
    形成第三无机绝缘层；
    在所述第三无机绝缘层上形成第三有机绝缘层；
    对所述第三有机绝缘层进行曝光显影，形成第三有机绝缘层的图形，所 述第三有机绝缘层的图形包括第三有机绝缘层保留区域和第三有机绝缘层去除区域，所述第三有机绝缘层去除区域与所述种子层的图形所在区域重合；
    以所述第三有机绝缘层的图形为掩膜，对所述第三无机绝缘层进行刻蚀，形成所述第三无机绝缘层的图形。
  16. 根据权利要求11、12、13或14所述的驱动基板的制作方法，其特征在于，所述第一绝缘层包括层叠设置的第一无机绝缘层和第一有机绝缘层，形成所述第一绝缘层包括：
    形成第一无机绝缘层；
    形成第一有机绝缘层；
    对所述第一有机绝缘层进行曝光显影，形成包括第三过孔的第一有机绝缘层的图形，以所述第一有机绝缘层的图形为掩膜，对所述第一无机绝缘层进行刻蚀，形成包括第四过孔的所述第一无机绝缘层的图形，所述第三过孔与所述第四过孔连通组成所述第一过孔。
  17. 根据权利要求11所述的驱动基板的制作方法，其特征在于，所述第二走线结构包括至少一层第二走线层，每一所述第二走线层包括多条第二走线，形成位于所述第一绝缘层上的所述第二走线包括：
    在所述第一绝缘层上溅射形成第二导电层，对所述第二导电层进行构图，形成所述第二走线；或
    在所述第一绝缘层上通过低温沉积方式形成第二导电层，对所述第二导电层进行构图，形成所述第二走线，低温沉积的温度不大于50摄氏度。
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